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590 Commits

Author SHA1 Message Date
Bob Wilson
60f34b9fb0 Tail duplication still needs to iterate. Duplicating new instructions onto 
the tail of a block may make that block a new candidate for duplication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89264 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-18 22:52:37 +00:00
Anton Korobeynikov
d2aad77261 Forgot to commit test fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89138 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 20:38:36 +00:00
Jim Grosbach
a44321776e Detect need for autoalignment of the stack earlier to catch spills more 
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-15 21:45:34 +00:00
Evan Cheng
d57cdd5683 - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-14 02:55:43 +00:00
Evan Cheng
e17ae4f82e Add radar number. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88739 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-14 02:11:32 +00:00
Evan Cheng
8fdd84cfa7 Fix PR5412: Fix an inverted check and another missing sub-register check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88738 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-14 02:09:09 +00:00
Evan Cheng
1f6a3c820a Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88719 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-13 23:16:41 +00:00
Evan Cheng
236490d870 Fix PR5410: LiveVariables lost subreg def: 
D0<def,dead> = ...
...
             = S0<use, kill>
S0<def>      = ...
...
D0<def>      = 

The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88690 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-13 20:36:40 +00:00
Jim Grosbach
e5165490b7 Use Unified Assembly Syntax for the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 00:11:35 +00:00
Anton Korobeynikov
e8ea011cc7 It turns out that the testcase in question uncovered subreg-handling bug. 
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86375 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 15:20:32 +00:00
Anton Korobeynikov
fc2cba8362 Honour subreg machine operands during asmprinting 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86303 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:45:15 +00:00
Bob Wilson
54c78ef2fe Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86301 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:33:28 +00:00
Evan Cheng
e7e0d62efd Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86294 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 22:24:13 +00:00
Dan Gohman
3f131328ff Update these tests for the new label names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86192 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 23:31:40 +00:00
Bob Wilson
8a008cc49d Attempt again to fix buildbot failures: make expected output less specific 
and compile with -mtriple to specify *-apple-darwin targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 00:30:35 +00:00
Bob Wilson
1709dd73d6 Fix broken test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86045 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 20:04:11 +00:00
Bob Wilson
0d48d6106e Add test for ARM indirectbr codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 19:25:34 +00:00
Evan Cheng
b23b2015eb fconsts / fconstd immediate should be proceeded with #. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85952 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 21:59:33 +00:00
Evan Cheng
777c6b7caa Re-apply 85799. It turns out my code isn't buggy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85947 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 21:40:02 +00:00
Evan Cheng
ba908640b3 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:52:54 +00:00
Anton Korobeynikov
ab453e0641 Revert r85049, it is causing PR5367 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85847 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 00:24:48 +00:00
Evan Cheng
454ac8961b Revert 85799 for now. It might be breaking llvm-gcc driver. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85827 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 21:49:14 +00:00
Evan Cheng
72ed88feac Initilize the machine LICM CSE map upon the first time an instruction is hoisted to 
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85799 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 08:09:49 +00:00
Evan Cheng
580e791ded Remove an irrelevant and poorly reduced test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85794 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 07:11:54 +00:00
Anton Korobeynikov
2ae0eec1c0 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
2e1da9fea4 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85765 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:06 +00:00
Jim Grosbach
8cd0a8cb82 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 22:57:36 +00:00
Jim Grosbach
07d236ba88 Update test to be more explicit about what instruction sequences are expected for each operation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85689 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:52:58 +00:00
Jim Grosbach
bcf2f2c159 Expand 64-bit logical shift right inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:42:19 +00:00
Jim Grosbach
b4a976c304 Expand 64-bit arithmetic shift right inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:00:56 +00:00
Jim Grosbach
c2b879fcfe Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 19:38:01 +00:00
Benjamin Kramer
823bdbc770 Add missing colons for FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85674 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 19:22:24 +00:00
Jim Grosbach
4a26092248 Convert to FileCheck 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85673 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 19:06:53 +00:00
Rafael Espindola
c1382b745f This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 14:33:14 +00:00
Evan Cheng
39382427f1 Use fconsts and fconstd to materialize small fp constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 01:44:26 +00:00
Rafael Espindola
2bda533e1c Add missing testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85266 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 17:59:03 +00:00
Bob Wilson
b9350315d2 Fix the rest of the ARM failures by converting them to FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85208 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 06:16:45 +00:00
Bob Wilson
13e80bdb71 Fix some more failures by converting to FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85207 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 05:50:28 +00:00
Bob Wilson
8bb080e71b Convert to FileCheck, fixing failure due to tab change in the process. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85204 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 05:30:47 +00:00
Evan Cheng
cc7a5b91de Update tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85050 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 07:53:48 +00:00
Bob Wilson
bac6ed4ba4 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 16:52:21 +00:00
Evan Cheng
87689d3b70 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 06:48:32 +00:00
Evan Cheng
8000c6c535 Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 00:40:00 +00:00
Evan Cheng
2095659a85 Match more patterns to movt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 08:15:52 +00:00
Anton Korobeynikov
2bcf60a9cc Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign) 
transform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84683 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 21:37:45 +00:00
Chris Lattner
7bf4bc5a1d convert to filecheck syntax and make a lot more aggressive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:27:56 +00:00
Chris Lattner
baa989ed6e rename test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84515 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:18:07 +00:00
Evan Cheng
d3dd50fec0 Enable post-alloc scheduling for all ARM variants except for Thumb1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 06:11:08 +00:00
Bob Wilson
765cc0b9d5 Revise ARM inline assembly memory operands to require the memory address to 
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84022 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 20:50:28 +00:00
Sandeep Patel
47eedaa8fa Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 18:59:48 +00:00
Benjamin Kramer
90869455b5 Eliminate some redundant llvm-as calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83837 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-12 09:31:55 +00:00
Dan Gohman
cda49a0b29 Update this test; the code is the same but it gets counted as one 
fewer remat.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83690 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 23:31:04 +00:00
Bob Wilson
83815aeb29 Merge a bunch of NEON tests into larger files so they run faster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83667 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 20:20:54 +00:00
Bob Wilson
e8e72be33a Convert some ARM tests with lots of greps to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83651 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 17:20:46 +00:00
Bob Wilson
8795070d50 Commit one last NEON test to use FileCheck. That's all of them now! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83617 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 05:31:56 +00:00
Bob Wilson
0305dd745e Convert more NEON tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83616 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 05:14:48 +00:00
Bob Wilson
5631139a69 Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 00:01:36 +00:00
Bob Wilson
8cdb269686 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 23:51:31 +00:00
Bob Wilson
c5c6edb74f Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83596 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 23:38:24 +00:00
Bob Wilson
4cf0189d5a Convert more NEON tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83595 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 23:33:03 +00:00
Bob Wilson
62e053e5a1 Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83590 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 22:53:57 +00:00
Bob Wilson
5d78275493 Convert more NEON tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83587 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 22:33:53 +00:00
Bob Wilson
0bf7d998b4 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 22:27:33 +00:00
Anton Korobeynikov
632606c724 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83572 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 20:43:22 +00:00
Bob Wilson
30aea9d96e Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 18:56:10 +00:00
Bob Wilson
67a6103a34 Convert more NEON tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83528 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 06:02:10 +00:00
Bob Wilson
deb3141cf5 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 05:18:18 +00:00
Bob Wilson
5adf60c03b Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:28:28 +00:00
Bob Wilson
24e04c535f Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:21:01 +00:00
Bob Wilson
0ea38bb939 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 23:54:04 +00:00
Bob Wilson
fe27c512e8 Convert more NEON tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83507 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 23:47:21 +00:00
Bob Wilson
c67160c010 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 23:39:57 +00:00
Bob Wilson
a4288080e6 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:57:01 +00:00
Bob Wilson
b2cae81ac4 Convert more NEON tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83497 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:30:19 +00:00
Bob Wilson
99c372e723 Convert test to FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83487 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 20:51:42 +00:00
Bob Wilson
63c9063434 Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 20:49:18 +00:00
Bob Wilson
66a70639da Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 20:30:08 +00:00
Bob Wilson
d285575f87 Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:47:39 +00:00
Bob Wilson
7708c22baa Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:09:32 +00:00
Bob Wilson
ff8952e8a9 Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:24:55 +00:00
Bob Wilson
967f87578d Add tests for vld2 of 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:19:13 +00:00
Bob Wilson
ec1d81c389 Update NEON struct names to match llvm-gcc changes. 
(This is not required for correctness but might help with sanity.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83415 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 21:16:19 +00:00
Evan Cheng
3825ce8c24 Fix tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83241 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-02 06:53:57 +00:00
Evan Cheng
62a1b5db44 Move load / store multiple before post-alloc scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-02 04:57:15 +00:00
David Goodwin
9843a93e83 Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 22:19:57 +00:00
David Goodwin
471850ab84 Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 21:46:35 +00:00
David Goodwin
0dad89fa94 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 00:10:16 +00:00
David Goodwin
8971c4a30e Post-RA regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83075 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-29 17:10:26 +00:00
Evan Cheng
fa1be5d991 Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83058 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-29 07:07:30 +00:00
Evan Cheng
0e6b590b91 Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of 
physical registers. This is especially critical for the later two since they
start the live interval of a super-register. e.g.
%DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
If this instruction is eliminated, the register scavenger will not be happy as
D0 is not defined previously.
This fixes PR5055.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82968 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-28 05:28:43 +00:00
Anton Korobeynikov
6a2fa325c1 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. 
This should be better than single load from constpool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-27 23:52:58 +00:00
Evan Cheng
2fcf85efe7 Remove this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82869 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-26 18:51:37 +00:00
Daniel Dunbar
c8e9314a41 "Update" tests for -disable-if-conversion removal. I think branch.ll should just 
be removed, but I XFAIL'd it for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82847 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-26 05:29:36 +00:00
Evan Cheng
9fde6ca2c7 Convert test to filecheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82835 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-26 02:41:17 +00:00
Evan Cheng
483011018e Flip -disable-post-RA-scheduler to -post-RA-scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82803 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-25 21:38:11 +00:00
Dan Gohman
c76909abfe Improve MachineMemOperand handling. 
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-25 20:36:54 +00:00
Bob Wilson
0035f9c3b9 pr4926: ARM requires the stack pointer to be aligned, even for leaf functions. 
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned.  For the older ARM APCS ABI, the stack
alignment is just always 4 bytes.  For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.

After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo.  This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4.  (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-25 14:41:49 +00:00
Bob Wilson
08ae76c042 Convert to FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82710 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-24 20:23:02 +00:00
Evan Cheng
393e277ecd Fix PR5024 with a big hammer: disable the double-def assertion in the scavenger. 
LiveVariables add implicit kills to correctly track partial register kills. This works well enough and is fairly accurate. But coalescer can make it impossible to maintain these markers. e.g.

        BL <ga:sss1>, %R0<kill,undef>, %S0<kill>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def>, ...
...
	%reg1031<def> = FLDS <cp#1>, 0, 14, %reg0, Mem:LD4[ConstantPool]
...
   	%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>

When reg1031 and S0 are coalesced, the copy (FCPYS) will be eliminated the the implicit-kill of D0 is lost. In this case it's possible to move the marker to the FLDS. But in many cases, this is not possible. Suppose

	%reg1031<def> = FOO <cp#1>, %D0<imp-def>
...
   	%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>

When FCPYS goes away, the definition of S0 is the "FOO" instruction. However, transferring the D0 implicit-kill to FOO doesn't work since it is the def of D0 itself. We need to fix this in another time by introducing a "kill" pseudo instruction to track liveness.

Disabling the assertion is not ideal, but machine verifier is doing that job now. It's important to know double-def is not a miscomputation since it means a register should be free but it's not tracked as free. It's a performance issue instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82677 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-24 02:27:09 +00:00
Evan Cheng
296925dc16 Fix PR5024. LiveVariables physical register defs should *commit* only after all 
of the defs are processed.
Also fix a implicit_def propagation bug: a implicit_def of a physical register
should be applied to uses of the sub-registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82616 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-23 06:28:31 +00:00