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1112 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
eab5f7678b Add a catch-all WriteSystem SchedWrite type. 
This is used for all the expensive system instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177598 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-20 23:09:50 +00:00
Jakob Stoklund Olesen
dcb4d349b6 Annotate the remaining SSE MOV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177592 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-20 22:37:16 +00:00
Jakob Stoklund Olesen
2e9aadda63 Annotate SSE horizontal and integer instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177591 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-20 22:37:13 +00:00
Jakob Stoklund Olesen
279ad470b6 Add some missing SSE annotations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177540 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-20 16:56:39 +00:00
Jakob Stoklund Olesen
361706a718 Annotate various null idioms with SchedRW lists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177461 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-19 23:23:31 +00:00
Jakob Stoklund Olesen
f2914c3b2b Annotate SSE float conversions with SchedRW lists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177460 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-19 23:23:29 +00:00
Jakob Stoklund Olesen
9beae49622 Add SchedRW annotations to most of X86InstrSSE.td. 
We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.

Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177326 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-18 22:01:35 +00:00
Nadav Rotem
dd7a300c10 Unaligned loads should use the VMOVUPS opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177130 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-14 23:49:44 +00:00
Craig Topper
4aee1bb222 Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-28 06:48:25 +00:00
Craig Topper
c2cbcc3acf Combine AVX and SSE forms of MOVSS and MOVSD into the same multiclasses so they get instantiated together. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172704 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-17 06:59:42 +00:00
Craig Topper
29344a6349 Simplify nested strconcats in X86 td files since strconcat can take more than 2 arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172379 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-14 07:46:34 +00:00
Craig Topper
33160cf376 Create a single multiclass for SSE and AVX version of MOVL/MOVH. Prevents needing to specify everything twice. No functional change intended 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172378 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-14 07:26:58 +00:00
Benjamin Kramer
08219ea2b4 X86: Add patterns for X86ISD::VSEXT in registers. 
Those can occur when something between the sextload and the store is on the same
chain and blocks isel. Fixes PR14887.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172353 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-13 11:37:04 +00:00
Craig Topper
df3bf55d49 Remove unnecessary # tokens at the beginning and end of defm names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171694 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-07 05:04:39 +00:00
Craig Topper
f564a9389d Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior. 
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.

Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171668 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-06 20:39:29 +00:00
Craig Topper
3af9323228 Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171356 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-02 08:00:39 +00:00
Craig Topper
3cca7df7c7 Merge SSE and AVX instruction definitions for PSHUFD/PSHUFHW/PSHUFLW. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171355 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-02 07:27:49 +00:00
Rafael Espindola
9478673ce0 Revert 171351. It broke MC/X86/x86-32-avx.s. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171352 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-02 01:35:11 +00:00
Craig Topper
b511048cd0 Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171351 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 20:53:20 +00:00
Craig Topper
117e4d2e19 Remove unused argument from a multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171340 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 03:42:44 +00:00
Craig Topper
76f94fd361 Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS and RSQRTPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171339 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 03:30:21 +00:00
Craig Topper
42ab0d75ab Remove 2 unused multiclasses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171338 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 02:02:45 +00:00
Craig Topper
5284f97632 Merge AVX/SSE instruction definitions for SQRTPS/PD, RSQRTPS, RCPPS. No funcitonal change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171337 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 00:11:07 +00:00
Craig Topper
dd9ccdb050 Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and RSQRTPS. VEX-encoded forms already use packed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171336 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-31 23:49:05 +00:00
Craig Topper
22d8f0d685 Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171237 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-29 18:18:20 +00:00
Craig Topper
6d183e4007 Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171227 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-29 16:44:25 +00:00
Craig Topper
cccccabd07 Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171171 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 22:53:47 +00:00
Craig Topper
d5fc507ff1 Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171166 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 18:51:50 +00:00
Craig Topper
068aec586d Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171143 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 07:16:08 +00:00
Craig Topper
d0f28c0958 Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171141 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 06:34:54 +00:00
Craig Topper
37cb8398c8 Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171118 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:30:22 +00:00
Craig Topper
a85cbfeba7 Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171117 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:04:30 +00:00
Craig Topper
0a5ead92ff Merge still more SSE/AVX instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171103 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 07:54:43 +00:00
Craig Topper
07555fc640 Merge more SSE/AVX instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171102 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 07:20:35 +00:00
Craig Topper
755841d9d7 Fix 80 column violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171097 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:15:53 +00:00
Craig Topper
6f9d44e072 Fix class name in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171096 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:15:09 +00:00
Craig Topper
219bc2db1f Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171095 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:14:15 +00:00
Craig Topper
02082efaab Remove 'v' from mnemonic to fix asm matching failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171093 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:02:15 +00:00
Craig Topper
3cdc3827ce Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 05:49:15 +00:00
Craig Topper
09a326d3f0 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 04:36:03 +00:00
Craig Topper
1fe132ae7d Merge an AVX/SSE 256-bit and 128-bit multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:56:47 +00:00
Craig Topper
b5c590a586 Mark VANDNPD/VANDNPDS as not commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171085 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:48:10 +00:00
Benjamin Kramer
739c7a83e1 X86: Match the SSE/AVX min/max vector ops using a custom node instead of intrinsics 
This is very mechanical, no functionality change. Preparation for PR14667.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170898 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 14:04:55 +00:00
Elena Demikhovsky
4b977312c7 Optimized load + SIGN_EXTEND patterns in the X86 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170506 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 07:50:20 +00:00
Benjamin Kramer
388fc6a988 X86: Add a couple of target-specific dag combines that turn VSELECTS into psubus if possible. 
We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases
if y is a constant. DAGCombiner canonicalizes those so we first have to undo the
canonicalization for those cases. The pattern occurs in gzip when the loop
vectorizer is enabled. Part of PR14613.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170273 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-15 16:47:44 +00:00
Craig Topper
da92646875 Remove intrinsic specific instructions for (V)MOVQUmr with patterns pointing to the normal instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169482 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-06 07:31:16 +00:00
Craig Topper
ab69b25f4b Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169477 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-06 06:49:16 +00:00
Elena Demikhovsky
226e0e6264 Simplified BLEND pattern matching for shuffles. 
Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169366 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-05 09:24:57 +00:00
Craig Topper
d577552c66 Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of vector types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168141 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-16 06:37:56 +00:00
Craig Topper
9c7ae01f39 Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167652 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-10 01:23:36 +00:00
Michael Liao
0f6a599434 Remove tailing whitespaces 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167445 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-06 08:06:35 +00:00
Manman Ren
dfd0b9b460 X86 SSE: update rsqrtss and rcpss to use two source operands and 
the first source operand is tied to the destination operand.

This is to accurately model the corresponding instructions where the upper
bits are unmodified.

rdar://12558838
PR14221


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-30 23:53:59 +00:00
Michael Liao
2a2263e744 Fix PR14204 
- Add missing pattern on X86ISD::VZEXT from VR256 to VR256 when AVX2 is enabled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166947 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-29 17:57:12 +00:00
Michael Liao
991b6a22b6 Add custom conversion from v2u32 to v2f32 in 32-bit mode 
- As there's no 64-bit GPRs in 32-bit mode, a custom conversion from v2u32 to
  v2f32 is added to improve the efficiency of the code generated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166545 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-24 04:09:32 +00:00
Michael Liao
d9d09600ee Enable lowering ZERO_EXTEND/ANY_EXTEND to PMOVZX from SSE4.1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166486 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-23 17:34:00 +00:00
Michael Liao
44c2d61b67 Add support for FP_ROUND from v2f64 to v2f32 
- Due to the current matching vector elements constraints in
  ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from
  v2f32) is scalarized. Add a customized v2f32 widening to convert it
  into a target-specific X86ISD::VFPROUND to work around this
  constraints.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165631 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-10 16:53:28 +00:00
Craig Topper
8a312fb3aa Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 06:37:45 +00:00
Craig Topper
cbf3daee0b Add explicit VEX_L tags to all 256-bit instructions. This will allow us to remove code from the code emitters that examined operands to set the L-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164202 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 06:06:34 +00:00
Nadav Rotem
638e4c13cb The PMOVZXWD family of functions had patterns extends narrow vector types to wide vector types. 
It had patterns for zext-loading and extending. This commit adds patterns for loading a wide type, performing a bitcast,
and extending. This is an odd pattern, but it is commonly used when writing code with intrinsics.

rdar://11897677



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163995 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-16 07:39:07 +00:00
Michael Liao
b8150d8523 Enhance PR11334 fix to support extload from v2f32/v4f32 
- Fix an remaining issue of PR11674 as well



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163528 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 18:33:51 +00:00
Craig Topper
12fb5c667f Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163473 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-08 17:42:27 +00:00
Craig Topper
b8d9da13fa Use iPTR instead of i32 for extract_subvector/insert_subvector index in lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163293 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 06:09:01 +00:00
Craig Topper
07149fe715 Add patterns for converting stores of subvector_extracts of lower 128-bits of a 256-bit vector to VMOVAPSmr/VMOVUPSmr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163292 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 05:15:01 +00:00
Craig Topper
4e4e6c0d73 Remove some of the patterns added in r163196. Increasing the complexity on insert_subvector into undef accomplishes the same thing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163198 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-05 07:26:35 +00:00
Craig Topper
c17177f893 Add patterns for integer forms of VINSERTF128/VINSERTI128 folded with loads. Also add patterns to turn subvector inserts with loads to index 0 of an undef into VMOVAPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163196 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-05 06:58:39 +00:00
Craig Topper
f6dc792df1 Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163192 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-05 05:48:09 +00:00
Craig Topper
8365e9bcc2 Typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163053 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-01 06:33:50 +00:00
Michael Liao
5d60c67318 Clean up AddedComplexity further after adding UseSSEx 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162973 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 03:01:35 +00:00
Jim Grosbach
9765c6ecde X86: Fix encoding of 'movd %xmm0, %rax' 
The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v'
prefix, resulting in mis-assembly of the vanilla movd instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162963 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 00:30:30 +00:00
Michael Liao
a03c44117b Introduce 'UseSSEx' to force SSE legacy encoding 
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
  enabled.

  As the penalty of inter-mixing SSE and AVX instructions, we need
  prevent SSE legacy insn from being generated except explicitly
  specified through some intrinsics. For patterns supported by both
  SSE and AVX, so far, we force AVX insn will be tried first relying on
  AddedComplexity or position in td file. It's error-prone and
  introduces bugs accidentally.

  'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
  by AVX, we need this predicate to force VEX encoding or SSE legacy
  encoding only.

  For insns not inherited by AVX, we still use the previous predicates,
  i.e. 'HasSSEx'. So far, these insns fall into the following
  categories:
  * SSE insns with MMX operands
  * SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
    CRC, and etc.)
  * SSE4A insns.
  * MMX insns.
  * x87 insns added by SSE.

2 test cases are modified:

 - test/CodeGen/X86/fast-isel-x86-64.ll
   AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
   selected by fast-isel due to complicated pattern and fast-isel
   fallback to materialize it from constant pool.

 - test/CodeGen/X86/widen_load-1.ll
   AVX code generation is different from SSE one after fixing SSE/AVX
   inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
   'vmovaps'.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162919 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-30 16:54:46 +00:00
Bill Wendling
eeba6e8317 The commutative flag is already correctly set within the multiclass. If we set 
it here, then a 'register-memory' version would wrongly get the commutative
flag.
<rdar://problem/12180135>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162741 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-28 07:36:46 +00:00
Craig Topper
d902194631 Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162740 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-28 07:30:47 +00:00
Craig Topper
13897fb263 Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162738 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-28 07:05:28 +00:00
Jakob Stoklund Olesen
2f1c6f52bd More missing mayLoad flags on AVX multiclasses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162714 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-28 00:02:01 +00:00
Craig Topper
58bfb27c4b Don't allow vextractf128 to be folded with unaligned stores. We don't fold unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162658 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-27 07:19:59 +00:00
Craig Topper
903090c55e Fold some patterns into instruction definitons so tablegen can infer flags removing the need for an explicit 'neverHasSideEffects = 1' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162656 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-27 07:04:50 +00:00
Craig Topper
3a1683f88f Add HasAVX1Only predicate and use it for patterns that have an AVX1 instruction and an AVX2 instruction rather than relying on AddedComplexity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162654 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-27 06:08:57 +00:00
Jakob Stoklund Olesen
cac59d8ae8 Add missing mayLoad flags to a large class of AVX *_Int instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162622 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 23:29:07 +00:00
Jakob Stoklund Olesen
6211386799 Remove some spurious mayLoad = 0 flags. 
They were inserted to silence TableGen's warning about
redundant properties. That warning is now gone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162517 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 00:31:20 +00:00
Nadav Rotem
d60cb11afd When unsafe math is used, we can use commutative FMAX and FMIN. In some cases 
this allows for better code generation.

Added a new DAGCombine transformation to convert FMAX and FMIN to FMANC and
FMINC, which are commutative.

For example:

  movaps  %xmm0, %xmm1
  movsd LC(%rip), %xmm0
  minsd %xmm1, %xmm0

becomes:

  minsd LC(%rip), %xmm0




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162187 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-19 13:06:16 +00:00
Michael Liao
7091b2451d fix PR11334 
- FP_EXTEND only support extending from vectors with matching elements.
  This results in the scalarization of extending to v2f64 from v2f32,
  which will be legalized to v4f32 not matching with v2f64.
- add X86-specific VFPEXT supproting extending from v4f32 to v2f64.
- add BUILD_VECTOR lowering helper to recover back the original
  extending from v4f32 to v2f64.
- test case is enhanced to include different vector width.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161894 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-14 21:24:47 +00:00
Craig Topper
4feb647283 Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-06 06:22:36 +00:00
Craig Topper
cc915951eb Remove custom inserter for MWAIT. It doesn't do anything that couldn't be represented in a pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161306 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-05 00:36:57 +00:00
Manman Ren
5641424a6c X86: mark GATHER instructios as mayLoad 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161143 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 23:28:59 +00:00
Craig Topper
706698e0b7 Give VCVTTPD2DQ priority over CVTTPD2DQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160942 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 02:20:32 +00:00
Craig Topper
80e13a5506 Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160941 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 02:14:02 +00:00
Craig Topper
3ff91c3ac6 Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160939 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-30 01:38:57 +00:00
Craig Topper
19006bdee1 Fix load types on intrinsic forms of SS2SD and SD2SS AVX/SSE convert instruction patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160938 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-29 23:26:34 +00:00
Craig Topper
26a79b7b94 Move more SSE/AVX convert instruction patterns into their definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-29 22:30:06 +00:00
Craig Topper
7fe1b96ef0 Fold patterns for some of the SSE/AVX convert instructions into their instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160922 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 18:59:19 +00:00
Craig Topper
eb6d794834 Mark some of the SSE/AVX convert instructions as mayLoad/neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160921 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 18:36:39 +00:00
Craig Topper
cdfbcdeeed Make CVTSS2SI instruction definition consistent with CVTSD2SI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160914 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 08:28:23 +00:00
Craig Topper
e96d11c833 Fix up memory load types for SSE scalar convert intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160913 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-28 07:59:59 +00:00
Jakob Stoklund Olesen
f992348ffb Remove the last mentions of sub_ss and sub_sd from patterns. 
I'll remove these two sub-register indexes shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160831 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 23:03:08 +00:00
Jakob Stoklund Olesen
4db2dbf921 Eliminate sub_ss, sub_sd from broadcast patterns. 
The (COPY_TO_REGCLASS GR32:$src, VR128) pattern looks odd, but
copyPhysReg does the right thing with it. (The old pattern would
eventually produce the same cross-class copy).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160830 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 22:59:06 +00:00
Jakob Stoklund Olesen
79ad138a33 Eliminate more sub_ss / sub_sd patterns. 
This gets rid of some more INSERT_SUBREG - IMPLICIT_DEF patterns,
simplifying the emitted code a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160820 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 22:30:18 +00:00
Jakob Stoklund Olesen
0cf3c93c99 Eliminate some SUBREG_TO_REG patterns with sub_ss and sub_sd. 
The SUBREG_TO_REG instruction has magic semantics asserting that the
source value was defined by an instruction that cleared the high half of
the register. Those semantics are never actually exploited for xmm
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160818 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 22:03:21 +00:00
Jakob Stoklund Olesen
369a4c7759 Eliminate a batch of uses of sub_ss and sub_sd in the X86 target. 
These idempotent sub-register indices don't do anything --- They simply
map XMM registers to themselves.  They no longer affect register classes
either since the SubRegClasses field has been removed from Target.td.

This patch replaces XMM->XMM EXTRACT_SUBREG and INSERT_SUBREG patterns
with COPY_TO_REGCLASS patterns which simply become COPY instructions.

The number of IMPLICIT_DEF instructions before register allocation is
reduced, and that is the cause of the test case changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160816 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 21:40:42 +00:00
Craig Topper
7f76cb6666 Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 07:48:28 +00:00
Nadav Rotem
fd34c110cf The vbroadcast family of instructions has 'fallback patterns' in case where the 
load source operand is used by multiple nodes. The v2i64 broadcast was emulated
by shuffling the two lower i32 elements to the upper two.
We had a bug in the immediate used for the broadcast.
Replacing 0 to 0x44.
0x44 means [01|00|01|00] which corresponds to the correct lane.

Patch by Michael Kuperstein.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160430 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-18 08:14:48 +00:00
Craig Topper
75dc33a60b Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-18 04:11:12 +00:00
Nadav Rotem
aec9f382dd Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention. 
Allow the folding of vbroadcastRR to vbroadcastRM, where the memory operand is a spill slot.

PR12782.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160230 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-15 12:26:30 +00:00
Craig Topper
836c99db9b Mark VINSERTI128rm as MayLoad=1. Fixes PR13348. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160162 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-13 05:46:28 +00:00
Craig Topper
5aba78bd80 Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-12 06:52:41 +00:00
Craig Topper
97a0c6bc91 Reverse assembler/disassembler operand order for gather instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-10 06:38:33 +00:00
Craig Topper
1e59c78ab7 Remove extra space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159647 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-03 06:48:58 +00:00
Craig Topper
f2c1cf2f98 Change i128mem/i256mem to f128mem/f256mem on some floating point vector instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159646 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-03 06:11:06 +00:00
Craig Topper
a101014026 Add aliases for pblendvb, blendvpd, and blendvps instructions with the implicit xmm0 operand specified. Fixes PR13252. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159644 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-03 05:49:45 +00:00
Elena Demikhovsky
8f40f7b867 Optimization of shuffle node that can fit to the register form of VBROADCAST instruction on AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159504 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-01 06:12:26 +00:00
Manman Ren
40307c7dbe X86: add more GATHER intrinsics in LLVM 
Corrected type for index of llvm.x86.avx2.gather.d.pd.256
  from 256-bit to 128-bit.
Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256
  from 256-bit to 128-bit.

Support the following intrinsics:
  llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q
  llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256
  llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d
  llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-29 00:54:20 +00:00
Manman Ren
1f7a1b68a0 X86: add GATHER intrinsics (AVX2) in LLVM 
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256

Modified Disassembler to handle VSIB addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-26 19:47:59 +00:00
Craig Topper
952caee4f6 Remove some duplicate instructions that exist only to given different mnemonics for the assembler. Use InstAlias instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159184 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-26 04:12:49 +00:00
Craig Topper
fd1753bedb Add SSE2 predicate to CVTPS2PD instructions. Doesn't matter much because there are no patterns in the instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159127 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-25 06:51:42 +00:00
Craig Topper
13d89c7976 Remove codegen only instruction in favor of one that has the same definition. Make some pattern operands more explicit about types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159126 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-25 06:16:00 +00:00
Craig Topper
e7f702fc2d Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 07:07:16 +00:00
Craig Topper
2123b18247 Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159108 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 06:55:37 +00:00
Craig Topper
081f931077 Fix build failures from r159106. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159107 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 06:08:31 +00:00
Craig Topper
66a69fa729 Remove intrinsic specific instructions for CVTPD2PS and replace with just patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159106 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 05:44:31 +00:00
Craig Topper
7f2ea14c68 Remove intrinsic specific instructions for CVTPD2DQ. Replace with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159105 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 05:33:24 +00:00
Craig Topper
c82b9a51a2 Remove intrinsic specific instructions for (V)CVTDQ2PS. Use a Pat instead instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159090 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 22:33:14 +00:00
Craig Topper
624a9c49d4 Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional change because there are no patterns in the instructions. Also fix a typo in a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 20:52:45 +00:00
Craig Topper
6fc218e3a1 Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and PD2DQ to the SSE2 section of the file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 20:15:42 +00:00
Craig Topper
fc76b8691e Use correct memory types for (V)CVTDQ2PD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159075 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 08:30:27 +00:00
Craig Topper
eea4a9b1e6 Remove intrinsic specific instructions for 128-bit (V)CVTDQ2PD. Replace with intrinsic patterns. Mem forms omitted because the load size is only 64-bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159070 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 04:23:36 +00:00
Craig Topper
65d36f0367 Add predicate check around some patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158797 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-20 07:30:23 +00:00
Craig Topper
af4166cd09 Add predicate check around some patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158795 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-20 07:01:11 +00:00
Kay Tiong Khoo
19e5015e5f *no need to pollute Intel syntax with bonus mnemonics; operand size is explicitly specified 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158603 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-16 17:19:49 +00:00
Craig Topper
3949b8382d Mark several instructions SSE2 instead of SSE3 as they should be. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 06:45:27 +00:00
Benjamin Kramer
c8e340da82 X86: Rename the CLMUL target feature to PCLMUL. 
It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157745 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 14:34:17 +00:00
Craig Topper
0559a2f8ae Add intrinsic for pclmulqdq instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157731 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 04:37:40 +00:00
Benjamin Kramer
1386e9b7b1 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-29 19:05:25 +00:00
Craig Topper
189bce48c7 Remove 256-bit AVX non-temporal store intrinsics. Similar was previously done for 128-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156375 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-08 06:58:15 +00:00
Craig Topper
ef2b8bda02 Fix some issues in the f16c instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156287 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:00:15 +00:00
Craig Topper
5f9cccc509 Add SSE4A MOVNTSS/MOVNTSD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156281 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:36:19 +00:00
Nadav Rotem
7bc9698f3a AVX: Add additional vbroadcast replacement sequences for integers. 
Remove the v2f64 patterns because it does not match any vbroadcast
instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155461 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 18:09:59 +00:00
Nadav Rotem
d1a79136e3 AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructions 
using the pattern (vbroadcast (i32load src)). In some cases, after we generate
this pattern new users are added to the load node, which prevent the selection
of the blend pattern. This commit provides fallback patterns which perform
in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155437 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 11:07:03 +00:00
Elena Demikhovsky
1da5867236 ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155309 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-22 09:39:03 +00:00
Craig Topper
ffa6c40ecf Replace vpermd/vpermps intrinic patterns with custom lowering to target specific nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154801 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 07:13:00 +00:00
Craig Topper
7e9f7fbc11 Flip the arguments when converting vpermd/vpermps intrinsics into instructions. The intrinsic has the mask as the last operand, but the instruction has it as the second. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154797 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 06:26:15 +00:00
Craig Topper
8325c11d47 Merge vpermps/vpermd and vpermpd/vpermq SD nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154782 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 00:41:45 +00:00
Craig Topper
2cb1e9dc7d Remove AVX2 vpermq and vpermpd intrinsics. These can now be handled with normal shuffle vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154778 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 22:43:31 +00:00
Nadav Rotem
f16af0a053 Fix PR12529. The Vxx family of instructions are only supported by AVX. 
Use non-vex instructions for SSE4.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154770 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 19:36:44 +00:00
Elena Demikhovsky
73c504af9d Added VPERM optimization for AVX2 shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 11:18:59 +00:00
Craig Topper
bf596c9c61 Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are integer instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154580 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 07:23:00 +00:00
Nadav Rotem
e611378a6e Reapply 154396 after fixing a test. 
Original message:
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendV uses a register for the selection while Vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154483 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 06:40:27 +00:00
Eric Christopher
a139051654 Temporarily revert this patch to see if it brings the buildbots back. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154425 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 19:33:16 +00:00
Nadav Rotem
50e64cfe6e Modify the code that lowers shuffles to blends from using blendvXX to vblendXX. 
blendv uses a register for the selection while vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154396 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 14:33:13 +00:00
Craig Topper
b45c969959 Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove patterns for selecting the intrinsic. Similar was already done for avx1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154272 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-07 22:32:29 +00:00
Craig Topper
f16ffb1259 Move vinsertf128 patterns near the instruction definitions. Add AddedComplexity to AVX2 vextracti128 patterns to give them priority over the integer versions of vextractf128 patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154268 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-07 21:57:43 +00:00
Craig Topper
769bbfd951 Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 05:20:24 +00:00