Michael J. Spencer
d955cf2366
llvm-objdump: Add tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 17:13:05 +00:00
Hal Finkel
3bca0b9d6e
use FileCheck and not grep in new tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 16:01:41 +00:00
Nadav Rotem
39c14efd6d
Clean the triple, add check lines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 07:07:51 +00:00
Nadav Rotem
ee6fd6a2b2
Previously v2i32 vectors were legalized to v4i32. Now, they are legalized to
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v2i64. These tests do not check MMX nor zmoving into them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 06:59:01 +00:00
Hal Finkel
87525be07a
Test case for CanLowerReturn fix (r141981)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 04:03:59 +00:00
Hal Finkel
b31d3d271f
Add PPC 440 scheduler and some associated tests (new files)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 04:03:55 +00:00
Chandler Carruth
602650c988
Add a routine to swap branch instruction operands, and update any
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profile metadata at the same time. Use it to preserve metadata attached
to a branch when re-writing it in InstCombine.
Add metadata to the canonicalize_branch InstCombine test, and check that
it is tranformed correctly.
Reviewed by Nick Lewycky!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 01:11:57 +00:00
Nadav Rotem
f6481aee43
Add tripple and stabalize a few more tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 21:20:54 +00:00
Nadav Rotem
acb10f1519
Add triple to tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 20:53:20 +00:00
Nadav Rotem
9eee96a598
fix a typo in the test
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 20:43:41 +00:00
Nadav Rotem
8fb06b3e8f
Enable element promotion type legalization by deafault.
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Changed tests which assumed that vectors are legalized by widening them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 20:31:33 +00:00
Nick Lewycky
c4a90c5271
Oops! Fix testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 20:20:15 +00:00
Nick Lewycky
36c7e6c36c
When looking for dependencies on the src pointer, scan the src pointer. Scanning
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on the memcpy call will pull up other unrelated stuff. Fixes PR11142.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 20:13:32 +00:00
Nadav Rotem
ea6578b72a
Remove the the test which checks the saving of a vector of booleans into memory.
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The decision was to pack the bits. Currently no codegen supports this.
Currently, all of the bits in the vector are saved into the same address
in memory.
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2011-10-16 19:06:06 +00:00
Craig Topper
ee62e4f6d1
Add X86 PEXTR and PDEP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
Nadav Rotem
c32a8c9073
Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
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no pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 10:02:06 +00:00
Craig Topper
b53fa8bf19
Add X86 BZHI instruction as well as BMI2 feature detection.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:55:05 +00:00
Craig Topper
dc479c4a89
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:05:40 +00:00
Chris Lattner
d8b7aa2613
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
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the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 04:47:35 +00:00
Craig Topper
17730847d5
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 03:51:13 +00:00
NAKAMURA Takumi
40a4360186
test/Makefile: Inspect $(PROJ_OBJ_ROOT)/tools/clang/Makefile instead of $(PROJ_SRC_ROOT)/tools/clang for "check-all".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 02:54:14 +00:00
Craig Topper
566f233ba6
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 20:46:47 +00:00
Nico Weber
e688f8896b
Let this test pass even if 'int' is somewhere in its directory path.
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On my machine, grep matched:
; ModuleID = '/Volumes/MacintoshHD2/src/chrome-git/src/third_party/llvm/test/Linker/2011-08-18-unique-debug-type.ll'
!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
Explicitly filter out the ModuleID line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142077 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 18:07:16 +00:00
Andrew Trick
365c9f1ff5
Fix SCEVExpander assert during LSR: "argument of incompatible type".
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Just because we're dealing with a GEP doesn't mean we can assert the
SCEV has a pointer type. The fix is simply to ignore the SCEV pointer
type, which we really didn't need.
Fixes PR11138 webkit crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 06:19:55 +00:00
Eli Friedman
46995fa7e2
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 23:58:49 +00:00
Owen Anderson
008c838434
Update test for disabling of code/data marker labels in ELF.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 21:12:55 +00:00
Torok Edwin
ff616cb440
OCaml bindings: add some missing functions and testcases.
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The C bindings exposed some APIs that weren't covered by the OCaml bindings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 20:38:33 +00:00
Torok Edwin
2c4ae181c4
OCaml bindings: fix infinite recursion on string_of_lltype
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 20:38:14 +00:00
Jakob Stoklund Olesen
ac7caa0d43
Update live-in lists when splitting critical edges.
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Fixes PR10814. Patch by Jan Sjödin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 17:25:46 +00:00
Craig Topper
54a11176f6
Add X86 ANDN instruction. Including instruction selection.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 07:06:56 +00:00
Craig Topper
909652f687
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 03:21:46 +00:00
Jakob Stoklund Olesen
a80444f88d
Add value numbers when spilling dead defs.
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When spilling around an instruction with a dead def, remember to add a
value number for the def.
The missing value number wouldn't normally create problems since there
would be an incoming live range as well. However, due to another bug
we could spill a dead V_SET0 instruction which doesn't read any values.
The missing value number caused an empty live range to be created which
is dangerous since it doesn't interfere with anything.
This fixes part of PR11125.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 00:34:31 +00:00
Michael J. Spencer
63b2f8c710
ELF: Fix the section that relocations apply to. Add test to verify. Patch by Danil Malyshev!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 22:30:10 +00:00
Michael J. Spencer
942eb00911
llvm-object: Add inline relocation information to disassembly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 22:17:18 +00:00
Andrew Trick
48ba0e45ed
Reapply r141870, SCEV expansion of post-inc.
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Speculatively reapply to see if this test case still crashes on
linux. I may have fixed it in my last checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 21:55:29 +00:00
Andrew Trick
753e02ad5d
Revert r141870. The test case crashes on linux with data corruption. A deeper issue was exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 17:58:24 +00:00
Andrew Trick
b00175913a
LSR: Reuse the post-inc expansion of expressions.
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This avoids unnecessary expansion of expressions and allows the SCEV
expander to work on expression DAGs, not just trees.
Fixes PR11090.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 17:31:47 +00:00
Benjamin Kramer
d38e99e949
Force CPU type on test so it doesn't accidentally emit movbe instead of bswap on Intel Atom CPUs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 14:27:54 +00:00
Kalle Raiskila
898f336c51
Mark 'branch indirect' instruction as an indirect branch.
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Not having it confused assembly printing of jumptables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 11:40:03 +00:00
Bill Wendling
4e68054b20
More closely follow libgcc, which has code after the `ret' instruction to
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release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 08:24:19 +00:00
Bill Wendling
1203fe7fc8
Revert r141854 because it was causing failures:
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http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:48:07 +00:00
Bill Wendling
82222c20be
Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:42:32 +00:00
Craig Topper
8ab1d1e900
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:09:14 +00:00
Jakob Stoklund Olesen
dee83c90bb
Also inflate register classes around inline asm.
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Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.
This fixes PR11078.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 23:37:40 +00:00
Bill Wendling
f6fb7ed53c
We need to verify that the machine instruction we're using as a replacement for
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our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>
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2011-10-12 23:03:40 +00:00
Lang Hames
68df750a4f
Removed colons from some target datalayout strings in test, since they don't match the required format.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 22:24:17 +00:00
Kevin Enderby
acbaecd4c8
Finish supporting cpp #file/line comments in assembler for error messages. So
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for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895
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2011-10-12 21:38:39 +00:00
Jim Grosbach
c66e7afcf2
Thumb2 assembly parsing and encoding for LDC/STC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 20:54:17 +00:00
Jim Grosbach
9f45754750
ARM encoding tests for STC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 17:36:13 +00:00
Jim Grosbach
9b8f2a0b36
ARM parsing and encoding for the <option> form of LDC/STC instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 17:34:41 +00:00
Jakob Stoklund Olesen
1c062c24ab
Fix -widen-vmovs liveness issues.
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When widening a copy, we are reading a larger register that may not be
live. Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.
We now widen:
%S6<def> = COPY %S4<kill>, %D3<imp-def>
into:
%D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>
This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.
Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 00:06:23 +00:00
Bob Wilson
b75e5d96dd
Make this test more specific. There are 3 stats that matched "machine-licm".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 23:34:31 +00:00
Eric Christopher
6618a241f7
Add a new wrapper node for a DILexicalBlock that encapsulates it and a
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file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.
This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.
Part of rdar://10246360
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2011-10-11 22:59:11 +00:00
Jim Grosbach
2bd0118472
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
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Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:55:36 +00:00
Bill Wendling
e575499d83
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:40:47 +00:00
Cameron Zwarich
c055a8782e
Fix PR11106 by correcting a typo that has been in the code for over a year. This
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would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:26:40 +00:00
Jim Grosbach
fbab2206cf
Update test for r141704.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 20:18:50 +00:00
Devang Patel
2e35047947
Add dominance check for the instruction being hoisted.
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For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 18:09:58 +00:00
Nadav Rotem
6fe4e51547
Add support for legalization of vector SHL/SRA/SRL instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 14:36:35 +00:00
Nick Lewycky
b1b8f5f7cd
Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take
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that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.
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2011-10-11 06:58:11 +00:00
Craig Topper
a6f386b4cd
Test case for X86 LZCNT instruction selection.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141652 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 06:47:01 +00:00
Craig Topper
37f2167f15
Add X86 LZCNT instruction. Including instruction selection support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 06:44:02 +00:00
Cameron Zwarich
66b20c4db6
Add a test for PR10565.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 06:10:37 +00:00
Cameron Zwarich
446d95224b
Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's
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lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141646 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 06:10:30 +00:00
Bill Wendling
3606f75f35
Test simplification that Ana Pazos noticed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 04:43:15 +00:00
Craig Topper
29480fd798
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 04:34:23 +00:00
Nick Lewycky
7aabcb1fc0
Also create a shndx even if there are no symbols. This lets us test
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.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 03:54:50 +00:00
NAKAMURA Takumi
b1044b042f
test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak win32 hosts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141640 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 03:41:03 +00:00
Andrew Trick
204494149b
Move replaceCongruentIVs into SCEVExapander and bias toward "expanded"
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IVs.
Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 02:28:51 +00:00
Akira Hatanaka
b58078be33
Test cases for 64-bit load and store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 01:52:31 +00:00
Lang Hames
eafc8192d1
Added a testcase for r141599, rdar://problem/10063881.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141628 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 01:32:10 +00:00
Bill Wendling
26e8ca34fe
Add testcase for PR11107.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141607 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:26:57 +00:00
Devang Patel
db7334dbc5
Revert r141569 and r141576.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 23:18:02 +00:00
Bill Wendling
ef2c86f876
Reapply r141365 now that PR11107 is fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:59:55 +00:00
Eli Friedman
dca62d53b7
Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:28:47 +00:00
Nick Lewycky
023bb15bea
Add support for dumping section headers to llvm-objdump. This uses the same
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flags as binutils objdump but the output is different, not just in format but
also showing different sections. Compare its results against readelf, not
objdump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 21:21:34 +00:00
Devang Patel
6b50bc9d88
If loop header is also loop exiting block then it may not be safe to hoist instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 20:32:03 +00:00
Nadav Rotem
a7934dd8e4
Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
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instruction set has no 64-bit SRA support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 19:31:45 +00:00
Devang Patel
9ac743a4ee
Add dominance check for the instruction being hoisted.
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For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 19:09:20 +00:00
Benjamin Kramer
a86a58695d
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:34:56 +00:00
Jakob Stoklund Olesen
a0ed0c0fcd
Insert dummy ED table entries for pseudo-instructions.
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The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:30:16 +00:00
Bill Wendling
eba564ceac
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
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hang, and possibly SPEC/CINT2006/464_h264ref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:27:30 +00:00
Benjamin Kramer
5d53ff54c0
XFAIL tblgen tests on leak checkers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141533 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 13:09:59 +00:00
Bill Wendling
8129d21396
When getting the number of bits necessary for addressing mode
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ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 07:24:23 +00:00
Craig Topper
da394041c4
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen
ed74482704
Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
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In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.
TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.
This fixes PR11088.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141499 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 18:28:28 +00:00
Jakob Stoklund Olesen
a55f6575ae
Add missing test case for r141410.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 18:06:54 +00:00
Andrew Trick
861a410cb6
Unit test for LSR phi reuse in r141442.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141472 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 02:34:51 +00:00
Michael J. Spencer
27781b78e1
llvm-objdump: Add relocation and archive support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 00:18:30 +00:00
Jim Grosbach
051fee0312
Enable ARM mode VDUP(scalar) tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:57:03 +00:00
Jim Grosbach
460a90540b
ARM NEON assembly parsing and encoding for VDUP(scalar).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:56:00 +00:00
David Greene
a1b1b79be1
Remove Multidefs
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Multidefs are a bit unwieldy and incomplete. Remove them in favor of
another mechanism, probably for loops.
Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 18:25:05 +00:00
Evan Cheng
7c1780c5fe
High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 17:21:44 +00:00
Bob Wilson
6d2f9cec71
Reenable tail calls for iOS 5.0 and later.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 17:17:49 +00:00
Bob Wilson
2fef4573df
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 16:59:21 +00:00
Anton Korobeynikov
244455e6d6
Peephole optimization for ABS on ARM.
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Patch by Ana Pazos!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 16:15:08 +00:00
Duncan Sands
3f329cb781
Teach GVN to also propagate switch cases. For example, in this code
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switch (n) {
case 27:
do_something(x);
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}
the call do_something(x) will be replaced with do_something(27). In
gcc-as-one-big-file this results in the removal of about 500 lines of
bitcode (about 0.02%), so has about 1/10 of the effect of propagating
branch conditions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 08:29:06 +00:00
Craig Topper
75fe5f3bab
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
Craig Topper
1b526a98e3
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:53:50 +00:00
Craig Topper
25f6dfd108
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:35:38 +00:00
Jim Grosbach
bee5d2fac8
Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 22:04:05 +00:00
Jim Grosbach
7abb795635
Fix and clean up tests. Un-XFAIL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 21:32:50 +00:00
Jim Grosbach
d6f85098e1
Fix and clean up tests. Un-XFAIL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 21:28:30 +00:00
David Greene
2f0722c105
Make Test More Thorough
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Check that all ADD patters are processed.
Add a SUB test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 21:20:44 +00:00
Peter Collingbourne
5d5c0624d0
s/tblgen/llvm-tblgen/g in a few missed places, including the tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141294 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 13:39:59 +00:00
Torok Edwin
624c5edcd4
ocaml bindings: add llvm_ipo based on IPO.h
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141284 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 12:12:27 +00:00
Torok Edwin
0e68e90175
add more tests for the OCaml bindings
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 12:12:12 +00:00
Craig Topper
7ea16b01fa
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 06:44:41 +00:00
Cameron Zwarich
d78ebe1e12
Remove a check from ARM shifted operand isel helper methods, which were blocking
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merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 23:38:50 +00:00
David Greene
fd56d75396
Update Test for Multidefs
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Update the MultiPat.td test to create some defs via multidefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 22:42:48 +00:00
David Greene
e5d5cdf2e9
Add a Multidef Test
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Add a simple test for multidefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 22:42:47 +00:00
Eli Friedman
792860883e
PR11061: Make simplifylibcalls fold strcmp("", x) correctly.
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While I'm here, fix the related issue with strncmp, add some actual tests for strcmp and strncmp, and start using StringRef::compare for constant folding instead of using strcmp/strncmp so that the optimized IR isn't dependent on the host's implementation of strcmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141227 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 22:27:16 +00:00
Jim Grosbach
e2999b4899
Revert 141203. InstCombine is looping on unit tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141209 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 20:44:29 +00:00
Rafael Espindola
11f1a8335e
Check for the returns_twice attribute in callsFunctionThatReturnsTwice. This
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fixes PR11038, but there are still some cleanups to be done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 20:05:13 +00:00
Jim Grosbach
30c1ff234d
Update InstCombine worklist after instruction transform is complete.
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When updating the worklist for InstCombine, the Add/AddUsersToWorklist
functions may access the instruction(s) being added, for debug output for
example. If the instructions aren't yet added to the basic block, this
can result in a crash. Finish the instruction transformation before
adjusting the worklist instead.
rdar://10238555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 20:05:00 +00:00
Dan Gohman
da5836572d
Make this test less sensitive to codegen optimizations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141195 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 18:13:08 +00:00
Owen Anderson
2dbb46a0a0
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 17:16:40 +00:00
Duncan Sands
02b5e72ac6
GVN does simple propagation of conditions: when it sees a conditional
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branch "br i1 %x, label %if_true, label %if_false" then it replaces
"%x" with "true" in places only reachable via the %if_true arm, and
with "false" in places only reachable via the %if_false arm. Except
that actually it doesn't: if value numbering shows that %y is equal
to %x then, yes, %y will be turned into true/false in this way, but
any occurrences of %x itself are not transformed. Fix this. What's
more, it's often the case that %x is an equality comparison such as
"%x = icmp eq %A, 0", in which case every occurrence of %A that is
only reachable via the %if_true arm can be replaced with 0. Implement
this and a few other variations on this theme. This reduces the number
of lines of LLVM IR in "GCC as one big file" by 0.2%. It has a bigger
impact on Ada code, typically reducing the number of lines of bitcode
by around 0.4% by removing repeated compiler generated checks. Passes
the LLVM nightly testsuite and the Ada ACATS testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 14:28:49 +00:00
Duncan Sands
452c58f4c4
Generalize GVN's conditional propagation logic slightly:
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it's OK for the false/true destination to have multiple
predecessors as long as the extra ones are dominated by
the branch destination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 14:17:01 +00:00
Andrew Trick
0c388583fb
Missing test case for r141164.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141166 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 06:23:32 +00:00
Owen Anderson
2fec6c5ff1
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 23:26:17 +00:00
Jim Grosbach
0ebefdf834
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 21:43:51 +00:00
Jim Grosbach
fdf6bb41a4
Un-XFAIL file. Comment out individual failing instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 21:16:42 +00:00
Jim Grosbach
20f8eb2fc1
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:52:57 +00:00
Jim Grosbach
e5c933848a
Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:50:05 +00:00
Jim Grosbach
dc6c93531d
Un-XFAIL file. Fix incorrect CHECK line. General format cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:46:49 +00:00
Jim Grosbach
100902c6da
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:42:35 +00:00
Jim Grosbach
0c0cf47ed5
Un-XFAIL file. Fix incorrect CHECK line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:42:09 +00:00
Jim Grosbach
62ea269b9a
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:34:11 +00:00
David Greene
764b29e1c8
Test Operand Arguments
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Add a test to do list manipulation and pass the result as arguments.
This tests the new list element operator resolve code and provides an
example of using list manipulation to do instruction pattern
substitution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 18:55:40 +00:00
Jim Grosbach
a02dfe7a6b
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 18:43:15 +00:00
Jim Grosbach
36db6fbe57
Tidy up. Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 17:49:45 +00:00
David Dean
8a567f1fb9
Fix PR9833/PR11054 (patch provided by Patrik Hägglund)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 16:26:41 +00:00
Craig Topper
6744a17dcf
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 06:30:42 +00:00
Andrew Trick
f143b79b78
LSR should avoid redundant edge splitting.
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This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 03:50:44 +00:00
Andrew Trick
d974ea22a5
Unit test for r140919, loop unroll heuristics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 00:07:02 +00:00
Jim Grosbach
3207e6c6b7
Tidy up. These tests are covered in the .s file tests now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 23:40:13 +00:00
Jim Grosbach
9d39036f62
ARM assembly parsing and encoding for VMOV immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 23:38:36 +00:00
Jim Grosbach
68259145d9
ARM parsing/encoding for VCMP/VCMPE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 22:30:24 +00:00
Akira Hatanaka
bbb47b320d
Move CHECK after entry label.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:24:30 +00:00
Akira Hatanaka
43e43f7d8b
Add support for 64-bit logical NOR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:23:18 +00:00
Akira Hatanaka
2d57088ff0
Add support for 64-bit count leading ones and zeros instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:16:50 +00:00
Jim Grosbach
5cd5ac6ad4
ARM assembly parsing and encoding for VMRS/FMSTAT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:12:43 +00:00
Akira Hatanaka
dda4a07cd8
Add support for 64-bit divide instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:06:13 +00:00
Jim Grosbach
f8bf43ec99
Update test for 141010.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 20:58:08 +00:00
Akira Hatanaka
04d3762ff1
Add support for 64-bit integer multiply instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 20:01:11 +00:00
Jim Grosbach
c82c101147
Tidy up a bit. Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 17:59:31 +00:00
Craig Topper
581fe82c84
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 17:28:23 +00:00
Rafael Espindola
25456ef74c
Add the returns_twice attribute to LLVM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 14:45:37 +00:00
Craig Topper
04c5be9f12
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 08:14:29 +00:00
Craig Topper
04b0b34b3a
Test updates that were supposed to go with r140993.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 07:53:59 +00:00
Nick Lewycky
1cbae18cf6
Reapply r140979 with fix! We never did get a testcase, but careful review of the
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logic by David Meyer revealed this bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 07:10:45 +00:00
Torok Edwin
48488a64fa
attempt to fix ocaml bindings: landing pads
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140991 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 06:41:46 +00:00
Nick Lewycky
4fcc80a486
Revert r140979 due to reports of bootstrap failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 05:14:59 +00:00
Nick Lewycky
8fde4f5842
Add one more case we compute a max trip count.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140979 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 01:03:57 +00:00
Craig Topper
82f131a017
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 21:08:12 +00:00
Craig Topper
146c6d77f0
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 16:56:09 +00:00
Nick Lewycky
11357d4f40
Add a new icmp+select optz'n. Also shows off the load(cst) folding added in
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r140966.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 10:37:37 +00:00
Craig Topper
846a2dcada
Fix disassembling of INVEPT and INVVPID to take operands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 21:20:14 +00:00
Craig Topper
e1b4a1a07e
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 19:54:56 +00:00
Bill Wendling
0676d2a04c
Filecheck-ize.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 23:40:29 +00:00
Bill Wendling
127f410c3a
Add new line at end of file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 23:21:11 +00:00
Bill Wendling
e09b2a0d49
When inferring the pointer alignment, if the global doesn't have an initializer
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and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.
For instance, in file A.c:
struct S s;
In file B.c:
struct {
// something long
};
extern S s;
void foo() {
struct S p = s;
// ...
}
this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 23:19:55 +00:00
David Greene
90b6e346ee
Test More Complicated Lists
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Test of indexing lists of lists of lists works. This also exercises
some operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 20:59:52 +00:00
David Greene
f6c8cbba4e
Test VarListElementInit:: resolveListElementReference
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Add a TableGen test to check if indexing lists of lists works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140883 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 20:59:51 +00:00
Akira Hatanaka
5773fd52ef
Remove unnecessary checking of register operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 19:18:24 +00:00
Akira Hatanaka
c7bafe9241
Add definitions of Mips64 rotate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 18:51:46 +00:00
Jim Grosbach
cbf676b3ba
float comparison to double 'zero' constant can just be a float 'zero.'
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InstCombine was incorrectly considering the conversion of the constant
zero to be unsafe.
We want to transform:
define float @bar(float %x) nounwind readnone optsize ssp {
%conv = fpext float %x to double
%cmp = fcmp olt double %conv, 0.000000e+00
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
Into:
define float @bar(float %x) nounwind readnone optsize ssp {
%cmp = fcmp olt float %x, 0.000000e+00 ; <---- This
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
rdar://10215914
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 18:45:50 +00:00
Jim Grosbach
6f09fcf5da
ARM Darwin default relocation model is PIC.
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This matches clang, so default options in llc and friends are now closer to
clang's defaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 17:41:35 +00:00
Akira Hatanaka
d80c13bfed
Check values of immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140860 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 17:19:21 +00:00
Duncan Sands
5bc93e782e
Add forgotten tests that the cleanup flag is cleared if there
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is a catch-all landingpad clause.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 17:00:34 +00:00
Duncan Sands
0ad7b6e773
Inlining often produces landingpad instructions with repeated
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catch or repeated filter clauses. Teach instcombine a bunch
of tricks for simplifying landingpad clauses. Currently the
code only recognizes the GNU C++ and Ada personality functions,
but that doesn't stop it doing a bunch of "generic" transforms
which are hopefully fine for any real-world personality function.
If these "generic" transforms turn out not to be generic, they
can always be conditioned on the personality function. Probably
someone should add the ObjC++ personality function. I didn't as
I don't know anything about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 13:12:16 +00:00
Akira Hatanaka
25a7d94e81
Mips64 shift instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 03:18:46 +00:00
Akira Hatanaka
f549ab7853
Mips64 arithmetic and logical instructions with one source register and
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immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140839 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 02:08:54 +00:00
Akira Hatanaka
a3defb07a0
Fill delay slot with useful instructions. Modified from Sparc's version of delay
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slot filler.
Patch by Reed Kotler at Mips Technologies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 23:52:13 +00:00
Dan Gohman
27e0666725
When eliminating unnecessary retain+autorelease on return values,
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handle the case where the retain is in a different basic block.
rdar://10210274.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140815 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 22:27:34 +00:00
Dan Gohman
597fece886
Don't eliminate objc_retainBlock calls on stack objects if the
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objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 22:25:23 +00:00
Akira Hatanaka
c0be26909f
Mips64 arithmetic and logical instructions with two source registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140806 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 20:37:56 +00:00
Andrew Trick
0c01bc385a
LSR: rewrite inner loops only.
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Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140762 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 01:33:38 +00:00
Andrew Trick
03b08764d2
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140761 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 01:31:48 +00:00
Justin Holewinski
d57c1bc0b6
PTX: Add new patterns for bitconvert and any_extend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140753 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 01:13:12 +00:00
Evan Cheng
9b88d2d782
Tighten a ARM dag combine condition to avoid an identity transformation, which
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ends up introducing a cycle in the DAG.
rdar://10196296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 23:16:31 +00:00
Eli Friedman
7d3e2b78c7
PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 21:00:25 +00:00
Justin Holewinski
d8e4ed2686
PTX: MC-ize the PTX back-end (patch 1 of N)
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Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140697 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:32:04 +00:00
James Molloy
acad68da50
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
Andrew Trick
52164eaddc
Test case for r140670: indvars should hoist sext.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140671 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 02:13:32 +00:00
Eli Friedman
e6fadced87
PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 00:34:27 +00:00
Jakob Stoklund Olesen
df4b35e3dd
Remove X86-dependent stuff from SSEDomainFix.
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This also enables domain swizzling for AVX code which required a few
trivial test changes.
The pass will be moved to lib/CodeGen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140659 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 23:50:46 +00:00
Jim Grosbach
25ddc2bf7e
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
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Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 22:18:54 +00:00
NAKAMURA Takumi
5bac1146d9
test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 21:54:50 +00:00
Benjamin Kramer
a9390a4d5f
Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit.
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If someone prefers %tmp42 to %42, run instnamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 20:39:19 +00:00
Michael J. Spencer
9142ae2cf8
Add binary archive support to llvm-nm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 19:37:18 +00:00
Michael J. Spencer
98d0416fbf
Unbreak tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140622 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 19:06:37 +00:00
Justin Holewinski
13e0c805a2
PTX: Add support for sitofp in backend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 01:04:47 +00:00
Bill Wendling
d5520987d1
Split the landing pad basic block with the correct function. Also merge the
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split landingpad instructions into a PHI node.
PR11016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 00:59:31 +00:00
Eli Friedman
139e6699c4
Last batch of test conversions to new atomic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 00:17:29 +00:00
Eli Friedman
184944acdf
Convert a bunch more tests over to the new atomic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 23:15:09 +00:00
Owen Anderson
21733e8f80
Fix an incorrect decoder test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 23:08:34 +00:00
Owen Anderson
256e10f964
Remove incorrect testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140572 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 22:13:55 +00:00
Eli Friedman
47d3ee559a
Convert more tests to new atomic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 21:36:10 +00:00