Francois Pichet
1f121e844f
Unbreak MSVC build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 16:28:07 +00:00
Jakob Stoklund Olesen
01faf432d9
Teach PPCInstrInfo to handle sub-classes.
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This has already been done for most other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141083 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 15:28:47 +00:00
Che-Liang Chiou
f987425657
tblgen: add preprocessor as a separate mode
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This patch adds a preprocessor that can expand nested for-loops for
saving some copy-n-paste in *.td files.
The preprocessor is not yet integrated with TGParser, and so it has
no direct effect on *.td inputs. However, you may preprocess an td
input (and only preprocess it).
To test the proprecessor, type:
tblgen -E -o $@ $<
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141079 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 15:14:51 +00:00
Nadav Rotem
34804c4f47
Set operation actions to legal types only.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141075 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 12:05:35 +00:00
Nadav Rotem
e8783096d2
Operations should be custom lowered only if their type is legal.
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Test: CellSPU/v2i32.ll when running with -promote-elements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 10:03:32 +00:00
Nick Lewycky
e97728ecf8
The product of two chrec's can always be represented as a chrec.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141066 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 06:51:26 +00:00
Craig Topper
6744a17dcf
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 06:30:42 +00:00
Andrew Trick
f143b79b78
LSR should avoid redundant edge splitting.
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This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 03:50:44 +00:00
Andrew Trick
2aeb8027d6
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 03:34:49 +00:00
Rafael Espindola
b3c4e26dc5
Remove last references to hotpatch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 03:08:43 +00:00
Bill Wendling
da7e6a9c88
Generic cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 00:16:40 +00:00
Jim Grosbach
9d39036f62
ARM assembly parsing and encoding for VMOV immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 23:38:36 +00:00
Jim Grosbach
2a3f19d7e3
Tidy up. 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141043 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 23:03:26 +00:00
Bill Wendling
ff4216a68a
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 22:44:15 +00:00
Bill Wendling
f8520d564c
Don't carry over the dispatchsetup hack from the old system.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 22:42:40 +00:00
Jim Grosbach
68259145d9
ARM parsing/encoding for VCMP/VCMPE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 22:30:24 +00:00
Nick Lewycky
03dd4e8bd3
Fix typo in comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:30:08 +00:00
Bill Wendling
f7e4aefd0f
Check-pointing the new SjLj EH lowering.
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This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:25:38 +00:00
Akira Hatanaka
43e43f7d8b
Add support for 64-bit logical NOR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:23:18 +00:00
Akira Hatanaka
2d57088ff0
Add support for 64-bit count leading ones and zeros instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:16:50 +00:00
Bill Wendling
631d11765b
Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:15:28 +00:00
Jim Grosbach
5cd5ac6ad4
ARM assembly parsing and encoding for VMRS/FMSTAT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:12:43 +00:00
Akira Hatanaka
dda4a07cd8
Add support for 64-bit divide instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:06:13 +00:00
Devang Patel
0e6a24d92a
Add C api for Instruction->eraseFromParent().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 20:59:18 +00:00
Jim Grosbach
b95ed6ec46
Thumb2 ADD/SUB can take SP as a destination register.
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It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 20:51:59 +00:00
Akira Hatanaka
2ad766851d
Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer
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registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 20:38:08 +00:00
Akira Hatanaka
04d3762ff1
Add support for 64-bit integer multiply instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 20:01:11 +00:00
Akira Hatanaka
36787939b2
Add definitions of instructions which move values between 64-bit integer
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registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 19:28:44 +00:00
Craig Topper
581fe82c84
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 17:28:23 +00:00
Eric Christopher
8cf5e74a9c
Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 15:49:20 +00:00
Eric Christopher
1aeb7ac624
Typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 15:49:16 +00:00
Rafael Espindola
25456ef74c
Add the returns_twice attribute to LLVM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 14:45:37 +00:00
Craig Topper
04c5be9f12
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 08:14:29 +00:00
Craig Topper
7b22976de3
Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 07:51:09 +00:00
Nick Lewycky
1cbae18cf6
Reapply r140979 with fix! We never did get a testcase, but careful review of the
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logic by David Meyer revealed this bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 07:10:45 +00:00
Nick Lewycky
4fcc80a486
Revert r140979 due to reports of bootstrap failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 05:14:59 +00:00
Nick Lewycky
8fde4f5842
Add one more case we compute a max trip count.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140979 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 01:03:57 +00:00
Craig Topper
82f131a017
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 21:08:12 +00:00
Craig Topper
146c6d77f0
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 16:56:09 +00:00
Nick Lewycky
11357d4f40
Add a new icmp+select optz'n. Also shows off the load(cst) folding added in
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r140966.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 10:37:37 +00:00
Nick Lewycky
267236ade3
Enhance a couple places where we were doing constant folding of instructions,
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but not load instructions. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 09:12:55 +00:00
Craig Topper
846a2dcada
Fix disassembling of INVEPT and INVVPID to take operands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 21:20:14 +00:00
Craig Topper
e1b4a1a07e
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 19:54:56 +00:00
Chad Rosier
2bfaf521ae
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
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to appease nightly testers. Not quite there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 19:30:36 +00:00
Nadav Rotem
cbf26e3b57
Moved type construction out of the loop and added an assert on the legality of the type. Formatted lines to the 80 char limit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 18:39:28 +00:00
Peter Collingbourne
7c78888887
Move TableGen's parser and entry point into a library
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This is the first step towards splitting LLVM and Clang's tblgen executables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 16:41:13 +00:00
Bill Wendling
2e6b97bbf8
No one should be using the method directly. Assert if they do.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 12:47:34 +00:00
Bill Wendling
405ca137a1
Add a convenience method to tell if two things are equal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 12:44:28 +00:00
Bill Wendling
3320f2a3bf
Use the ARMConstantPoolMBB class to handle the MBB values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140943 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 09:30:42 +00:00
Bill Wendling
9c18f51daa
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140942 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 09:19:10 +00:00
Bill Wendling
14a1a6b018
Remove dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140941 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 09:05:12 +00:00
Bill Wendling
9aca75c4f8
Remove now dead methods and ivar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 09:04:18 +00:00
Bill Wendling
fe31e67350
Use the new ARMConstantPoolSymbol class to handle external symbols.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 08:58:29 +00:00
Bill Wendling
ff4a8023ec
Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 08:36:59 +00:00
Bill Wendling
3f4e4592c3
Remove now dead methods and ivar from ARMConstantPoolValue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 08:02:05 +00:00
Bill Wendling
5bb779976a
Switch over to using ARMConstantPoolConstant for global variables, functions,
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and block addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 08:00:54 +00:00
Bill Wendling
3e944e38ea
Some more refactoring.
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* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 07:52:37 +00:00
Bill Wendling
029e93888d
Add a Create method that accepts 'kind' and 'pcadj' arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140934 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 06:44:24 +00:00
Bill Wendling
f2b76aae2b
Refactoring: Separate out the ARM constant pool Constant from the ARM constant
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pool value.
It's not used right now, but will be soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140933 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 06:40:33 +00:00
Chad Rosier
5249041125
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
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useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140924 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 02:03:18 +00:00
Andrew Trick
b2ab2fa524
Inlining and unrolling heuristics should be aware of free truncs.
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We want heuristics to be based on accurate data, but more importantly
we don't want llvm to behave randomly. A benign trunc inserted by an
upstream pass should not cause a wild swings in optimization
level. See PR11034. It's a general problem with threshold-based
heuristics, but we can make it less bad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140919 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 01:39:05 +00:00
Andrew Trick
5c655413cf
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 01:27:56 +00:00
Michael J. Spencer
0bcd9c70b1
Add Windows x64 stack walking support. Patch by Aaron Ballman!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 00:05:20 +00:00
Bill Wendling
e09b2a0d49
When inferring the pointer alignment, if the global doesn't have an initializer
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and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.
For instance, in file A.c:
struct S s;
In file B.c:
struct {
// something long
};
extern S s;
void foo() {
struct S p = s;
// ...
}
this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 23:19:55 +00:00
Nick Lewycky
8de34006cf
Promote comment to doxycomment. Adjust whitespace. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140899 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 22:19:53 +00:00
Jakob Stoklund Olesen
c8e2bb68bb
Store sub-class lists as a bit vector.
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This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 22:19:07 +00:00
Jakob Stoklund Olesen
e27e1ca3c9
Move getCommonSubClass() into TRI.
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It will soon need the context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 22:18:51 +00:00
Jim Grosbach
f391e9f696
Correct for my over-eager delete finger.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 22:02:45 +00:00
Akira Hatanaka
291512f96f
Add definition of MipsELFObjectWriter.
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Patch by Reed Kotler at Mips Technologies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 21:55:40 +00:00
Akira Hatanaka
09a2e0f794
Register the MC object streamer.
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Patch by Reed Kotler at Mips Technologies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 21:29:38 +00:00
Akira Hatanaka
4b6ee7a352
Register Asm backend. Add functions to MipsAsmBackend.
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Patch by Reed Kotler at Mips Technologies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 21:23:45 +00:00
Akira Hatanaka
82ea7314ca
Add MCELFObjectTargetWriter and MCAsmBackend classes.
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Patch by Reed Kotler at Mips Technologies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 21:04:02 +00:00
Benjamin Kramer
310c9ea874
Update CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140879 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 20:44:33 +00:00
Akira Hatanaka
4520a10fdb
Initial implementation of MipsMCCodeEmitter.
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Patch by Reed Kotler at Mips Technologies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140878 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 20:40:03 +00:00
Jim Grosbach
68e05fb368
Don't modify constant in-place.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 19:58:46 +00:00
Andrew Trick
62e0590c0e
Tracing or debug-printing a newly formed instruction should not crash.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 19:50:40 +00:00
Andrew Trick
18801ecd48
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 19:48:58 +00:00
Akira Hatanaka
c7bafe9241
Add definitions of Mips64 rotate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 18:51:46 +00:00
Jim Grosbach
cbf676b3ba
float comparison to double 'zero' constant can just be a float 'zero.'
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InstCombine was incorrectly considering the conversion of the constant
zero to be unsafe.
We want to transform:
define float @bar(float %x) nounwind readnone optsize ssp {
%conv = fpext float %x to double
%cmp = fcmp olt double %conv, 0.000000e+00
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
Into:
define float @bar(float %x) nounwind readnone optsize ssp {
%cmp = fcmp olt float %x, 0.000000e+00 ; <---- This
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
rdar://10215914
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 18:45:50 +00:00
Bill Wendling
d98f838284
Constify 'isLSDA' and move a method out-of-line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 18:42:06 +00:00
Jim Grosbach
0cc4a958f3
Tidy up. Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 18:09:53 +00:00
Jim Grosbach
6f09fcf5da
ARM Darwin default relocation model is PIC.
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This matches clang, so default options in llc and friends are now closer to
clang's defaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 17:41:35 +00:00
Akira Hatanaka
a64556ffda
isCommutable should be 0 for DSUBu.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 17:26:36 +00:00
Jim Grosbach
98602ac9a9
ARM Fixup valus for movt/movw are for the whole value.
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Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 17:23:05 +00:00
Jakob Stoklund Olesen
7850dd0f25
Fix a bug in compare_numeric().
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Thanks to Alexandru Dura and Jonas Paulsson for finding it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 17:03:55 +00:00
Danil Malyshev
0ba3c0ab63
MCJIT initialization TargetData
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 16:40:10 +00:00
Justin Holewinski
f51b7e5d74
PTX: Various stylistic and code readability changes recommended by Jim Grosbach.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140855 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 14:36:36 +00:00
Justin Holewinski
8c1dac54f2
PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs.
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Also take this opportunity to clean up the rounding mode pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 13:46:52 +00:00
Duncan Sands
0ad7b6e773
Inlining often produces landingpad instructions with repeated
...
catch or repeated filter clauses. Teach instcombine a bunch
of tricks for simplifying landingpad clauses. Currently the
code only recognizes the GNU C++ and Ada personality functions,
but that doesn't stop it doing a bunch of "generic" transforms
which are hopefully fine for any real-world personality function.
If these "generic" transforms turn out not to be generic, they
can always be conditioned on the personality function. Probably
someone should add the ObjC++ personality function. I didn't as
I don't know anything about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 13:12:16 +00:00
Torok Edwin
d398bae0e0
Comment grammar fixes.
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thanks to Duncan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 13:07:47 +00:00
Justin Holewinski
c90e149ee4
PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires
...
us to manually provide Pat<> definitions for all FP instruction patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 12:54:43 +00:00
Torok Edwin
10a11ecb59
Instead of crashing when MCAsmInfo is NULL, add an assert.
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This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location,
and if you include the old one by accident you will trigger this assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140848 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 12:31:57 +00:00
Akira Hatanaka
25a7d94e81
Mips64 shift instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 03:18:46 +00:00
Akira Hatanaka
f549ab7853
Mips64 arithmetic and logical instructions with one source register and
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immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140839 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 02:08:54 +00:00
Jim Grosbach
4ebbf7b8a8
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
...
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 00:50:06 +00:00
Akira Hatanaka
a3defb07a0
Fill delay slot with useful instructions. Modified from Sparc's version of delay
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slot filler.
Patch by Reed Kotler at Mips Technologies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 23:52:13 +00:00
Bill Wendling
e00897c5a9
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140824 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 23:50:42 +00:00
Bill Wendling
4dd9b091cc
Support creating a constant pool value for a machine basic block.
...
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140823 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 23:48:44 +00:00
Nick Lewycky
48105286cb
Fold two identical set lookups into one. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 23:40:12 +00:00
Dan Gohman
27e0666725
When eliminating unnecessary retain+autorelease on return values,
...
handle the case where the retain is in a different basic block.
rdar://10210274.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140815 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 22:27:34 +00:00
Dan Gohman
597fece886
Don't eliminate objc_retainBlock calls on stack objects if the
...
objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 22:25:23 +00:00
Akira Hatanaka
c0be26909f
Mips64 arithmetic and logical instructions with two source registers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140806 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 20:37:56 +00:00
Eli Friedman
bb5a7442e3
Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 20:21:17 +00:00
Devang Patel
7a50202be5
Cosmetic changes, as per Nick's review.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140785 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 16:46:47 +00:00
Duncan Sands
9a7d48ae67
Place this bracket according to the LLVM style.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140784 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 16:01:46 +00:00
Justin Holewinski
2097d702d4
PTX: Fix broken shared library build
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140783 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 14:25:48 +00:00
Jakob Stoklund Olesen
92fb79b7a6
Expand the x86 V_SET0* pseudos right after register allocation.
...
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 05:10:54 +00:00
NAKAMURA Takumi
13f4a6c940
Target/ARM: Unbreak! CMake! Build!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140774 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 03:32:49 +00:00
Jakob Stoklund Olesen
adcb634d85
Delete NEONMoveFix, now unused.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140773 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 02:56:45 +00:00
Jakob Stoklund Olesen
8bb3d3cb30
Use ExecutionDepsFix instead of NEONMoveFix.
...
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140772 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 02:48:41 +00:00
Andrew Trick
5219f86a0b
typo + pasto
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140769 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 01:53:08 +00:00
Jakob Stoklund Olesen
cc84cda919
Remove NumImplicitOps which is now unused.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 01:47:36 +00:00
Andrew Trick
0c01bc385a
LSR: rewrite inner loops only.
...
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140762 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 01:33:38 +00:00
Bill Wendling
3511cedf36
Move to ISelLowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140754 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 01:13:55 +00:00
Justin Holewinski
d57c1bc0b6
PTX: Add new patterns for bitconvert and any_extend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140753 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 01:13:12 +00:00
Eric Christopher
12eb3ad5d6
Use the local we already set up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140745 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 00:50:59 +00:00
Jakob Stoklund Olesen
3627a46293
Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.
...
The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.
This also fixes a bug when adding operands after an implicit operand has
been added manually. The NumImplicitOps count wasn't kept up to date.
MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added. It is possible to change an MI opcode and add additional
explicit operands. They will be inserted before any existing implicit
operands.
The only exception is inline asm instructions where operands are never
reordered. This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29 00:40:51 +00:00
Jakob Stoklund Olesen
5cd4ee7770
Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
...
It broke the unit tests. Please reapply with tests fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 23:59:28 +00:00
Evan Cheng
9b88d2d782
Tighten a ARM dag combine condition to avoid an identity transformation, which
...
ends up introducing a cycle in the DAG.
rdar://10196296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 23:16:31 +00:00
Akira Hatanaka
d42ca4607b
Define classes for unary and binary FP instructions and use them to define
...
multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 21:58:01 +00:00
Bill Wendling
cc8cf97be4
Have the SjLjEHPrepare pass do some more heavy lifting.
...
Upon further review, most of the EH code should remain written at the IR
level. The part which breaks SSA form is the dispatch table, so that part will
be moved to the back-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140730 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 21:56:53 +00:00
Eli Friedman
7d3e2b78c7
PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 21:00:25 +00:00
Michael J. Spencer
13afc5eff2
Object: Add isSection{Data,BSS}.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 20:57:30 +00:00
Bill Wendling
b18abd077e
Perform the lowering only if there are invokes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 20:29:45 +00:00
Bill Wendling
39689c8154
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 20:29:28 +00:00
Justin Holewinski
cfab2be391
PTX: Fix alignment logic
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 18:24:58 +00:00
Akira Hatanaka
aa7579025f
Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 18:11:19 +00:00
Akira Hatanaka
d9f958375f
Remove definitions of branch-on-FP-likely instructions. They are deprecated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 17:56:55 +00:00
Akira Hatanaka
d2d00edc01
Mips64 predicate definitions. Patch by Liu.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140703 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 17:50:27 +00:00
Andrew Trick
f63ae2159d
indvars: generalize SCEV getPreStartForSignExtend.
...
Handle general Add expressions to avoid leaving around redundant
32-bit IVs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 17:02:54 +00:00
Justin Holewinski
ed0e4c85c4
PTX: MC-ize the PTX backend (patch 2 of N)
...
Get rid of some of the no-longer-needed parts of PTXAsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140698 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:32:06 +00:00
Justin Holewinski
d8e4ed2686
PTX: MC-ize the PTX back-end (patch 1 of N)
...
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140697 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:32:04 +00:00
James Molloy
acad68da50
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
Duncan Sands
42e5c799b6
A typeid of zero means a cleanup, not a catch. This case occurs
...
when there is both a catch and a cleanup. Correct the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140686 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 09:13:02 +00:00
Benjamin Kramer
ca9215970d
PTX: Simplify code. No functionality change.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 04:32:36 +00:00
Benjamin Kramer
8adae0c940
PTX: Pass param name strings per const reference.
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The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140679 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 04:08:02 +00:00
Bill Wendling
adbf7b2c56
Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 03:52:41 +00:00
Bill Wendling
eef108d560
Bitcast the alloca to an i8* to match the intrinsic's signature.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 03:47:11 +00:00
Bill Wendling
6ef94175d1
Create and use an llvm.eh.sjlj.functioncontext intrinsic.
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This intrinsic is used to pass the index of the function context to the back-end
for further processing. The back-end is in charge of filling in the rest of the
entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140676 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 03:36:43 +00:00
Bill Wendling
2b6bd7ba58
In the new EH model, setup the function context and the call site info.
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The DWARF exception pass uses the call site information, which is set up here. A
pre-RA pass is too late for it to use this information. So create and setup the
function context here, and then insert the call site values here (and map the
call sites for the DWARF EH pass). This is simpler than the original pass, and
doesn't make the CFG lose its SSA-ness.
It's a win-win-win-win-lose-win-win situation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 03:14:05 +00:00
Bill Wendling
4b6736bdb0
Don't conditionalize execution of the SjLj EH prepare pass.
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We may need an SjLj EH preparation pass for some call site information, at least
in the short term.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 03:07:34 +00:00
Andrew Trick
909ef7db3d
indvars should hoist [sz]ext because licm is not rerun.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 01:35:36 +00:00
Eli Friedman
e6fadced87
PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 00:34:27 +00:00
Jakob Stoklund Olesen
56ab875e55
Rename class and clean up source.
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No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 00:01:56 +00:00
Jakob Stoklund Olesen
d4d4fca9c3
Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.
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I'll clean up the source in the next commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140663 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 00:01:54 +00:00
Akira Hatanaka
6c6db25c10
Remove MipsFPRound. Mips1 is no longer supported.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 23:55:37 +00:00
Jakob Stoklund Olesen
df4b35e3dd
Remove X86-dependent stuff from SSEDomainFix.
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This also enables domain swizzling for AVX code which required a few
trivial test changes.
The pass will be moved to lib/CodeGen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140659 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 23:50:46 +00:00
Ted Kremenek
833217bfb9
Unbreak CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 23:29:59 +00:00
Jakob Stoklund Olesen
13fd601e0f
Implement TII::get/setExecutionDomain() for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 22:57:21 +00:00
Jakob Stoklund Olesen
98e933f9ad
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.
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I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140652 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 22:57:18 +00:00
Jim Grosbach
25ddc2bf7e
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
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Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 22:18:54 +00:00
Bill Wendling
0481d29d49
This is the start of the new SjLj EH preparation pass, which will replace the
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current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140646 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 22:14:12 +00:00
Akira Hatanaka
8eea4616bf
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
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of the instruction definitions using Pat<>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 22:01:01 +00:00
Cameron Zwarich
d6d9dd647f
Remove an invalid assert that is really just asserting when the scheduler emits
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a suboptimal schedule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140643 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 21:59:16 +00:00
Jim Grosbach
5405d58e21
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
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Naming conventions consistency. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 20:59:33 +00:00
Benjamin Kramer
a9390a4d5f
Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit.
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If someone prefers %tmp42 to %42, run instnamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 20:39:19 +00:00
Chad Rosier
ce496ca9c8
These symbols appear to be visible by SearchForAddressOfSymbol and no longer
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require special case handling.
rdar://10117377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140629 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 20:01:41 +00:00
Michael J. Spencer
a51d7d97b0
Object: Add archive support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 19:36:55 +00:00
Duncan Sands
040bff0bc2
Check that catch clauses have pointer type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 19:34:22 +00:00
Justin Holewinski
332850d8cc
PTX: Fix case where printed alignment could be 0
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140624 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 19:25:49 +00:00
Justin Holewinski
f47dfba023
PTX: Use external symbols to keep track of params and locals. This also fixes
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a couple of outstanding issues with frame objects occuring as instruction
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140616 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 18:12:55 +00:00
Jakob Stoklund Olesen
8e695eb5fa
Use existing function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140615 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 17:55:08 +00:00
Akira Hatanaka
237e7a278a
Fix function MipsRegisterInfo::getRegisterNumbering.
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Return numbers of 64-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140609 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 17:15:27 +00:00
Akira Hatanaka
78fec58c07
Do not add the pass that restores $gp if target is Mips64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140607 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 16:58:43 +00:00
Duncan Sands
00418ea91c
Have the verifier check that all landingpad operands are constants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 16:43:19 +00:00
Nadav Rotem
a3c42f3d4e
Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.
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Add a new method: getAnyExtOrTrunc and use it to replace the manual check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140603 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 11:16:47 +00:00
Nadav Rotem
a1c415cfc2
Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,
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while the decision is to bit-pack small values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140601 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 10:48:29 +00:00
Akira Hatanaka
854222fa47
Mark MipsPseudo isPseudo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140598 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 04:57:54 +00:00
Justin Holewinski
13e0c805a2
PTX: Add support for sitofp in backend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 01:04:47 +00:00
Bill Wendling
d5520987d1
Split the landing pad basic block with the correct function. Also merge the
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split landingpad instructions into a PHI node.
PR11016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 00:59:31 +00:00
Andrew Trick
80ef1b287f
Disable LSR retry by default.
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Disabling aggressive LSR saves compilation time, and with the new
indvars behavior usually improves performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 00:44:14 +00:00
Andrew Trick
25b689e067
LSR, one of the new Cost::isLoser() checks did not get merged in the previous checkin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 23:35:25 +00:00
Owen Anderson
2dafe200ca
Remove extraneous commit garbage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140581 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 23:14:02 +00:00
Andrew Trick
7d11bd850f
LSR cost metric minor fix and verification.
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The minor bug heuristic was noticed by inspection. I added the
isLoser/isValid helpers because they will become more
important with subsequent checkins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140580 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 23:11:04 +00:00
Akira Hatanaka
f40de9d287
Set register class of a register according to value of HasMips64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140570 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 21:55:17 +00:00
Akira Hatanaka
8b4198da9d
Define variable HasMips64 in MipsTargetLowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 21:47:02 +00:00
Akira Hatanaka
09dd60feef
In single float mode, double precision FP arguments are passed in integer
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registers, so there is no need to check here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 21:37:50 +00:00
Owen Anderson
0afa0094af
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 21:06:22 +00:00
Eli Friedman
46cb5afdcd
Enhance alias analysis for atomic instructions a bit. Upgrade a couple alias-analysis tests to the new atomic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 20:15:28 +00:00
Justin Holewinski
22d54da918
PTX: Fix memcpy intrinsic to handle 64-bit pointers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140556 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 19:19:48 +00:00
Justin Holewinski
bc97f4402b
PTX: Implement PTXSelectionDAGInfo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140549 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 18:57:27 +00:00
Justin Holewinski
63bce90c0d
PTX: Implement ISD::ANY_EXTEND
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140548 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 18:57:24 +00:00
Justin Holewinski
63602ed876
PTX: Fix detection of stack load/store vs. global load/store, as well as fix the
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printing of local offsets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 18:57:22 +00:00
James Molloy
439780eeae
Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140539 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 17:40:42 +00:00
Justin Holewinski
22f3c59ec3
PTX: SM > 2.0 implies +double
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 16:20:36 +00:00
Justin Holewinski
58788503b8
PTX: Fix some lingering issues with stack allocation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140535 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 16:20:34 +00:00
Justin Holewinski
d5c3920f8d
PTX: Split up the TableGen instruction definitions into logical units
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 16:20:31 +00:00
Justin Holewinski
c1d8fbd41a
PTX: Unify handling of loads/stores
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140533 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 16:20:28 +00:00
Justin Holewinski
6b8990df42
PTX: Handle FrameIndex nodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 16:20:25 +00:00
David Meyer
8f418b11d2
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 06:13:20 +00:00
Craig Topper
100d86ada5
Fix VEX decoding in i386 mode. Fixes PR11008.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 05:12:43 +00:00
Jakob Stoklund Olesen
c291e2f578
Add target hook for pseudo instruction expansion.
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Many targets use pseudo instructions to help register allocation. Like
the COPY instruction, these pseudos can be expanded after register
allocation. The early expansion can make life easier for PEI and the
post-ra scheduler.
This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-25 19:21:35 +00:00
Nadav Rotem
0eba4fe292
[vector-select] Address one of the issues in pr10902. EXTRACT_VECTOR_ELEMENT
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SDNodes may return values which are wider than the incoming element types. In
this patch we fix the integer promotion of these nodes.
Fixes spill-q.ll when running -promote-elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-25 18:59:42 +00:00
Jakob Stoklund Olesen
74e2d6ea66
Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.
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No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-25 16:46:08 +00:00
Jakob Stoklund Olesen
fb96574fca
Rename LowerSubregs to ExpandPostRAPseudos.
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I'll fix the file contents in the next commit.
This pass is currently expanding the COPY and SUBREG_TO_REG pseudos. I
am going to add a hook so targets can expand more pseudo-instructions
after register allocation.
Many targets have pseudo-instructions that assist the register
allocator. They can be expanded after register allocation, before PEI
and PostRA scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140469 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-25 16:46:00 +00:00
Benjamin Kramer
dd16400033
Sort CMakeLists.txt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140465 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-24 22:06:35 +00:00
Nadav Rotem
17e76bda55
Implement Duncan's suggestion to use the result of getSetCCResultType if it is legal
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(this is always the case for scalars), otherwise use the promoted result type.
Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140464 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-24 19:48:19 +00:00
Nadav Rotem
0d5357e3d5
[Vector-Select] Address one of the problems in 10902.
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When generating the trunc-store of i1's, we need to use the vector type and not
the scalar type.
This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when
running with -promote-elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140463 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-24 18:32:19 +00:00
Akira Hatanaka
8aa4b4cb6f
Add .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-24 01:40:18 +00:00
Akira Hatanaka
95934844e3
Preparation for adding simple Mips64 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-24 01:34:44 +00:00
Jakob Stoklund Olesen
51f0c76419
Only run MF.verify() with EXPENSIVE_CHECKS=1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-24 01:11:19 +00:00
Daniel Dunbar
bb0a6126cf
sys::Process: Add a SetWorkingDirectory method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 23:23:36 +00:00
Andrew Trick
b5b7c96ce4
LSR minor bug fix in RateRegister.
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No test case. Noticed by inspection and I doubt it ever affects the
outcome of the overall heuristic, let alone final codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 23:05:19 +00:00
Jakob Stoklund Olesen
5adc07ebe8
Verify that terminators follow non-terminators.
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This exposes a -segmented-stacks bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140429 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 22:45:39 +00:00
Eli Friedman
bde81d5be9
PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140428 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 22:41:57 +00:00
Owen Anderson
4d2a00147d
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 22:25:02 +00:00
Jakob Stoklund Olesen
11ebe3d7c1
Also match negative offsets for addrmode3 and addrmode5.
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Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140425 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 22:10:33 +00:00
Owen Anderson
4a713570b6
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:57:50 +00:00
Owen Anderson
0781c1f700
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:26:40 +00:00
Owen Anderson
31d485ec9a
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:07:25 +00:00
Owen Anderson
df0caeb6ec
Revert r140412. This affects more instructions than intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:02:01 +00:00
Owen Anderson
d256056581
Thumb2 register-shifted-register loads cannot target the PC or the SP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:00:32 +00:00
Akira Hatanaka
45b73e2f3f
Implement N32/64 calling convention. Patch by Liu.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140401 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 19:08:15 +00:00
Akira Hatanaka
792016bc22
Make FGR64RegisterClass available if target is Mips64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 18:28:39 +00:00
Akira Hatanaka
b1dcff0fe3
Add definitions of 64-bit register files. Add code for returning Mips64's sets of
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callee-saved registers and reserved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140395 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 18:11:56 +00:00
Justin Holewinski
a5745569b6
PTX: Fix parameter order bug
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140394 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 17:59:11 +00:00
Wesley Peck
2e3441e5e5
Fix a couple of 80 column violations.
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patch contributed by Jia Liu!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 17:24:41 +00:00
Justin Holewinski
dc0baf9b40
PTX: Cleanup unused code in PTXMachineFunctionInfo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140390 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 17:15:53 +00:00
Justin Holewinski
d7070fe6df
PTX: Fix another 80-column violation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140387 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 16:50:35 +00:00
Justin Holewinski
75d809599b
PTX: Handle function call return values
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140386 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 16:48:41 +00:00
Richard Osborne
0353dab90e
Fix 80 column violations.
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Original patch by Liu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140385 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 16:28:10 +00:00
Duncan Sands
04aa4aee89
Implement Chris's suggestion of legalizing the various SSE and AVX
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hadd/hsub intrinsics into the new fhadd/fhsub X86 node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 16:10:22 +00:00
Justin Holewinski
e953a64cb5
PTX: Start fixing function calls
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 14:31:12 +00:00
Justin Holewinski
d3dec06447
PTX: Remove PTX calling convention files
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 14:18:27 +00:00
Justin Holewinski
1cde87d202
[PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columns
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From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
lib/Target/PTX/PTXInstrInfo.td | 165 ++++++++++++++++++++----------
lib/Target/PTX/PTXIntrinsicInstrInfo.td | 88 +++++++++++------
2 files changed, 167 insertions(+), 86 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 14:18:24 +00:00
Justin Holewinski
27f08fc619
PTX: Generalize handling of .param types
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 14:18:22 +00:00
Justin Holewinski
04b5ebc74c
PTX: Cleanup unused code in the PTXMFInfoExtract pass
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140374 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 14:18:19 +00:00
Duncan Sands
4c19e12d28
Tweak the handling of MERGE_VALUES nodes: remove the need for
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DecomposeMERGE_VALUES to "know" that results are legalized in
a particular order, by passing it the number of the result
being legalized (the type legalization core provides this, it
just needs to be passed on).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140373 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 13:59:22 +00:00
Nadav Rotem
c56d65f63c
Vector-Select: Address one of the problems in pr10902. Add handling for the
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integer-promotion of CONCAT_VECTORS.
Test: test/CodeGen/X86/widen_shuffle-1.ll
This patch fixes the above tests (when running in with -promote-elements).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 09:33:24 +00:00
Akira Hatanaka
aaa9fc2e37
Add definitions of 64-bit int registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140366 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 02:33:15 +00:00
Akira Hatanaka
373e3a4091
Do not rely on the enum values of argument registers A0-A3 being consecutive.
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Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140363 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 00:58:33 +00:00
Eli Friedman
7666c7e4d2
PR10989: Don't print .hidden on Windows.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 00:13:02 +00:00
Eli Friedman
a6176adc8a
PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140355 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 23:41:28 +00:00
Akira Hatanaka
40eda4626d
Make changes in instruction and pattern definitions so that tablegen does not
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complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 23:31:54 +00:00
Owen Anderson
db01cdd06b
Add new files to CMake.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140352 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 23:20:48 +00:00
Dan Gohman
7b316c9327
Fix SimplifySelectCC to add newly created nodes to the DAGCombiner
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worklist, as it may be possible to perform further optimization on them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140349 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 23:01:29 +00:00
Jakob Stoklund Olesen
4bd89873be
Add support for GR32 <-> FR32 cross class copies.
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We already support GR64 <-> VR128 copies. All of these copies break
partial register dependencies by zeroing the high part of the target
register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 22:45:24 +00:00
Benjamin Kramer
da7d6ccef5
Update CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 22:38:34 +00:00
Owen Anderson
124e182103
Start stubbing out MCModule and MCAtom, which provide an API for accessing the rich disassembly of a complete object or executable.
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These are very much a work in progress, and not really useful yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 22:32:22 +00:00
Jakob Stoklund Olesen
08f5cdf5b3
Constrain register classes instead of emitting copies.
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Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR. Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.
Normally, these copies are handled by the coalescer. This saves some
coalescer work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 21:39:34 +00:00
Jakob Stoklund Olesen
91fb536a34
Add a MinNumRegs argument to MRI::constrainRegClass().
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The function will refuse to use a register class with fewer registers
than MinNumRegs. This can be used by clients to avoid accidentally
increase register pressure too much.
The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 21:39:31 +00:00
Duncan Sands
17470bee5f
Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from
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floating point add/sub of appropriate shuffle vectors. Does not
synthesize the 256 bit AVX versions because they work differently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 20:15:48 +00:00
Eli Friedman
d102a03b36
PR10987: add a missed safety check to isSafePHIToSpeculate in scalarrepl.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140327 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 18:56:30 +00:00
Akira Hatanaka
98f49c4413
Print parentheses in next line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140325 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 18:29:29 +00:00
Akira Hatanaka
ebb90dbb54
Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 18:24:21 +00:00
Akira Hatanaka
95a091a0b6
Define a new sub-register index sub_32 for accessing the 32-bit sub-register of
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a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140319 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 17:57:32 +00:00
Bill Wendling
711395527e
Use the C personality function instead of the C++ personality function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 17:56:40 +00:00
Akira Hatanaka
26bcc701a2
Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or
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VK_Mips_GPOFF_LO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 17:44:37 +00:00
Akira Hatanaka
d27fda49c4
Add F31 to the set of callee-saved registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140315 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 17:35:03 +00:00
Akira Hatanaka
4e41416359
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 17:26:58 +00:00
Justin Holewinski
7c9dd62441
PTX: Remove physical register defs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140310 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 16:45:48 +00:00
Justin Holewinski
5422a0f166
PTX: Use .param space for device function return values on SM 2.0+, and attempt
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to fix up parameter passing on SM < 2.0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140309 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 16:45:46 +00:00
Justin Holewinski
05591be5ed
PTX: Fix style issues
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140308 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 16:45:43 +00:00
Justin Holewinski
297984d7c6
PTX: Fixup codegen to handle emission of virtual registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140307 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 16:45:40 +00:00
Justin Holewinski
40466cc758
PTX: Customize codegen passes in backend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140306 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 16:45:37 +00:00
Justin Holewinski
247ee00bce
PTX: Add new PTX-specific register allocator that keeps virtual registers
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instead of allocating physical registers.
This is part of a work-in-progress overhaul of the PTX register allocation scheme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140305 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 16:45:33 +00:00
Craig Topper
adf01b3f18
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 07:01:50 +00:00
Akira Hatanaka
bb7d289aeb
Add definition of 64-bit floating registers used for Mips64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140297 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 03:48:47 +00:00
Benjamin Kramer
2c2ccbf108
The SSE version differences for fmin/fmax are more involved than I thought.
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- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140296 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 03:27:22 +00:00
Akira Hatanaka
e33ca9ce1f
Add enums and functions for symbols Mips64 uses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 03:09:07 +00:00
Benjamin Kramer
74f3501d15
X86: Don't form min/max nodes if the target is missing SSE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140294 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 03:01:42 +00:00
Akira Hatanaka
459cad2dfd
Mips64 aligns stack on 16-byte boundary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 02:53:37 +00:00
Akira Hatanaka
c56f5ea4c3
Remove unnecessary condition check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140291 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 02:41:29 +00:00
Owen Anderson
6126870193
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 23:53:44 +00:00
Owen Anderson
e136872970
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 23:44:46 +00:00
Devang Patel
1dd4e56d55
Do not unnecessarily use AT_specification DIE because it does not add any value.
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Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140282 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 23:41:11 +00:00
Galina Kistanova
ef01f32d07
Fix for DbgInfoPrinter.cpp:174:12: warning: ‘LineNo’ may be used uninitialized in this function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 23:34:23 +00:00
Bill Wendling
cccfd194ec
The last verification check for the new EH model.
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This makes sure that the unwind destination of an invoke is a landing pad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140280 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 22:57:02 +00:00
Bill Wendling
3ca2ad1156
Attempt to update the shadow stack GC pass to the new EH model.
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This inserts a cleanup landingpad instruction and a resume to mimic the old
unwind instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140277 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 22:14:28 +00:00
Benjamin Kramer
15c9a1f60c
X86Disassembler: if verbose logging is going to nulls(), disable logging completely.
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Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140276 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 21:47:35 +00:00
Jim Grosbach
fe59d853c6
Tidy up. Whitepsace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140275 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 21:36:53 +00:00
Wesley Peck
91b60c1487
Fix some simple copy-paste errors in MBlaze ASM Parser and Makefile.
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patch contributed by Jia Liu!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140273 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 19:23:46 +00:00
Owen Anderson
519020adf1
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 17:58:45 +00:00
Akira Hatanaka
0e64f810a5
Undo a change made in r140254.
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MipsArchVersion needs to be initialized to Mips32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140261 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 17:31:45 +00:00
Benjamin Kramer
1d13d9ed96
DWARF: avoid unnecessary map lookups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140260 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 17:31:42 +00:00
Nadav Rotem
64ac73bb15
fix comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 17:14:40 +00:00
Akira Hatanaka
47c40a2cf9
MipsArchVersion does not need to be in the initialization list and MipsABI
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should be initialized to UnknownABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 16:41:43 +00:00
Nadav Rotem
1147248e6f
[VECTOR-SELECT] Address one of the bugs in pr10902.
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Vector SetCC result types need to be type-legalized.
This code worked before because scalar result types are known to be legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140249 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 14:34:38 +00:00
Nadav Rotem
9c6cdf4c1c
Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 08:45:10 +00:00
Richard Trieu
23946fcaae
Change:
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assert(!"error message");
To:
assert(0 && "error message");
which is more consistant across the code base.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 03:09:09 +00:00
Akira Hatanaka
2464810ac2
Add a base class for Mips TargetMachines and add Mips64 TargetMachines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 03:00:58 +00:00
Akira Hatanaka
8c1b4bf066
Set ABI if it hasn't been set on the command line.
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Check if architecture & ABI combination is valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140230 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 02:45:29 +00:00
Akira Hatanaka
50fa74e8d2
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 02:24:25 +00:00
Andrew Trick
3be654f808
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
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This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 02:20:46 +00:00
Andrew Trick
e23dc9c0ef
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140227 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 02:17:37 +00:00
Owen Anderson
317eaf1993
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 00:25:23 +00:00
Akira Hatanaka
5663344127
Change the names of functions isMips* to hasMips*.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140214 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 23:53:09 +00:00
Eli Friedman
79782fc864
Make sure IPSCCP never marks a tracked call as overdefined in SCCPSolver::ResolvedUndefsIn. If we do, we can end up in a situation where a function is resolved to return a constant, but the caller is marked overdefined, which confuses the code later.
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<rdar://problem/9956541> (again).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140210 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 23:28:51 +00:00
Bruno Cardoso Lopes
e97190fdf8
Add a DAGCombine for subvector extracts to remove useless chains of
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subvector inserts and extracts. Initial patch by Rackover, Zvi with
some tweak done by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 23:19:33 +00:00
Bruno Cardoso Lopes
f4b841d4e2
Revert r140097, working on a better approach
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 23:19:29 +00:00
Ivan Krasin
5f2318e065
lib/Linker: add support of deps which does not end with ".so".
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It happens (for example) when you want to have a dependency on the .so
with the specific version, like liblzma.so.1.0.0 or
libcrypto.so.0.9.8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140201 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 22:52:35 +00:00
Bruno Cardoso Lopes
149f29f1fd
Simplify max/minp[s|d] dagcombine matching
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140199 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 22:34:45 +00:00
Bill Wendling
f0dc257a8f
Relax this condition.
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Some passes require breaking critical edges before they're called. Don't
segfault because of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140196 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 22:28:17 +00:00
Bill Wendling
b7e807f9a9
Place the check for an exit landing pad where it will be run on both code paths through the if-then-else.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140195 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 22:27:16 +00:00
Bill Wendling
84b6706d90
Omit extracting a loop if one of the exits is a landing pad.
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The landing pad must accompany the invoke when it's extracted. However, if it
does, then the loop isn't properly extracted. I.e., the resulting extraction has
a loop in it. The extracted function is then extracted, etc. resulting in an
infinite loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 22:23:09 +00:00
Bob Wilson
aabc6a9b79
Remove the hack to check UNAME_RELEASE when identifying the Darwin version.
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This was only needed to locate llvm-gcc's installation directory when clang
falls back to run llvm-gcc for i386 kexts. As of clang svn r140187, we're
now just searching paths with several different Darwin versions on either
side of the current version, so this is no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140188 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 22:05:56 +00:00
Bruno Cardoso Lopes
4e42335972
Tidy up a bit more, fix tab and remove trailing whitespaces
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140186 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 21:45:26 +00:00
Bruno Cardoso Lopes
448d986858
The wrong relocation was being emitted for several SSSE3 instructions.
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This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 21:39:21 +00:00
Bruno Cardoso Lopes
77169a9197
Tidy up code!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 21:39:06 +00:00
Evan Cheng
0d18174f0f
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 21:38:18 +00:00