Commit Graph

405 Commits

Author SHA1 Message Date
Evan Cheng
7b4d31176e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 07:17:46 +00:00
Evan Cheng
11db068721 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:22:01 +00:00
Evan Cheng
ac096808a3 Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 19:30:19 +00:00
Jim Grosbach
6ccfc507dc Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
  mls r0,r9,r0,sp
instead of:
  mov r2, sp
  mls r0, r9, r0, r2

This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.

PR7499




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
Dale Johannesen
f630c712b1 Implement vector constants which are splat of
integers with mov + vdup.  8003375.  This is
currently disabled by default because LICM will
not hoist a VDUP, so it pessimizes the code if
the construct occurs inside a loop (8248029).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 20:10:08 +00:00
Jim Grosbach
f27ca42552 update tests for smarter BIC usage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 16:16:48 +00:00
Jim Grosbach
5423856e44 Add combiner patterns to more effectively utilize the BFI (bitfield insert)
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17 03:30:54 +00:00
Jim Grosbach
469bbdb597 Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 23:05:05 +00:00
Jim Grosbach
502e0aa628 Improve 64-subtraction of immediates when parts of the immediate can fit
in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 17:45:16 +00:00
Bob Wilson
7a52e65ca6 Fix test to appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 16:43:47 +00:00
Bob Wilson
a0148c360e Print "dregpair" NEON operands with a space between them, for readability and
consistency with other instructions that have lists of register operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:47:20 +00:00
Dale Johannesen
7835f1fcdb Changes to ARM tail calls, mostly cosmetic.
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 01:18:23 +00:00
Evan Cheng
c36b5b9730 PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 05:38:36 +00:00
Bob Wilson
8eab75f390 Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:

1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch.  Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).

The change relative to the previous patch is:

@@ -1036,10 +1036,6 @@
     IterIfcvt = false;
   }
 
-  // RemoveExtraEdges won't work if the block has an unanalyzable branch,
-  // which is typically the case for IfConvertSimple, so explicitly remove
-  // CvtBBI as a successor.
-  BBI.BB->removeSuccessor(CvtBBI->BB);
   RemoveExtraEdges(BBI);
 
   // Update block info. BB can be iteratively if-converted.


2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised.  The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond.  I added the following change to check for
that:

@@ -1276,7 +1276,18 @@
   // tail, add a unconditional branch to it.
   if (TailBB) {
     BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
-    if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+    bool CanMergeTail = !TailBBI.HasFallThrough;
+    // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+    // check if there are any other predecessors besides those.
+    unsigned NumPreds = TailBB->pred_size();
+    if (NumPreds > 1)
+      CanMergeTail = false;
+    else if (NumPreds == 1 && CanMergeTail) {
+      MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+      if (*PI != BBI1->BB && *PI != BBI2->BB)
+        CanMergeTail = false;
+    }
+    if (CanMergeTail) {
       MergeBlocks(BBI, TailBBI);
       TailBBI.IsDone = true;
     } else {

With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107110 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 00:55:23 +00:00
Bob Wilson
de4fe23139 Revert my if-conversion cleanup since it caused a bunch of nightly test
regressions.

--- Reverse-merging r106939 into '.':
U    test/CodeGen/Thumb2/thumb2-ifcvt3.ll
U    lib/CodeGen/IfConversion.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 17:47:06 +00:00
Eli Friedman
56df4a079b Remove bogus test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 04:59:56 +00:00
Bob Wilson
ccd9bcca14 Clean up some problems with extra CFG edges being introduced during
if-conversion.  The RemoveExtraEdges function doesn't work for blocks that
end with unanalyzable branches, so in those cases, the "extra" edges must
be explicitly removed.  The CopyAndPredicateBlock and MergeBlocks methods
can also avoid copying successor edges due to branches that have already
been removed.  The latter case is especially helpful when MergeBlocks is
called for handling "diamond" if-conversions, where otherwise you can end
up with some weird intermediate states in the CFG.  Unfortunately I've
been unable to find cases where this cleanup actually makes a significant
difference in the code.  There is one test where we manage to remove an
empty block at the end of a function.  Radar 6911268.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106939 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 04:27:33 +00:00
Bob Wilson
789fef987f PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
form so they can be narrowed to 16-bit instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 16:50:20 +00:00
Dan Gohman
102f3851bb Eliminate the first have of the optimization which eliminates BRCOND
when the condition is constant. This optimization shouldn't be
necessary, because codegen shouldn't be able to find dead control
paths that the IR-level optimizer can't find. And it's undesirable,
because it encourages bugpoint to leave "br i1 false" branches
in its output. And it wasn't updating the CFG.

I updated all the tests I could, but some tests are too reduced
and I wasn't able to meaningfully preserve them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106748 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 15:04:11 +00:00
Evan Cheng
4d54e5b2dd Tail merging pass shall not break up IT blocks. rdar://8115404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 01:18:16 +00:00
Evan Cheng
859df5e9f9 Fix a crash caused by dereference of MBB.end(). rdar://8110842
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-20 00:54:38 +00:00
Evan Cheng
0110ac66eb Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:01:32 +00:00
Evan Cheng
96c3da6436 Move ARM if-conversion before post-ra scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:32:07 +00:00
Evan Cheng
86050dc8cc Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:09:54 +00:00
Jakob Stoklund Olesen
0465bcffbb TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG
instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.

Fix it in LiveVariableAnalysis by adding the <undef> flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 22:29:44 +00:00
Evan Cheng
6a5e2832d0 Fix an inverted condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 22:17:13 +00:00
Dale Johannesen
c66cdf74a9 Enable tail calls on ARM by default, with some
basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 19:00:18 +00:00
Rafael Espindola
1e81966626 Remove arm_apcscc from the test files. It is the default and doing this
matches what llvm-gcc and clang now produce.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 15:18:27 +00:00
Jakob Stoklund Olesen
c66d0f2a93 Allow a register to be redefined multiple times in a basic block.
LiveVariableAnalysis was a bit picky about a register only being redefined once,
but that really isn't necessary.

Here is an example of chained INSERT_SUBREGs that we can handle now:

68      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
                register: %reg1040 +[70,134:0)
76      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
                register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0)  0@78-(134) 1@70-(78)
84      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
                register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0)  0@86-(134) 1@70-(78) 2@78-(86)
92      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
                register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0)  0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94)

rdar://problem/8096390

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106152 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 21:29:40 +00:00
Evan Cheng
46df4eb46e Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 07:35:02 +00:00
Rafael Espindola
2ebb4f81f7 Remove the arm_aapcscc marker from the tests. It is the default
for the linux targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 19:04:29 +00:00
Jakob Stoklund Olesen
40d07bbebb Add CoalescerPair helper class.
Given a copy instruction, CoalescerPair can determine which registers to
coalesce in order to eliminate the copy. It deals with all the subreg fun to
determine a tuple (DstReg, SrcReg, SubIdx) such that:

- SrcReg is a virtual register that will disappear after coalescing.
- DstReg is a virtual or physical register whose live range will be extended.
- SubIdx is 0 when DstReg is a physical register.
- SrcReg can be joined with DstReg:SubIdx.

CoalescerPair::isCoalescable() determines if another copy instruction is
compatible with the same tuple. This fixes some NEON miscompilations where
shuffles are getting coalesced as if they were copies.

The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy
later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 16:04:21 +00:00
Dale Johannesen
73c943fb43 More tail call removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 21:14:24 +00:00
Dale Johannesen
da8dd92c9f Remove tail call. A tail call version will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 00:03:37 +00:00
Dale Johannesen
127e5244a0 Remove tail call to preserve this test. A tail
call version will follow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 21:57:48 +00:00
Dale Johannesen
9452ce30bc Make this test not use tail calls. A tail call
version will follow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 21:53:01 +00:00
Bob Wilson
bb7ecb2bf5 Thumb2 RSBS instructions were being printed without the 'S' suffix.
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:44:06 +00:00
Bob Wilson
be751cfe9c Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:23:12 +00:00
Evan Cheng
9085f98b32 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 07:28:01 +00:00
Jim Grosbach
4b77f6a85a Clean up the conditional for handling of sign_extend_inreg based on
whether the extract instructions are available.

rdar://7956878



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 18:34:55 +00:00
Jim Grosbach
29402132f3 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 23:44:43 +00:00
Jim Grosbach
bc1c98d538 fix copy/paste oops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 21:07:46 +00:00
Jim Grosbach
3a548e717f Add tests for ARMV7M divide instruction use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 20:47:15 +00:00
Dan Gohman
30fc5bbfd1 Fix a bug which prevented tail merging of return instructions in
beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.

The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.

Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.

And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 14:35:47 +00:00
Bob Wilson
5dfa87ecc6 Handle register-to-register copies within the tGPR class.
Radar 7896289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 23:20:08 +00:00
Jim Grosbach
3a1287b470 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
extraction. This fixes PR5998.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 23:24:18 +00:00
Evan Cheng
30fdb5c2ac - Clean up some crappy code which deals with coalescing of copies which look at
extract_subreg / insert_subreg, etc.
- Add support for more aggressive insert_subreg coalescing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 00:44:22 +00:00
Dan Gohman
9f23dee08c Start function numbering at 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101638 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 16:29:15 +00:00
Evan Cheng
3a1588a2e3 Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 22:20:34 +00:00
Evan Cheng
0ea7d219ec ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
llvm is generating poor code for dynamic alloca, I'll fix that later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101383 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 18:42:28 +00:00
Jim Grosbach
7ec7a0e96b switch the flag for using NEON for SP floating point to a subtarget 'feature'.
Re-commit. This time complete with testsuite updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 23:47:34 +00:00
Johnny Chen
9e08876a2a Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-17 17:52:21 +00:00
Bob Wilson
49d9dc4dd2 --- Reverse-merging r98637 into '.':
U    test/CodeGen/ARM/tls2.ll
U    test/CodeGen/ARM/arm-negative-stride.ll
U    test/CodeGen/ARM/2009-10-30.ll
U    test/CodeGen/ARM/globals.ll
U    test/CodeGen/ARM/str_pre-2.ll
U    test/CodeGen/ARM/ldrd.ll
U    test/CodeGen/ARM/2009-10-27-double-align.ll
U    test/CodeGen/Thumb2/thumb2-strb.ll
U    test/CodeGen/Thumb2/ldr-str-imm12.ll
U    test/CodeGen/Thumb2/thumb2-strh.ll
U    test/CodeGen/Thumb2/thumb2-ldr.ll
U    test/CodeGen/Thumb2/thumb2-str_pre.ll
U    test/CodeGen/Thumb2/thumb2-str.ll
U    test/CodeGen/Thumb2/thumb2-ldrh.ll
U    utils/TableGen/TableGen.cpp
U    utils/TableGen/DisassemblerEmitter.cpp
D    utils/TableGen/RISCDisassemblerEmitter.h
D    utils/TableGen/RISCDisassemblerEmitter.cpp
U    Makefile.rules
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/Makefile
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D    lib/Target/ARM/Disassembler
U    lib/Target/ARM/ARMInstrFormats.td
U    lib/Target/ARM/ARMAddressingModes.h
U    lib/Target/ARM/Thumb2ITBlockPass.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 16:59:47 +00:00
Johnny Chen
d30a98e43a Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 16:36:54 +00:00
Bob Wilson
ea7f22c31d Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.
This does not move entirely to UAL syntax, since the default "increment after"
suffix is empty but we still use "IA" for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 16:19:07 +00:00
Bob Wilson
7cfb6d373a Add a testcase for the change in r98586.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98610 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 05:33:29 +00:00
Evan Cheng
fac4f1f181 Enable machine cse pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98132 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 03:07:41 +00:00
Bob Wilson
f5fd499791 Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand.  We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 22:56:15 +00:00
Johnny Chen
267124cff2 Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 22:24:41 +00:00
Jakob Stoklund Olesen
657baec0af Create a stack frame on ARM when
- Function uses all scratch registers AND
- Function does not use any callee saved registers AND
- Stack size is too big to address with immediate offsets.

In this case a register must be scavenged to calculate the address of a stack
object, and the scavenger needs a spare register or emergency spill slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 22:43:17 +00:00
Jim Grosbach
f9a4b7653d LowerCall() should always do getCopyFromReg() to reference the stack pointer.
Machine instruction selection is much happier when operands are in virtual
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 01:43:03 +00:00
Bob Wilson
f1b0a345d3 Last week we were generating code with duplicate induction variables in this
test, but the problem seems to have gone away today.  Add a check to make sure
it doesn't come back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-15 21:56:40 +00:00
Bob Wilson
bf9b221c00 Besides removing phi cycles that reduce to a single value, also remove dead
phi cycles.  Adjust a few tests to keep dead instructions from being optimized
away.  This (together with my previous change for phi cycles) fixes Apple
radar 7627077.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96057 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:31:44 +00:00
Dan Gohman
572645cf84 Reapply the new LoopStrengthReduction code, with compile time and
bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.

This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95975 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 10:34:29 +00:00
Bob Wilson
fe61fb1e10 Add a new pass on machine instructions to optimize away PHI cycles that
reduce down to a single value.  InstCombine already does this transformation
but DAG legalization may introduce new opportunities.  This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized.  I measured the compile time 
impact of this (running llc on 176.gcc) and it was not significant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 01:30:21 +00:00
Jakob Stoklund Olesen
4a540f0593 Reapply coalescer fix for better cross-class coalescing.
This time with fixed test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-11 23:55:29 +00:00
Bob Wilson
e6373eb826 Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.
Radar 7614112.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-06 00:24:38 +00:00
Dan Gohman
7979b72feb Revert LoopStrengthReduce.cpp to pre-r94061 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-22 00:46:49 +00:00
Dan Gohman
a10756ee65 Re-implement the main strength-reduction portion of LoopStrengthReduction.
This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.

It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-21 02:09:26 +00:00
Jakob Stoklund Olesen
35f0febcb6 Remove predicates when changing an add into an unpredicable mov.
Since the mov is executed unconditionally, make sure that the add didn't have
any predicate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93909 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-19 21:08:28 +00:00
Bob Wilson
516ab96de3 Run the pre-register allocation tail duplication pass by default. Remove
the -pre-regalloc-taildup command-line option, and add a new
-disable-early-taildup option.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-16 00:29:50 +00:00
Jakob Stoklund Olesen
d1862037f0 Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-07 00:51:04 +00:00
Jakob Stoklund Olesen
30ac0467ce Add Target hook to duplicate machine instructions.
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-06 23:47:07 +00:00
Dan Gohman
aceba31b7a Delete useless trailing semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05 17:55:26 +00:00
Nick Lewycky
0588bcef8d Make this test pass on Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 07:35:25 +00:00
Anton Korobeynikov
7cca606aaa Dynamic stack realignment use of sp register as source/dest register
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90724 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-06 22:39:50 +00:00
Jim Grosbach
2a37b9c750 test case for IV-Users simplification loop improvement
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90260 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01 21:53:51 +00:00
Evan Cheng
d7f0810c93 Enable predication of NEON instructions in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89748 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-24 08:06:15 +00:00
Jim Grosbach
77b02beb1f move fconst[sd] to UAL. <rdar://7414913>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89700 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23 21:08:25 +00:00
Jim Grosbach
bbf56bb37b update test for 89694
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89695 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23 20:39:53 +00:00
Edward O'Callaghan
18d18b71d5 Miss two, PR5307.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89596 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 15:35:28 +00:00
Edward O'Callaghan
f4a93dd70e Convert Thumb2 tests to FileCheck for PR5307.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89595 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 15:18:27 +00:00
Jim Grosbach
21ce2e3c74 Revert 89562. We're being sneakier than I was giving us credit for, and this
isn't necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89568 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21 23:34:09 +00:00
Jim Grosbach
f3b33d0b2a Darwin requires a frame pointer for all non-leaf functions to support correct
backtraces.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89562 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21 21:40:08 +00:00
Evan Cheng
c26abd9487 Enable hoisting load from constant memories.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89510 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 23:31:34 +00:00
Evan Cheng
4aedb61d03 Remat VLDRD from constpool. Clean up some instruction property specifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 19:57:15 +00:00
Evan Cheng
9b82425cb0 Also CSE non-pic load from constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89440 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 02:10:27 +00:00
Evan Cheng
2ef9c8a43d More consistent thumb1 asm printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-19 06:57:41 +00:00
Evan Cheng
5b397c93a5 Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89326 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-19 06:32:27 +00:00
Jim Grosbach
f04777b945 Enable arm jumpt table adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89143 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 21:24:11 +00:00
Anton Korobeynikov
d2aad77261 Forgot to commit test fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89138 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 20:38:36 +00:00
Jim Grosbach
1187285e90 Convert to FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89007 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 00:20:26 +00:00
Jim Grosbach
727f0c37fb Convert to FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89002 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 00:03:38 +00:00
Jim Grosbach
2c0fb63738 Cleanup. Missed removing these when converting. Oops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89001 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 00:00:33 +00:00
Jim Grosbach
9f07f3b009 Convert to FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88991 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 23:19:29 +00:00
Jim Grosbach
2f74603460 Convert to FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88947 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 20:04:15 +00:00
Jim Grosbach
4adcade9b7 Convert to FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88942 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 19:46:46 +00:00
Jim Grosbach
c0517504e5 tbb opt off by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88921 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 17:24:45 +00:00
Jim Grosbach
a44321776e Detect need for autoalignment of the stack earlier to catch spills more
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-15 21:45:34 +00:00
Jim Grosbach
e11d26b3d8 remove xfail
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88817 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 21:57:35 +00:00
Evan Cheng
0cd22dd738 When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 01:50:00 +00:00
Jim Grosbach
cb2c2b738a Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86997 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 17:19:09 +00:00
Benjamin Kramer
9e3728be62 Fix typo in run line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86984 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 12:35:27 +00:00
Evan Cheng
60f9061820 RegScavenger::enterBasicBlock should always reset register state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86972 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 07:49:10 +00:00
Evan Cheng
586f69a118 - Teach LSR to avoid changing cmp iv stride if it will create an immediate that
cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
  later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
  users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
  iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86969 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 07:35:05 +00:00
Dan Gohman
2210c0bea8 Add support for tail duplication to BranchFolding, and extend
tail merging support to handle more cases.
 - Recognize several cases where tail merging is beneficial even when
   the tail size is smaller than the generic threshold.
 - Make use of MachineInstrDesc::isBarrier to help detect
   non-fallthrough blocks.
 - Check for and avoid disrupting fall-through edges in more cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86871 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 19:48:59 +00:00
Jim Grosbach
3f51147d44 Update test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86614 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 22:59:01 +00:00
Jim Grosbach
e5165490b7 Use Unified Assembly Syntax for the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 00:11:35 +00:00
Evan Cheng
d457e6e9a5 Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 04:04:34 +00:00
Evan Cheng
78e5c1140a - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07 03:52:02 +00:00
Evan Cheng
b9803a8fa6 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 23:52:48 +00:00
Bob Wilson
d51722a7e3 Fix a broken test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86298 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 23:06:42 +00:00
Evan Cheng
ad95ff9fab Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-04 00:42:33 +00:00
Evan Cheng
ba908640b3 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 05:52:54 +00:00
Anton Korobeynikov
7b360e7f29 Temporary xfail until PR5367 will be resolved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85848 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 00:37:36 +00:00
Evan Cheng
7baae87d8f Unbreak ARMBaseRegisterInfo::copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85787 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 04:44:55 +00:00
Evan Cheng
48d8afab73 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85743 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-01 21:12:51 +00:00
Evan Cheng
1107f03ef4 Fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85723 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-01 18:13:29 +00:00
Evan Cheng
de17fb6e4d Use cbz and cbnz instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85698 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 23:46:45 +00:00
Jim Grosbach
8cd0a8cb82 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
them for scalar floating point operations for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 22:57:36 +00:00
Jim Grosbach
1820ec5e7a Consolidate test files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85696 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 22:20:56 +00:00
Jim Grosbach
91c0aebe68 Change to use FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85695 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 22:16:14 +00:00
Jim Grosbach
0e5c9beeed Make tests more explicit about which instructions are expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85694 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 22:14:17 +00:00
Jim Grosbach
6b0b4b3eaf Grammar tweak to comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85693 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 22:12:44 +00:00
Jim Grosbach
199a4b4c70 Update test to be more explicit about what instruction sequences are expected for each operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85691 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 22:10:38 +00:00
Benjamin Kramer
e3246fc6ab Force triple; darwin's ASM syntax differs from linux's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85676 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 19:54:06 +00:00
Benjamin Kramer
823bdbc770 Add missing colons for FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85674 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 19:22:24 +00:00
Evan Cheng
9eda68988e It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 03:39:36 +00:00
Bob Wilson
37986053b4 Fix Thumb2 failures by converting them to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85210 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27 06:31:02 +00:00
Evan Cheng
21a45557c6 Add a couple of ARM cross-rc coalescing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85051 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 08:01:41 +00:00
Evan Cheng
cc7a5b91de Update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85050 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 07:53:48 +00:00
Jim Grosbach
65b7f3af76 Improve handling of immediates by splitting 32-bit immediates into two 16-bit
immediate operands when they will fit into the using instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 20:44:34 +00:00
Evan Cheng
2095659a85 Match more patterns to movt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 08:15:52 +00:00
Dan Gohman
c1ae8c9b8f Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84727 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 01:44:44 +00:00
David Goodwin
480c529e02 Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84658 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 19:54:44 +00:00
Sandeep Patel
452b54a8ae Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84212 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15 22:25:32 +00:00
Evan Cheng
3825ce8c24 Fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83241 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02 06:53:57 +00:00
David Goodwin
9843a93e83 Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 22:19:57 +00:00
Evan Cheng
48af260bb1 Forgot this test earlier.
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2009-09-30 08:41:27 +00:00
Evan Cheng
5adb66a646 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.


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2009-09-28 09:14:39 +00:00
Evan Cheng
e298ab26b1 Enable pre-regalloc load / store multiple pass for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82893 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27 09:46:04 +00:00
Daniel Dunbar
c8e9314a41 "Update" tests for -disable-if-conversion removal. I think branch.ll should just
be removed, but I XFAIL'd it for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 05:29:36 +00:00
Dan Gohman
b7c0b246da Convert more tests to avoid llvm-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81545 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-11 18:36:27 +00:00
Evan Cheng
28d63b1699 Cast MO.getImm() to unsigned before comparing with an unsigned limit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81318 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 06:05:16 +00:00
Dan Gohman
fce288fc91 Eliminate more uses of llvm-as and llvm-dis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00
Chris Lattner
fc227be725 update various tests for signedness changes in .s file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81289 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08 23:51:06 +00:00
Chris Lattner
94d1077d99 adjust for signedness change. I'd appreciate it if an ARM flavored person
could look at this: the top undefined bits of an immediate shouldn't affect
isel (cmp vs cmp.w)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81288 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08 23:44:53 +00:00
Chris Lattner
543d57352c merge thumb2-bic2.ll into thumb2-bic.ll and update for signedness changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81285 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08 23:41:06 +00:00
Evan Cheng
030a0a0cdb Run branch folding if if-converter make some transformations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80994 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-04 07:47:40 +00:00
Evan Cheng
029599bf01 Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80615 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-31 20:14:07 +00:00
Evan Cheng
e4e4ed3b56 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-28 23:18:09 +00:00
Evan Cheng
cdbb3f5d33 Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80191 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-27 01:23:50 +00:00
Bob Wilson
81fece667e Fix a typo. Somehow I thought this had passed before, but I guess not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79937 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-24 21:17:17 +00:00
Bob Wilson
ef63f70794 Convert slow test to use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79935 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-24 20:33:47 +00:00
Dan Gohman
da65822cfc Make tail merging handle blocks with repeated predecessors correctly, and
remove RemoveDuplicateSuccessor, as it is no longer necessary, and because
it breaks assumptions made in
MachineBasicBlock::isOnlyReachableByFallthrough.

Convert test/CodeGen/X86/omit-label.ll to FileCheck and add a testcase
for PR4732.

test/CodeGen/Thumb2/thumb2-ifcvt2.ll sees a diff with this commit due to
it being bugpoint-reduced to the point where it doesn't matter what the
condition for the branch is.

Add some more interesting code to
test/CodeGen/X86/2009-08-06-branchfolder-crash.ll, which is the testcase
that originally motivated the RemoveDuplicateSuccessor code, to help
verify that the original problem isn't being re-broken.


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2009-08-18 15:18:18 +00:00
Evan Cheng
51f39961c3 Fix revsh pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79318 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18 05:43:23 +00:00
Evan Cheng
39f4d470b6 Fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79086 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 08:23:11 +00:00
Evan Cheng
bc9b754091 Turn on if-conversion for thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 07:59:10 +00:00
Evan Cheng
98a0104014 Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79039 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:48:13 +00:00
Evan Cheng
31b99dd760 Also shrink immediate branches; also more assembler workarounds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79014 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 18:31:44 +00:00
Evan Cheng
a1efbbdbf3 Shrink ADR and LDR from constantpool late during constantpool island pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78970 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 00:32:16 +00:00
Evan Cheng
ea253b99e9 Remove an Darwin assembler workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78777 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 01:56:42 +00:00
Evan Cheng
05c269c645 Shrink ADDS, ADC, RSB, and SUBS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78776 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 01:49:45 +00:00
Evan Cheng
b89030ab65 Shrinkify Thumb2 r = add sp, imm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78745 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 23:00:31 +00:00
Evan Cheng
4b322e58b7 Shrinkify Thumb2 load / store multiple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 21:11:32 +00:00
Evan Cheng
195c71b472 Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78659 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 09:37:40 +00:00
Evan Cheng
3a1f0f6785 Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 23:56:04 +00:00
Evan Cheng
e2b861f7d9 Handle the constantfp created during post-legalization dag combiner phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78594 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 20:25:59 +00:00
Jakob Stoklund Olesen
dffb051c21 Simplify RegScavenger::forward a bit more.
Verify that early clobber registers and their aliases are not used.

All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.

The included test case is from PR4686. It has behaviour that was dependent on the order of operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78465 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 13:18:47 +00:00
Evan Cheng
d77c7aba83 Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78410 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 21:19:10 +00:00
Evan Cheng
1d2426c470 Fix support to use NEON for single precision fp math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78397 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 19:30:41 +00:00
Evan Cheng
15c592ddff Another coalescer bug. When a dead copy is eliminated, transfer the kill to a def of the exact register rather than a super-register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78376 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 07:14:14 +00:00
Evan Cheng
861986401e It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.


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2009-08-07 00:34:42 +00:00
Evan Cheng
6248fa4529 Disable stack coloring with register for now. It's not able to set kill markers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78179 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 07:26:17 +00:00
Evan Cheng
9cd1632814 Another nasty coalescer bug (is there another kind):
After coalescing reg1027's def and kill are both at the same point:
 %reg1027,0.000000e+00 = [56,814:0)  0@70-(814)

bb5:
60   %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
68   %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
76   t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
84   %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
96   t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>

Do not remove the kill marker on t2LDRi12.


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2009-08-05 07:05:41 +00:00
Evan Cheng
b018a1e5a7 One more. Transfer kill of the larger register when lowering an EXTRACT_SUBREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78145 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 02:25:11 +00:00
Evan Cheng
a72dfb522d One more place where subreg lowering forgot to transfer undefness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78144 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:57:22 +00:00
Evan Cheng
518ad1a880 If the insert_subreg source is <undef>, insert an implicit_def instead of a copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78141 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:24 +00:00
Evan Cheng
35d6c41fde Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 23:47:55 +00:00
Evan Cheng
57035994f7 Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78113 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 22:22:58 +00:00
Evan Cheng
9e7a312391 Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 21:12:13 +00:00
Evan Cheng
3425df44b5 In thumb mode, r7 is used as frame register. This fixes pr4681.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78086 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 18:46:17 +00:00
Evan Cheng
fa2ea1a8cf Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 01:41:15 +00:00
Evan Cheng
eed0ff147c Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77967 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03 08:41:59 +00:00
Evan Cheng
a8e8984ee4 Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77939 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03 02:38:06 +00:00
Evan Cheng
b9bcdd9ca4 Test both darwin and linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77852 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02 02:54:34 +00:00
Eli Friedman
f67e84edef Hack to make this test work on platforms which aren't Macs. Fixing this
myself because I'm getting tired of seeing the red buildbots, which have 
been red since 5:30PM PDT last night.

Proposed supplement to developer policy: committers should make sure to 
be around to watch for buildbot failures after committing.



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2009-08-01 16:37:18 +00:00
Evan Cheng
25f7cfc3cc Workaround a couple of Darwin assembler bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-01 06:13:52 +00:00
Evan Cheng
13f8b36205 Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-01 01:43:45 +00:00
Evan Cheng
b620724e61 Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-01 00:16:10 +00:00
Evan Cheng
ff6ab17619 Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 18:35:56 +00:00
Evan Cheng
ee42fd309e When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30 23:29:25 +00:00
David Goodwin
8f65253236 Darwin assembler now recognizes "orn", so remove workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30 21:51:41 +00:00
David Goodwin
7c92f3ac99 Darwin assembler now supports "rrx", so remove workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30 21:38:40 +00:00
David Goodwin
d8c95b5ac2 Cleanup and include code selection for some frame index cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30 18:56:48 +00:00
Evan Cheng
8770f747a9 tbb / tbh instructions only branch forward, not backwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77522 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 23:20:20 +00:00
Evan Cheng
5657c01949 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 02:18:14 +00:00
Evan Cheng
e7c329bf4b In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28 20:53:24 +00:00
David Goodwin
6340632d3b Remove support for ORN to workaround <rdar://problem/7096522>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28 20:51:25 +00:00
David Goodwin
5743854f47 Add workaround for <rdar://problem/7098328>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77340 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28 18:15:38 +00:00