Jim Grosbach
a77295db19
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:07:06 +00:00
Bruno Cardoso Lopes
7ec8fb8830
Add a AVX version of a simple i64 -> f64 bitcast. This could be
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triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
cbf479df8a
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
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single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.
* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.
* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).
Patch by David Meyer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:35:57 +00:00
Bruno Cardoso Lopes
814c6ced85
Add AVX versions of blend vector operations and fix some issues noticed
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in Nadav's r139285 and r139287 commits.
1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
7db2d3a504
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
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Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:02 +00:00
Nadav Rotem
ffe3e7da84
Add X86-SSE4 codegen support for vector-select.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:11:19 +00:00
Jim Grosbach
e64fb28da1
Thumb2 assembly parsing and encoding for LDR post-indexed.
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More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 01:01:32 +00:00
Jim Grosbach
eeec025cf5
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
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Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 00:39:19 +00:00
Owen Anderson
170580e8f4
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 00:11:18 +00:00
Jim Grosbach
f0eee6eca8
Thumb2 assembly parsing and encoding for LDRBT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 23:39:14 +00:00
Jim Grosbach
ab899c1bcc
Thumb2 assembly parsing and encoding for LDR(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 23:10:15 +00:00
Benjamin Kramer
3e328ecbd8
Add two notes for correlated-expression optimizations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139263 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 22:49:26 +00:00
Jim Grosbach
8bb5a861a0
Thumb2 assembly parsing and encoding for LDRB(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 21:41:25 +00:00
Owen Anderson
8a83f71301
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 21:10:42 +00:00
Jim Grosbach
a8307dd1c9
Thumb2 parsing and encoding for LDR(immediate).
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The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 20:58:57 +00:00
Jim Grosbach
94f914e3fd
Thumb2 parsing and encoding for LDMDB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139251 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 19:57:53 +00:00
James Molloy
a5d5856854
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 19:42:28 +00:00
Eli Friedman
d5ccb0558f
Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
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This isn't exactly ideal, but it is good enough for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 18:48:32 +00:00
Jim Grosbach
cfbb3a78db
Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.
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There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 18:39:47 +00:00
Jim Grosbach
76ecc3d35b
Thumb2 parsing and encoding for LDMIA.
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Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 18:05:34 +00:00
Owen Anderson
6de3c6f1a9
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 17:55:19 +00:00
James Molloy
b950585cc5
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 17:24:38 +00:00
Jim Grosbach
ffa5a76344
Thumb2 use 'ldm' as default mnemonic.
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Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 16:22:42 +00:00
Rafael Espindola
ca59221fdc
Detect attempt to use segmented stacks on non ELF systems and error
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(not assert) early.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 16:10:57 +00:00
Jim Grosbach
81d2e3901e
Better diagnostic location information for mnemonic suffices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139232 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 16:06:04 +00:00
Bill Wendling
c8725d11f8
Reenable compact unwind by default. However, also emit the old version of unwind
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information for older linkers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139206 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 23:47:14 +00:00
Jim Grosbach
218affc710
ISB is HasDB, not just HasV7.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139202 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 23:09:19 +00:00
Jim Grosbach
aa833e53dc
Thumb2 parsing and encoding for ISB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 22:53:27 +00:00
Jim Grosbach
06c1a51241
Thumb2 parsing and encoding for DMB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 22:14:58 +00:00
Jim Grosbach
77951908b7
Thumb2 parsing and encoding for DBG.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 22:06:40 +00:00
Jim Grosbach
ef88a92677
Thumb2 parsing and encoding for CMN and CMP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139188 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 21:44:58 +00:00
Eli Friedman
34c4485b74
Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 20:53:37 +00:00
Jim Grosbach
ad2dad930d
Thumb2 parsing and encoding for CLREX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 20:27:04 +00:00
Rafael Espindola
5c984df26b
Fix comment. Noticed by Duncan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139161 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 19:29:31 +00:00
Duncan Sands
28b77e968d
Add codegen support for vector select (in the IR this means a select
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with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 19:07:46 +00:00
Evan Cheng
4a51708448
Fix fall outs from my recent change on how carry bit is modeled during isel.
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Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 18:52:20 +00:00
Jim Grosbach
98447daa95
ARM .code directive should always go to the streamer.
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Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 18:46:23 +00:00
Rafael Espindola
96428cea3d
Fix style issues and typos found by Duncan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 18:43:08 +00:00
Jakob Stoklund Olesen
9b0e1e7a5b
Atomic pseudos don't use (as in read) CPSR. They clobber it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 17:40:35 +00:00
Duncan Sands
4a544a79bd
Split the init.trampoline intrinsic, which currently combines GCC's
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init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 13:37:06 +00:00
Nick Lewycky
1fac6b50ea
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
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instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-05 21:51:43 +00:00
Nick Lewycky
3bca101329
Update the C++ backend to use the new ArrayRef'ified APIs. Patch by arrowdodger!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-05 18:50:59 +00:00
Nick Lewycky
7442a03dcc
Fix typo in comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-05 18:35:03 +00:00
Benjamin Kramer
c53479d9c2
Use internal storage for command line option.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139079 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 03:45:06 +00:00
Bruno Cardoso Lopes
2c84e96d3e
Add AVX versions to match AESENC/AESDEC intrinsics. This hopefully ends
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the cycle of missing AVX counterparts of already present SSE* patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:47:08 +00:00
Bruno Cardoso Lopes
9f63615b17
Add AVX version of a SSE4.1 VPBLENDVB pattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139072 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:47:05 +00:00
Bruno Cardoso Lopes
d01ef7d978
Add AVX versions of SSE4.1 EXTRACTPS patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:47:03 +00:00
Bruno Cardoso Lopes
2b0e0a42d1
Add AVX versions for SSE4.1 MOVZX* patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:47:01 +00:00
Bruno Cardoso Lopes
a67806530c
Add one more AVX pattern for MOVZPQILo2PQI
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:58 +00:00
Bruno Cardoso Lopes
d29dd5ec9f
Move PUNPCKLQDQ splat pattern close to the instruction definition and
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duplicate it for AVX mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:56 +00:00
Bruno Cardoso Lopes
914a2a319c
Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:54 +00:00
Bruno Cardoso Lopes
a4ac989a1c
Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate
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that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139066 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:51 +00:00
Bruno Cardoso Lopes
152a287374
Enforce subtarget checks in a few places to be explicit when the
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pattern should be matched
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:49 +00:00
Bruno Cardoso Lopes
5ab6dcc4bb
Tidy up code moving patterns to their appropriate place!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:47 +00:00
Bruno Cardoso Lopes
0e59a04849
Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use
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it!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:45 +00:00
Bruno Cardoso Lopes
645b8be38a
Teach X86FastISel to use AVX versions of instructions when possible
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:42 +00:00
Bruno Cardoso Lopes
1aab5515f6
Fix 80-column and style
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139061 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:40 +00:00
Bruno Cardoso Lopes
e4ccf8a86c
Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of
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OptForSize pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:38 +00:00
Jakob Stoklund Olesen
5047d76575
Pseudo CMOV instructions don't clobber EFLAGS.
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The explanation about a 0 argument being materialized as xor is no
longer valid. Rematerialization will check if EFLAGS is live before
clobbering it.
The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.
This causes one less testb instruction to be generated in the cmov.ll
test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:52:55 +00:00
Jakob Stoklund Olesen
b8e052e123
Check for EFLAGS live-out before clobbering it.
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It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:52:52 +00:00
Jakob Stoklund Olesen
4a1b9d82a4
Use existing function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139055 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:52:49 +00:00
Jim Grosbach
6c3e11ea55
Thumb2 parsing and encoding for BXJ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139053 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:43:09 +00:00
Jim Grosbach
a110988b39
Thumb2 parsing and encoding of B instruction.
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Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:22:08 +00:00
Jakob Stoklund Olesen
439f71eb30
Remove unused variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 22:41:25 +00:00
Eli Friedman
4136d23c48
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 22:33:24 +00:00
Jim Grosbach
5f25fb01b4
Thumb2 parsing and encoding for ASR.
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For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 21:28:54 +00:00
Kevin Enderby
d5705fe50d
Change X86 disassembly to print immediates values as signed by default. Special
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case those instructions that the immediate is not sign-extend. radr://8795217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 20:01:23 +00:00
Jim Grosbach
8e0c7697fd
Tidy up. Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:46:15 +00:00
Jim Grosbach
d2990107a9
Tidy up. 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:43:25 +00:00
Jim Grosbach
5c1ac55542
Thumb2 parsing and encoding for AND (register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:41:35 +00:00
Bill Wendling
d199aa012b
Revert r138826 until PR10834 can be fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:15:04 +00:00
Jim Grosbach
f0851e5d95
Thumb2 parsing and encoding for ADD (register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:14:46 +00:00
Kalle Raiskila
989621f1f8
Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 10:05:01 +00:00
Owen Anderson
a1c110045a
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 23:35:51 +00:00
Owen Anderson
a6804444e8
Fix 80 columns violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 23:23:50 +00:00
Benjamin Kramer
36a16015ac
Don't drop alignment info on local common symbols.
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- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 23:04:27 +00:00
Eli Friedman
7df496d2ad
Null-initialize to shut up -Wuninitialized warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 22:27:41 +00:00
Jim Grosbach
2f25d9b933
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 18:22:13 +00:00
Bruno Cardoso Lopes
a39ccdb9d4
Fix vbroadcast matching logic to early unmatch if the node doesn't have
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only one use. Fix PR10825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 18:15:06 +00:00
James Molloy
c047dcade5
Fix up r137380 based on post-commit review by Jim Grosbach.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 18:02:14 +00:00
Owen Anderson
7f17b5a483
t2Bcc is allowed to have a predicate without a preceding IT instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 17:47:45 +00:00
Jim Grosbach
20ed2e7939
Thumb2 assembly parsing and encoding for ADD(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 00:28:52 +00:00
Chad Rosier
dd1e7517b5
Fixup for functions that return a bool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138918 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 23:49:05 +00:00
Jim Grosbach
de98273189
Static relocation model Thumb jump table interworking.
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Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138912 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 22:23:09 +00:00
Owen Anderson
b45b11bce1
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 22:00:41 +00:00
Jim Grosbach
c075510e43
Thumb2 t2Bcc should encode as t2B when condition is 'always'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138898 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 21:17:31 +00:00
Bruno Cardoso Lopes
fc7bc5889b
Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 21:15:32 +00:00
Bruno Cardoso Lopes
06c982d0e0
Move MOVAPS,MOVUPS patterns close to the instructions definition
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 21:15:29 +00:00
Bruno Cardoso Lopes
453f4954f2
Remove "_Int" forms of MOVUPSmr and MOVAPSmr
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 21:15:22 +00:00
Owen Anderson
721cb1fde0
Fix encoding for tBcc with immediate offset operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 20:26:14 +00:00
Owen Anderson
d84192fe4f
When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well.
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<rdar://problem/10046188>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 20:00:11 +00:00
Jim Grosbach
b80ab8e369
Remove FIXME. Thumb2 MOV instruction will use separate custom tricks.
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When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138879 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 18:39:39 +00:00
Owen Anderson
559c277aa9
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 18:30:20 +00:00
Jim Grosbach
c9a9b44285
tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 18:29:05 +00:00
Jim Grosbach
72335d55d9
Thumb2 parsing and encoding for ADC(register).
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Also add instruction aliases for non-.w versions of SBC since they're the
same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138871 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 18:23:08 +00:00
Eli Friedman
4d3f329453
64-bit atomic cmpxchg for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 17:52:22 +00:00
Akira Hatanaka
334b5305a6
Fix typo. Patch by Liu.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138866 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 17:49:04 +00:00
Jim Grosbach
0f3abd8d68
Tweak Thumb1 ADD encoding selection a bit.
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When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 17:07:33 +00:00
Jakob Stoklund Olesen
6154582983
Put VMOVS widening under a command line option, off by default.
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It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.
The failing test case is complicated, I am working on a reduction.
<rdar://problem/10044201>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 17:00:02 +00:00
Rafael Espindola
e81abfd30b
Spelling and grammar fixes to problems found by Duncan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 16:43:33 +00:00
Eli Friedman
ac86d43eae
Make sure we don't crash when -miphoneos-version-min is specified on x86. Hopefully this will fix gcc testsuite failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 16:19:51 +00:00
Eric Christopher
c967ad8c88
Rework this conditional a bit.
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Patch by Sanjoy Das
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 04:17:21 +00:00
Bruno Cardoso Lopes
57d6a5e491
- Move all MOVSS and MOVSD patterns close to their definitions
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- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
and update a testcase to check it properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 03:04:20 +00:00
Bruno Cardoso Lopes
fc646a6b06
Remove unnecessary AVX checks
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 03:04:14 +00:00
Bruno Cardoso Lopes
5affa5196f
Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS,
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whenever AVX is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 03:04:09 +00:00
Evan Cheng
0899f5c62d
Fix (movhps load) lowering / pattern to match more cases. rdar://10050549
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138848 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 02:05:24 +00:00
Eli Friedman
3d93861c23
Some minor cleanups for r138845.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 00:41:05 +00:00
Eli Friedman
2bdffe4882
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 00:31:29 +00:00
Owen Anderson
eaca928a37
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 22:58:27 +00:00
Owen Anderson
21df36c57a
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138837 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 22:15:17 +00:00
Owen Anderson
a7710edd98
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138835 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 22:10:03 +00:00
Owen Anderson
391ac65377
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 22:03:20 +00:00
Owen Anderson
10096dbdef
Clean up whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 21:58:18 +00:00
Bill Wendling
e716124feb
Fix off-by-one error Benjamin noticed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 21:23:24 +00:00
Bill Wendling
011a8e1684
Enable compact unwind info by default. This only applies to Darwin when CFI is
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disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 20:54:11 +00:00
Jeffrey Yasskin
cda2a146d1
Fix C++0x narrowing errors when char is unsigned.
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In the case of EDInstInfo, this would actually cause a bug when -1 became 255
and was then compared >=0 in llvm-mc/Disassembler.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 20:53:29 +00:00
Rafael Espindola
151ab3e2f7
Adds support for variable sized allocas. For a variable sized alloca,
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code is inserted to first check if the current stacklet has enough
space. If so, space is allocated by simply decrementing the stack
pointer. Otherwise a runtime routine (__morestack_allocate_stack_space
in libgcc) is called which allocates the required memory from the
heap.
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 19:47:04 +00:00
Rafael Espindola
d07b7ec772
Adds a SelectionDAG node X86SegAlloca which will be custom lowered
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from DYNAMIC_STACKALLOC.
Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added. They
will be custom emitted to inject the actual stack handling code.
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 19:43:21 +00:00
Rafael Espindola
76927d7586
Emit segmented-stack specific code into function prologues for
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X86. Modify the pass added in the previous patch to call this new
code.
This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 19:39:58 +00:00
Rafael Espindola
0f9827cd94
Command line option to enable support for segmented stacks:
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-segmented-stacks.
Patch by Sanjoy Das!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 19:29:02 +00:00
Evan Cheng
37fefc20d3
Follow up to r138791.
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Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 19:09:48 +00:00
Roman Divacky
0aaa9195b5
Set CR1EQ only when lowering vararg floating arguments (not any vararg
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arguments as before), unset CR1EQ otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138802 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 17:04:16 +00:00
James Molloy
e7815c22fc
Fix typos in SPUMCTargetDesc.h
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Patch supplied by Liu (projlc@gmail.com )
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138799 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 07:27:02 +00:00
James Molloy
7e14b240a8
Fix typo in BlackfinFrameLowering.h
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Patch supplied by Liu (projlc@gmail.com )
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 07:26:11 +00:00
James Molloy
4d8af4ee6e
Fix typo in MSP430MCTargetDesc.h.
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Patch supplied by Liu (projlc@gmail.com )
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138797 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 07:24:47 +00:00
James Molloy
afaf80a13b
Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc@gmail.com)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138796 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 07:23:29 +00:00
Evan Cheng
342e3161d9
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
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register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
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2011-08-30 01:34:54 +00:00
Jim Grosbach
d3765189bf
Revert 138781. It's not playing nicely with the immediate forms for ADC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 23:24:15 +00:00
Jim Grosbach
e94a5b1218
Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 23:20:54 +00:00
Owen Anderson
694e0ffb8a
Add missing encoding information for some of the GPR<->FP register moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138780 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 23:15:25 +00:00
Jim Grosbach
f8e1e3e729
Thumb2 parsing and encoding for IT blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 22:24:09 +00:00
Eli Friedman
f3704769bb
Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138768 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 21:15:46 +00:00
Owen Anderson
acb274baac
Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 21:14:19 +00:00
Owen Anderson
1f26758510
Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138760 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 20:42:00 +00:00
Owen Anderson
c4e16de765
addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138758 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 20:16:50 +00:00
Owen Anderson
0da10cf44d
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 19:36:44 +00:00
Eli Friedman
4db5acaf48
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 18:23:02 +00:00
Owen Anderson
07700d486e
Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 17:59:41 +00:00
Bruno Cardoso Lopes
41dfabb0e3
Move non-intruction patterns to a more appropriate place!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 17:51:24 +00:00
Owen Anderson
63553c77cd
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 17:17:09 +00:00
Nicolas Geoffray
1c36ba50ac
Remove premature previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138725 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-28 14:52:51 +00:00
Nicolas Geoffray
c98da24bed
Encoding of instructions referencing segments has changed. Do what X86MCCodeEmitter does.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-28 13:07:57 +00:00
Benjamin Kramer
2753ae314f
Silence GCC warnings and make an array const.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138706 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-27 17:36:14 +00:00
Owen Anderson
f1eab597b2
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 23:32:08 +00:00
Owen Anderson
d7568e1c35
Correct encoding of BL with immediate offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 22:54:51 +00:00
Jim Grosbach
4af54a461f
ARM assembly parsing tweak for pldw.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 22:21:51 +00:00
Owen Anderson
9f7e831994
Spelling fail.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 21:47:57 +00:00
Jim Grosbach
89df996ab2
Thumb2 assembler parsing and encoding of IT instruction.
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This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 21:43:41 +00:00
Eli Friedman
43f51aeca8
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 21:21:21 +00:00
Owen Anderson
2b568fb3ce
Fix ARM codegen breakage caused by r138653.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 21:12:37 +00:00
Owen Anderson
9ab0f25fc1
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 20:43:14 +00:00
Owen Anderson
1af7f7291d
Update for feedback from Jim.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 19:39:26 +00:00
Benjamin Kramer
86ce852a15
ARMDisassembler: Always return a size, even when disassembling fails.
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This should fix PR10772.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 18:21:36 +00:00
Owen Anderson
96425c8464
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 18:09:22 +00:00
Kalle Raiskila
54f8a9f54d
Don't insert branch hint lables that are never used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 10:14:56 +00:00
Owen Anderson
9bd655dcde
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
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This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 06:19:51 +00:00
Craig Topper
8fd13b6de5
Fix disassembling of VCVTSD2SI
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 04:49:29 +00:00
Eli Friedman
069e2ed794
Atomic load/store on ARM/Thumb.
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I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 02:59:24 +00:00
Bruno Cardoso Lopes
f1a264232c
Do the same as r138461. Mark VZEROALL as clobbering all YMM registers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 22:23:58 +00:00
Nick Lewycky
b210cbf692
Remove stray fullstop.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 21:46:20 +00:00
Bruno Cardoso Lopes
6292eceea0
Add support for AVX 256-bit version of MOVDDUP!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 21:40:37 +00:00
Bruno Cardoso Lopes
06ef923d14
Make isMOVDDUP mask check more strict and update comments!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 21:40:34 +00:00
Owen Anderson
99906830e8
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 18:30:18 +00:00
Andrew Trick
b9ca5124f8
ARM fix for missing implicit operands on ldmia_ret.
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rdar://10005094: miscompile of 176.gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 17:50:53 +00:00
Andrew Trick
51972da576
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 17:40:54 +00:00
Jim Grosbach
0c49ac05cd
Explicitly disallow predication in Thumb1 assembly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 17:23:55 +00:00
Craig Topper
ebc1db0fac
Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 08:11:01 +00:00
Craig Topper
ea03659d23
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 06:57:46 +00:00
Bruno Cardoso Lopes
07b7f672a0
Add support for 256-bit versions of VSHUFPD and VSHUFPS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138546 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 02:58:26 +00:00
Bruno Cardoso Lopes
e7461c0353
Add memory version of SHUFPD to mask decoding!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138545 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 02:58:21 +00:00
Evan Cheng
77eaaf0a0c
Hide -global-merge option.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138540 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 01:22:49 +00:00
Evan Cheng
b8cfe4ff41
Add a command line option to disable global merge pass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 01:00:36 +00:00
Evan Cheng
0f660260e6
Remove a out-of-place comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 00:54:42 +00:00
Bruno Cardoso Lopes
27831e5e6f
Create a section for non-instructions patterns in the beginning of the
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file, and move more code around!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138521 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:18:11 +00:00
Bruno Cardoso Lopes
9993499057
Move code around!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:18:09 +00:00
Bruno Cardoso Lopes
de79231468
Organize UNPCK* patterns, also add remaining for AVX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:18:06 +00:00
Bruno Cardoso Lopes
4cf4778ac4
Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate
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the missing ones for AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:18:04 +00:00
Bruno Cardoso Lopes
4724f25ed6
Organize and tidy up MOVDDUP section. Also update comments!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:18:02 +00:00
Bruno Cardoso Lopes
6140294363
Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the
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pattern for 128-bit AVX mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:17:59 +00:00
Bruno Cardoso Lopes
954d5eabb7
Move all PSHUF* patterns close to the PSHUF* definitions. Also be
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explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:17:57 +00:00
Bruno Cardoso Lopes
af002d8405
Move all SHUFP* patterns close to the SHUFP* definitions. Also be
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explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138514 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 23:17:55 +00:00
Owen Anderson
f44082091c
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 22:40:22 +00:00
Eli Friedman
f8f90f0174
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 22:33:28 +00:00
Jim Grosbach
b9d3ff8729
ARM asm backend initialize isThumbMode based on target triple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138501 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 22:27:35 +00:00
Jim Grosbach
4d23e99d2a
Thumb .n mnemonic qualifiers can be ignored for now.
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We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 22:19:48 +00:00
Jim Grosbach
f69c804036
Thumb parsing and encoding for SUB (SP minu immediate).
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Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:42:27 +00:00
Owen Anderson
12a1e3bbcb
Be careful not to walk off the end of the operand info list while updating VFP predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:35:46 +00:00
Jim Grosbach
72f39f8436
Thumb parsing and encoding support for ADD SP instructions.
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Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:22:15 +00:00
Eli Friedman
4317fe1fc6
Fix whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:17:30 +00:00
Eli Friedman
327236cd6c
Basic x86 code generation for atomic load and store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 20:50:09 +00:00
Jim Grosbach
df9ce6bbc5
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
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rdar://10015134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138467 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 20:06:14 +00:00
Bruno Cardoso Lopes
356e988110
Mark VZEROALL as clobbering all YMM registers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138461 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:48:33 +00:00
Jim Grosbach
f95aaf951b
Add missing explicit writeback operand to tSTMIA_UPD.
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rdar://10014745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:19:42 +00:00
Evan Cheng
3e74d6fdd2
Move TargetRegistry and TargetSelect from Target to Support where they belong.
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These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:08:43 +00:00
Jim Grosbach
c7e0bb2325
Thumb add SP assembly syntax fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:04:27 +00:00
Jim Grosbach
5b81584f74
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
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Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 17:46:13 +00:00
Owen Anderson
e234d02204
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 17:21:43 +00:00
Richard Osborne
8f9c5cca4f
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
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variable sized alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 13:32:43 +00:00
Craig Topper
13894fa135
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 06:14:18 +00:00
Bruno Cardoso Lopes
d8b7dd5252
Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit
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permutations. Also tidy up some patterns and make them close to their
instruction definition!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138392 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 22:06:37 +00:00