Akira Hatanaka
48ae99fac4
Support for PSP is gone too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139622 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 18:55:33 +00:00
Owen Anderson
b6b7f515e2
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139610 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 17:59:19 +00:00
Akira Hatanaka
2152307933
It is not necessary to search for mipsallegrex in target triple string.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139607 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 17:35:28 +00:00
Owen Anderson
12c7e90d36
Fix encoding of Thumb2 shifted register operands with RRX shifts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 17:34:32 +00:00
Craig Topper
4bbeb18f76
Only disassembler instructions with vvvv != 1111 if the instruction actually uses the vvvv field to encode an operand. Fixes PR10851.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 07:37:44 +00:00
Craig Topper
58bbb81764
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
Craig Topper
6b0b2d6c41
Fix encoding of VMOVDQU to not simultaneously be 'TB OpSize' and 'XS'. 'XS' is correct and seems to have been taking priority.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:39:34 +00:00
Eli Friedman
885f1a0c04
Zap some junk from the ARM instruction descriptions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 02:29:58 +00:00
Eli Friedman
f73c881f4a
Fix the assembler strings for a couple of atomic instructions. Doesn't really matter much in practice, but it's a bit cleaner.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 00:27:04 +00:00
Jim Grosbach
2d539691a1
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 23:36:42 +00:00
Bruno Cardoso Lopes
5fc48100ee
Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
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destination types are equal!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 22:59:23 +00:00
Owen Anderson
cd00dc6852
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 21:28:46 +00:00
Bruno Cardoso Lopes
457d53d9ce
Revert the wrong part of r139528, and fix testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139541 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 21:24:07 +00:00
Owen Anderson
fd92d2e106
Fix encoding of PC-relative LDRSHW with an immediate offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 20:36:51 +00:00
Owen Anderson
a073795023
There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 20:07:22 +00:00
Bruno Cardoso Lopes
8e03a821f9
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
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However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139528 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:40 +00:00
Bruno Cardoso Lopes
93474f5f7f
Organize a bit the operand names for CMPPS and CMPPD
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:36 +00:00
Bruno Cardoso Lopes
cf355422d6
Realign BLEND patterns to match the general style for patterns in .td file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139526 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:33 +00:00
Bruno Cardoso Lopes
3445df77d4
Fix 80-columns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:29 +00:00
Owen Anderson
a3157b4026
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 18:56:30 +00:00
Richard Osborne
a1d16b53e8
Associate a MemOperand with LDWCP nodes introduced during ISel.
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This information is required if we want LDWCP to be hoisted out of loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:43:23 +00:00
Richard Osborne
2cb6c1bd20
Mark LDWCP as having no side effects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:41:31 +00:00
Nadav Rotem
5ed0983200
Format patterns, remove unused X86blend patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139491 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 08:41:50 +00:00
Craig Topper
136046c9a2
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
Craig Topper
038197988b
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 21:41:45 +00:00
Nadav Rotem
fbad25e120
CR fixes per Bruno's request.
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Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 15:02:23 +00:00
Eli Friedman
106f6e7a27
r139454 activates an assert in a case where we were doing the right thing anyway. Make that explicit, and un-XFAIL the testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 02:01:42 +00:00
Richard Trieu
81cbb0ad60
Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and
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lib/ExecutionEngine/MCJIT/MCJIT.cpp from:
assert("error");
to:
assert(0 && "error");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:42:07 +00:00
Richard Trieu
2db8628085
Fixed an assert from:
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assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:26:21 +00:00
Jim Grosbach
1ad60c2adc
Thumb2 parsing and encoding for MOV(immediate).
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Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 00:15:36 +00:00
Owen Anderson
921d01ae1f
LDM writeback is not allowed if Rn is in the target register list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:13:33 +00:00
Owen Anderson
112fb73502
Fix an ambiguously nested if.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:13:02 +00:00
Owen Anderson
cd4338fff5
Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139429 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:05:14 +00:00
Owen Anderson
08fef885eb
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:24:36 +00:00
Akira Hatanaka
46ac94ba8b
O64 will not be supported.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139421 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:22:48 +00:00
Akira Hatanaka
5881586745
Make F31 and D15 non-reserved registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:11:26 +00:00
Owen Anderson
51f6a7abf2
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:48:23 +00:00
Akira Hatanaka
9a439affd7
Mips32 does not reserve even-numbered floating point registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:31:46 +00:00
Akira Hatanaka
8ddf6531b8
Drop support for Mips1 and Mips2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:45:50 +00:00
Nadav Rotem
8ffad56f8e
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:29:17 +00:00
Jim Grosbach
468709e43d
Thumb2 assembly parsing and encoding for MLA and MLS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:24:45 +00:00
Jim Grosbach
0811fe13d6
Thumb2 assembly parsing and encoding for LDRSB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:42:40 +00:00
Akira Hatanaka
d199d0c59c
Drop support for Allegrex. Allegrex implements a variant of Mips2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:00:51 +00:00
Jim Grosbach
b6aed508e3
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 18:37:27 +00:00
Craig Topper
ccfa4ed4e0
Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 05:40:53 +00:00
Akira Hatanaka
ad5f0c9e73
Change default target architecture from Mips1 to Mips32r1 in preparation for
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removing support for Mips1 and Mips2.
This change and the ones that follow have been discussed with and approved by
Bruno.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 01:13:27 +00:00
Akira Hatanaka
404507e7d8
80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 00:13:35 +00:00
Owen Anderson
441462f932
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:48:37 +00:00
Owen Anderson
d2fc31b3f7
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:42:49 +00:00
Nadav Rotem
ee64be9c17
Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:17:35 +00:00
Jim Grosbach
a77295db19
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:07:06 +00:00
Bruno Cardoso Lopes
7ec8fb8830
Add a AVX version of a simple i64 -> f64 bitcast. This could be
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triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
cbf479df8a
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
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single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.
* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.
* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).
Patch by David Meyer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:35:57 +00:00
Bruno Cardoso Lopes
814c6ced85
Add AVX versions of blend vector operations and fix some issues noticed
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in Nadav's r139285 and r139287 commits.
1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
7db2d3a504
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
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Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:02 +00:00
Nadav Rotem
ffe3e7da84
Add X86-SSE4 codegen support for vector-select.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:11:19 +00:00
Jim Grosbach
e64fb28da1
Thumb2 assembly parsing and encoding for LDR post-indexed.
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More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 01:01:32 +00:00
Jim Grosbach
eeec025cf5
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
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Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 00:39:19 +00:00
Owen Anderson
170580e8f4
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 00:11:18 +00:00
Jim Grosbach
f0eee6eca8
Thumb2 assembly parsing and encoding for LDRBT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 23:39:14 +00:00
Jim Grosbach
ab899c1bcc
Thumb2 assembly parsing and encoding for LDR(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 23:10:15 +00:00
Benjamin Kramer
3e328ecbd8
Add two notes for correlated-expression optimizations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139263 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 22:49:26 +00:00
Jim Grosbach
8bb5a861a0
Thumb2 assembly parsing and encoding for LDRB(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 21:41:25 +00:00
Owen Anderson
8a83f71301
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 21:10:42 +00:00
Jim Grosbach
a8307dd1c9
Thumb2 parsing and encoding for LDR(immediate).
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The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 20:58:57 +00:00
Jim Grosbach
94f914e3fd
Thumb2 parsing and encoding for LDMDB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139251 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 19:57:53 +00:00
James Molloy
a5d5856854
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 19:42:28 +00:00
Eli Friedman
d5ccb0558f
Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
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This isn't exactly ideal, but it is good enough for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 18:48:32 +00:00
Jim Grosbach
cfbb3a78db
Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.
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There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 18:39:47 +00:00
Jim Grosbach
76ecc3d35b
Thumb2 parsing and encoding for LDMIA.
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Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 18:05:34 +00:00
Owen Anderson
6de3c6f1a9
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 17:55:19 +00:00
James Molloy
b950585cc5
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 17:24:38 +00:00
Jim Grosbach
ffa5a76344
Thumb2 use 'ldm' as default mnemonic.
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Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 16:22:42 +00:00
Rafael Espindola
ca59221fdc
Detect attempt to use segmented stacks on non ELF systems and error
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(not assert) early.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 16:10:57 +00:00
Jim Grosbach
81d2e3901e
Better diagnostic location information for mnemonic suffices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139232 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 16:06:04 +00:00
Bill Wendling
c8725d11f8
Reenable compact unwind by default. However, also emit the old version of unwind
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information for older linkers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139206 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 23:47:14 +00:00
Jim Grosbach
218affc710
ISB is HasDB, not just HasV7.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139202 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 23:09:19 +00:00
Jim Grosbach
aa833e53dc
Thumb2 parsing and encoding for ISB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 22:53:27 +00:00
Jim Grosbach
06c1a51241
Thumb2 parsing and encoding for DMB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 22:14:58 +00:00
Jim Grosbach
77951908b7
Thumb2 parsing and encoding for DBG.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 22:06:40 +00:00
Jim Grosbach
ef88a92677
Thumb2 parsing and encoding for CMN and CMP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139188 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 21:44:58 +00:00
Eli Friedman
34c4485b74
Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 20:53:37 +00:00
Jim Grosbach
ad2dad930d
Thumb2 parsing and encoding for CLREX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 20:27:04 +00:00
Rafael Espindola
5c984df26b
Fix comment. Noticed by Duncan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139161 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 19:29:31 +00:00
Duncan Sands
28b77e968d
Add codegen support for vector select (in the IR this means a select
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with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 19:07:46 +00:00
Evan Cheng
4a51708448
Fix fall outs from my recent change on how carry bit is modeled during isel.
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Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 18:52:20 +00:00
Jim Grosbach
98447daa95
ARM .code directive should always go to the streamer.
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Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 18:46:23 +00:00
Rafael Espindola
96428cea3d
Fix style issues and typos found by Duncan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 18:43:08 +00:00
Jakob Stoklund Olesen
9b0e1e7a5b
Atomic pseudos don't use (as in read) CPSR. They clobber it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 17:40:35 +00:00
Duncan Sands
4a544a79bd
Split the init.trampoline intrinsic, which currently combines GCC's
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init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 13:37:06 +00:00
Nick Lewycky
1fac6b50ea
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
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instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-05 21:51:43 +00:00
Nick Lewycky
3bca101329
Update the C++ backend to use the new ArrayRef'ified APIs. Patch by arrowdodger!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-05 18:50:59 +00:00
Nick Lewycky
7442a03dcc
Fix typo in comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-05 18:35:03 +00:00
Benjamin Kramer
c53479d9c2
Use internal storage for command line option.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139079 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 03:45:06 +00:00
Bruno Cardoso Lopes
2c84e96d3e
Add AVX versions to match AESENC/AESDEC intrinsics. This hopefully ends
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the cycle of missing AVX counterparts of already present SSE* patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:47:08 +00:00
Bruno Cardoso Lopes
9f63615b17
Add AVX version of a SSE4.1 VPBLENDVB pattern
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139072 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:47:05 +00:00
Bruno Cardoso Lopes
d01ef7d978
Add AVX versions of SSE4.1 EXTRACTPS patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:47:03 +00:00
Bruno Cardoso Lopes
2b0e0a42d1
Add AVX versions for SSE4.1 MOVZX* patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:47:01 +00:00
Bruno Cardoso Lopes
a67806530c
Add one more AVX pattern for MOVZPQILo2PQI
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:58 +00:00
Bruno Cardoso Lopes
d29dd5ec9f
Move PUNPCKLQDQ splat pattern close to the instruction definition and
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duplicate it for AVX mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:56 +00:00
Bruno Cardoso Lopes
914a2a319c
Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:54 +00:00
Bruno Cardoso Lopes
a4ac989a1c
Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate
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that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139066 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:51 +00:00
Bruno Cardoso Lopes
152a287374
Enforce subtarget checks in a few places to be explicit when the
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pattern should be matched
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:49 +00:00
Bruno Cardoso Lopes
5ab6dcc4bb
Tidy up code moving patterns to their appropriate place!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:47 +00:00
Bruno Cardoso Lopes
0e59a04849
Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use
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it!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:45 +00:00
Bruno Cardoso Lopes
645b8be38a
Teach X86FastISel to use AVX versions of instructions when possible
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:42 +00:00
Bruno Cardoso Lopes
1aab5515f6
Fix 80-column and style
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139061 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:40 +00:00
Bruno Cardoso Lopes
e4ccf8a86c
Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of
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OptForSize pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03 00:46:38 +00:00
Jakob Stoklund Olesen
5047d76575
Pseudo CMOV instructions don't clobber EFLAGS.
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The explanation about a 0 argument being materialized as xor is no
longer valid. Rematerialization will check if EFLAGS is live before
clobbering it.
The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.
This causes one less testb instruction to be generated in the cmov.ll
test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:52:55 +00:00
Jakob Stoklund Olesen
b8e052e123
Check for EFLAGS live-out before clobbering it.
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It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:52:52 +00:00
Jakob Stoklund Olesen
4a1b9d82a4
Use existing function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139055 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:52:49 +00:00
Jim Grosbach
6c3e11ea55
Thumb2 parsing and encoding for BXJ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139053 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:43:09 +00:00
Jim Grosbach
a110988b39
Thumb2 parsing and encoding of B instruction.
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Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 23:22:08 +00:00
Jakob Stoklund Olesen
439f71eb30
Remove unused variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 22:41:25 +00:00
Eli Friedman
4136d23c48
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 22:33:24 +00:00
Jim Grosbach
5f25fb01b4
Thumb2 parsing and encoding for ASR.
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For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 21:28:54 +00:00
Kevin Enderby
d5705fe50d
Change X86 disassembly to print immediates values as signed by default. Special
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case those instructions that the immediate is not sign-extend. radr://8795217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 20:01:23 +00:00
Jim Grosbach
8e0c7697fd
Tidy up. Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:46:15 +00:00
Jim Grosbach
d2990107a9
Tidy up. 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:43:25 +00:00
Jim Grosbach
5c1ac55542
Thumb2 parsing and encoding for AND (register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:41:35 +00:00
Bill Wendling
d199aa012b
Revert r138826 until PR10834 can be fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:15:04 +00:00
Jim Grosbach
f0851e5d95
Thumb2 parsing and encoding for ADD (register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:14:46 +00:00
Kalle Raiskila
989621f1f8
Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 10:05:01 +00:00
Owen Anderson
a1c110045a
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 23:35:51 +00:00
Owen Anderson
a6804444e8
Fix 80 columns violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 23:23:50 +00:00
Benjamin Kramer
36a16015ac
Don't drop alignment info on local common symbols.
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- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 23:04:27 +00:00
Eli Friedman
7df496d2ad
Null-initialize to shut up -Wuninitialized warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 22:27:41 +00:00
Jim Grosbach
2f25d9b933
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 18:22:13 +00:00
Bruno Cardoso Lopes
a39ccdb9d4
Fix vbroadcast matching logic to early unmatch if the node doesn't have
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only one use. Fix PR10825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 18:15:06 +00:00
James Molloy
c047dcade5
Fix up r137380 based on post-commit review by Jim Grosbach.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 18:02:14 +00:00
Owen Anderson
7f17b5a483
t2Bcc is allowed to have a predicate without a preceding IT instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 17:47:45 +00:00
Jim Grosbach
20ed2e7939
Thumb2 assembly parsing and encoding for ADD(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 00:28:52 +00:00
Chad Rosier
dd1e7517b5
Fixup for functions that return a bool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138918 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 23:49:05 +00:00
Jim Grosbach
de98273189
Static relocation model Thumb jump table interworking.
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Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138912 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 22:23:09 +00:00
Owen Anderson
b45b11bce1
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 22:00:41 +00:00
Jim Grosbach
c075510e43
Thumb2 t2Bcc should encode as t2B when condition is 'always'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138898 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 21:17:31 +00:00
Bruno Cardoso Lopes
fc7bc5889b
Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 21:15:32 +00:00
Bruno Cardoso Lopes
06c982d0e0
Move MOVAPS,MOVUPS patterns close to the instructions definition
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 21:15:29 +00:00
Bruno Cardoso Lopes
453f4954f2
Remove "_Int" forms of MOVUPSmr and MOVAPSmr
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 21:15:22 +00:00
Owen Anderson
721cb1fde0
Fix encoding for tBcc with immediate offset operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 20:26:14 +00:00
Owen Anderson
d84192fe4f
When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well.
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<rdar://problem/10046188>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 20:00:11 +00:00
Jim Grosbach
b80ab8e369
Remove FIXME. Thumb2 MOV instruction will use separate custom tricks.
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When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138879 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 18:39:39 +00:00
Owen Anderson
559c277aa9
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 18:30:20 +00:00
Jim Grosbach
c9a9b44285
tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 18:29:05 +00:00
Jim Grosbach
72335d55d9
Thumb2 parsing and encoding for ADC(register).
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Also add instruction aliases for non-.w versions of SBC since they're the
same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138871 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 18:23:08 +00:00
Eli Friedman
4d3f329453
64-bit atomic cmpxchg for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 17:52:22 +00:00
Akira Hatanaka
334b5305a6
Fix typo. Patch by Liu.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138866 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 17:49:04 +00:00
Jim Grosbach
0f3abd8d68
Tweak Thumb1 ADD encoding selection a bit.
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When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 17:07:33 +00:00
Jakob Stoklund Olesen
6154582983
Put VMOVS widening under a command line option, off by default.
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It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.
The failing test case is complicated, I am working on a reduction.
<rdar://problem/10044201>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 17:00:02 +00:00
Rafael Espindola
e81abfd30b
Spelling and grammar fixes to problems found by Duncan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 16:43:33 +00:00