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8215 Commits

Author SHA1 Message Date
Rafael Espindola
1242d28093 small cleanup: use LowerMemArgument in LowerFastCCArguments also 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42189 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-21 14:55:38 +00:00
Evan Cheng
76a4023096 Honor user-defined section specification of a global, ignores whether its initializer is null. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42182 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-21 00:41:19 +00:00
Devang Patel
0f0daea654 Do not override user specified section. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42179 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-20 23:07:37 +00:00
Dan Gohman
a4ddacf60b Fix several more entries in the x86 reload/remat folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42162 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-20 14:17:21 +00:00
Dale Johannesen
41de436ca3 another long double buglet 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42159 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-20 01:27:54 +00:00
Evan Cheng
17207ddf38 Enable if-conversion for ARM by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42156 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-20 00:48:22 +00:00
Dale Johannesen
73328d14ac More long double fixes. x86_64 should build now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42155 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-19 23:55:34 +00:00
Evan Cheng
e71bff7405 Avoid referencing deleted instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42153 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-19 21:48:07 +00:00
Evan Cheng
fab7eff0fa PSHUFDmi, etc. are actually folding a load, not a store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42147 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-19 19:02:47 +00:00
Evan Cheng
dcfa73fe3c Set CCR (EFLAGS) copy cost to -1, i.e. extremely expensive to copy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42124 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-19 01:36:39 +00:00
Evan Cheng
a3ca3149f2 Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value 
between two registers in the specific class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42123 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-19 01:35:01 +00:00
Dan Gohman
869b2b2c23 Move the entries for 64-bit CMP, IMUL, and a few others into the correct 
tables so that they are eligible for reload/remat folding. And add
entries for JMP and CALL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42094 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-18 14:59:14 +00:00
Dale Johannesen
ca8035e356 Remove RSTRegClass case from loadRegFromStackSlot 
and storeRegToStackSlot.  Evan and I concluded this
should never be needed and it appears to be true.
(It if is needed, adjustment would be needed for
long double to work.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42049 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-17 20:15:38 +00:00
Chris Lattner
76c1b97e40 Merge DenseMapKeyInfo & DenseMapValueInfo into DenseMapInfo 
Add a new DenseMapInfo::isEqual method to allow clients to redefine
the equality predicate used when probing the hash table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42042 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-17 18:34:04 +00:00
Evan Cheng
7d6ff3a25d X86ISD::TEST is dead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42037 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-17 17:42:53 +00:00
Dan Gohman
a0a7c1de9c Add 64-bit jmp instructions to the list of instructions that 
can terminate a block with no fall-through.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42029 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-17 15:19:08 +00:00
Dan Gohman
959062475d Use xorl instead of xorq to enter a zero into a 64-bit register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42027 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-17 14:55:08 +00:00
Dan Gohman
5f6913cecd Emit integer x<1 as x<=0, as comparisons with zero (now includeing 
64-bit) can use test instead of cmp with an immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42026 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-17 14:49:27 +00:00
Dan Gohman
11f7bfbb83 Use "test reg,reg" in place of "cmp reg,0" for 64-bit operands. This was 
previously only done for 32-bit and smaller operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42024 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-17 14:35:24 +00:00
Dale Johannesen
53f0bc1b25 Implement x86 long double (uses host long double, 
so only works on x86 target).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42019 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-17 00:38:27 +00:00
Bill Wendling
bd626b885f Follow-up to patch r41999. Make the conditional that emits the personality stub 
match the conditional that turns on exception handling emittion in the asm
printer.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42008 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-16 19:21:08 +00:00
Bill Wendling
656ab16c56 Only emit the personality function as a global value if the backend actually 
supports it. This solves this error on the Darwin x86-64 platform:

$ cat testcase.ii
struct A {
  A();
};

A *bork() {
  return new A;
}
$ llvm-g++ -arch x86_64 -c testcase.ii
/var/tmp//cc3U8fd8.s:52:unknown section type: non_lazy_symbol_pointers
/var/tmp//cc3U8fd8.s:52:Rest of line ignored. 1st junk character valued 76 (L).
/var/tmp//cc3U8fd8.s:53:Unknown pseudo-op: .indirect_symbol
/var/tmp//cc3U8fd8.s:53:Rest of line ignored. 1st junk character valued 95 (_).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41999 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-16 10:36:17 +00:00
Chris Lattner
5bda9e49ec Fix PR1666, SPASS with the CBE and 254.gap with the CBE. 
GCC optimizes away things like ptr < NULL  to false.  To "fix" this,
have the CBE emit casts of pointers to intptr_t when doing relational
pointer comparisons.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41983 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-15 06:51:03 +00:00
Dan Gohman
e47f1f9633 Add patterns for SHLD64* and SHRD64*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41975 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-14 23:17:45 +00:00
Dale Johannesen
9e3d3abd93 Remove the assumption that FP's are either float or 
double from some of the many places in the optimizers
it appears, and do something reasonable with x86
long double.
Make APInt::dump() public, remove newline, use it to
dump ConstantSDNode's.
Allow APFloats in FoldingSet.
Expand X86 backend handling of long doubles (conversions
to/from int, mostly).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41967 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-14 22:26:36 +00:00
Evan Cheng
24f2ea3971 Add implicit def of EFLAGS on those instructions that may modify flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41962 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-14 21:48:26 +00:00
Dan Gohman
92dfe2001e Remove isReg, isImm, and isMBB, and change all their users to use 
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-14 20:33:02 +00:00
Rafael Espindola
7effac5475 Add support for functions with byval arguments on x86 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41953 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-14 15:48:13 +00:00
Evan Cheng
fdd9f006bc Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41947 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-14 01:57:02 +00:00
Evan Cheng
85dbe1a1d2 Initial support for multi-result patterns: 
1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41897 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-12 23:30:14 +00:00
Dale Johannesen
9d5f456077 Revise previous patch per review comments. 
Next round of x87 long double stuff.
Getting close now, basically works.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41875 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-12 03:30:33 +00:00
Bill Wendling
fe4afb17d3 Enable indirect encoding for the personality function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41873 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 23:55:40 +00:00
Evan Cheng
071a279e94 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 19:55:27 +00:00
Evan Cheng
3054dde813 Added status flags register: EFLAGS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41862 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 19:53:28 +00:00
Dale Johannesen
3f6eb7419d Add APInt interfaces to APFloat (allows directly 
access to bits).  Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling 
(untested, probably does not work).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41858 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 18:32:33 +00:00
Bill Wendling
ef4a661725 Add a bool to indicate if we should set the "indirect encoding" bit in the Dwarf 
information for EH.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41852 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 17:20:55 +00:00
Duncan Sands
f7331b3dd7 Fold the adjust_trampoline intrinsic into 
init_trampoline.  There is now only one
trampoline intrinsic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 14:10:23 +00:00
Duncan Sands
49c23935e0 My compiler warns about the semicolon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41840 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 12:30:25 +00:00
Bill Wendling
d60da495cd The personality function on Darwin needs a global stub. We then refer to 
that global stub instead of doing the ".set" thingy we were doing before.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41838 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 08:27:17 +00:00
Evan Cheng
be36798bfe 80 col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41812 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-10 22:22:23 +00:00
Evan Cheng
f618e7c2a1 New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41810 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-10 22:16:37 +00:00
Chris Lattner
bf8ae84a21 Add some notes about better flag handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41808 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-10 21:43:18 +00:00
Evan Cheng
b0869ed44d It's not safe to rematerialize MOV32r0 etc. by simply cloning the original 
instruction. These are implemented with xor which will modify the conditional
code. They should be rematerialized as move instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41802 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-10 20:48:53 +00:00
Evan Cheng
ef61ed3507 TableGen no longer emit CopyFromReg nodes for implicit results in physical 
registers. The scheduler is now responsible for emitting them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41781 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-07 23:59:02 +00:00
Bill Wendling
82d25148a7 Add missing index versions of instructions to the map. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41776 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-07 22:01:02 +00:00
Dan Gohman
1ab79897e2 Avoid storing and reloading zeros and other constants from stack slots 
by flagging the associated instructions as being trivially rematerializable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41775 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-07 21:32:51 +00:00
Dale Johannesen
cdd509aecd Apply feedback from previous patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41774 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-07 21:07:57 +00:00
Rafael Espindola
588af2fb99 Add support for having different alignment for objects on call frames. 
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41768 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-07 14:52:14 +00:00
Owen Anderson
718cb665ca Add lengthof and endof templates that hide a lot of sizeof computations. 
Patch by Sterling Stein!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-07 04:06:50 +00:00
Dale Johannesen
43421b3dd7 Next round of APFloat changes. 
Use APFloat in UpgradeParser and AsmParser.
Change all references to ConstantFP to use the
APFloat interface rather than double.  Remove
the ConstantFP double interfaces.
Use APFloat functions for constant folding arithmetic
and comparisons.
(There are still way too many places APFloat is
just a wrapper around host float/double, but we're
getting there.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41747 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-06 18:13:44 +00:00
Evan Cheng
61d9c861fd Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen: 
leal    (,%rcx,8), %rcx
It should be
leal    (,%rcx,8), %ecx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41735 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-06 00:14:41 +00:00
Bill Wendling
399ea50dc3 LVXL and STVXL are also a load and store resp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41733 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-05 23:47:12 +00:00
Bill Wendling
c3536b8ecb Add the 64-bit versions of the DS* Altivec instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41717 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-05 04:05:20 +00:00
Evan Cheng
67c906dce7 Fix for PR1613: added 64-bit rotate left PPC instructions and patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41711 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-04 20:20:29 +00:00
Evan Cheng
29d62bebd9 Mac OS X X86-64 ABI is same as the standard. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41700 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-04 16:44:41 +00:00
Anton Korobeynikov
3825262399 Reapply r41578 with proper fix 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41680 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-03 00:36:06 +00:00
Dale Johannesen
ee8476847d Revise per review of previous patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41645 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-31 17:03:33 +00:00
Rafael Espindola
1b5dcc34b7 Initial support for calling functions with byval arguments on x86-64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41643 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-31 15:06:30 +00:00
Rafael Espindola
7240ae3cac Align i64 and f64 at 8 byte on x86-64. 
This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41642 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-31 12:23:58 +00:00
Dale Johannesen
eaf089430e Enhance APFloat to retain bits of NaNs (fixes oggenc). 
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-31 04:03:46 +00:00
Raul Herbster
8c132633c8 Instruction formats added used to generate multiply instructions of V5TE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41629 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:34:14 +00:00
Raul Herbster
b94e60872e Unused relocation type reloc_arm_absolute removed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41628 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:31:35 +00:00
Raul Herbster
9c1a3827ce Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41627 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:29:26 +00:00
Raul Herbster
37fb5b154c ARM instruction table was modified by adding information to generate multiply instruction of V5TE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41626 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:25:47 +00:00
Raul Herbster
d05c04c169 JITInfo now resolves function addrs and also relocations. It always emits a stub. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41625 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 23:21:27 +00:00
Evan Cheng
f4c3a59dba Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41599 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 05:54:07 +00:00
Evan Cheng
35b35c5c32 Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 05:52:20 +00:00
Evan Cheng
2f39426ec9 Mark load instructions with isLoad = 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41595 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 05:49:43 +00:00
Bill Wendling
b8a80f03bf Use i64 on a PPC64 machine 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41590 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 00:59:19 +00:00
Dale Johannesen
f04afdbb48 Change LegalFPImmediates to use APFloat. 
Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41587 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-30 00:23:21 +00:00
Duncan Sands
ee46574931 Move getX86RegNum into X86RegisterInfo and use it 
in the trampoline lowering.  Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41577 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-29 19:01:20 +00:00
Bruno Cardoso Lopes
51195af45f Added method to get Mips register numbers 
Changed the stack frame layout, StackGrowsUp fits better to Mips strange stack.
Stack offset calculation bug fixed!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41529 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-28 05:13:42 +00:00
Bruno Cardoso Lopes
a2b1bb5296 Changed stack allocation On LowerFORMAL_ARGUMENTS. 
Added comments about new stack allocation.
Expand SelectCC for i32 results


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41527 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-28 05:08:16 +00:00
Bruno Cardoso Lopes
dc0c04c0ed Mask directive completed with CalleeSave info 
Comments for Mips directives added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41526 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-28 05:06:17 +00:00
Bruno Cardoso Lopes
2d4575ea5a Added methods to record SPOffsets from LowerFORMAL_ARGUMENTS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41525 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-28 05:04:41 +00:00
Rafael Espindola
44c8265cf8 Add a comment about using libc memset/memcpy or generating inline code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41502 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-27 17:48:26 +00:00
Rafael Espindola
6b83b5d1ae call libc memcpy/memset if array size is bigger then threshold. 
Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41479 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-27 10:18:20 +00:00
Chris Lattner
48884cd80b rename isOperandValidForConstraint to LowerAsmOperandForConstraint, 
changing the interface to allow for future changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41384 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-25 00:47:38 +00:00
Chris Lattner
90e167a908 Disable EH generation until PPC works 100%. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41360 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-24 16:00:15 +00:00
Chris Lattner
b23f4c5f44 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41359 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-24 15:17:59 +00:00
Chris Lattner
9e43d6316f add some notes on really poor codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41319 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-23 15:22:07 +00:00
Chris Lattner
aabd0359a3 new example 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41318 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-23 15:16:03 +00:00
Bill Wendling
adbda021e7 Add the PCSymbol for Darwin x86 platforms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41284 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-22 18:44:05 +00:00
Bruno Cardoso Lopes
84f47c52fd InlineAsm asm support for integer registers added 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41225 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-21 16:09:25 +00:00
Bruno Cardoso Lopes
edeede2bb5 Instruction Itinerary attribution fixed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41224 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-21 16:06:45 +00:00
Anton Korobeynikov
095546ce34 Use only 1 knob to enable exceptions on Darwin :). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41208 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-21 00:31:30 +00:00
Rafael Espindola
21485be444 Partial implementation of calling functions with byval arguments: 
*) The needed information is propagated to the DAG
 *) The X86-64 backend detects it and aborts


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41179 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-20 15:18:24 +00:00
Chris Lattner
cf8ba696b3 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41178 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-20 02:14:33 +00:00
Bruno Cardoso Lopes
9710536b44 MipsHi now has ouput flag 
MipsAdd SDNode created to add support to an Add opcode which supports input flag
Added an instruction itinerary to all instruction classes
Added branches with zero cond codes
Now call clobbers all non-callee saved registers
Call w/ register support added
Added DelaySlot to branch and load instructions
Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41161 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 02:37:46 +00:00
Bruno Cardoso Lopes
055c7eb4a4 Fixed stack frame addressing bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41160 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 02:19:09 +00:00
Bruno Cardoso Lopes
6d32ca0762 support for Schedule included on Mips.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41159 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 02:18:07 +00:00
Bruno Cardoso Lopes
7ff6fa2503 Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress 
fixed to generate instructions (add, lui) glued!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41158 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 02:16:30 +00:00
Bruno Cardoso Lopes
250a1714be Couple of small changes. Delay Slot handle header declared. 
Newline added after macros at function init on generated asm!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41157 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 02:05:24 +00:00
Bruno Cardoso Lopes
e88c36819e Added InstrItinClass support for instruction formats 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41156 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 02:01:28 +00:00
Bruno Cardoso Lopes
0b2cd89a39 Branch Analysis and InsertNoop inserted into header files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41155 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 01:59:45 +00:00
Bruno Cardoso Lopes
aff42dcf5d createMipsDelaySlotFillerPass added to mips codegen runtime 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41154 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 01:58:15 +00:00
Bruno Cardoso Lopes
35d2a47994 Added Branch Analysis support 
Added InsertNoop support


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41153 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 01:56:48 +00:00
Bruno Cardoso Lopes
de6a9411db LowerRETURNADDR removed since it was wrong and does not have utility yet! 
MipsAdd opcode added


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41152 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 01:54:09 +00:00
Bruno Cardoso Lopes
13d1b7bbb3 InstrItineraryData support on added. 
Added Mips3 ISA feature (needed when supporting R4000 machines)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41151 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 01:52:27 +00:00
Bruno Cardoso Lopes
9684a697d5 A Pass to insert Nops on intructions with DelaySlot 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41150 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 01:50:47 +00:00
Bruno Cardoso Lopes
a5793899e3 Mips generic fallback instruction schedule support! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41149 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-18 01:46:44 +00:00
Anton Korobeynikov
a2780e11ef Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixed 
hard to catch bugs with retaddr lowering


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41104 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-15 17:12:32 +00:00
Chris Lattner
d42b8be3da add a note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41103 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-15 16:58:38 +00:00
Evan Cheng
12914380ed Fix a typo pointd out by Maarten ter Huurne. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41059 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-13 23:27:11 +00:00
Dan Gohman
badb2d23d1 When x86 addresses matching exceeds its recursion limit, check to 
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41049 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-13 20:03:06 +00:00
Chris Lattner
a45d9a15ba Fix PR1607 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41048 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-13 18:42:37 +00:00
Chris Lattner
ace2e8ad0c expand a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41021 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-11 18:19:07 +00:00
Chris Lattner
384f4a94f8 With evan's explicit flag representation, hopefully we will finally be 
able to 3-addressify away stuff like this:

        movl    %ecx, %eax
        decl    %eax



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41020 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-11 18:16:46 +00:00
Bill Wendling
01284b4d55 64-bit SSSE3 ops that use MMX registers don't require 16-byte alignment. 
Make a 'memop' pattern just for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41017 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-11 09:52:53 +00:00
Christopher Lamb
a1eb155e52 Use subregs to improve any_extend code generation when feasible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41013 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 22:22:41 +00:00
Christopher Lamb
c59e52108b Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41010 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 21:48:46 +00:00
Christopher Lamb
6f41435879 Edit README in light of previous LEA16 commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41009 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 21:29:05 +00:00
Christopher Lamb
b81337117c Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41007 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 21:18:25 +00:00
Rafael Espindola
594d37e21a propagate struct size and alignment of byval arguments to the DAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40986 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 14:44:42 +00:00
Bill Wendling
ae9671b838 For kicks, I though it would be fun to use the correct opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40985 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 09:00:17 +00:00
Bill Wendling
76d708b76f Adding SSSE3 intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 06:22:27 +00:00
Evan Cheng
a3231ba237 Temporarily backing out this change until we know why some dejagnu tests are failing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40973 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 22:25:35 +00:00
Evan Cheng
f7ef26e701 divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40972 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 21:59:35 +00:00
Evan Cheng
a333b41af9 GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40970 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 18:05:17 +00:00
Dale Johannesen
5411a3937f long double 9 of N. This finishes up the X86-32 bits 
(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40958 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 01:04:01 +00:00
Dale Johannesen
48bd15ed72 Fix arguments for some Altivec instructions. From SWB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40957 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 00:49:19 +00:00
Dale Johannesen
84109cd015 Fix spelling of mtvscr and mfvscr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40908 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 23:08:00 +00:00
Dale Johannesen
cdbe4d3ebe Long double patch 8 of N: make it partially work in 
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40906 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 20:29:26 +00:00
Evan Cheng
0ff94f7fcc Initial JIT support for ARM by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 01:37:15 +00:00
Dale Johannesen
a996d52e37 Long double patch 7 of N, unless I lost count:). 
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40886 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 01:17:37 +00:00
Dale Johannesen
9989a65693 Replace 4-line function with 10-line version per review comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40881 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-06 22:10:35 +00:00
Dale Johannesen
27f92be8b7 Move lengthy conditional down 1 level per review comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40878 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-06 21:48:35 +00:00
Dale Johannesen
6a30811d5c Get X86 long double calling convention to work 
(on Darwin, anyway).  Fix some table omissions for
LD arithmetic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40877 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-06 21:31:06 +00:00
Dale Johannesen
88835735f4 Make 80-bit store maintain simulated FP stack correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40868 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-06 19:50:32 +00:00
Reid Spencer
181b6c9cb5 Fix minor doxygen nits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40854 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-05 20:06:04 +00:00
Dale Johannesen
59a587337e Long double patch 4 of N: initial x87 implementation. 
Lots of problems yet but some simple things work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40847 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-05 18:49:15 +00:00
Chandler Carruth
6994040a95 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. 
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40807 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-04 01:51:18 +00:00
Dale Johannesen
8c78a26955 Make x86 long double alignment 32 for everything but 
Darwin (which makes size within a struct==96)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40796 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-03 22:46:15 +00:00
Dale Johannesen
8c1e6a119a long double patch 2 of N. Handle it in TargetData. 
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40792 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-03 20:20:50 +00:00
Chris Lattner
107f54a002 add an observation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40772 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-03 00:17:42 +00:00
Dan Gohman
61e729e2e9 More explicit keywords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 21:21:54 +00:00
Dan Gohman
7f55fcbc6b Fix the alignment requirements of several unpck and shuf instructions. 
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40756 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 21:17:01 +00:00
Dan Gohman
f3372d1d64 Fix pastos in vector arithmetic intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40754 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 21:06:40 +00:00
Dan Gohman
73a902b228 Mark the SSE and MMX load instructions that 
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40736 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 14:27:55 +00:00
Evan Cheng
7afa166c76 Switch some multiplication instructions over to the new scheme for testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40723 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 05:48:35 +00:00
Evan Cheng
5278784621 Can't handle offset and scale if rip-relative addressing is to be used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40703 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 23:46:47 +00:00
Evan Cheng
0db079e2e6 Mac OS X X86-64 low 4G address not available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40702 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 23:46:10 +00:00
Evan Cheng
f6844ca0e4 Mac OS X X86-64 low 4G address not available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40701 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 23:45:51 +00:00
Evan Cheng
caf778ab3b Some out operands were incorrectly specified as input operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40697 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 23:07:38 +00:00
Evan Cheng
c5dd54154a Missing Requires. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40691 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 21:42:24 +00:00
Evan Cheng
1c3017c51e Be more precise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40689 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 20:22:37 +00:00
Dan Gohman
a9f643432d Change a .size directive to use a tab instead of a space, for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40672 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 14:42:30 +00:00
Evan Cheng
7fc77611ef Indexed loads each has 2 outputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40658 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 00:12:08 +00:00
Dan Gohman
b1576f56c8 Change the x86 assembly output to use tab characters to separate the 
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40648 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-31 20:11:57 +00:00
Evan Cheng
c64a1a921c Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40628 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-31 08:04:03 +00:00
Evan Cheng
4ebcc8c2f8 This isn't safe when there are uses of load's chain result. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40617 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-31 06:21:44 +00:00
Dan Gohman
825811dc83 Use tabs more consistently in assembler pseudo-ops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40594 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-30 15:08:02 +00:00
Dan Gohman
fb71d38247 Fix the comment for getClosestTargetForJIT to reflect the fact that 
it does not have a Module parameter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40590 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-30 14:58:59 +00:00
Dan Gohman
f452207d20 More explicit keywords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40589 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-30 14:51:59 +00:00
Evan Cheng
66ffe6be0c Vector fneg must be expanded into fsub -0.0, X. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40586 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-30 07:51:22 +00:00
Christopher Lamb
2dc6dc619c Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40578 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-29 01:24:57 +00:00
Christopher Lamb
f9b90ea955 Add register info needed to use subreg sets on X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40572 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-28 19:03:30 +00:00
Duncan Sands
b116fac90f Trampoline codegen support for X86-32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40566 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-27 20:02:49 +00:00
Dan Gohman
d300622eba Re-apply 40504, but with a fix for the segfault it caused in oggenc: 
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40555 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-27 17:16:43 +00:00
Duncan Sands
36397f5034 Support for trampolines, except for X86 codegen which is 
still under discussion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-27 12:58:54 +00:00
Evan Cheng
3e22947d9a Reverting 40504 for now. It's breaking oggenc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40547 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-27 01:37:47 +00:00
Evan Cheng
fcc8793dc8 Make sure epilogue esp adjustment is placed before any terminator and pop instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40538 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 17:45:41 +00:00
Evan Cheng
85dce6cf78 Don't pollute the meaning of isUnpredicatedTerminator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40537 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 17:32:14 +00:00
Evan Cheng
cf5543c47e Minor bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40535 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 17:02:45 +00:00
Dan Gohman
b6bbe39ff9 In the .loc directive, print the fields as "debug" fields, so they 
don't get decorated as if for immediate fields for instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40529 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 15:24:15 +00:00
Dan Gohman
1704c2f9b9 Fix a whitespace difference between CMPSSrr and CMPSDrr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40528 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 15:11:50 +00:00
Christopher Lamb
08d52071ba Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 07:48:21 +00:00
Evan Cheng
518143d795 Same goes for constantpool, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40517 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 07:35:15 +00:00
Christopher Lamb
557c3631d3 Add selection DAG nodes for subreg insert/extract. PR1350 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40516 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 07:34:40 +00:00
Dan Gohman
d3283832aa Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the 
x86 target, replacing them with the new alignment attributes on memory
references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40504 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-26 00:31:09 +00:00
Evan Cheng
a49ed78c27 Mac OS X x86-64 lower 4G address is not available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40502 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-25 23:41:36 +00:00
Evan Cheng
ad5e9cac02 Mac OS X should use 0x90 to fill in gaps to satisfy function alignment requirements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40501 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-25 23:36:05 +00:00
Evan Cheng
d88ea4d9aa Functions with LinkOnce and weak linkage still need to be aligned. Doh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40499 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-25 22:28:16 +00:00
Dan Gohman
b8275a3f6f Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-25 19:33:14 +00:00
Nick Lewycky
e2b905232f Fix debug info and globals filled with zeros. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40483 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-25 03:48:45 +00:00
Anton Korobeynikov
59db3ec935 Minor cleanup: 
- Split EH and debug infiormation
 - Make DwarfWriter more verbose in some cases


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40481 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-25 00:06:28 +00:00
Dan Gohman
dc9b3d0bb5 Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40480 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-24 23:00:27 +00:00
Dan Gohman
a394117bc0 Use movaps to load a v4f32 build_vector of all-constant values into a 
register instead of loading each element individually.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40478 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-24 22:55:08 +00:00
Anton Korobeynikov
d97b8cd38c Heal EH handling stuff by emitting correct offsets to callee-saved registers. 
Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40472 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-24 21:07:39 +00:00
Dan Gohman
275769a77a Fix some uses of dyn_cast to be uses of cast. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40443 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-23 20:24:29 +00:00
Dan Gohman
63491b2e15 Delete the svn:executable property on these files, which aren't executable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40441 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-23 19:26:08 +00:00
Bill Wendling
6a20cf0776 Add missing SSE builtins: 
__builtin_ia32_cvtss2si64
    __builtin_ia32_cvttss2si64
    __builtin_ia32_cvtsi642ss
    __builtin_ia32_cvtsd2si64
    __builtin_ia32_cvttsd2si64
    __builtin_ia32_cvtsi642sd


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-23 03:07:27 +00:00
Evan Cheng
ffbaccae02 No more noResults. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-21 00:34:19 +00:00
Evan Cheng
8bd6035750 Added -print-emitted-asm to print out JIT generated asm to cerr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-20 21:56:13 +00:00
Evan Cheng
b4162fd393 Because we promote SSE logical ops and loads to v2i64, we often end up generate 
code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40076 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-20 00:27:43 +00:00
Evan Cheng
d5f181a665 Oops. These stores actually produce results. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40074 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-20 00:20:46 +00:00
Evan Cheng
d4d01b71a7 Fix custom lowering of SSE FXOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40071 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 23:36:01 +00:00
Evan Cheng
31d3a65052 Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40070 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 23:34:10 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Evan Cheng
4558b807a2 Only adjust esp around calls in presence of alloca. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40030 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 00:42:58 +00:00
Evan Cheng
7e7bbf8271 Only adjust esp around calls in presence of alloca. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40028 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 00:42:05 +00:00
Evan Cheng
3c46eefba2 Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40018 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-18 21:26:06 +00:00
Dan Gohman
4106f3714e Implement initial memory alignment awareness for SSE instructions. Vector loads 
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40015 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-18 20:23:34 +00:00
Evan Cheng
b5cd24973c New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39998 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-18 08:21:49 +00:00
Evan Cheng
9b8c674432 Fold prologue esp update when possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39984 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 21:26:42 +00:00
Evan Cheng
5b3332cc27 Make sure not to break eh_return. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39978 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 18:40:47 +00:00
Evan Cheng
698b63862c Update. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39977 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 18:39:45 +00:00
Evan Cheng
f27795d174 Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39974 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 18:03:34 +00:00
Evan Cheng
89d1659cf2 Use push / pop for prologues and epilogues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39967 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 07:59:08 +00:00
Chris Lattner
c3dbe70ce7 no email addrs in file headers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39962 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-17 05:56:43 +00:00
Dan Gohman
07a96765da Fix comments about vectors to use the current wording. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39921 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-16 14:29:03 +00:00
Anton Korobeynikov
2365f51ed0 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-14 14:06:15 +00:00
Evan Cheng
03494d7c8f Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39843 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-13 23:55:50 +00:00
Dale Johannesen
e7e7d0d7e3 Skeleton of post-RA scheduler; doesn't do anything yet. 
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-13 17:13:54 +00:00
Chris Lattner
8dc4b59b85 Fix CodeGen/Generic/print-arith-fp.ll on sparc (PR1551) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39813 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-13 16:24:10 +00:00
Dale Johannesen
66a2a8f878 ARM: make branch folder remove unconditional branches 
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39782 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-12 16:45:35 +00:00
Chris Lattner
ca23e17adf another missed SSE optimization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39772 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-12 06:31:38 +00:00
Bruno Cardoso Lopes
a4e8200366 Added support for Mips specific GAS directives 
Fixed print immediate 
Fixed Identation on MipsISelDAGToDAG.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39764 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 23:24:41 +00:00
Bruno Cardoso Lopes
7b155fbd60 Added support for framepointer 
Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39763 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 23:21:31 +00:00
Bruno Cardoso Lopes
758dcca57a Now that stack is represented the right way, LOA starts at 0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39761 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 23:17:41 +00:00
Bruno Cardoso Lopes
2ab22d1b93 Fixed AddLiveOut issues 
FI's created the write way to represent Mips stack


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39760 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 23:16:16 +00:00
Bruno Cardoso Lopes
332a3d22a2 Removed unused immediate PatLeaf, fixed lui instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39759 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 22:47:02 +00:00
Bruno Cardoso Lopes
4215a59a76 Added MipsMachineFunction class, to hold Mips dinamic stack info when inserting Prologue/Epilog 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39758 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 22:44:21 +00:00
Lauro Ramos Venancio
a126bb71d5 Handle packed structs in the CBackend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39752 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 19:56:53 +00:00
Dale Johannesen
5d9c4b6020 Fix hang compiling TimberWolf (allow for islands 
of size other than 4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39743 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 18:32:38 +00:00
Lauro Ramos Venancio
75ce010f7b Assert when TLS is not implemented. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39737 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 17:19:51 +00:00
Chris Lattner
082ced9391 Fix an oversight: for modules with no other identifying target info, 
the sparc backend should be preferred when running on sparcs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39142 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-11 16:32:10 +00:00
Evan Cheng
8202010364 Didn't mean the last commit. Revert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38515 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 22:00:16 +00:00
Dale Johannesen
afdc7fda65 Fix fp_constant_op failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38514 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 21:53:30 +00:00
Evan Cheng
c608ff22e7 Update. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38513 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 21:49:47 +00:00
Dale Johannesen
bf6b8272b1 fix 80 columnn violations, increasing the world's 
pedantic satisfaction level.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38512 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 20:53:41 +00:00
Chris Lattner
36c5155d0f add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38507 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 20:03:50 +00:00
Evan Cheng
13ab020ea0 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:08:01 +00:00
Evan Cheng
2bf821c4bf Remove clobbersPred. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38500 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:07:08 +00:00
Dan Gohman
2038252c6a Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp, 
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38478 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 00:05:58 +00:00
Dan Gohman
532dc2e1f2 Change getCopyToParts and getCopyFromParts to always use target-endian 
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38471 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-09 20:59:04 +00:00
Chris Lattner
87bdba6d6a The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38463 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-09 17:25:29 +00:00
Evan Cheng
9ad6f03166 No need for ccop anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:34:09 +00:00
Evan Cheng
4b9cb7d135 Incorrect check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37962 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:23:19 +00:00
Evan Cheng
06aae67b83 Do away with ImmutablePredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37961 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:22:46 +00:00
Evan Cheng
14c4655403 isUnpredicatedTerminator should treat conditional branches as unpredicated terminator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37960 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:22:03 +00:00
Evan Cheng
49ce02e408 Do away with ImmutablePredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37959 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:21:02 +00:00
Rafael Espindola
1aa7efbd2c Add the byval attribute 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37940 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 10:57:03 +00:00
Evan Cheng
dfb2ebac29 Print the s bit if the instruction is toggled to its CPSR setting form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37932 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 01:01:34 +00:00
Evan Cheng
04c813d00c PredicateDefOperand -> OptionalDefOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37931 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 01:00:49 +00:00
Evan Cheng
e496d78f16 Add OptionalDefOperand to stand for optionally defined result. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37930 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 01:00:16 +00:00
Evan Cheng
148b6a419f Initial ARM JIT support by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37926 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 21:15:40 +00:00
Anton Korobeynikov
4304bcc1ed Proper flag __alloca call 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37923 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 20:36:08 +00:00
Evan Cheng
c48072fed5 Doh 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37917 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 17:21:33 +00:00
Evan Cheng
1f6d77b54a Unbreak the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37915 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 17:13:56 +00:00
Evan Cheng
d54874a06d Unbreak the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37914 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 17:13:19 +00:00
Gabor Greif
a99be51bf5 Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 17:07:56 +00:00
Chris Lattner
461d79c2ee the arm backend is not building, temporarily disable it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37911 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 16:11:52 +00:00
Evan Cheng
0e1d37904a Reflects the chanegs made to PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37898 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:18:20 +00:00
Evan Cheng
16b6598325 Added ARM::CPSR to represent ARM CPSR status register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37897 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:17:13 +00:00
Evan Cheng
ee568cf794 Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37896 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:15:27 +00:00
Evan Cheng
c85e832eb7 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:13:32 +00:00
Evan Cheng
3b5b8368f3 Added ARM::CPSR to represent ARM CPSR status register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37894 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:11:03 +00:00
Evan Cheng
7e36966de4 PPC conditional branch predicate does not change after isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37893 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:09:50 +00:00
Evan Cheng
2aa133ef72 - Added zero_reg def to stand for register 0. 
- Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37892 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:09:09 +00:00