marqs
73dd1963b9
update to Quartus 20.1.1
2021-07-31 18:06:21 +03:00
marqs
015f63ddff
display profile name on infoscreen
2020-11-10 20:09:18 +02:00
marqs
238cf0b285
update epcq_controller_mod to epcq_controller2
2020-11-10 19:46:07 +02:00
marqs
9c5e7b5b83
advanced OSD implementation
2020-10-05 23:05:43 +03:00
Russell Harmon
45b093d768
Set only HDMI_TX VREF pins to fast output.
...
From the Cyclone IV device handbook:
> When you use the VREF pin as a regular input or output, you can expect
> a reduced performance of toggle rate and tCO because of higher pin
> capacitance.
Previously, we had set all HDMI_TX pins to fast output, but doing so
produces some worrying timing violations which were masked over by
relaxation of the SDC constraints. With fast output enabled, actually
fixing the timing constraints would require substantial RTL
optimization.
Instead, by only setting fast output on the VREF pins, I'm able to avoid
the glitching that would occur without any fast output pins when
displaying high clock rate line3x output, while also allowing fitter
enough flexibility to avoid timing violations.
In addition, this commit restores the previously relaxed HDMI_TX timing
constraints to those documented in the IT6613 datasheet.
2020-06-21 19:56:34 +00:00
marqs
daf9ec1611
optimize line3x timing
2020-06-14 20:07:24 +03:00
Russell Harmon
c2b0687e7b
Set fast output on HDMI_TX pins.
...
Also adjust timing constraits to reflect working state with line3x at
162 MHz.
2020-06-14 09:54:06 +00:00
marqs
0c55cc03bb
use LEDs for debug in latency tester mode
2020-02-09 21:35:50 +02:00
marqs
a076c6d2db
update quartus to 19.1
2020-02-09 21:28:24 +02:00
marqs
aeb164dd2f
increase OSD width in line4x and 5x modes
2019-10-15 20:18:44 +03:00
marqs
8e7236dc00
timing optimizations
2019-10-10 01:00:48 +03:00
marqs
9feb96888b
fix PLL reference clock switchover logic
2019-10-09 23:58:55 +03:00
marqs
3771d5cb14
fix OSD size in certain modes
2019-10-08 01:08:18 +03:00
marqs
3a12592c53
fix linebuf read address timing bottleneck
2019-10-07 01:25:33 +03:00
marqs
9d496383c3
optimize clock network
...
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-06 23:54:32 +03:00
marqs
d1fd30019f
osd_generator: add M9K support to allow larger character array
2019-10-05 11:33:59 +03:00
marqs
a6bdd8cfab
free up 1 M9K by modifying altera_jtag_avalon_master
2019-10-03 23:47:59 +03:00
marqs
6266976114
first OSD implementation
2019-10-03 02:03:43 +03:00
marqs
077ce8afdc
update fitter seed to more optimal value
2019-09-28 12:16:32 +03:00
marqs
5e0277fb48
add Panasonic hack for improving line count tolerance with line2x
2019-07-01 19:15:57 +03:00
marqs
f0a14679d9
make H. samplerate fine-tuning more intuitive
2019-06-25 00:23:45 +03:00
marqs
125814225f
make sampling phase mode-specific
2019-05-08 00:05:16 +03:00
marqs
978ac04a43
add name to profile struct
2018-11-03 18:28:30 +02:00
marqs
76d69d19bf
switch to RV32E
2018-10-30 01:31:40 +02:00
paulb-nl
f276cda190
Add support for GBI 360p
2018-10-13 17:33:10 +02:00
marqs
0905620b4d
update qsys+bsp build logic and instructions
2018-10-11 00:04:32 +03:00
marqs
7914a2ee83
clean up and update README
2018-10-08 00:37:42 +03:00
marqs
22e49300df
fix line2x reverse LPF trigger
2018-04-18 23:14:24 +03:00
marqs
37650ca22b
misc improvements
...
* add character LCD backlight timeout option
* increase h.mask range
* show accurate (fpga-calculated) timings on infoscreen
2018-03-28 20:09:40 +03:00
marqs
9ad696dbc3
optimize away one pp stage and unify code formatting
2018-03-12 01:25:23 +02:00
borti4938
a58255b8d1
suggested fitter seed
2018-03-07 10:21:40 +01:00
borti4938
985aeb1a93
use explicite ramstyle for post-processing pipeline to keep registers in logic (as suggested in pull-request #21 comments)
2018-03-07 09:45:27 +01:00
borti4938
0828addc83
Merge branch 'release' of https://github.com/marqs85/ossc into upstream
2018-03-07 08:29:49 +01:00
marqs
0ab31b30b4
simplify timing constraints
2018-03-07 09:21:19 +02:00
borti4938
d89c06b987
some fitter seeds for the current implementation
2018-03-06 14:43:49 +01:00
borti4938
9ba41ec240
Alternative fitter seed for current design
2018-03-06 12:14:30 +01:00
borti4938
10eff56f28
Merge branch 'release' of https://github.com/marqs85/ossc into upstream
2018-03-06 09:41:59 +01:00
borti4938
670f515141
various post processing pipeline updates:
...
- increase number of pipeline stages for scanline generation
- alternative hybrid strength implementation
- add missing file declaration in qsf
2018-03-06 09:36:21 +01:00
borti4938
ba8ad6ce4c
add missing IP files
2018-03-06 09:33:28 +01:00
borti4938
0b51fd7758
- resolve conflicts from merge
...
- use hybrid contrast for both sl generation methods: multiplication and linear
2018-03-06 09:32:02 +01:00
borti4938
1a405c1e2e
Merge branch 'scanline_contrast' of https://github.com/paulb-nl/ossc into upstream
...
# Conflicts:
# rtl/scanconverter.v
# software/sys_controller/ossc/av_controller.c
2018-03-06 09:30:22 +01:00
marqs
bc1b7419f2
pcm1862: add pre-ADC gain setting
2018-03-02 23:11:52 +02:00
paulb-nl
990bc1563e
Add Scanline contrast
...
Reduce scanline strength for bright pixels
2018-02-24 21:56:18 +01:00
borti4938
5249d313d8
scanlines generation via multiplication
2018-02-22 08:11:26 +01:00
marqs
dd4ffde231
update to Quartus 17.1
2017-12-07 21:35:08 +02:00
marqs
a24d6b0e3a
Update latency tester
...
* Enable operation with all sources
* Measure strobe length on low-persistence displays
2017-10-28 12:10:54 +03:00
marqs
1bf279b2a7
Initial latency tester implementation
2017-10-22 22:45:29 +03:00
marqs
75e072d622
Revert some drive strength adjustments to meet timing requirements
2017-10-13 21:03:48 +03:00
marqs
76623292a9
Use lower FPGA pad drive strength on chip-to-chip connections
2017-10-12 02:32:59 +03:00
paulb-nl
ac16008076
Add reverse LPF feature
...
reverse LPF can be used to mostly reverse the blur on pre 1-CHIP SNES.
For best results use 256x240 optimized mode.
2017-09-27 22:43:26 +02:00
