Compare commits
123 Commits
| Author | SHA1 | Date |
|---|---|---|
Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Unknown
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Unknown
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Unknown
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Unknown
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Unknown
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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0f92b7cf03 | |
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freitz85
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505fe10434 | |
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Florian Reitz
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freitz85
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Florian Reitz
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freitz85
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Florian Reitz
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Florian Reitz
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freitz85
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freitz85
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Unknown
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freitz85
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Florian Reitz
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f20a1d529d | |
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freitz85
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freitz85
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freitz85
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freitz85
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freitz85
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freitz85
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freitz85
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freitz85
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freitz85
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freitz85
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freitz85
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freitz85
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freitz85
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Unknown
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freitz85
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Florian Reitz
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ff074dc995 | |
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Florian Reitz
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763a99022c | |
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Florian Reitz
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d0a9254893 | |
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Florian Reitz
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c438775789 |
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@ -3,6 +3,42 @@
|
|||
Thumbs.db
|
||||
.DS_Store
|
||||
|
||||
#Ignore files build by Visual Studio
|
||||
*.obj
|
||||
*.exe
|
||||
*.pdb
|
||||
*.user
|
||||
*.aps
|
||||
*.pch
|
||||
*.vspscc
|
||||
*_i.c
|
||||
*_p.c
|
||||
*.ncb
|
||||
*.suo
|
||||
*.tlb
|
||||
*.tlh
|
||||
*.bak
|
||||
*.cache
|
||||
*.ilk
|
||||
*.log
|
||||
[Bb]in
|
||||
[Dd]ebug*/
|
||||
*.lib
|
||||
*.sbr
|
||||
obj/
|
||||
[Rr]elease*/
|
||||
_ReSharper*/
|
||||
[Tt]est[Rr]esult*
|
||||
.vs/
|
||||
|
||||
*.opendb
|
||||
**/Debug
|
||||
*.db
|
||||
*.dbg
|
||||
*.lbl
|
||||
*.map
|
||||
Makefile\.options
|
||||
|
||||
# Ignore list for Eagle, a PCB layout tool
|
||||
|
||||
# Backup files
|
||||
|
|
@ -177,3 +213,14 @@ Hardware/SD_A2\.b\$1
|
|||
*.nga
|
||||
|
||||
*.tspec
|
||||
|
||||
|
||||
VHDL/_pace\.ucf
|
||||
|
||||
VHDL/AppleIISd\.tim
|
||||
|
||||
VHDL/AppleIISd\.jed
|
||||
|
||||
Firmware/AppleIISd.bin
|
||||
|
||||
Software/Flasher.bin
|
||||
|
|
|
|||
BIN
AppleIISd.bin
BIN
AppleIISd.bin
Binary file not shown.
|
|
@ -1,21 +0,0 @@
|
|||
Stückliste exportiert aus C:/Projekte/AppleIISd/trunk/Hardware/SD_A2.sch am 24.08.2017 17:37
|
||||
|
||||
Qty Value Device Package Parts Description
|
||||
1 A2-50PINSLOT1-3 A2-50PIN-SL1-3 ST1 Apple ][ Peripheral Card Connector
|
||||
1 LEDSQR2X5 LED2X5 LED1 LED
|
||||
1 MA03-1 MA03-1 SV1 PIN HEADER
|
||||
1 MA06-1 MA06-1 SV2 PIN HEADER
|
||||
6 100k R-EU_R0603 R0603 R3, R5, R6, R7, R9, R11 RESISTOR, European symbol
|
||||
6 100n C-EUC0603K C0603K C1, C3, C4, C5, C6, C7 CAPACITOR, European symbol
|
||||
1 104H-TDA0-R 104H-TDA0-R 104H-TDA0-R U$2
|
||||
1 10k R-EU_R0603 R0603 R10 RESISTOR, European symbol
|
||||
3 10n C-EUC0603K C0603K C8, C9, C10 CAPACITOR, European symbol
|
||||
1 1u CPOL-EU153CLV-0405 153CLV-0405 C2 POLARIZED CAPACITOR, European symbol
|
||||
1 200 R-EU_R0603 R0603 R1 RESISTOR, European symbol
|
||||
1 2716 / 2732 2716 DIL24 IC3 MEMORY
|
||||
1 330 R-EU_R0603 R0603 R2 RESISTOR, European symbol
|
||||
1 470 R-EU_R0603 R0603 R4 RESISTOR, European symbol
|
||||
1 68k R-EU_R0603 R0603 R8 RESISTOR, European symbol
|
||||
1 74HCT245N 74HCT245N DIL20 IC1 Octal BUS TRANSCEIVER, 3-state
|
||||
1 LM317 LM317TL 317TL IC2 VOLTAGE REGULATOR
|
||||
1 XC9572XL XC9572_S44 S44 IC4
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
:10000000A220A000A203A0FF2058FFBABD00018DCE
|
||||
:10001000F807290F853D0A0A0A0A852BAA2CFFCF6B
|
||||
:1000200020AECA9003A927002000C9C900F0010032
|
||||
:10003000A9018542A52BAA85436444A90885456486
|
||||
:100040004664472CFFCF20DDCA4C0108D82058FF5A
|
||||
:10005000BABD00018DF807290F853D0A0A0A0A85F5
|
||||
:100060002BAA2CFFCF20AECA9004A927801BA98001
|
||||
:100070003C83C0F022A542C900F010C901F00FC9AD
|
||||
:1000800002F00EC903F00DA90138604CC6CA4CDD60
|
||||
:10009000CA4C4BCB4CC1CB2000C9B0ED80D700007F
|
||||
:1000A0000000000000000000000000000000000050
|
||||
:1000B0000000000000000000000000000000000040
|
||||
:1000C0000000000000000000000000000000000030
|
||||
:1000D0000000000000000000000000000000000020
|
||||
:1000E0000000000000000000000000000000000010
|
||||
:1000F000000000000000000000000000FFFF174C9F
|
||||
:10010000D8A9039D81C0BD83C009019D83C0A907F3
|
||||
:100110009D82C0A00AA9FF9D80C03C81C010FB88C1
|
||||
:10012000D0F5BD83C029FE9D83C0A9C58540A9CB5C
|
||||
:10013000854120F0C92004CAC901D039A9D1854020
|
||||
:10014000A9CB854120F0C9201FCAC901D02AA9DD49
|
||||
:100150008540A9CB854120F0C92004CAA9E3854088
|
||||
:10016000A9CB854120F0C92004CAC901F0E0C9002B
|
||||
:10017000D0034CB2C94CDEC9A9DD8540A9CB85416D
|
||||
:1001800020F0C9A9E98540A9CB854120F0C9200408
|
||||
:10019000CAC901F0E3C900D0034CB2C9A9CB85405C
|
||||
:1001A000A9CB854120F0C92004CAC901F0F6C900D5
|
||||
:1001B000D02CA9D78540A9CB854120F0C92004CAFD
|
||||
:1001C000C900D01ABD83C009809D83C0BD81C0090C
|
||||
:1001D000049D81C018A000900838A02FB00338A05B
|
||||
:1001E00027BD83C009019D83C0A9009D82C098607E
|
||||
:1001F0005AA000B1409D80C03C81C010FBC8C00621
|
||||
:1002000090F17A60A9FF9D80C03C81C010FBBD8049
|
||||
:10021000C0853C2980D0EDA9FF9D80C0A53C602011
|
||||
:1002200004CA485AA004A9FF9D80C03C81C010FBAD
|
||||
:10023000BD80C04888D0EFA43D6899F805689978DA
|
||||
:10024000056899F804689978047AA9FF9D80C068C8
|
||||
:1002500060DA5AA63DA5469DF805A5479D7805A9F3
|
||||
:10026000009DF8049D7804A9802443F005A9019D10
|
||||
:10027000F804A0091EF8053E78053EF8043E78040F
|
||||
:1002800088D0F17AFA605AA43D9D80C0B978049D67
|
||||
:1002900080C0B9F8049D80C0B978059D80C0B9F8C8
|
||||
:1002A000059D80C0A9FF9D80C02004CA7A6048A92E
|
||||
:1002B000403C83C018F00138686048A9203C83C0E6
|
||||
:1002C00018F001386860A900A2FFA0FF20AECA9014
|
||||
:1002D00004A92F800720BACA9002A92B6020AECAB9
|
||||
:1002E000B0642051CABD83C029FE9D83C0A951209E
|
||||
:1002F00086CAC900D050A9FF9D80C0BD80C0C9FE7C
|
||||
:10030000D0F4A002BD81C009109D81C0A9FF9D80CD
|
||||
:10031000C0643CBD80C09244E644D002E645E63C61
|
||||
:10032000D0F188D0ECBD80C0BD80C0BD80C0BD8193
|
||||
:10033000C029EF9D81C018A9000848BD83C00901EC
|
||||
:100340009D83C068286038A92780EE20AECAB067B8
|
||||
:1003500020BACAB0672051CABD83C029FE9D83C0A0
|
||||
:10036000A9582086CAC900D04EA9FF9D80C0A9FE09
|
||||
:100370009D80C0A002643CB2449D80C0E644D0028F
|
||||
:10038000E645E63CD0F188D0EC9D80C09D80C09DC4
|
||||
:1003900080C0BD80C0291FC905D01C18A90008480D
|
||||
:1003A000A9FF9D80C0BD80C0C900F0F4BD83C00915
|
||||
:1003B000019D83C068286038A92780E238A92B8076
|
||||
:1003C000DD38A901604000000000954100000000F8
|
||||
:1003D000F948000001AA875000000200FF770000E2
|
||||
:0F03E0000000656940000000776900000000FF21
|
||||
:00000001FF
|
||||
833
AppleIISd.lst
833
AppleIISd.lst
|
|
@ -1,833 +0,0 @@
|
|||
1 ********************************
|
||||
2 *
|
||||
3 * Apple][Sd Firmware
|
||||
4 * Version 0.6
|
||||
5 *
|
||||
6 * (c) Florian Reitz, 2017
|
||||
7 *
|
||||
8 * X register usually contains SLOT16
|
||||
9 * Y register is used for counting or SLOT
|
||||
10 *
|
||||
11 ********************************
|
||||
12
|
||||
3-OCT-17 17:26
|
||||
14
|
||||
15 XC ; enable 65C02 code
|
||||
16 DEBUG = 0
|
||||
17 DO DEBUG
|
||||
18 ORG $8000
|
||||
19 ELSE
|
||||
20 ORG $C800 ; Expansion ROM
|
||||
21 FIN
|
||||
22
|
||||
23 * Memory defines
|
||||
24
|
||||
25 SLOT16 = $2B ; $s0 -> slot * 16
|
||||
26 WORK = $3C
|
||||
27 SLOT = $3D ; $0s
|
||||
28 CMDLO = $40
|
||||
29 CMDHI = $41
|
||||
30
|
||||
31 CURSLOT = $07F8 ; $Cs
|
||||
32 DATA = $C080
|
||||
33 CTRL = DATA+1
|
||||
34 DIV = DATA+2
|
||||
35 SS = DATA+3
|
||||
36 R30 = $0478
|
||||
37 R31 = $04F8
|
||||
38 R32 = $0578
|
||||
39 R33 = $05F8
|
||||
40
|
||||
41 * Constants
|
||||
42
|
||||
43 DUMMY = $FF
|
||||
44 FRX = $10 ; CTRL register
|
||||
45 ECE = $04
|
||||
46 SS0 = $01 ; SS register
|
||||
47 WP = $20
|
||||
48 CD = $40
|
||||
49 INITED = $80
|
||||
50
|
||||
51
|
||||
52 * signature bytes
|
||||
53
|
||||
C800: A2 20 54 LDX #$20
|
||||
C802: A0 00 55 LDY #$00
|
||||
C804: A2 03 56 LDX #$03
|
||||
C806: A0 FF 57 LDY #$FF ; neither 5.25 nor Smartport
|
||||
58
|
||||
59 * find slot nr
|
||||
60
|
||||
61 DO DEBUG
|
||||
62 LDA #$04
|
||||
63 STA SLOT
|
||||
64 LDA #$C4
|
||||
65 STA CURSLOT
|
||||
66 LDA #$40
|
||||
67 STA SLOT16
|
||||
68
|
||||
69 ELSE
|
||||
C808: 20 58 FF 70 JSR $FF58
|
||||
C80B: BA 71 TSX
|
||||
C80C: BD 00 01 72 LDA $0100,X
|
||||
C80F: 8D F8 07 73 STA CURSLOT ; $Cs
|
||||
C812: 29 0F 74 AND #$0F
|
||||
C814: 85 3D 75 STA SLOT ; $0s
|
||||
C816: 0A 76 ASL A
|
||||
C817: 0A 77 ASL A
|
||||
C818: 0A 78 ASL A
|
||||
C819: 0A 79 ASL A
|
||||
C81A: 85 2B 80 STA SLOT16 ; $s0
|
||||
81 FIN
|
||||
82
|
||||
C81C: AA 83 TAX ; X holds now SLOT16
|
||||
C81D: 2C FF CF 84 BIT $CFFF
|
||||
C820: 20 AE CA 85 JSR CARDDET
|
||||
C823: 90 03 86 BCC :INIT
|
||||
C825: A9 27 87 LDA #$27 ; no card inserted
|
||||
C827: 00 88 BRK
|
||||
89
|
||||
C828: 20 00 C9 90 :INIT JSR INIT
|
||||
91
|
||||
92
|
||||
93 ********************************
|
||||
94 *
|
||||
95 * Install SD card driver
|
||||
96 *
|
||||
97 ********************************
|
||||
98
|
||||
99 DO DEBUG
|
||||
100
|
||||
101 * see if slot has a driver already
|
||||
102
|
||||
103 LDX $BF31 ; get devcnt
|
||||
104 INSTALL LDA $BF32,X ; get a devnum
|
||||
105 AND #$70 ; isolate slot
|
||||
106 CMP SLOT16 ; slot?
|
||||
107 BEQ :INSOUT ; yes, skip it
|
||||
108 DEX
|
||||
109 BPL INSTALL ; keep up the search
|
||||
110
|
||||
111 * restore the devnum to the list
|
||||
112
|
||||
113 LDX $BF31 ; get devcnt again
|
||||
114 CPX #$0D ; device table full?
|
||||
115 BNE :INST2
|
||||
116
|
||||
117 JSR $FF3A ; bell
|
||||
118 JMP :INSOUT ; do something!
|
||||
119
|
||||
120 :INST2 LDA $BF32-1,X ; move all entries down
|
||||
121 STA $BF32,X ; to make room at front
|
||||
122 DEX ; for a new entry
|
||||
123 BNE :INST2
|
||||
124 LDA #$04 ; ProFile type device
|
||||
125 ORA SLOT16
|
||||
126 STA $BF32 ; slot, drive 1 at top of list
|
||||
127 INC $BF31 ; update devcnt
|
||||
128
|
||||
129 * now insert the device driver vector
|
||||
130
|
||||
131 LDA SLOT
|
||||
132 ASL
|
||||
133 TAX
|
||||
134 LDA #<DRIVER
|
||||
135 STA $BF10,X ; write to driver table
|
||||
136 LDA #>DRIVER
|
||||
137 STA $BF11,X
|
||||
138 :INSOUT RTS
|
||||
139
|
||||
140
|
||||
141 ********************************
|
||||
142 *
|
||||
143 * Boot from SD card
|
||||
144 *
|
||||
145 ********************************
|
||||
146
|
||||
147 ELSE
|
||||
148
|
||||
C82B: C9 00 149 BOOT CMP #0 ; check for error
|
||||
C82D: F0 01 150 BEQ :BOOT1
|
||||
C82F: 00 151 BRK
|
||||
152
|
||||
C830: A9 01 153 :BOOT1 LDA #$01
|
||||
C832: 85 42 154 STA $42 ; load command
|
||||
C834: A5 2B 155 LDA SLOT16
|
||||
C836: AA 156 TAX
|
||||
C837: 85 43 157 STA $43 ; slot number
|
||||
C839: 64 44 158 STZ $44 ; buffer lo
|
||||
C83B: A9 08 159 LDA #$08
|
||||
C83D: 85 45 160 STA $45 ; buffer hi
|
||||
C83F: 64 46 161 STZ $46 ; block lo
|
||||
C841: 64 47 162 STZ $47 ; block hi
|
||||
C843: 2C FF CF 163 BIT $CFFF
|
||||
C846: 20 DD CA 164 JSR READ ; call driver
|
||||
C849: 4C 01 08 165 JMP $801 ; goto bootloader
|
||||
166
|
||||
167 FIN
|
||||
168
|
||||
169
|
||||
170 ********************************
|
||||
171 *
|
||||
172 * Jump table
|
||||
173 *
|
||||
174 ********************************
|
||||
175
|
||||
C84C: D8 176 DRIVER CLD
|
||||
177
|
||||
178 DO DEBUG
|
||||
179 LDA #$04
|
||||
180 STA SLOT
|
||||
181 LDA #$C4
|
||||
182 STA CURSLOT
|
||||
183 LDA #$40
|
||||
184 STA SLOT16
|
||||
185
|
||||
186 ELSE
|
||||
C84D: 20 58 FF 187 JSR $FF58 ; find slot nr
|
||||
C850: BA 188 TSX
|
||||
C851: BD 00 01 189 LDA $0100,X
|
||||
C854: 8D F8 07 190 STA CURSLOT ; $Cs
|
||||
C857: 29 0F 191 AND #$0F
|
||||
C859: 85 3D 192 STA SLOT ; $0s
|
||||
C85B: 0A 193 ASL A
|
||||
C85C: 0A 194 ASL A
|
||||
C85D: 0A 195 ASL A
|
||||
C85E: 0A 196 ASL A
|
||||
C85F: 85 2B 197 STA SLOT16 ; $s0
|
||||
198 FIN
|
||||
199
|
||||
C861: AA 200 TAX ; X holds now SLOT16
|
||||
C862: 2C FF CF 201 BIT $CFFF
|
||||
C865: 20 AE CA 202 JSR CARDDET
|
||||
C868: 90 04 203 BCC :INITED
|
||||
C86A: A9 27 204 LDA #$27 ; no card inserted
|
||||
C86C: 80 1B 205 BRA :DONE
|
||||
206
|
||||
C86E: A9 80 207 :INITED LDA #INITED ; check for init
|
||||
C870: 3C 83 C0 208 BIT SS,X
|
||||
C873: F0 22 209 BEQ :INIT
|
||||
210
|
||||
C875: A5 42 211 :CMD LDA $42 ; get command
|
||||
C877: C9 00 212 CMP #0
|
||||
C879: F0 10 213 BEQ :STATUS
|
||||
C87B: C9 01 214 CMP #1
|
||||
C87D: F0 0F 215 BEQ :READ
|
||||
C87F: C9 02 216 CMP #2
|
||||
C881: F0 0E 217 BEQ :WRITE
|
||||
C883: C9 03 218 CMP #3
|
||||
C885: F0 0D 219 BEQ :FORMAT
|
||||
C887: A9 01 220 LDA #1 ; unknown command
|
||||
221
|
||||
C889: 38 222 :DONE SEC
|
||||
C88A: 60 223 RTS
|
||||
224
|
||||
C88B: 4C C6 CA 225 :STATUS JMP STATUS
|
||||
C88E: 4C DD CA 226 :READ JMP READ
|
||||
C891: 4C 4B CB 227 :WRITE JMP WRITE
|
||||
C894: 4C C1 CB 228 :FORMAT JMP FORMAT
|
||||
C897: 20 00 C9 229 :INIT JSR INIT
|
||||
C89A: B0 ED 230 BCS :DONE ; init failure
|
||||
C89C: 80 D7 231 BRA :CMD
|
||||
232
|
||||
233
|
||||
234 * Signature bytes
|
||||
235
|
||||
C89E: 00 00 00 236 DS \ ; fill with zeroes
|
||||
C8A1: 00 00 00 00
|
||||
C8A5: 00 00 00 00
|
||||
C8A9: 00 00 00 00
|
||||
C8AD: 00 00 00 00
|
||||
C8B1: 00 00 00 00
|
||||
C8B5: 00 00 00 00
|
||||
C8B9: 00 00 00 00
|
||||
C8BD: 00 00 00 00
|
||||
C8C1: 00 00 00 00
|
||||
C8C5: 00 00 00 00
|
||||
C8C9: 00 00 00 00
|
||||
C8CD: 00 00 00 00
|
||||
C8D1: 00 00 00 00
|
||||
C8D5: 00 00 00 00
|
||||
C8D9: 00 00 00 00
|
||||
C8DD: 00 00 00 00
|
||||
C8E1: 00 00 00 00
|
||||
C8E5: 00 00 00 00
|
||||
C8E9: 00 00 00 00
|
||||
C8ED: 00 00 00 00
|
||||
C8F1: 00 00 00 00
|
||||
C8F5: 00 00 00 00
|
||||
C8F9: 00 00 00 00
|
||||
C8FD: 00 00 00
|
||||
237 DS -4 ; locate to $xxFC
|
||||
C8FC: FF FF 238 DW $FFFF ; 65535 blocks
|
||||
C8FE: 17 239 DB $17 ; Status bits
|
||||
C8FF: 4C 240 DB #<DRIVER ; LSB of driver
|
||||
241
|
||||
242
|
||||
243 ********************************
|
||||
244 *
|
||||
245 * Initialize SD card
|
||||
246 *
|
||||
247 * C Clear - No error
|
||||
248 * Set - Error
|
||||
249 * A $00 - No error
|
||||
250 * $27 - I/O error - Init failed
|
||||
251 * $2F - No card inserted
|
||||
252 *
|
||||
253 ********************************
|
||||
254
|
||||
C900: D8 255 INIT CLD
|
||||
C901: A9 03 256 LDA #$03 ; set SPI mode 3
|
||||
C903: 9D 81 C0 257 STA CTRL,X
|
||||
C906: BD 83 C0 258 LDA SS,X
|
||||
C909: 09 01 259 ORA #SS0 ; set CS high
|
||||
C90B: 9D 83 C0 260 STA SS,X
|
||||
C90E: A9 07 261 LDA #7
|
||||
C910: 9D 82 C0 262 STA DIV,X
|
||||
C913: A0 0A 263 LDY #10
|
||||
C915: A9 FF 264 LDA #DUMMY
|
||||
265
|
||||
C917: 9D 80 C0 266 :LOOP STA DATA,X
|
||||
C91A: 3C 81 C0 267 :WAIT BIT CTRL,X
|
||||
C91D: 10 FB 268 BPL :WAIT
|
||||
C91F: 88 269 DEY
|
||||
C920: D0 F5 270 BNE :LOOP ; do 10 times
|
||||
C922: BD 83 C0 271 LDA SS,X
|
||||
C925: 29 FE 272 AND #$FF!SS0 ; set CS low
|
||||
C927: 9D 83 C0 273 STA SS,X
|
||||
274
|
||||
C92A: A9 C5 275 LDA #<CMD0 ; send CMD0
|
||||
C92C: 85 40 276 STA CMDLO
|
||||
C92E: A9 CB 277 LDA #>CMD0
|
||||
C930: 85 41 278 STA CMDHI
|
||||
C932: 20 F0 C9 279 JSR CMD
|
||||
C935: 20 04 CA 280 JSR GETR1 ; get response
|
||||
C938: C9 01 281 CMP #$01
|
||||
C93A: D0 39 282 BNE :ERROR1 ; error!
|
||||
283
|
||||
C93C: A9 D1 284 LDA #<CMD8 ; send CMD8
|
||||
C93E: 85 40 285 STA CMDLO
|
||||
C940: A9 CB 286 LDA #>CMD8
|
||||
C942: 85 41 287 STA CMDHI
|
||||
C944: 20 F0 C9 288 JSR CMD
|
||||
C947: 20 1F CA 289 JSR GETR3
|
||||
C94A: C9 01 290 CMP #$01
|
||||
C94C: D0 2A 291 BNE :SDV1 ; may be SD Ver. 1
|
||||
292
|
||||
293 * check for $01aa match!
|
||||
C94E: A9 DD 294 :SDV2 LDA #<CMD55
|
||||
C950: 85 40 295 STA CMDLO
|
||||
C952: A9 CB 296 LDA #>CMD55
|
||||
C954: 85 41 297 STA CMDHI
|
||||
C956: 20 F0 C9 298 JSR CMD
|
||||
C959: 20 04 CA 299 JSR GETR1
|
||||
C95C: A9 E3 300 LDA #<ACMD4140
|
||||
C95E: 85 40 301 STA CMDLO
|
||||
C960: A9 CB 302 LDA #>ACMD4140
|
||||
C962: 85 41 303 STA CMDHI
|
||||
C964: 20 F0 C9 304 JSR CMD
|
||||
C967: 20 04 CA 305 JSR GETR1
|
||||
C96A: C9 01 306 CMP #$01
|
||||
C96C: F0 E0 307 BEQ :SDV2 ; wait for ready
|
||||
C96E: C9 00 308 CMP #$00
|
||||
C970: D0 03 309 BNE :ERROR1 ; error!
|
||||
310 * send CMD58
|
||||
311 * SD Ver. 2 initialized!
|
||||
C972: 4C B2 C9 312 JMP :BLOCKSZ
|
||||
313
|
||||
C975: 4C DE C9 314 :ERROR1 JMP :IOERROR ; needed for far jump
|
||||
315
|
||||
C978: A9 DD 316 :SDV1 LDA #<CMD55
|
||||
C97A: 85 40 317 STA CMDLO
|
||||
C97C: A9 CB 318 LDA #>CMD55
|
||||
C97E: 85 41 319 STA CMDHI
|
||||
C980: 20 F0 C9 320 JSR CMD ; ignore response
|
||||
C983: A9 E9 321 LDA #<ACMD410
|
||||
C985: 85 40 322 STA CMDLO
|
||||
C987: A9 CB 323 LDA #>ACMD410
|
||||
C989: 85 41 324 STA CMDHI
|
||||
C98B: 20 F0 C9 325 JSR CMD
|
||||
C98E: 20 04 CA 326 JSR GETR1
|
||||
C991: C9 01 327 CMP #$01
|
||||
C993: F0 E3 328 BEQ :SDV1 ; wait for ready
|
||||
C995: C9 00 329 CMP #$00
|
||||
C997: D0 03 330 BNE :MMC ; may be MMC card
|
||||
331 * SD Ver. 1 initialized!
|
||||
C999: 4C B2 C9 332 JMP :BLOCKSZ
|
||||
333
|
||||
C99C: A9 CB 334 :MMC LDA #<CMD1
|
||||
C99E: 85 40 335 STA CMDLO
|
||||
C9A0: A9 CB 336 LDA #>CMD1
|
||||
C9A2: 85 41 337 STA CMDHI
|
||||
C9A4: 20 F0 C9 338 :LOOP1 JSR CMD
|
||||
C9A7: 20 04 CA 339 JSR GETR1
|
||||
C9AA: C9 01 340 CMP #$01
|
||||
C9AC: F0 F6 341 BEQ :LOOP1 ; wait for ready
|
||||
C9AE: C9 00 342 CMP #$00
|
||||
C9B0: D0 2C 343 BNE :IOERROR ; error!
|
||||
344 * MMC Ver. 3 initialized!
|
||||
345
|
||||
C9B2: A9 D7 346 :BLOCKSZ LDA #<CMD16
|
||||
C9B4: 85 40 347 STA CMDLO
|
||||
C9B6: A9 CB 348 LDA #>CMD16
|
||||
C9B8: 85 41 349 STA CMDHI
|
||||
C9BA: 20 F0 C9 350 JSR CMD
|
||||
C9BD: 20 04 CA 351 JSR GETR1
|
||||
C9C0: C9 00 352 CMP #$00
|
||||
C9C2: D0 1A 353 BNE :IOERROR ; error!
|
||||
354
|
||||
C9C4: BD 83 C0 355 :END LDA SS,X
|
||||
C9C7: 09 80 356 ORA #INITED ; initialized
|
||||
C9C9: 9D 83 C0 357 STA SS,X
|
||||
C9CC: BD 81 C0 358 LDA CTRL,X
|
||||
C9CF: 09 04 359 ORA #ECE ; enable 7MHz
|
||||
C9D1: 9D 81 C0 360 STA CTRL,X
|
||||
C9D4: 18 361 CLC ; all ok
|
||||
C9D5: A0 00 362 LDY #0
|
||||
C9D7: 90 08 363 BCC :END1
|
||||
C9D9: 38 364 :CDERROR SEC
|
||||
C9DA: A0 2F 365 LDY #$2F ; no card error
|
||||
C9DC: B0 03 366 BCS :END1
|
||||
C9DE: 38 367 :IOERROR SEC
|
||||
C9DF: A0 27 368 LDY #$27 ; init error
|
||||
C9E1: BD 83 C0 369 :END1 LDA SS,X ; set CS high
|
||||
C9E4: 09 01 370 ORA #SS0
|
||||
C9E6: 9D 83 C0 371 STA SS,X
|
||||
C9E9: A9 00 372 LDA #0 ; set div to 2
|
||||
C9EB: 9D 82 C0 373 STA DIV,X
|
||||
C9EE: 98 374 TYA ; retval in A
|
||||
C9EF: 60 375 RTS
|
||||
376
|
||||
377
|
||||
378 ********************************
|
||||
379 *
|
||||
380 * Send SD command
|
||||
381 * Call with command in CMDHI and CMDLO
|
||||
382 *
|
||||
383 ********************************
|
||||
384
|
||||
C9F0: 5A 385 CMD PHY
|
||||
C9F1: A0 00 386 LDY #0
|
||||
C9F3: B1 40 387 :LOOP LDA (CMDLO),Y
|
||||
C9F5: 9D 80 C0 388 STA DATA,X
|
||||
C9F8: 3C 81 C0 389 :WAIT BIT CTRL,X ; TC is in N
|
||||
C9FB: 10 FB 390 BPL :WAIT
|
||||
C9FD: C8 391 INY
|
||||
C9FE: C0 06 392 CPY #6
|
||||
CA00: 90 F1 393 BCC :LOOP
|
||||
CA02: 7A 394 PLY
|
||||
CA03: 60 395 RTS
|
||||
396
|
||||
397
|
||||
398 ********************************
|
||||
399 *
|
||||
400 * Get R1
|
||||
401 * R1 is in A
|
||||
402 *
|
||||
403 ********************************
|
||||
404
|
||||
CA04: A9 FF 405 GETR1 LDA #DUMMY
|
||||
CA06: 9D 80 C0 406 STA DATA,X
|
||||
CA09: 3C 81 C0 407 :WAIT BIT CTRL,X
|
||||
CA0C: 10 FB 408 BPL :WAIT
|
||||
CA0E: BD 80 C0 409 LDA DATA,X ; get response
|
||||
CA11: 85 3C 410 STA WORK ; save R1
|
||||
CA13: 29 80 411 AND #$80
|
||||
CA15: D0 ED 412 BNE GETR1 ; wait for MSB=0
|
||||
CA17: A9 FF 413 LDA #DUMMY
|
||||
CA19: 9D 80 C0 414 STA DATA,X ; send another dummy
|
||||
CA1C: A5 3C 415 LDA WORK ; restore R1
|
||||
CA1E: 60 416 RTS
|
||||
417
|
||||
418
|
||||
419 ********************************
|
||||
420 *
|
||||
421 * Get R3
|
||||
422 * R1 is in A
|
||||
423 * R3 is in scratchpad ram
|
||||
424 *
|
||||
425 ********************************
|
||||
426
|
||||
CA1F: 20 04 CA 427 GETR3 JSR GETR1 ; get R1 first
|
||||
CA22: 48 428 PHA ; save R1
|
||||
CA23: 5A 429 PHY ; save Y
|
||||
CA24: A0 04 430 LDY #04 ; load counter
|
||||
CA26: A9 FF 431 :LOOP LDA #DUMMY ; send dummy
|
||||
CA28: 9D 80 C0 432 STA DATA,X
|
||||
CA2B: 3C 81 C0 433 :WAIT BIT CTRL,X
|
||||
CA2E: 10 FB 434 BPL :WAIT
|
||||
CA30: BD 80 C0 435 LDA DATA,X
|
||||
CA33: 48 436 PHA
|
||||
CA34: 88 437 DEY
|
||||
CA35: D0 EF 438 BNE :LOOP ; do 4 times
|
||||
CA37: A4 3D 439 LDY SLOT
|
||||
CA39: 68 440 PLA
|
||||
CA3A: 99 F8 05 441 STA R33,Y ; save R3
|
||||
CA3D: 68 442 PLA
|
||||
CA3E: 99 78 05 443 STA R32,Y
|
||||
CA41: 68 444 PLA
|
||||
CA42: 99 F8 04 445 STA R31,Y
|
||||
CA45: 68 446 PLA
|
||||
CA46: 99 78 04 447 STA R30,Y
|
||||
CA49: 7A 448 PLY ; restore Y
|
||||
CA4A: A9 FF 449 LDA #DUMMY
|
||||
CA4C: 9D 80 C0 450 STA DATA,X ; send another dummy
|
||||
CA4F: 68 451 PLA ; restore R1
|
||||
CA50: 60 452 RTS
|
||||
453
|
||||
454
|
||||
455 ********************************
|
||||
456 *
|
||||
457 * Calculate block address
|
||||
458 * Unit number is in $43 DSSS0000
|
||||
459 * Block no is in $46-47
|
||||
460 * Address is in R30-R33
|
||||
461 *
|
||||
462 ********************************
|
||||
463
|
||||
CA51: DA 464 BLOCK PHX ; save X
|
||||
CA52: 5A 465 PHY ; save Y
|
||||
CA53: A6 3D 466 LDX SLOT
|
||||
CA55: A5 46 467 LDA $46 ; store block num
|
||||
CA57: 9D F8 05 468 STA R33,X ; in R30-R33
|
||||
CA5A: A5 47 469 LDA $47
|
||||
CA5C: 9D 78 05 470 STA R32,X
|
||||
CA5F: A9 00 471 LDA #0
|
||||
CA61: 9D F8 04 472 STA R31,X
|
||||
CA64: 9D 78 04 473 STA R30,X
|
||||
474
|
||||
CA67: A9 80 475 LDA #$80 ; drive number
|
||||
CA69: 24 43 476 BIT $43
|
||||
CA6B: F0 05 477 BEQ :SHIFT ; D1
|
||||
CA6D: A9 01 478 LDA #1 ; D2
|
||||
CA6F: 9D F8 04 479 STA R31,X
|
||||
480
|
||||
CA72: A0 09 481 :SHIFT LDY #9 ; ASL can't be used with Y
|
||||
CA74: 1E F8 05 482 :LOOP ASL R33,X ; mul block num
|
||||
CA77: 3E 78 05 483 ROL R32,X ; by 512 to get
|
||||
CA7A: 3E F8 04 484 ROL R31,X ; real address
|
||||
CA7D: 3E 78 04 485 ROL R30,X
|
||||
CA80: 88 486 DEY
|
||||
CA81: D0 F1 487 BNE :LOOP
|
||||
CA83: 7A 488 PLY ; restore Y
|
||||
CA84: FA 489 PLX ; restore X
|
||||
CA85: 60 490 RTS
|
||||
491
|
||||
492
|
||||
493 ********************************
|
||||
494 *
|
||||
495 * Send SD command
|
||||
496 * Cmd is in A
|
||||
497 *
|
||||
498 ********************************
|
||||
499
|
||||
CA86: 5A 500 COMMAND PHY ; save Y
|
||||
CA87: A4 3D 501 LDY SLOT
|
||||
CA89: 9D 80 C0 502 STA DATA,X ; send command
|
||||
CA8C: B9 78 04 503 LDA R30,Y ; get arg from R30 on
|
||||
CA8F: 9D 80 C0 504 STA DATA,X
|
||||
CA92: B9 F8 04 505 LDA R31,Y
|
||||
CA95: 9D 80 C0 506 STA DATA,X
|
||||
CA98: B9 78 05 507 LDA R32,Y
|
||||
CA9B: 9D 80 C0 508 STA DATA,X
|
||||
CA9E: B9 F8 05 509 LDA R33,Y
|
||||
CAA1: 9D 80 C0 510 STA DATA,X
|
||||
CAA4: A9 FF 511 LDA #DUMMY
|
||||
CAA6: 9D 80 C0 512 STA DATA,X ; dummy crc
|
||||
CAA9: 20 04 CA 513 JSR GETR1
|
||||
CAAC: 7A 514 PLY ; restore Y
|
||||
CAAD: 60 515 RTS
|
||||
516
|
||||
517
|
||||
518 ********************************
|
||||
519 *
|
||||
520 * Check for card detect
|
||||
521 *
|
||||
522 * C Clear - card in slot
|
||||
523 * Set - no card in slot
|
||||
524 *
|
||||
525 ********************************
|
||||
526
|
||||
CAAE: 48 527 CARDDET PHA
|
||||
CAAF: A9 40 528 LDA #CD ; 0: card in
|
||||
CAB1: 3C 83 C0 529 BIT SS,X ; 1: card out
|
||||
CAB4: 18 530 CLC
|
||||
CAB5: F0 01 531 BEQ :DONE ; card is in
|
||||
CAB7: 38 532 SEC ; card is out
|
||||
CAB8: 68 533 :DONE PLA
|
||||
CAB9: 60 534 RTS
|
||||
535
|
||||
536
|
||||
537 ********************************
|
||||
538 *
|
||||
539 * Check for write protect
|
||||
540 *
|
||||
541 * C Clear - card not protected
|
||||
542 * Set - card write protected
|
||||
543 *
|
||||
544 ********************************
|
||||
545
|
||||
CABA: 48 546 WRPROT PHA
|
||||
CABB: A9 20 547 LDA #WP ; 0: write enabled
|
||||
CABD: 3C 83 C0 548 BIT SS,X ; 1: write disabled
|
||||
CAC0: 18 549 CLC
|
||||
CAC1: F0 01 550 BEQ :DONE
|
||||
CAC3: 38 551 SEC
|
||||
CAC4: 68 552 :DONE PLA
|
||||
CAC5: 60 553 RTS
|
||||
554
|
||||
555
|
||||
556 ********************************
|
||||
557 *
|
||||
558 * Status request
|
||||
559 * $43 Unit number DSSS000
|
||||
560 * $44-45 Unused
|
||||
561 * $46-47 Unused
|
||||
562 *
|
||||
563 * C Clear - No error
|
||||
564 * Set - Error
|
||||
565 * A $00 - No error
|
||||
566 * $2B - Card write protected
|
||||
567 * $2F - No card inserted
|
||||
568 * X - Blocks avail (low byte)
|
||||
569 * Y - Blocks avail (high byte)
|
||||
570 *
|
||||
571 ********************************
|
||||
572
|
||||
CAC6: A9 00 573 STATUS LDA #0 ; no error
|
||||
CAC8: A2 FF 574 LDX #$FF ; 32 MB partition
|
||||
CACA: A0 FF 575 LDY #$FF
|
||||
576
|
||||
CACC: 20 AE CA 577 JSR CARDDET
|
||||
CACF: 90 04 578 BCC :WRPROT
|
||||
CAD1: A9 2F 579 LDA #$2F ; no card inserted
|
||||
CAD3: 80 07 580 BRA :DONE
|
||||
581
|
||||
CAD5: 20 BA CA 582 :WRPROT JSR WRPROT
|
||||
CAD8: 90 02 583 BCC :DONE
|
||||
CADA: A9 2B 584 LDA #$2B ; card write protected
|
||||
585
|
||||
CADC: 60 586 :DONE RTS
|
||||
587
|
||||
588
|
||||
589 ********************************
|
||||
590 *
|
||||
591 * Read 512 byte block
|
||||
592 * $43 Unit number DSSS0000
|
||||
593 * $44-45 Address (LO/HI) of buffer
|
||||
594 * $46-47 Block number (LO/HI)
|
||||
595 *
|
||||
596 * C Clear - No error
|
||||
597 * Set - Error
|
||||
598 * A $00 - No error
|
||||
599 * $27 - Bad block number
|
||||
600 * $28 - No card inserted
|
||||
601 *
|
||||
602 ********************************
|
||||
603
|
||||
CADD: 20 AE CA 604 READ JSR CARDDET
|
||||
CAE0: B0 64 605 BCS :ERROR ; no card inserted
|
||||
606
|
||||
CAE2: 20 51 CA 607 JSR BLOCK ; calc block address
|
||||
608
|
||||
CAE5: BD 83 C0 609 LDA SS,X ; enable /CS
|
||||
CAE8: 29 FE 610 AND #$FF!SS0
|
||||
CAEA: 9D 83 C0 611 STA SS,X
|
||||
CAED: A9 51 612 LDA #$51 ; send CMD17
|
||||
CAEF: 20 86 CA 613 JSR COMMAND ; send command
|
||||
614
|
||||
CAF2: C9 00 615 CMP #0 ; check for error
|
||||
CAF4: D0 50 616 BNE :ERROR
|
||||
617
|
||||
CAF6: A9 FF 618 :GETTOK LDA #DUMMY ; get data token
|
||||
CAF8: 9D 80 C0 619 STA DATA,X
|
||||
CAFB: BD 80 C0 620 LDA DATA,X ; get response
|
||||
CAFE: C9 FE 621 CMP #$FE
|
||||
CB00: D0 F4 622 BNE :GETTOK ; wait for $FE
|
||||
623
|
||||
CB02: A0 02 624 LDY #2 ; read data from card
|
||||
CB04: BD 81 C0 625 LDA CTRL,X ; enable FRX
|
||||
CB07: 09 10 626 ORA #FRX
|
||||
CB09: 9D 81 C0 627 STA CTRL,X
|
||||
CB0C: A9 FF 628 LDA #DUMMY
|
||||
CB0E: 9D 80 C0 629 STA DATA,X
|
||||
CB11: 64 3C 630 :LOOPY STZ WORK
|
||||
CB13: BD 80 C0 631 :LOOPW LDA DATA,X
|
||||
CB16: 92 44 632 STA ($44)
|
||||
CB18: E6 44 633 INC $44
|
||||
CB1A: D0 02 634 BNE :INW
|
||||
CB1C: E6 45 635 INC $45 ; inc msb on page boundary
|
||||
CB1E: E6 3C 636 :INW INC WORK
|
||||
CB20: D0 F1 637 BNE :LOOPW
|
||||
CB22: 88 638 DEY
|
||||
CB23: D0 EC 639 BNE :LOOPY
|
||||
640
|
||||
CB25: BD 80 C0 641 :CRC LDA DATA,X ; read two bytes crc
|
||||
CB28: BD 80 C0 642 LDA DATA,X ; and ignore
|
||||
CB2B: BD 80 C0 643 LDA DATA,X ; read a dummy byte
|
||||
644
|
||||
CB2E: BD 81 C0 645 LDA CTRL,X ; disable FRX
|
||||
CB31: 29 EF 646 AND #$FF!FRX
|
||||
CB33: 9D 81 C0 647 STA CTRL,X
|
||||
CB36: 18 648 CLC ; no error
|
||||
CB37: A9 00 649 LDA #0
|
||||
650
|
||||
CB39: 08 651 :DONE PHP
|
||||
CB3A: 48 652 PHA
|
||||
CB3B: BD 83 C0 653 LDA SS,X
|
||||
CB3E: 09 01 654 ORA #SS0
|
||||
CB40: 9D 83 C0 655 STA SS,X ; disable /CS
|
||||
CB43: 68 656 PLA
|
||||
CB44: 28 657 PLP
|
||||
CB45: 60 658 RTS
|
||||
659
|
||||
CB46: 38 660 :ERROR SEC ; an error occured
|
||||
CB47: A9 27 661 LDA #$27
|
||||
CB49: 80 EE 662 BRA :DONE
|
||||
663
|
||||
664
|
||||
665 ********************************
|
||||
666 *
|
||||
667 * Write 512 byte block
|
||||
668 * $43 Unit number DSSS0000
|
||||
669 * $44-45 Address (LO/HI) of buffer
|
||||
670 * $46-47 Block number (LO/HI)
|
||||
671 *
|
||||
672 * C Clear - No error
|
||||
673 * Set - Error
|
||||
674 * A $00 - No error
|
||||
675 * $27 - I/O error or bad block number
|
||||
676 * $2B - Card write protected
|
||||
677 *
|
||||
678 ********************************
|
||||
679
|
||||
CB4B: 20 AE CA 680 WRITE JSR CARDDET
|
||||
CB4E: B0 67 681 BCS :IOERROR ; no card inserted
|
||||
682
|
||||
CB50: 20 BA CA 683 JSR WRPROT
|
||||
CB53: B0 67 684 BCS :WPERROR ; card write protected
|
||||
685
|
||||
CB55: 20 51 CA 686 JSR BLOCK ; calc block address
|
||||
687
|
||||
CB58: BD 83 C0 688 LDA SS,X ; enable /CS
|
||||
CB5B: 29 FE 689 AND #$FF!SS0
|
||||
CB5D: 9D 83 C0 690 STA SS,X
|
||||
CB60: A9 58 691 LDA #$58 ; send CMD24
|
||||
CB62: 20 86 CA 692 JSR COMMAND ; send command
|
||||
693
|
||||
CB65: C9 00 694 CMP #0 ; check for error
|
||||
CB67: D0 4E 695 BNE :IOERROR
|
||||
696
|
||||
CB69: A9 FF 697 LDA #DUMMY
|
||||
CB6B: 9D 80 C0 698 STA DATA,X ; send dummy
|
||||
CB6E: A9 FE 699 LDA #$FE
|
||||
CB70: 9D 80 C0 700 STA DATA,X ; send data token
|
||||
701
|
||||
CB73: A0 02 702 LDY #2 ; send data to card
|
||||
CB75: 64 3C 703 :LOOPY STZ WORK
|
||||
CB77: B2 44 704 :LOOPW LDA ($44)
|
||||
CB79: 9D 80 C0 705 STA DATA,X
|
||||
CB7C: E6 44 706 INC $44
|
||||
CB7E: D0 02 707 BNE :INW
|
||||
CB80: E6 45 708 INC $45 ; inc msb on page boundary
|
||||
CB82: E6 3C 709 :INW INC WORK
|
||||
CB84: D0 F1 710 BNE :LOOPW
|
||||
CB86: 88 711 DEY
|
||||
CB87: D0 EC 712 BNE :LOOPY
|
||||
713
|
||||
CB89: 9D 80 C0 714 :CRC STA DATA,X ; send 2 dummy crc bytes
|
||||
CB8C: 9D 80 C0 715 STA DATA,X
|
||||
716
|
||||
CB8F: 9D 80 C0 717 STA DATA,X ; get data response
|
||||
CB92: BD 80 C0 718 LDA DATA,X
|
||||
CB95: 29 1F 719 AND #$1F
|
||||
CB97: C9 05 720 CMP #$05
|
||||
CB99: D0 1C 721 BNE :IOERROR ; check for write error
|
||||
CB9B: 18 722 CLC ; no error
|
||||
CB9C: A9 00 723 LDA #0
|
||||
724
|
||||
CB9E: 08 725 :DONE PHP
|
||||
CB9F: 48 726 PHA
|
||||
CBA0: A9 FF 727 :WAIT LDA #DUMMY
|
||||
CBA2: 9D 80 C0 728 STA DATA,X ; wait for write cycle
|
||||
CBA5: BD 80 C0 729 LDA DATA,X ; to complete
|
||||
CBA8: C9 00 730 CMP #$00
|
||||
CBAA: F0 F4 731 BEQ :WAIT
|
||||
732
|
||||
CBAC: BD 83 C0 733 LDA SS,X ; disable /CS
|
||||
CBAF: 09 01 734 ORA #SS0
|
||||
CBB1: 9D 83 C0 735 STA SS,X
|
||||
CBB4: 68 736 PLA
|
||||
CBB5: 28 737 PLP
|
||||
CBB6: 60 738 RTS
|
||||
739
|
||||
CBB7: 38 740 :IOERROR SEC ; an error occured
|
||||
CBB8: A9 27 741 LDA #$27
|
||||
CBBA: 80 E2 742 BRA :DONE
|
||||
743
|
||||
CBBC: 38 744 :WPERROR SEC
|
||||
CBBD: A9 2B 745 LDA #$2B
|
||||
CBBF: 80 DD 746 BRA :DONE
|
||||
747
|
||||
748
|
||||
749
|
||||
750 ********************************
|
||||
751 *
|
||||
752 * Format
|
||||
753 * not supported!
|
||||
754 *
|
||||
755 ********************************
|
||||
756
|
||||
CBC1: 38 757 FORMAT SEC
|
||||
CBC2: A9 01 758 LDA #$01 ; invalid command
|
||||
CBC4: 60 759 RTS
|
||||
760
|
||||
761
|
||||
CBC5: 40 00 00 762 CMD0 HEX 400000
|
||||
CBC8: 00 00 95 763 HEX 000095
|
||||
CBCB: 41 00 00 764 CMD1 HEX 410000
|
||||
CBCE: 00 00 F9 765 HEX 0000F9
|
||||
CBD1: 48 00 00 766 CMD8 HEX 480000
|
||||
CBD4: 01 AA 87 767 HEX 01AA87
|
||||
CBD7: 50 00 00 768 CMD16 HEX 500000
|
||||
CBDA: 02 00 FF 769 HEX 0200FF
|
||||
CBDD: 77 00 00 770 CMD55 HEX 770000
|
||||
CBE0: 00 00 65 771 HEX 000065
|
||||
CBE3: 69 40 00 772 ACMD4140 HEX 694000
|
||||
CBE6: 00 00 77 773 HEX 000077
|
||||
CBE9: 69 00 00 774 ACMD410 HEX 690000
|
||||
CBEC: 00 00 FF 775 HEX 0000FF
|
||||
|
||||
|
||||
--End assembly, 1007 bytes, Errors: 0
|
||||
|
||||
|
||||
Symbol table - alphabetical order:
|
||||
|
||||
ACMD410 =$CBE9 ACMD4140=$CBE3 BLOCK =$CA51 ? BOOT =$C82B
|
||||
CARDDET =$CAAE CD =$40 CMD =$C9F0 CMD0 =$CBC5
|
||||
CMD1 =$CBCB CMD16 =$CBD7 CMD55 =$CBDD CMD8 =$CBD1
|
||||
CMDHI =$41 CMDLO =$40 COMMAND =$CA86 CTRL =$C081
|
||||
CURSLOT =$07F8 DATA =$C080 DEBUG =$00 DIV =$C082
|
||||
DRIVER =$C84C DUMMY =$FF ECE =$04 FORMAT =$CBC1
|
||||
FRX =$10 GETR1 =$CA04 GETR3 =$CA1F INIT =$C900
|
||||
INITED =$80 R30 =$0478 R31 =$04F8 R32 =$0578
|
||||
R33 =$05F8 READ =$CADD SLOT =$3D SLOT16 =$2B
|
||||
SS =$C083 SS0 =$01 STATUS =$CAC6 WORK =$3C
|
||||
WP =$20 WRITE =$CB4B WRPROT =$CABA
|
||||
|
||||
|
||||
Symbol table - numerical order:
|
||||
|
||||
DEBUG =$00 SS0 =$01 ECE =$04 FRX =$10
|
||||
WP =$20 SLOT16 =$2B WORK =$3C SLOT =$3D
|
||||
CMDLO =$40 CD =$40 CMDHI =$41 INITED =$80
|
||||
DUMMY =$FF R30 =$0478 R31 =$04F8 R32 =$0578
|
||||
R33 =$05F8 CURSLOT =$07F8 DATA =$C080 CTRL =$C081
|
||||
DIV =$C082 SS =$C083 ? BOOT =$C82B DRIVER =$C84C
|
||||
INIT =$C900 CMD =$C9F0 GETR1 =$CA04 GETR3 =$CA1F
|
||||
BLOCK =$CA51 COMMAND =$CA86 CARDDET =$CAAE WRPROT =$CABA
|
||||
STATUS =$CAC6 READ =$CADD WRITE =$CB4B FORMAT =$CBC1
|
||||
CMD0 =$CBC5 CMD1 =$CBCB CMD8 =$CBD1 CMD16 =$CBD7
|
||||
CMD55 =$CBDD ACMD4140=$CBE3 ACMD410 =$CBE9
|
||||
|
||||
BIN
AppleIISd.pdf
BIN
AppleIISd.pdf
Binary file not shown.
776
AppleIISd.s
776
AppleIISd.s
|
|
@ -1,776 +0,0 @@
|
|||
********************************
|
||||
*
|
||||
* Apple][Sd Firmware
|
||||
* Version 0.6
|
||||
*
|
||||
* (c) Florian Reitz, 2017
|
||||
*
|
||||
* X register usually contains SLOT16
|
||||
* Y register is used for counting or SLOT
|
||||
*
|
||||
********************************
|
||||
|
||||
DAT
|
||||
|
||||
XC ; enable 65C02 code
|
||||
DEBUG = 0
|
||||
DO DEBUG
|
||||
ORG $8000
|
||||
ELSE
|
||||
ORG $C800 ; Expansion ROM
|
||||
FIN
|
||||
|
||||
* Memory defines
|
||||
|
||||
SLOT16 = $2B ; $s0 -> slot * 16
|
||||
WORK = $3C
|
||||
SLOT = $3D ; $0s
|
||||
CMDLO = $40
|
||||
CMDHI = $41
|
||||
|
||||
CURSLOT = $07F8 ; $Cs
|
||||
DATA = $C080
|
||||
CTRL = DATA+1
|
||||
DIV = DATA+2
|
||||
SS = DATA+3
|
||||
R30 = $0478
|
||||
R31 = $04F8
|
||||
R32 = $0578
|
||||
R33 = $05F8
|
||||
|
||||
* Constants
|
||||
|
||||
DUMMY = $FF
|
||||
FRX = $10 ; CTRL register
|
||||
ECE = $04
|
||||
SS0 = $01 ; SS register
|
||||
WP = $20
|
||||
CD = $40
|
||||
INITED = $80
|
||||
|
||||
|
||||
* signature bytes
|
||||
|
||||
LDX #$20
|
||||
LDY #$00
|
||||
LDX #$03
|
||||
LDY #$FF ; neither 5.25 nor Smartport
|
||||
|
||||
* find slot nr
|
||||
|
||||
DO DEBUG
|
||||
LDA #$04
|
||||
STA SLOT
|
||||
LDA #$C4
|
||||
STA CURSLOT
|
||||
LDA #$40
|
||||
STA SLOT16
|
||||
|
||||
ELSE
|
||||
JSR $FF58
|
||||
TSX
|
||||
LDA $0100,X
|
||||
STA CURSLOT ; $Cs
|
||||
AND #$0F
|
||||
STA SLOT ; $0s
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
STA SLOT16 ; $s0
|
||||
FIN
|
||||
|
||||
TAX ; X holds now SLOT16
|
||||
BIT $CFFF
|
||||
JSR CARDDET
|
||||
BCC :INIT
|
||||
LDA #$27 ; no card inserted
|
||||
BRK
|
||||
|
||||
:INIT JSR INIT
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Install SD card driver
|
||||
*
|
||||
********************************
|
||||
|
||||
DO DEBUG
|
||||
|
||||
* see if slot has a driver already
|
||||
|
||||
LDX $BF31 ; get devcnt
|
||||
INSTALL LDA $BF32,X ; get a devnum
|
||||
AND #$70 ; isolate slot
|
||||
CMP SLOT16 ; slot?
|
||||
BEQ :INSOUT ; yes, skip it
|
||||
DEX
|
||||
BPL INSTALL ; keep up the search
|
||||
|
||||
* restore the devnum to the list
|
||||
|
||||
LDX $BF31 ; get devcnt again
|
||||
CPX #$0D ; device table full?
|
||||
BNE :INST2
|
||||
|
||||
JSR $FF3A ; bell
|
||||
JMP :INSOUT ; do something!
|
||||
|
||||
:INST2 LDA $BF32-1,X ; move all entries down
|
||||
STA $BF32,X ; to make room at front
|
||||
DEX ; for a new entry
|
||||
BNE :INST2
|
||||
LDA #$04 ; ProFile type device
|
||||
ORA SLOT16
|
||||
STA $BF32 ; slot, drive 1 at top of list
|
||||
INC $BF31 ; update devcnt
|
||||
|
||||
* now insert the device driver vector
|
||||
|
||||
LDA SLOT
|
||||
ASL
|
||||
TAX
|
||||
LDA #<DRIVER
|
||||
STA $BF10,X ; write to driver table
|
||||
LDA #>DRIVER
|
||||
STA $BF11,X
|
||||
:INSOUT RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Boot from SD card
|
||||
*
|
||||
********************************
|
||||
|
||||
ELSE
|
||||
|
||||
BOOT CMP #0 ; check for error
|
||||
BEQ :BOOT1
|
||||
BRK
|
||||
|
||||
:BOOT1 LDA #$01
|
||||
STA $42 ; load command
|
||||
LDA SLOT16
|
||||
TAX
|
||||
STA $43 ; slot number
|
||||
STZ $44 ; buffer lo
|
||||
LDA #$08
|
||||
STA $45 ; buffer hi
|
||||
STZ $46 ; block lo
|
||||
STZ $47 ; block hi
|
||||
BIT $CFFF
|
||||
JSR READ ; call driver
|
||||
JMP $801 ; goto bootloader
|
||||
|
||||
FIN
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Jump table
|
||||
*
|
||||
********************************
|
||||
|
||||
DRIVER CLD
|
||||
|
||||
DO DEBUG
|
||||
LDA #$04
|
||||
STA SLOT
|
||||
LDA #$C4
|
||||
STA CURSLOT
|
||||
LDA #$40
|
||||
STA SLOT16
|
||||
|
||||
ELSE
|
||||
JSR $FF58 ; find slot nr
|
||||
TSX
|
||||
LDA $0100,X
|
||||
STA CURSLOT ; $Cs
|
||||
AND #$0F
|
||||
STA SLOT ; $0s
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
STA SLOT16 ; $s0
|
||||
FIN
|
||||
|
||||
TAX ; X holds now SLOT16
|
||||
BIT $CFFF
|
||||
JSR CARDDET
|
||||
BCC :INITED
|
||||
LDA #$27 ; no card inserted
|
||||
BRA :DONE
|
||||
|
||||
:INITED LDA #INITED ; check for init
|
||||
BIT SS,X
|
||||
BEQ :INIT
|
||||
|
||||
:CMD LDA $42 ; get command
|
||||
CMP #0
|
||||
BEQ :STATUS
|
||||
CMP #1
|
||||
BEQ :READ
|
||||
CMP #2
|
||||
BEQ :WRITE
|
||||
CMP #3
|
||||
BEQ :FORMAT
|
||||
LDA #1 ; unknown command
|
||||
|
||||
:DONE SEC
|
||||
RTS
|
||||
|
||||
:STATUS JMP STATUS
|
||||
:READ JMP READ
|
||||
:WRITE JMP WRITE
|
||||
:FORMAT JMP FORMAT
|
||||
:INIT JSR INIT
|
||||
BCS :DONE ; init failure
|
||||
BRA :CMD
|
||||
|
||||
|
||||
* Signature bytes
|
||||
|
||||
DS \ ; fill with zeroes
|
||||
DS -4 ; locate to $xxFC
|
||||
DW $FFFF ; 65535 blocks
|
||||
DB $17 ; Status bits
|
||||
DB #<DRIVER ; LSB of driver
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Initialize SD card
|
||||
*
|
||||
* C Clear - No error
|
||||
* Set - Error
|
||||
* A $00 - No error
|
||||
* $27 - I/O error - Init failed
|
||||
* $2F - No card inserted
|
||||
*
|
||||
********************************
|
||||
|
||||
INIT CLD
|
||||
LDA #$03 ; set SPI mode 3
|
||||
STA CTRL,X
|
||||
LDA SS,X
|
||||
ORA #SS0 ; set CS high
|
||||
STA SS,X
|
||||
LDA #7
|
||||
STA DIV,X
|
||||
LDY #10
|
||||
LDA #DUMMY
|
||||
|
||||
:LOOP STA DATA,X
|
||||
:WAIT BIT CTRL,X
|
||||
BPL :WAIT
|
||||
DEY
|
||||
BNE :LOOP ; do 10 times
|
||||
LDA SS,X
|
||||
AND #$FF!SS0 ; set CS low
|
||||
STA SS,X
|
||||
|
||||
LDA #<CMD0 ; send CMD0
|
||||
STA CMDLO
|
||||
LDA #>CMD0
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR1 ; get response
|
||||
CMP #$01
|
||||
BNE :ERROR1 ; error!
|
||||
|
||||
LDA #<CMD8 ; send CMD8
|
||||
STA CMDLO
|
||||
LDA #>CMD8
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR3
|
||||
CMP #$01
|
||||
BNE :SDV1 ; may be SD Ver. 1
|
||||
|
||||
* check for $01aa match!
|
||||
:SDV2 LDA #<CMD55
|
||||
STA CMDLO
|
||||
LDA #>CMD55
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR1
|
||||
LDA #<ACMD4140
|
||||
STA CMDLO
|
||||
LDA #>ACMD4140
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ :SDV2 ; wait for ready
|
||||
CMP #$00
|
||||
BNE :ERROR1 ; error!
|
||||
* send CMD58
|
||||
* SD Ver. 2 initialized!
|
||||
JMP :BLOCKSZ
|
||||
|
||||
:ERROR1 JMP :IOERROR ; needed for far jump
|
||||
|
||||
:SDV1 LDA #<CMD55
|
||||
STA CMDLO
|
||||
LDA #>CMD55
|
||||
STA CMDHI
|
||||
JSR CMD ; ignore response
|
||||
LDA #<ACMD410
|
||||
STA CMDLO
|
||||
LDA #>ACMD410
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ :SDV1 ; wait for ready
|
||||
CMP #$00
|
||||
BNE :MMC ; may be MMC card
|
||||
* SD Ver. 1 initialized!
|
||||
JMP :BLOCKSZ
|
||||
|
||||
:MMC LDA #<CMD1
|
||||
STA CMDLO
|
||||
LDA #>CMD1
|
||||
STA CMDHI
|
||||
:LOOP1 JSR CMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ :LOOP1 ; wait for ready
|
||||
CMP #$00
|
||||
BNE :IOERROR ; error!
|
||||
* MMC Ver. 3 initialized!
|
||||
|
||||
:BLOCKSZ LDA #<CMD16
|
||||
STA CMDLO
|
||||
LDA #>CMD16
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR1
|
||||
CMP #$00
|
||||
BNE :IOERROR ; error!
|
||||
|
||||
:END LDA SS,X
|
||||
ORA #INITED ; initialized
|
||||
STA SS,X
|
||||
LDA CTRL,X
|
||||
ORA #ECE ; enable 7MHz
|
||||
STA CTRL,X
|
||||
CLC ; all ok
|
||||
LDY #0
|
||||
BCC :END1
|
||||
:CDERROR SEC
|
||||
LDY #$2F ; no card error
|
||||
BCS :END1
|
||||
:IOERROR SEC
|
||||
LDY #$27 ; init error
|
||||
:END1 LDA SS,X ; set CS high
|
||||
ORA #SS0
|
||||
STA SS,X
|
||||
LDA #0 ; set div to 2
|
||||
STA DIV,X
|
||||
TYA ; retval in A
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Send SD command
|
||||
* Call with command in CMDHI and CMDLO
|
||||
*
|
||||
********************************
|
||||
|
||||
CMD PHY
|
||||
LDY #0
|
||||
:LOOP LDA (CMDLO),Y
|
||||
STA DATA,X
|
||||
:WAIT BIT CTRL,X ; TC is in N
|
||||
BPL :WAIT
|
||||
INY
|
||||
CPY #6
|
||||
BCC :LOOP
|
||||
PLY
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Get R1
|
||||
* R1 is in A
|
||||
*
|
||||
********************************
|
||||
|
||||
GETR1 LDA #DUMMY
|
||||
STA DATA,X
|
||||
:WAIT BIT CTRL,X
|
||||
BPL :WAIT
|
||||
LDA DATA,X ; get response
|
||||
STA WORK ; save R1
|
||||
AND #$80
|
||||
BNE GETR1 ; wait for MSB=0
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send another dummy
|
||||
LDA WORK ; restore R1
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Get R3
|
||||
* R1 is in A
|
||||
* R3 is in scratchpad ram
|
||||
*
|
||||
********************************
|
||||
|
||||
GETR3 JSR GETR1 ; get R1 first
|
||||
PHA ; save R1
|
||||
PHY ; save Y
|
||||
LDY #04 ; load counter
|
||||
:LOOP LDA #DUMMY ; send dummy
|
||||
STA DATA,X
|
||||
:WAIT BIT CTRL,X
|
||||
BPL :WAIT
|
||||
LDA DATA,X
|
||||
PHA
|
||||
DEY
|
||||
BNE :LOOP ; do 4 times
|
||||
LDY SLOT
|
||||
PLA
|
||||
STA R33,Y ; save R3
|
||||
PLA
|
||||
STA R32,Y
|
||||
PLA
|
||||
STA R31,Y
|
||||
PLA
|
||||
STA R30,Y
|
||||
PLY ; restore Y
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send another dummy
|
||||
PLA ; restore R1
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Calculate block address
|
||||
* Unit number is in $43 DSSS0000
|
||||
* Block no is in $46-47
|
||||
* Address is in R30-R33
|
||||
*
|
||||
********************************
|
||||
|
||||
BLOCK PHX ; save X
|
||||
PHY ; save Y
|
||||
LDX SLOT
|
||||
LDA $46 ; store block num
|
||||
STA R33,X ; in R30-R33
|
||||
LDA $47
|
||||
STA R32,X
|
||||
LDA #0
|
||||
STA R31,X
|
||||
STA R30,X
|
||||
|
||||
LDA #$80 ; drive number
|
||||
BIT $43
|
||||
BEQ :SHIFT ; D1
|
||||
LDA #1 ; D2
|
||||
STA R31,X
|
||||
|
||||
:SHIFT LDY #9 ; ASL can't be used with Y
|
||||
:LOOP ASL R33,X ; mul block num
|
||||
ROL R32,X ; by 512 to get
|
||||
ROL R31,X ; real address
|
||||
ROL R30,X
|
||||
DEY
|
||||
BNE :LOOP
|
||||
PLY ; restore Y
|
||||
PLX ; restore X
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Send SD command
|
||||
* Cmd is in A
|
||||
*
|
||||
********************************
|
||||
|
||||
COMMAND PHY ; save Y
|
||||
LDY SLOT
|
||||
STA DATA,X ; send command
|
||||
LDA R30,Y ; get arg from R30 on
|
||||
STA DATA,X
|
||||
LDA R31,Y
|
||||
STA DATA,X
|
||||
LDA R32,Y
|
||||
STA DATA,X
|
||||
LDA R33,Y
|
||||
STA DATA,X
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; dummy crc
|
||||
JSR GETR1
|
||||
PLY ; restore Y
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Check for card detect
|
||||
*
|
||||
* C Clear - card in slot
|
||||
* Set - no card in slot
|
||||
*
|
||||
********************************
|
||||
|
||||
CARDDET PHA
|
||||
LDA #CD ; 0: card in
|
||||
BIT SS,X ; 1: card out
|
||||
CLC
|
||||
BEQ :DONE ; card is in
|
||||
SEC ; card is out
|
||||
:DONE PLA
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Check for write protect
|
||||
*
|
||||
* C Clear - card not protected
|
||||
* Set - card write protected
|
||||
*
|
||||
********************************
|
||||
|
||||
WRPROT PHA
|
||||
LDA #WP ; 0: write enabled
|
||||
BIT SS,X ; 1: write disabled
|
||||
CLC
|
||||
BEQ :DONE
|
||||
SEC
|
||||
:DONE PLA
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Status request
|
||||
* $43 Unit number DSSS000
|
||||
* $44-45 Unused
|
||||
* $46-47 Unused
|
||||
*
|
||||
* C Clear - No error
|
||||
* Set - Error
|
||||
* A $00 - No error
|
||||
* $2B - Card write protected
|
||||
* $2F - No card inserted
|
||||
* X - Blocks avail (low byte)
|
||||
* Y - Blocks avail (high byte)
|
||||
*
|
||||
********************************
|
||||
|
||||
STATUS LDA #0 ; no error
|
||||
LDX #$FF ; 32 MB partition
|
||||
LDY #$FF
|
||||
|
||||
JSR CARDDET
|
||||
BCC :WRPROT
|
||||
LDA #$2F ; no card inserted
|
||||
BRA :DONE
|
||||
|
||||
:WRPROT JSR WRPROT
|
||||
BCC :DONE
|
||||
LDA #$2B ; card write protected
|
||||
|
||||
:DONE RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Read 512 byte block
|
||||
* $43 Unit number DSSS0000
|
||||
* $44-45 Address (LO/HI) of buffer
|
||||
* $46-47 Block number (LO/HI)
|
||||
*
|
||||
* C Clear - No error
|
||||
* Set - Error
|
||||
* A $00 - No error
|
||||
* $27 - Bad block number
|
||||
* $28 - No card inserted
|
||||
*
|
||||
********************************
|
||||
|
||||
READ JSR CARDDET
|
||||
BCS :ERROR ; no card inserted
|
||||
|
||||
JSR BLOCK ; calc block address
|
||||
|
||||
LDA SS,X ; enable /CS
|
||||
AND #$FF!SS0
|
||||
STA SS,X
|
||||
LDA #$51 ; send CMD17
|
||||
JSR COMMAND ; send command
|
||||
|
||||
CMP #0 ; check for error
|
||||
BNE :ERROR
|
||||
|
||||
:GETTOK LDA #DUMMY ; get data token
|
||||
STA DATA,X
|
||||
LDA DATA,X ; get response
|
||||
CMP #$FE
|
||||
BNE :GETTOK ; wait for $FE
|
||||
|
||||
LDY #2 ; read data from card
|
||||
LDA CTRL,X ; enable FRX
|
||||
ORA #FRX
|
||||
STA CTRL,X
|
||||
LDA #DUMMY
|
||||
STA DATA,X
|
||||
:LOOPY STZ WORK
|
||||
:LOOPW LDA DATA,X
|
||||
STA ($44)
|
||||
INC $44
|
||||
BNE :INW
|
||||
INC $45 ; inc msb on page boundary
|
||||
:INW INC WORK
|
||||
BNE :LOOPW
|
||||
DEY
|
||||
BNE :LOOPY
|
||||
|
||||
:CRC LDA DATA,X ; read two bytes crc
|
||||
LDA DATA,X ; and ignore
|
||||
LDA DATA,X ; read a dummy byte
|
||||
|
||||
LDA CTRL,X ; disable FRX
|
||||
AND #$FF!FRX
|
||||
STA CTRL,X
|
||||
CLC ; no error
|
||||
LDA #0
|
||||
|
||||
:DONE PHP
|
||||
PHA
|
||||
LDA SS,X
|
||||
ORA #SS0
|
||||
STA SS,X ; disable /CS
|
||||
PLA
|
||||
PLP
|
||||
RTS
|
||||
|
||||
:ERROR SEC ; an error occured
|
||||
LDA #$27
|
||||
BRA :DONE
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Write 512 byte block
|
||||
* $43 Unit number DSSS0000
|
||||
* $44-45 Address (LO/HI) of buffer
|
||||
* $46-47 Block number (LO/HI)
|
||||
*
|
||||
* C Clear - No error
|
||||
* Set - Error
|
||||
* A $00 - No error
|
||||
* $27 - I/O error or bad block number
|
||||
* $2B - Card write protected
|
||||
*
|
||||
********************************
|
||||
|
||||
WRITE JSR CARDDET
|
||||
BCS :IOERROR ; no card inserted
|
||||
|
||||
JSR WRPROT
|
||||
BCS :WPERROR ; card write protected
|
||||
|
||||
JSR BLOCK ; calc block address
|
||||
|
||||
LDA SS,X ; enable /CS
|
||||
AND #$FF!SS0
|
||||
STA SS,X
|
||||
LDA #$58 ; send CMD24
|
||||
JSR COMMAND ; send command
|
||||
|
||||
CMP #0 ; check for error
|
||||
BNE :IOERROR
|
||||
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send dummy
|
||||
LDA #$FE
|
||||
STA DATA,X ; send data token
|
||||
|
||||
LDY #2 ; send data to card
|
||||
:LOOPY STZ WORK
|
||||
:LOOPW LDA ($44)
|
||||
STA DATA,X
|
||||
INC $44
|
||||
BNE :INW
|
||||
INC $45 ; inc msb on page boundary
|
||||
:INW INC WORK
|
||||
BNE :LOOPW
|
||||
DEY
|
||||
BNE :LOOPY
|
||||
|
||||
:CRC STA DATA,X ; send 2 dummy crc bytes
|
||||
STA DATA,X
|
||||
|
||||
STA DATA,X ; get data response
|
||||
LDA DATA,X
|
||||
AND #$1F
|
||||
CMP #$05
|
||||
BNE :IOERROR ; check for write error
|
||||
CLC ; no error
|
||||
LDA #0
|
||||
|
||||
:DONE PHP
|
||||
PHA
|
||||
:WAIT LDA #DUMMY
|
||||
STA DATA,X ; wait for write cycle
|
||||
LDA DATA,X ; to complete
|
||||
CMP #$00
|
||||
BEQ :WAIT
|
||||
|
||||
LDA SS,X ; disable /CS
|
||||
ORA #SS0
|
||||
STA SS,X
|
||||
PLA
|
||||
PLP
|
||||
RTS
|
||||
|
||||
:IOERROR SEC ; an error occured
|
||||
LDA #$27
|
||||
BRA :DONE
|
||||
|
||||
:WPERROR SEC
|
||||
LDA #$2B
|
||||
BRA :DONE
|
||||
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Format
|
||||
* not supported!
|
||||
*
|
||||
********************************
|
||||
|
||||
FORMAT SEC
|
||||
LDA #$01 ; invalid command
|
||||
RTS
|
||||
|
||||
|
||||
CMD0 HEX 400000
|
||||
HEX 000095
|
||||
CMD1 HEX 410000
|
||||
HEX 0000F9
|
||||
CMD8 HEX 480000
|
||||
HEX 01AA87
|
||||
CMD16 HEX 500000
|
||||
HEX 0200FF
|
||||
CMD55 HEX 770000
|
||||
HEX 000065
|
||||
ACMD4140 HEX 694000
|
||||
HEX 000077
|
||||
ACMD410 HEX 690000
|
||||
HEX 0000FF
|
||||
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
|
||||
Microsoft Visual Studio Solution File, Format Version 12.00
|
||||
# Visual Studio 14
|
||||
VisualStudioVersion = 14.0.25420.1
|
||||
MinimumVisualStudioVersion = 10.0.40219.1
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "AppleIISd", "Firmware\AppleIISd.vcxproj", "{9EA7EC3D-1771-420F-932F-231A35ED1200}"
|
||||
EndProject
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Flasher", "Software\Flasher.vcxproj", "{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}"
|
||||
EndProject
|
||||
Global
|
||||
GlobalSection(SolutionConfigurationPlatforms) = preSolution
|
||||
Debug|x86 = Debug|x86
|
||||
Release|x86 = Release|x86
|
||||
EndGlobalSection
|
||||
GlobalSection(ProjectConfigurationPlatforms) = postSolution
|
||||
{9EA7EC3D-1771-420F-932F-231A35ED1200}.Debug|x86.ActiveCfg = Debug|Win32
|
||||
{9EA7EC3D-1771-420F-932F-231A35ED1200}.Debug|x86.Build.0 = Debug|Win32
|
||||
{9EA7EC3D-1771-420F-932F-231A35ED1200}.Release|x86.ActiveCfg = Release|Win32
|
||||
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</None>
|
||||
<None Include="src\ProDOS.s">
|
||||
<Filter>src</Filter>
|
||||
</None>
|
||||
<None Include="src\Smartport.s">
|
||||
<Filter>src</Filter>
|
||||
</None>
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="..\README.md" />
|
||||
<None Include="AppleIISd.bin.map" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<Filter Include="src">
|
||||
<UniqueIdentifier>{d301b76d-0aac-4430-a25a-193e6e572e60}</UniqueIdentifier>
|
||||
</Filter>
|
||||
</ItemGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
make clean
|
||||
make OPTIONS=mapfile,listing
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -d ..\Binary\Flasher.dsk appleiisd.bin
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -p ..\Binary\Flasher.dsk appleiisd.bin $00 < AppleIISd.bin
|
||||
copy AppleIISd.bin ..\Binary
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/bash
|
||||
|
||||
make clean
|
||||
make OPTIONS=mapfile,listing
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -d ../Binary/Flasher.dsk appleiisd.bin
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -p ../Binary/Flasher.dsk appleiisd.bin $00 < AppleIISd.bin
|
||||
cp AppleIISd.bin ../Binary/
|
||||
|
|
@ -0,0 +1,346 @@
|
|||
###############################################################################
|
||||
### Generic Makefile for cc65 projects - full version with abstract options ###
|
||||
### V1.3.0(w) 2010 - 2013 Oliver Schmidt & Patryk "Silver Dream !" ?ogiewa ###
|
||||
###############################################################################
|
||||
|
||||
###############################################################################
|
||||
### In order to override defaults - values can be assigned to the variables ###
|
||||
###############################################################################
|
||||
|
||||
# Space or comma separated list of cc65 supported target platforms to build for.
|
||||
# Default: c64 (lowercase!)
|
||||
TARGETS := apple2enh
|
||||
|
||||
# Name of the final, single-file executable.
|
||||
# Default: name of the current dir with target name appended
|
||||
PROGRAM := AppleIISd
|
||||
|
||||
# Path(s) to additional libraries required for linking the program
|
||||
# Use only if you don't want to place copies of the libraries in SRCDIR
|
||||
# Default: none
|
||||
LIBS :=
|
||||
|
||||
# Custom linker configuration file
|
||||
# Use only if you don't want to place it in SRCDIR
|
||||
# Default: none
|
||||
CONFIG :=
|
||||
|
||||
# Additional C compiler flags and options.
|
||||
# Default: none
|
||||
CFLAGS =
|
||||
|
||||
# Additional assembler flags and options.
|
||||
# Default: none
|
||||
ASFLAGS =
|
||||
|
||||
# Additional linker flags and options.
|
||||
# Default: none
|
||||
LDFLAGS =
|
||||
|
||||
# Path to the directory containing C and ASM sources.
|
||||
# Default: src
|
||||
SRCDIR :=
|
||||
|
||||
# Path to the directory where object files are to be stored (inside respective target subdirectories).
|
||||
# Default: obj
|
||||
OBJDIR :=
|
||||
|
||||
# Command used to run the emulator.
|
||||
# Default: depending on target platform. For default (c64) target: x64 -kernal kernal -VICIIdsize -autoload
|
||||
EMUCMD :=
|
||||
|
||||
# Optional commands used before starting the emulation process, and after finishing it.
|
||||
# Default: none
|
||||
# Examples
|
||||
#PREEMUCMD := osascript -e "tell application \"System Events\" to set isRunning to (name of processes) contains \"X11.bin\"" -e "if isRunning is true then tell application \"X11\" to activate"
|
||||
#PREEMUCMD := osascript -e "tell application \"X11\" to activate"
|
||||
#POSTEMUCMD := osascript -e "tell application \"System Events\" to tell process \"X11\" to set visible to false"
|
||||
#POSTEMUCMD := osascript -e "tell application \"Terminal\" to activate"
|
||||
PREEMUCMD :=
|
||||
POSTEMUCMD :=
|
||||
|
||||
# On Windows machines VICE emulators may not be available in the PATH by default.
|
||||
# In such case, please set the variable below to point to directory containing
|
||||
# VICE emulators.
|
||||
#VICE_HOME := "C:\Program Files\WinVICE-2.2-x86\"
|
||||
VICE_HOME :=
|
||||
|
||||
# Options state file name. You should not need to change this, but for those
|
||||
# rare cases when you feel you really need to name it differently - here you are
|
||||
STATEFILE := Makefile.options
|
||||
|
||||
###################################################################################
|
||||
#### DO NOT EDIT BELOW THIS LINE, UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! ####
|
||||
###################################################################################
|
||||
|
||||
###################################################################################
|
||||
### Mapping abstract options to the actual compiler, assembler and linker flags ###
|
||||
### Predefined compiler, assembler and linker flags, used with abstract options ###
|
||||
### valid for 2.14.x. Consult the documentation of your cc65 version before use ###
|
||||
###################################################################################
|
||||
|
||||
# Compiler flags used to tell the compiler to optimise for SPEED
|
||||
define _optspeed_
|
||||
CFLAGS += -Oris
|
||||
endef
|
||||
|
||||
# Compiler flags used to tell the compiler to optimise for SIZE
|
||||
define _optsize_
|
||||
CFLAGS += -Or
|
||||
endef
|
||||
|
||||
# Compiler and assembler flags for generating listings
|
||||
define _listing_
|
||||
CFLAGS += --listing $$(@:.o=.lst)
|
||||
ASFLAGS += --listing $$(@:.o=.lst)
|
||||
REMOVES += $(addsuffix .lst,$(basename $(OBJECTS)))
|
||||
endef
|
||||
|
||||
# Linker flags for generating map file
|
||||
define _mapfile_
|
||||
LDFLAGS += --mapfile $$@.map
|
||||
REMOVES += $(PROGRAM).map
|
||||
endef
|
||||
|
||||
# Linker flags for generating VICE label file
|
||||
define _labelfile_
|
||||
LDFLAGS += -Ln $$@.lbl
|
||||
REMOVES += $(PROGRAM).lbl
|
||||
endef
|
||||
|
||||
# Linker flags for generating a debug file
|
||||
define _debugfile_
|
||||
LDFLAGS += -Wl --dbgfile,$$@.dbg
|
||||
REMOVES += $(PROGRAM).dbg
|
||||
endef
|
||||
|
||||
###############################################################################
|
||||
### Defaults to be used if nothing defined in the editable sections above ###
|
||||
###############################################################################
|
||||
|
||||
# Presume the C64 target like the cl65 compile & link utility does.
|
||||
# Set TARGETS to override.
|
||||
ifeq ($(TARGETS),)
|
||||
TARGETS := c64
|
||||
endif
|
||||
|
||||
# Presume we're in a project directory so name the program like the current
|
||||
# directory. Set PROGRAM to override.
|
||||
ifeq ($(PROGRAM),)
|
||||
PROGRAM := $(notdir $(CURDIR))
|
||||
endif
|
||||
|
||||
# Presume the C and asm source files to be located in the subdirectory 'src'.
|
||||
# Set SRCDIR to override.
|
||||
ifeq ($(SRCDIR),)
|
||||
SRCDIR := src
|
||||
endif
|
||||
|
||||
# Presume the object and dependency files to be located in the subdirectory
|
||||
# 'obj' (which will be created). Set OBJDIR to override.
|
||||
ifeq ($(OBJDIR),)
|
||||
OBJDIR := obj
|
||||
endif
|
||||
TARGETOBJDIR := $(OBJDIR)
|
||||
|
||||
# On Windows it is mandatory to have CC65_HOME set. So do not unnecessarily
|
||||
# rely on cl65 being added to the PATH in this scenario.
|
||||
ifdef CC65_HOME
|
||||
CC := $(CC65_HOME)/bin/cl65
|
||||
else
|
||||
CC := cl65
|
||||
endif
|
||||
|
||||
# Default emulator commands and options for particular targets.
|
||||
# Set EMUCMD to override.
|
||||
c64_EMUCMD := $(VICE_HOME)x64 -kernal kernal -VICIIdsize -autoload
|
||||
c128_EMUCMD := $(VICE_HOME)x128 -kernal kernal -VICIIdsize -autoload
|
||||
vic20_EMUCMD := $(VICE_HOME)xvic -kernal kernal -VICdsize -autoload
|
||||
pet_EMUCMD := $(VICE_HOME)xpet -Crtcdsize -autoload
|
||||
plus4_EMUCMD := $(VICE_HOME)xplus4 -TEDdsize -autoload
|
||||
# So far there is no x16 emulator in VICE (why??) so we have to use xplus4 with -memsize option
|
||||
c16_EMUCMD := $(VICE_HOME)xplus4 -ramsize 16 -TEDdsize -autoload
|
||||
cbm510_EMUCMD := $(VICE_HOME)xcbm2 -model 510 -VICIIdsize -autoload
|
||||
cbm610_EMUCMD := $(VICE_HOME)xcbm2 -model 610 -Crtcdsize -autoload
|
||||
atari_EMUCMD := atari800 -windowed -xl -pal -nopatchall -run
|
||||
|
||||
ifeq ($(EMUCMD),)
|
||||
EMUCMD = $($(CC65TARGET)_EMUCMD)
|
||||
endif
|
||||
|
||||
###############################################################################
|
||||
### The magic begins ###
|
||||
###############################################################################
|
||||
|
||||
# The "Native Win32" GNU Make contains quite some workarounds to get along with
|
||||
# cmd.exe as shell. However it does not provide means to determine that it does
|
||||
# actually activate those workarounds. Especially $(SHELL) does NOT contain the
|
||||
# value 'cmd.exe'. So the usual way to determine if cmd.exe is being used is to
|
||||
# execute the command 'echo' without any parameters. Only cmd.exe will return a
|
||||
# non-empty string - saying 'ECHO is on/off'.
|
||||
#
|
||||
# Many "Native Win32" programs accept '/' as directory delimiter just fine. How-
|
||||
# ever the internal commands of cmd.exe generally require '\' to be used.
|
||||
#
|
||||
# cmd.exe has an internal command 'mkdir' that doesn't understand nor require a
|
||||
# '-p' to create parent directories as needed.
|
||||
#
|
||||
# cmd.exe has an internal command 'del' that reports a syntax error if executed
|
||||
# without any file so make sure to call it only if there's an actual argument.
|
||||
ifeq ($(shell echo),)
|
||||
MKDIR = mkdir -p $1
|
||||
RMDIR = rmdir $1
|
||||
RMFILES = $(RM) $1
|
||||
else
|
||||
MKDIR = mkdir $(subst /,\,$1)
|
||||
RMDIR = rmdir $(subst /,\,$1)
|
||||
RMFILES = $(if $1,del /f $(subst /,\,$1))
|
||||
endif
|
||||
COMMA := ,
|
||||
SPACE := $(N/A) $(N/A)
|
||||
define NEWLINE
|
||||
|
||||
|
||||
endef
|
||||
# Note: Do not remove any of the two empty lines above !
|
||||
|
||||
TARGETLIST := $(subst $(COMMA),$(SPACE),$(TARGETS))
|
||||
|
||||
ifeq ($(words $(TARGETLIST)),1)
|
||||
|
||||
# Set PROGRAM to something like 'myprog.c64'.
|
||||
override PROGRAM := $(PROGRAM).bin
|
||||
|
||||
# Set SOURCES to something like 'src/foo.c src/bar.s'.
|
||||
# Use of assembler files with names ending differently than .s is deprecated!
|
||||
SOURCES := $(wildcard $(SRCDIR)/*.c)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.s)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.asm)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.a65)
|
||||
|
||||
# Add to SOURCES something like 'src/c64/me.c src/c64/too.s'.
|
||||
# Use of assembler files with names ending differently than .s is deprecated!
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.c)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.s)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.asm)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.a65)
|
||||
|
||||
# Set OBJECTS to something like 'obj/c64/foo.o obj/c64/bar.o'.
|
||||
OBJECTS := $(addsuffix .o,$(basename $(addprefix $(TARGETOBJDIR)/,$(notdir $(SOURCES)))))
|
||||
|
||||
# Set DEPENDS to something like 'obj/c64/foo.d obj/c64/bar.d'.
|
||||
DEPENDS := $(OBJECTS:.o=.d)
|
||||
|
||||
# Add to LIBS something like 'src/foo.lib src/c64/bar.lib'.
|
||||
LIBS += $(wildcard $(SRCDIR)/*.lib)
|
||||
LIBS += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.lib)
|
||||
|
||||
# Add to CONFIG something like 'src/c64/bar.cfg src/foo.cfg'.
|
||||
CONFIG += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.cfg)
|
||||
CONFIG += $(wildcard $(SRCDIR)/*.cfg)
|
||||
|
||||
# Select CONFIG file to use. Target specific configs have higher priority.
|
||||
ifneq ($(word 2,$(CONFIG)),)
|
||||
CONFIG := $(firstword $(CONFIG))
|
||||
$(info Using config file $(CONFIG) for linking)
|
||||
endif
|
||||
|
||||
.SUFFIXES:
|
||||
.PHONY: all test clean zap love
|
||||
|
||||
all: $(PROGRAM)
|
||||
|
||||
-include $(DEPENDS)
|
||||
-include $(STATEFILE)
|
||||
|
||||
# If OPTIONS are given on the command line then save them to STATEFILE
|
||||
# if (and only if) they have actually changed. But if OPTIONS are not
|
||||
# given on the command line then load them from STATEFILE. Have object
|
||||
# files depend on STATEFILE only if it actually exists.
|
||||
ifeq ($(origin OPTIONS),command line)
|
||||
ifneq ($(OPTIONS),$(_OPTIONS_))
|
||||
ifeq ($(OPTIONS),)
|
||||
$(info Removing OPTIONS)
|
||||
$(shell $(RM) $(STATEFILE))
|
||||
$(eval $(STATEFILE):)
|
||||
else
|
||||
$(info Saving OPTIONS=$(OPTIONS))
|
||||
$(shell echo _OPTIONS_=$(OPTIONS) > $(STATEFILE))
|
||||
endif
|
||||
$(eval $(OBJECTS): $(STATEFILE))
|
||||
endif
|
||||
else
|
||||
ifeq ($(origin _OPTIONS_),file)
|
||||
$(info Using saved OPTIONS=$(_OPTIONS_))
|
||||
OPTIONS = $(_OPTIONS_)
|
||||
$(eval $(OBJECTS): $(STATEFILE))
|
||||
endif
|
||||
endif
|
||||
|
||||
# Transform the abstract OPTIONS to the actual cc65 options.
|
||||
$(foreach o,$(subst $(COMMA),$(SPACE),$(OPTIONS)),$(eval $(_$o_)))
|
||||
|
||||
# Strip potential variant suffix from the actual cc65 target.
|
||||
CC65TARGET := $(firstword $(subst .,$(SPACE),$(TARGETLIST)))
|
||||
|
||||
# The remaining targets.
|
||||
$(TARGETOBJDIR):
|
||||
$(call MKDIR,$@)
|
||||
|
||||
vpath %.c $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.c | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(CFLAGS) -o $@ $<
|
||||
|
||||
vpath %.s $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.s | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
vpath %.asm $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.asm | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
vpath %.a65 $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.a65 | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
$(PROGRAM): $(CONFIG) $(OBJECTS) $(LIBS)
|
||||
$(CC) -t $(CC65TARGET) $(LDFLAGS) -o $@ $(patsubst %.cfg,-C %.cfg,$^)
|
||||
|
||||
test: $(PROGRAM)
|
||||
$(PREEMUCMD)
|
||||
$(EMUCMD) $<
|
||||
$(POSTEMUCMD)
|
||||
|
||||
clean:
|
||||
$(call RMFILES,$(OBJECTS))
|
||||
$(call RMFILES,$(DEPENDS))
|
||||
$(call RMFILES,$(REMOVES))
|
||||
$(call RMFILES,$(PROGRAM))
|
||||
|
||||
else # $(words $(TARGETLIST)),1
|
||||
|
||||
all test clean:
|
||||
$(foreach t,$(TARGETLIST),$(MAKE) TARGETS=$t $@$(NEWLINE))
|
||||
|
||||
endif # $(words $(TARGETLIST)),1
|
||||
|
||||
OBJDIRLIST := $(wildcard $(OBJDIR)/*)
|
||||
|
||||
zap:
|
||||
$(foreach o,$(OBJDIRLIST),-$(call RMFILES,$o/*.o $o/*.d $o/*.lst)$(NEWLINE))
|
||||
$(foreach o,$(OBJDIRLIST),-$(call RMDIR,$o)$(NEWLINE))
|
||||
-$(call RMDIR,$(OBJDIR))
|
||||
-$(call RMFILES,$(basename $(PROGRAM)).* $(STATEFILE))
|
||||
|
||||
love:
|
||||
@echo "Not war, eh?"
|
||||
|
||||
###################################################################
|
||||
### Place your additional targets in the additional Makefiles ###
|
||||
### in the same directory - their names have to end with ".mk"! ###
|
||||
###################################################################
|
||||
-include *.mk
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
# Configuration for assembler programs which don't need a special setup
|
||||
|
||||
FEATURES {
|
||||
STARTADDRESS: default = $0803;
|
||||
}
|
||||
MEMORY {
|
||||
ZP: file = "", start = $0000, size = $00FF;
|
||||
HEADER: file = %O, start = %S - 4, size = $0004;
|
||||
MAIN: file = %O, define = yes, start = %S, size = $C000 - %S;
|
||||
BSS: file = "", start = __MAIN_LAST__, size = $C000 - __MAIN_LAST__;
|
||||
|
||||
SLOTROM: file = %O, fill = yes start = $C700, size = $00FB;
|
||||
SLOTID: file = %O, start = $C7FB, size = $0005;
|
||||
EXTROM: file = %O, fill = yes start = $C800, size = $0700;
|
||||
}
|
||||
SEGMENTS {
|
||||
ZEROPAGE: load = ZP, type = zp, optional = yes;
|
||||
EXEHDR: load = HEADER, type = ro, optional = yes;
|
||||
CODE: load = MAIN, type = rw;
|
||||
RODATA: load = MAIN, type = ro, optional = yes;
|
||||
DATA: load = MAIN, type = rw, optional = yes;
|
||||
BSS: load = BSS, type = bss, optional = yes, define = yes;
|
||||
|
||||
SLOTROM: load = SLOTROM, type = ro;
|
||||
SLOTID: load = SLOTID, type = ro;
|
||||
EXTROM: load = EXTROM, type = ro, optional = yes;
|
||||
}
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2.3
|
||||
; Defines
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
; ZP locations
|
||||
PSAVE := $3D ; P save location
|
||||
SLOT16 := $3E ; $s0 -> slot * 16
|
||||
SLOT := $3F ; $0s
|
||||
CMDLO := $40
|
||||
CMDHI := $41
|
||||
PDZPAREA = PSAVE
|
||||
PDZPSIZE = CMDHI-PDZPAREA+1
|
||||
|
||||
; ProDOS
|
||||
DCMD := $42 ; Command code
|
||||
DSNUMBER := $43 ; drive / slot number
|
||||
BUFFER := $44 ; buffer pointer, two bytes
|
||||
BLOCKNUM := $46 ; block number, two bytes
|
||||
|
||||
; Smartport
|
||||
SMPARAMLIST := $48 ; parameter list, two bytes
|
||||
SMCMDLIST := $4A ; command list, two bytes
|
||||
SMCSCODE := $4C
|
||||
SMZPAREA = SMPARAMLIST
|
||||
SMZPSIZE = SMCSCODE-SMZPAREA+1
|
||||
SMCMD = DCMD
|
||||
|
||||
|
||||
; Ram equates, access with SLOT offset
|
||||
R30 := $0478
|
||||
R31 := $04F8
|
||||
R32 := $0578
|
||||
R33 := $05F8
|
||||
DRVNUM := $0678
|
||||
CURSLOT := $07F8 ; $Cs
|
||||
|
||||
; Rom equates
|
||||
OAPPLE := $C061 ; open apple key
|
||||
DATA := $C080
|
||||
CTRL := DATA+1
|
||||
SS := DATA+3
|
||||
|
||||
; Constants
|
||||
DUMMY = $FF
|
||||
FRX = $10 ; CTRL register
|
||||
ECE = $04
|
||||
SS0 = $01 ; SS register
|
||||
SDHC = $10
|
||||
WP = $20
|
||||
CD = $40
|
||||
CARD_INIT = $80
|
||||
|
||||
SMDRIVERVER = $120B ; Version 1.2 Beta
|
||||
|
||||
; Error codes
|
||||
NO_ERR = $00
|
||||
ERR_BADCMD = $01
|
||||
ERR_BADPCNT = $04
|
||||
ERR_BUSERR = $06
|
||||
ERR_BADUNIT = $11
|
||||
ERR_NOINT = $1F
|
||||
ERR_BADCTL = $21
|
||||
ERR_BADCTLPARM = $22
|
||||
ERR_IOERR = $27
|
||||
ERR_NODRIVE = $28
|
||||
ERR_NOWRITE = $2B
|
||||
ERR_BADBLOCK = $2D
|
||||
ERR_OFFLINE = $2F
|
||||
|
|
@ -0,0 +1,378 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2.3
|
||||
; Main source
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.export INIT
|
||||
|
||||
.import PRODOS
|
||||
.import SMARTPORT
|
||||
.import GETR1
|
||||
.import GETR3
|
||||
.import SDCMD
|
||||
.import CARDDET
|
||||
.import INITED
|
||||
.import READ
|
||||
|
||||
.include "AppleIISd.inc"
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Signature bytes
|
||||
;
|
||||
; 65535 blocks
|
||||
; Removable media
|
||||
; Non-interruptable
|
||||
; 2 drives
|
||||
; Read, write and status allowed
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.segment "SLOTID"
|
||||
.byt $0 ; not extended, no SCSI, no RAM
|
||||
.word $0000 ; use status call
|
||||
.byt $97 ; Status bits
|
||||
.byt <DRIVER ; LSB of driver
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Bootcode
|
||||
;
|
||||
; Is executed on boot or PR#
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.segment "SLOTROM"
|
||||
LDX #$20
|
||||
LDX #$00
|
||||
LDX #$03
|
||||
LDX #$00 ; is Smartport controller
|
||||
;LDX #$3C ; is a disk controller
|
||||
|
||||
SEI ; find slot
|
||||
BIT $CFFF
|
||||
JSR KNOWNRTS
|
||||
TSX
|
||||
LDA $0100,X
|
||||
CLI
|
||||
STA CURSLOT ; $Cs
|
||||
AND #$0F
|
||||
STA SLOT ; $0s
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
STA SLOT16 ; $s0
|
||||
TAX ; X holds now SLOT16
|
||||
|
||||
LDY #0 ; display copyright message
|
||||
@DRAW: LDA TEXT,Y
|
||||
BEQ @OAPPLE ; check for NULL
|
||||
ORA #$80 ; set MSB
|
||||
STA $0750,Y ; put second to last line
|
||||
INY
|
||||
BPL @DRAW
|
||||
|
||||
LDA #197
|
||||
JSR $FCA8 ; wait for 100 ms
|
||||
|
||||
@OAPPLE: LDA OAPPLE ; check for OA key
|
||||
BPL @INIT ; and skip boot if pressed
|
||||
|
||||
@NEXTSLOT: LDA CURSLOT ; skip boot when no card
|
||||
DEC A
|
||||
STA CMDHI ; use CMDHI/LO as pointer
|
||||
STZ CMDLO
|
||||
JMP (CMDLO)
|
||||
|
||||
@INIT: JSR INIT
|
||||
BNE @NEXTSLOT ; init not successful
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Boot from SD card
|
||||
;
|
||||
;*******************************
|
||||
|
||||
; load disk blocks 0 and 1 to $800 and $A00
|
||||
@BOOT: LDA #$08 ; load to $800
|
||||
STA BUFFER+1 ; buffer hi
|
||||
STZ BUFFER ; buffer lo
|
||||
STZ BLOCKNUM+1 ; block hi
|
||||
STZ BLOCKNUM ; block lo
|
||||
LDA SLOT16
|
||||
STA DSNUMBER ; set to current slot
|
||||
JSR READ
|
||||
BCS @NEXTSLOT ; load not successful
|
||||
|
||||
LDA #$0A
|
||||
STA BUFFER+1 ; buffer hi
|
||||
STZ BUFFER ; buffer lo
|
||||
STZ BLOCKNUM+1 ; block hi
|
||||
LDA #$01
|
||||
STA BLOCKNUM ; block lo
|
||||
JSR READ
|
||||
BCS @NEXTSLOT ; load not successful
|
||||
JMP $801 ; goto bootloader
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Jump table
|
||||
;
|
||||
;*******************************
|
||||
|
||||
DRIVER: CLC ; ProDOS entry
|
||||
BCC @PRODOS
|
||||
SEC ; Smartport entry
|
||||
|
||||
@PRODOS: PHP ; transfer P to X
|
||||
PLX
|
||||
LDY #PDZPSIZE-1 ; save zeropage area for ProDOS
|
||||
@SAVEZP: LDA PDZPAREA,Y
|
||||
PHA
|
||||
DEY
|
||||
BPL @SAVEZP
|
||||
STX PSAVE ; save X (P)
|
||||
|
||||
; Has this to be done every time this gets called or only on boot???
|
||||
SEI
|
||||
BIT $CFFF
|
||||
JSR KNOWNRTS
|
||||
TSX
|
||||
LDA $0100,X
|
||||
CLI
|
||||
STA CURSLOT ; $Cs
|
||||
AND #$0F
|
||||
STA SLOT ; $0s
|
||||
TAY ; Y holds now SLOT
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
STA SLOT16 ; $s0
|
||||
TAX ; X holds now SLOT16
|
||||
|
||||
JSR INITED ; check for init
|
||||
BCC @DISP
|
||||
JSR INIT
|
||||
BCS @END ; Init failed
|
||||
|
||||
@DISP: LDA PSAVE ; get saved P value
|
||||
PHA ; and transfer to P
|
||||
PLP
|
||||
BCS @SMARTPORT ; Smartport dispatcher
|
||||
JSR PRODOS ; ProDOS dispatcher
|
||||
|
||||
@END: PHX
|
||||
LDX SLOT ; X holds $0s
|
||||
STA R30,X ; save A
|
||||
PLA
|
||||
STA R31,X ; save X
|
||||
TYA
|
||||
STA R32,X ; save Y
|
||||
PHP
|
||||
PLA
|
||||
STA R33,X ; save P
|
||||
|
||||
LDY #0
|
||||
@RESTZP: PLA ; restore zeropage area
|
||||
STA PDZPAREA,Y
|
||||
INY
|
||||
CPY #PDZPSIZE
|
||||
BCC @RESTZP
|
||||
|
||||
LDA R33,X ; get retval
|
||||
PHA
|
||||
LDA R32,X
|
||||
PHA
|
||||
LDA R31,X
|
||||
PHA
|
||||
LDA R30,X ; restore A
|
||||
PLX ; restore X
|
||||
PLY ; restore Y
|
||||
PLP ; restore P
|
||||
RTS
|
||||
|
||||
@SMARTPORT: CLC
|
||||
JSR SMARTPORT
|
||||
BRA @END
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Initialize SD card
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $27 - I/O error - Init failed
|
||||
; $2F - No card inserted
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.segment "EXTROM"
|
||||
INIT: STZ CTRL,X ; reset SPI controller
|
||||
LDA #SS0 ; set CS high
|
||||
STA SS,X
|
||||
LDY #10
|
||||
|
||||
@LOOP: LDA #DUMMY
|
||||
STA DATA,X
|
||||
@WAIT: LDA CTRL,X ; wait for TC (bit 7) to get high
|
||||
BPL @WAIT
|
||||
DEY
|
||||
BNE @LOOP ; do 10 times
|
||||
LDA SS,X
|
||||
AND #<~SS0 ; set CS low
|
||||
STA SS,X
|
||||
|
||||
LDA #<CMD0 ; send CMD0
|
||||
STA CMDLO
|
||||
LDA #>CMD0
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR1 ; get response
|
||||
CMP #$01
|
||||
BNE @ERROR1 ; error!
|
||||
|
||||
LDA #<CMD8 ; send CMD8
|
||||
STA CMDLO
|
||||
LDA #>CMD8
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR3 ; R7 is also 1+4 bytes
|
||||
CMP #$01
|
||||
BNE @SDV1 ; may be SD Ver. 1
|
||||
|
||||
LDY SLOT ; check for $aa in R33
|
||||
LDA R33,Y
|
||||
CMP #$AA
|
||||
BNE @ERROR1 ; error!
|
||||
|
||||
@SDV2: LDA #<CMD55
|
||||
STA CMDLO
|
||||
LDA #>CMD55
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR1
|
||||
LDA #<ACMD4140 ; enable SDHC support
|
||||
STA CMDLO
|
||||
LDA #>ACMD4140
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ @SDV2 ; wait for ready
|
||||
CMP #0
|
||||
BNE @ERROR1 ; error!
|
||||
|
||||
; SD Ver. 2 initialized!
|
||||
LDA #<CMD58 ; check for SDHC
|
||||
STA CMDLO
|
||||
LDA #>CMD58
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR3
|
||||
CMP #0
|
||||
BNE @ERROR1 ; error!
|
||||
LDY SLOT
|
||||
LDA R30,Y
|
||||
AND #$40 ; check CCS
|
||||
BEQ @BLOCKSZ
|
||||
|
||||
LDA SS,X ; card is SDHC
|
||||
ORA #SDHC
|
||||
STA SS,X
|
||||
JMP @END
|
||||
|
||||
@ERROR1: JMP @IOERROR ; needed for far jump
|
||||
|
||||
@SDV1: LDA #<CMD55
|
||||
STA CMDLO
|
||||
LDA #>CMD55
|
||||
STA CMDHI
|
||||
JSR SDCMD ; ignore response
|
||||
LDA #<ACMD410
|
||||
STA CMDLO
|
||||
LDA #>ACMD410
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ @SDV1 ; wait for ready
|
||||
CMP #0
|
||||
BNE @MMC ; may be MMC card
|
||||
; SD Ver. 1 initialized!
|
||||
JMP @BLOCKSZ
|
||||
|
||||
@MMC: LDA #<CMD1
|
||||
STA CMDLO
|
||||
LDA #>CMD1
|
||||
STA CMDHI
|
||||
@LOOP1: JSR SDCMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ @LOOP1 ; wait for ready
|
||||
CMP #0
|
||||
BNE @IOERROR ; error!
|
||||
; MMC Ver. 3 initialized!
|
||||
|
||||
@BLOCKSZ: LDA #<CMD16
|
||||
STA CMDLO
|
||||
LDA #>CMD16
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR1
|
||||
CMP #0
|
||||
BNE @IOERROR ; error!
|
||||
|
||||
@END: LDA SS,X
|
||||
ORA #CARD_INIT ; initialized
|
||||
STA SS,X
|
||||
LDA CTRL,X
|
||||
ORA #ECE ; enable 7MHz
|
||||
STA CTRL,X
|
||||
CLC ; all ok
|
||||
LDY #NO_ERR
|
||||
BCC @END1
|
||||
|
||||
@IOERROR: SEC
|
||||
LDY #ERR_IOERR ; init error
|
||||
@END1: LDA SS,X ; set CS high
|
||||
ORA #SS0
|
||||
STA SS,X
|
||||
TYA ; retval in A
|
||||
KNOWNRTS: RTS
|
||||
|
||||
|
||||
TEXT: .asciiz " Apple][Sd v1.2.2 (c)2021 Florian Reitz"
|
||||
.assert(*-TEXT)=40, error, "TEXT must be 40 bytes long"
|
||||
|
||||
|
||||
CMD0: .byt $40, $00, $00
|
||||
.byt $00, $00, $95
|
||||
CMD1: .byt $41, $00, $00
|
||||
.byt $00, $00, $F9
|
||||
CMD8: .byt $48, $00, $00
|
||||
.byt $01, $AA, $87
|
||||
CMD16: .byt $50, $00, $00
|
||||
.byt $02, $00, $FF
|
||||
CMD55: .byt $77, $00, $00
|
||||
.byt $00, $00, $FF
|
||||
CMD58: .byt $7A, $00, $00
|
||||
.byt $00, $00, $FF
|
||||
ACMD4140: .byt $69, $40, $00
|
||||
.byt $00, $00, $77
|
||||
ACMD410: .byt $69, $00, $00
|
||||
.byt $00, $00, $FF
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2.3
|
||||
; Helper functions
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.export SDCMD
|
||||
.export GETR1
|
||||
.export GETR3
|
||||
.export GETBLOCK
|
||||
.export COMMAND
|
||||
.export CARDDET
|
||||
.export WRPROT
|
||||
.export INITED
|
||||
|
||||
|
||||
.include "AppleIISd.inc"
|
||||
.segment "EXTROM"
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Send SD command
|
||||
; Call with command in CMDHI and CMDLO
|
||||
;
|
||||
;*******************************
|
||||
|
||||
SDCMD: PHY
|
||||
LDY #0
|
||||
@LOOP: LDA (CMDLO),Y
|
||||
STA DATA,X
|
||||
@WAIT: LDA CTRL,X ; TC is in N
|
||||
BPL @WAIT
|
||||
INY
|
||||
CPY #6
|
||||
BCC @LOOP
|
||||
PLY
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Get R1
|
||||
; R1 is in A
|
||||
;
|
||||
;*******************************
|
||||
|
||||
GETR1: LDA #DUMMY
|
||||
STA DATA,X
|
||||
@WAIT: LDA CTRL,X
|
||||
BPL @WAIT
|
||||
LDA DATA,X ; get response
|
||||
BMI GETR1 ; wait for MSB=0
|
||||
PHA
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send another dummy
|
||||
PLA ; restore R1
|
||||
RTS
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Get R3 or R7
|
||||
; R1 is in A
|
||||
; R3 is in scratchpad ram
|
||||
;
|
||||
;*******************************
|
||||
|
||||
GETR3: JSR GETR1 ; get R1 first
|
||||
PHA ; save R1
|
||||
PHY ; save Y
|
||||
LDY #04 ; load counter
|
||||
JMP @WAIT ; first byte is already there
|
||||
@LOOP: LDA #DUMMY ; send dummy
|
||||
STA DATA,X
|
||||
@WAIT: LDA CTRL,X
|
||||
BPL @WAIT
|
||||
LDA DATA,X
|
||||
PHA
|
||||
DEY
|
||||
BNE @LOOP ; do 4 times
|
||||
LDY SLOT
|
||||
PLA
|
||||
STA R33,Y ; save R3
|
||||
PLA
|
||||
STA R32,Y
|
||||
PLA
|
||||
STA R31,Y
|
||||
PLA
|
||||
STA R30,Y ; R30 is MSB
|
||||
PLY ; restore Y
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send another dummy
|
||||
PLA ; restore R1
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Calculate block address
|
||||
; Unit number is in $43 DSSS0000
|
||||
; Block no is in $46-47
|
||||
; Address is in R30-R33
|
||||
;
|
||||
;*******************************
|
||||
|
||||
GETBLOCK: PHX ; save X
|
||||
PHY ; save Y
|
||||
LDX SLOT ; SLOT is now in X
|
||||
LDY SLOT16
|
||||
LDA BLOCKNUM ; store block num
|
||||
STA R33,X ; in R30-R33
|
||||
LDA BLOCKNUM+1
|
||||
STA R32,X
|
||||
STZ R31,X
|
||||
STZ R30,X
|
||||
|
||||
TYA ; get SLOT16
|
||||
EOR DSNUMBER
|
||||
AND #$70 ; check only slot bits
|
||||
BEQ @DRIVE ; it is our slot
|
||||
LDA #2 ; it is a phantom slot
|
||||
STA R31,X
|
||||
|
||||
@DRIVE: LDA DSNUMBER ; drive number
|
||||
BPL @SDHC ; D1
|
||||
LDA R31,X ; D2
|
||||
INC A
|
||||
STA R31,X
|
||||
|
||||
@SDHC: LDA #SDHC
|
||||
AND SS,Y ; if card is SDHC,
|
||||
BNE @END ; use block addressing
|
||||
|
||||
LDY #9 ; ASL can't be used with Y
|
||||
@LOOP: ASL R33,X ; mul block num
|
||||
ROL R32,X ; by 512 to get
|
||||
ROL R31,X ; real address
|
||||
ROL R30,X
|
||||
DEY
|
||||
BNE @LOOP
|
||||
|
||||
@END: PLY ; restore Y
|
||||
PLX ; restore X
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Send SD command
|
||||
; Cmd is in A
|
||||
;
|
||||
;*******************************
|
||||
|
||||
COMMAND: PHY ; save Y
|
||||
LDY SLOT
|
||||
STA DATA,X ; send command
|
||||
LDA R30,Y ; get arg from R30 on
|
||||
STA DATA,X
|
||||
LDA R31,Y
|
||||
STA DATA,X
|
||||
LDA R32,Y
|
||||
STA DATA,X
|
||||
LDA R33,Y
|
||||
STA DATA,X
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; dummy crc
|
||||
JSR GETR1
|
||||
PLY ; restore Y
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Check for card detect
|
||||
; X must contain SLOT16
|
||||
;
|
||||
; C Clear - card in slot
|
||||
; Set - no card in slot
|
||||
;
|
||||
;*******************************
|
||||
|
||||
CARDDET: PHA
|
||||
LDA #CD ; 0: card in
|
||||
BIT SS,X ; 1: card out
|
||||
CLC
|
||||
BEQ @DONE ; card is in
|
||||
SEC ; card is out
|
||||
@DONE: PLA
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Check for write protect
|
||||
; X must contain SLOT16
|
||||
;
|
||||
; C Clear - card not protected
|
||||
; Set - card write protected
|
||||
;
|
||||
;*******************************
|
||||
|
||||
WRPROT: PHA
|
||||
LDA #WP ; 0: write enabled
|
||||
BIT SS,X ; 1: write disabled
|
||||
CLC
|
||||
BEQ @DONE
|
||||
SEC
|
||||
@DONE: PLA
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Check if card is initialized
|
||||
; X must contain SLOT16
|
||||
;
|
||||
; C Clear - card initialized
|
||||
; Set - card not initialized
|
||||
;
|
||||
;*******************************
|
||||
|
||||
INITED: PHA
|
||||
LDA #CARD_INIT ; 0: card not initialized
|
||||
BIT SS,X ; 1: card initialized
|
||||
CLC
|
||||
BNE @DONE
|
||||
SEC
|
||||
@DONE: PLA
|
||||
RTS
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2.3
|
||||
; ProDOS functions
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.export PRODOS
|
||||
.export STATUS
|
||||
.export READ
|
||||
.export WRITE
|
||||
|
||||
.import COMMAND
|
||||
.import SDCMD
|
||||
.import GETBLOCK
|
||||
.import CARDDET
|
||||
.import INITED
|
||||
.import INIT
|
||||
.import WRPROT
|
||||
.import GETR1
|
||||
.import GETR3
|
||||
|
||||
.include "AppleIISd.inc"
|
||||
.segment "EXTROM"
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; ProDOS command dispatcher
|
||||
;
|
||||
; $42-$47 MLI input locations
|
||||
; X Slot*16
|
||||
; Y Slot
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $01 - Unknown command
|
||||
;
|
||||
;*******************************
|
||||
|
||||
PRODOS: LDA DCMD ; get command
|
||||
BEQ @STATUS ; branch if cmd is 0
|
||||
CMP #1
|
||||
BEQ @READ
|
||||
CMP #2
|
||||
BEQ @WRITE
|
||||
LDA #ERR_BADCMD ; unknown command
|
||||
SEC
|
||||
RTS
|
||||
|
||||
@STATUS: JMP STATUS
|
||||
@READ: JMP READ
|
||||
@WRITE: JMP WRITE
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Status request
|
||||
; $43 Unit number DSSS000
|
||||
; $44-45 Unused
|
||||
; $46-47 Unused
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $28 - No card inserted
|
||||
; $2B - Card write protected
|
||||
; X - Blocks avail (low byte)
|
||||
; Y - Blocks avail (high byte)
|
||||
;
|
||||
;*******************************
|
||||
|
||||
STATUS: LDA #NO_ERR ; Thanks for this one, Antoine!
|
||||
JSR CARDDET
|
||||
BCC @WRPROT
|
||||
LDA #ERR_NODRIVE; no card inserted
|
||||
BNE @DONE
|
||||
|
||||
@WRPROT: JSR WRPROT
|
||||
BCC @DONE
|
||||
LDA #ERR_NOWRITE; card write protected
|
||||
|
||||
@DONE: LDX #$FF ; 32 MB partition
|
||||
LDY #$FF
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Read 512 byte block
|
||||
; $43 Unit number DSSS0000
|
||||
; $44-45 Address (LO/HI) of buffer
|
||||
; $46-47 Block number (LO/HI)
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $27 - Bad block number
|
||||
; $28 - No card inserted
|
||||
;
|
||||
;*******************************
|
||||
|
||||
READ: JSR CARDDET ; check for card
|
||||
BCS @NDERROR ; no card
|
||||
|
||||
JSR INITED ; check for initialization
|
||||
BCC @GETBLOCK
|
||||
|
||||
JSR INIT ; initialize card
|
||||
BCS @NDERROR ; init failed
|
||||
|
||||
@GETBLOCK: JSR GETBLOCK ; calc block address
|
||||
|
||||
LDA SS,X ; enable /CS
|
||||
AND #<~SS0
|
||||
STA SS,X
|
||||
LDA #$51 ; send CMD17
|
||||
JSR COMMAND ; send command
|
||||
CMP #0
|
||||
BNE @IOERROR ; check for error
|
||||
|
||||
@GETTOK: LDA #DUMMY ; get data token
|
||||
STA DATA,X
|
||||
LDA DATA,X ; get response
|
||||
CMP #$FE
|
||||
BNE @GETTOK ; wait for $FE
|
||||
|
||||
LDA CTRL,X ; enable FRX
|
||||
ORA #FRX
|
||||
STA CTRL,X
|
||||
LDA #DUMMY
|
||||
STA DATA,X
|
||||
|
||||
LDY #0
|
||||
@LOOP1: LDA DATA,X ; read data from card
|
||||
STA (BUFFER),Y
|
||||
INY
|
||||
BNE @LOOP1
|
||||
INC BUFFER+1 ; inc msb on page boundary
|
||||
@LOOP2: LDA DATA,X
|
||||
STA (BUFFER),Y
|
||||
INY
|
||||
BNE @LOOP2
|
||||
DEC BUFFER+1
|
||||
|
||||
@CRC: LDA DATA,X ; read two bytes crc
|
||||
LDA DATA,X ; and ignore
|
||||
LDA DATA,X ; read a dummy byte
|
||||
|
||||
LDA CTRL,X ; disable FRX
|
||||
AND #<~FRX
|
||||
STA CTRL,X
|
||||
CLC ; no error
|
||||
LDA #NO_ERR
|
||||
|
||||
@DONE: PHP
|
||||
PHA
|
||||
LDA SS,X
|
||||
ORA #SS0
|
||||
STA SS,X ; disable /CS
|
||||
PLA
|
||||
PLP
|
||||
RTS
|
||||
|
||||
@IOERROR: SEC ; an error occured
|
||||
LDA #ERR_IOERR
|
||||
BRA @DONE
|
||||
|
||||
@NDERROR: SEC ; an error occured
|
||||
LDA #ERR_NODRIVE
|
||||
BRA @DONE
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Write 512 byte block
|
||||
; $43 Unit number DSSS0000
|
||||
; $44-45 Address (LO/HI) of buffer
|
||||
; $46-47 Block number (LO/HI)
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $27 - I/O error or bad block number
|
||||
; $2B - Card write protected
|
||||
;
|
||||
;*******************************
|
||||
|
||||
WRITE: JSR WRPROT
|
||||
BCS @WPERROR ; card write protected
|
||||
|
||||
JSR GETBLOCK ; calc block address
|
||||
|
||||
LDA SS,X ; enable /CS
|
||||
AND #<~SS0
|
||||
STA SS,X
|
||||
LDA #$58 ; send CMD24
|
||||
JSR COMMAND ; send command
|
||||
CMP #0
|
||||
BNE @IOERROR ; check for error
|
||||
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send dummy
|
||||
LDA #$FE
|
||||
STA DATA,X ; send data token
|
||||
|
||||
LDY #0
|
||||
@LOOP1: LDA (BUFFER),Y
|
||||
STA DATA,X
|
||||
INY
|
||||
BNE @LOOP1
|
||||
INC BUFFER+1
|
||||
@LOOP2: LDA (BUFFER),Y
|
||||
STA DATA,X
|
||||
INY
|
||||
BNE @LOOP2
|
||||
DEC BUFFER+1
|
||||
|
||||
@CRC: LDA #DUMMY
|
||||
STA DATA,X ; send 2 dummy crc bytes
|
||||
STA DATA,X
|
||||
|
||||
STA DATA,X ; get data response
|
||||
LDA DATA,X
|
||||
AND #$1F
|
||||
CMP #$05
|
||||
BNE @IOERROR ; check for write error
|
||||
CLC ; no error
|
||||
LDA #NO_ERR
|
||||
|
||||
@DONE: PHP
|
||||
PHA
|
||||
@WAIT: LDA #DUMMY
|
||||
STA DATA,X ; wait for write cycle
|
||||
LDA DATA,X ; to complete
|
||||
BEQ @WAIT
|
||||
|
||||
LDA SS,X ; disable /CS
|
||||
ORA #SS0
|
||||
STA SS,X
|
||||
PLA
|
||||
PLP
|
||||
RTS
|
||||
|
||||
@IOERROR: SEC ; an error occured
|
||||
LDA #ERR_IOERR
|
||||
BRA @DONE
|
||||
|
||||
@WPERROR: SEC
|
||||
LDA #ERR_NOWRITE
|
||||
BRA @DONE
|
||||
|
|
@ -0,0 +1,418 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2.3
|
||||
; Smartport functions
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.export SMARTPORT
|
||||
|
||||
.import READ
|
||||
.import WRITE
|
||||
.import CARDDET
|
||||
.import WRPROT
|
||||
|
||||
.include "AppleIISd.inc"
|
||||
.segment "EXTROM"
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Smartport command dispatcher
|
||||
;
|
||||
; $42-$47 MLI input locations
|
||||
; X Slot*16
|
||||
; Y Slot
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $01 - Unknown command
|
||||
;
|
||||
;*******************************
|
||||
|
||||
SMARTPORT: LDY #SMZPSIZE-1 ; save zeropage area for Smarport
|
||||
@SAVEZP: LDA SMZPAREA,Y
|
||||
PHA
|
||||
DEY
|
||||
BPL @SAVEZP
|
||||
|
||||
TSX ; get call address
|
||||
LDA $103+PDZPSIZE+SMZPSIZE,X
|
||||
STA SMPARAMLIST ; store temporarily
|
||||
CLC
|
||||
ADC #3 ; adjust return address
|
||||
STA $103+PDZPSIZE+SMZPSIZE,X
|
||||
LDA $104+PDZPSIZE+SMZPSIZE,X
|
||||
STA SMPARAMLIST+1
|
||||
ADC #0
|
||||
STA $104+PDZPSIZE+SMZPSIZE,X
|
||||
|
||||
LDY #1 ; get command code
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA SMCMD
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
TAX
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA SMPARAMLIST+1 ; is now parameter list
|
||||
STX SMPARAMLIST
|
||||
|
||||
LDA #ERR_BADCMD ; suspect bad command
|
||||
LDX SMCMD
|
||||
CPX #$09+1 ; command too large
|
||||
BCS @END
|
||||
|
||||
LDA (SMPARAMLIST) ; parameter count
|
||||
CMP REQPARAMCOUNT,X
|
||||
BNE @COUNTMISMATCH
|
||||
|
||||
LDY #1 ; get drive number
|
||||
LDA (SMPARAMLIST),Y
|
||||
LDY SLOT
|
||||
STA DRVNUM,Y
|
||||
|
||||
TXA ; SMCMD
|
||||
ASL A ; shift for use of word addresses
|
||||
TAX
|
||||
JSR @JMPSPCOMMAND ; Y holds SLOT
|
||||
BCS @END ; jump on error
|
||||
LDA #NO_ERR
|
||||
|
||||
@END: TAX ; save retval
|
||||
LDY #0 ; restore zeropage
|
||||
@RESTZP: PLA
|
||||
STA SMZPAREA,Y
|
||||
INY
|
||||
CPY #SMZPSIZE
|
||||
BCC @RESTZP
|
||||
|
||||
TXA
|
||||
;warum feste anzahl an bytes f<>r return wert?
|
||||
LDY #2 ; highbyte of # bytes transferred
|
||||
LDX #0 ; low byte of # bytes transferred
|
||||
;warum wird mit #1 verglichen?
|
||||
CMP #1 ; C=1 if A != NO_ERR
|
||||
RTS
|
||||
|
||||
@COUNTMISMATCH:
|
||||
LDA #ERR_BADPCNT
|
||||
BRA @END
|
||||
|
||||
@JMPSPCOMMAND: ; use offset from cmd*2
|
||||
JMP (SPDISPATCH,X)
|
||||
|
||||
|
||||
|
||||
; Smartport Status command
|
||||
;
|
||||
SMSTATUS: JSR GETCSLIST
|
||||
LDY SLOT
|
||||
LDA DRVNUM,Y
|
||||
BNE @PARTITION ; status call for a partition
|
||||
|
||||
LDA SMCSCODE
|
||||
BEQ @STATUS00 ; status call 0 for the bus
|
||||
LDA #ERR_BADCTL ; calls other than 0 are not allowed
|
||||
SEC
|
||||
RTS
|
||||
|
||||
; TODO support partitions based on card size
|
||||
@STATUS00: LDA #4 ; support 4 partitions
|
||||
STA (SMCMDLIST)
|
||||
|
||||
LDY #7
|
||||
@LOOP00: LDA STATUS00DATA-1,Y
|
||||
STA (SMCMDLIST),Y
|
||||
DEY
|
||||
BNE @LOOP00
|
||||
CLC
|
||||
RTS
|
||||
|
||||
@PARTITION: LDX SMCSCODE
|
||||
BEQ @STATUS03 ; 0: device status
|
||||
DEX
|
||||
BEQ @GETDCB ; 1: get DCB
|
||||
DEX
|
||||
DEX
|
||||
BEQ @STATUS03 ; 3: get DIB
|
||||
LDA #ERR_BADCTL
|
||||
SEC
|
||||
RTS
|
||||
|
||||
@GETDCB: LDA #1 ; return 'empty' DCB, one byte
|
||||
STA (SMCMDLIST)
|
||||
TAY
|
||||
LDA #NO_ERR
|
||||
STA (SMCMDLIST),Y
|
||||
CLC
|
||||
RTS
|
||||
|
||||
@STATUS03: LDA #$E8 ; block device, read, write, format,
|
||||
; not online, no write-protect
|
||||
LDX SLOT16
|
||||
JSR CARDDET
|
||||
BCS @WRPROT
|
||||
ORA #$10 ; card inserted
|
||||
@WRPROT: JSR WRPROT
|
||||
BCC @STATUSBYTE
|
||||
ORA #$04 ; SD card write-protected
|
||||
@STATUSBYTE:STA (SMCMDLIST)
|
||||
|
||||
LDY #1 ; block count, always $00FFFF
|
||||
LDA #$FF
|
||||
STA (SMCMDLIST),Y
|
||||
INY
|
||||
STA (SMCMDLIST),Y
|
||||
INY
|
||||
LDA #0
|
||||
STA (SMCMDLIST),Y
|
||||
|
||||
LDA SMCSCODE
|
||||
BEQ @DONE ; done if code 0, else get DIB, 21 bytes
|
||||
|
||||
LDY #4
|
||||
@LOOP: LDA STATUS3DATA-4,Y
|
||||
STA (SMCMDLIST),Y
|
||||
INY
|
||||
CPY #21+4
|
||||
BCC @LOOP
|
||||
|
||||
@DONE: CLC
|
||||
RTS
|
||||
|
||||
|
||||
; Smartport Control command
|
||||
;
|
||||
; no controls supported, yet
|
||||
;
|
||||
SMCONTROL: JSR GETCSLIST
|
||||
LDX SMCSCODE
|
||||
BEQ @RESET ; 0: Reset
|
||||
DEX
|
||||
BEQ @SETDCB ; 1: SetDCB
|
||||
DEX
|
||||
BEQ @NEWLINE ; 2: SetNewLine
|
||||
DEX
|
||||
BEQ @IRQ ; 3: ServiceInterrupt
|
||||
DEX
|
||||
BEQ @EJECT ; 4: Eject
|
||||
|
||||
@NEWLINE: LDA #ERR_BADCTL
|
||||
SEC
|
||||
@RESET:
|
||||
@SETDCB:
|
||||
@EJECT: LDA #NO_ERR ; only return OK
|
||||
CLC
|
||||
RTS
|
||||
|
||||
@IRQ: LDA #ERR_NOINT ; interrupts not supported
|
||||
SEC
|
||||
RTS
|
||||
|
||||
|
||||
; Get control/status list pointer and code
|
||||
;
|
||||
GETCSLIST: LDY #2
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA SMCMDLIST ; get buffer pointer
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA SMCMDLIST+1
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA SMCSCODE ; get status/control code
|
||||
RTS
|
||||
|
||||
|
||||
; Smartport Read Block command
|
||||
;
|
||||
; reads a 512-byte block using the ProDOS function
|
||||
;
|
||||
SMREADBLOCK:
|
||||
JSR TRANSLATE
|
||||
BCC @READ
|
||||
RTS
|
||||
|
||||
@READ: LDX SLOT16
|
||||
LDY SLOT
|
||||
JMP READ ; call ProDOS read
|
||||
|
||||
|
||||
|
||||
; Smartport Write Block command
|
||||
;
|
||||
; writes a 512-byte block using the ProDOS function
|
||||
;
|
||||
SMWRITEBLOCK:
|
||||
JSR TRANSLATE
|
||||
BCC @WRITE
|
||||
RTS
|
||||
|
||||
@WRITE: LDX SLOT16
|
||||
LDY SLOT
|
||||
JMP WRITE ; call ProDOS write
|
||||
|
||||
|
||||
; Translates the Smartport unit number to a ProDOS device
|
||||
; and prepares the block number
|
||||
;
|
||||
; Unit 0: entire chain, not supported
|
||||
; Unit 1: this slot, drive 0
|
||||
; Unit 2: this slot, drive 1
|
||||
; Unit 3: phantom slot, drive 0
|
||||
; Unit 4: phantom slot, drive 1
|
||||
;
|
||||
TRANSLATE: LDA DRVNUM,Y
|
||||
BEQ @BADUNIT ; not supportd for unit 0
|
||||
CMP #1
|
||||
BEQ @UNIT1
|
||||
CMP #2
|
||||
BEQ @UNIT2
|
||||
CMP #3
|
||||
BEQ @UNIT3
|
||||
CMP #4
|
||||
BEQ @UNIT4
|
||||
BRA @BADUNIT ; only 4 partitions are supported
|
||||
|
||||
@UNIT1: LDA SLOT16 ; this slot
|
||||
BRA @STORE
|
||||
@UNIT2: LDA SLOT16
|
||||
ORA #$80 ; drive 1
|
||||
BRA @STORE
|
||||
@UNIT3: LDA SLOT16
|
||||
DEC A ; phantom slot
|
||||
BRA @STORE
|
||||
@UNIT4: LDA SLOT16
|
||||
DEC A ; phantom slot
|
||||
ORA #$80 ; drive 1
|
||||
|
||||
@STORE: STA DSNUMBER ; store in ProDOS variable
|
||||
|
||||
LDY #2 ; get buffer pointer
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA BUFFER
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA BUFFER+1
|
||||
|
||||
INY ; get block number
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA BLOCKNUM
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA BLOCKNUM+1
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
BNE @BADBLOCK ; bit 23-16 need to be 0
|
||||
|
||||
CLC
|
||||
RTS
|
||||
|
||||
@BADUNIT: LDA #ERR_BADUNIT
|
||||
SEC
|
||||
RTS
|
||||
|
||||
@BADBLOCK: LDA #ERR_BADBLOCK
|
||||
SEC
|
||||
RTS
|
||||
|
||||
|
||||
; Smartport Format command
|
||||
;
|
||||
; supported, but doesn't do anything
|
||||
; unit number must not be 0
|
||||
;
|
||||
SMFORMAT: LDA DRVNUM,Y
|
||||
BEQ @ERROR
|
||||
LDA #NO_ERR
|
||||
CLC
|
||||
RTS
|
||||
|
||||
@ERROR: LDA #ERR_BADUNIT
|
||||
SEC
|
||||
RTS
|
||||
|
||||
|
||||
; Smartport Init comand
|
||||
;
|
||||
; supported, but doesn't do anything
|
||||
; unit number must be 0
|
||||
;
|
||||
SMINIT: LDA DRVNUM,Y
|
||||
CLC
|
||||
BEQ @END ; error if not 0
|
||||
LDA #ERR_BADUNIT
|
||||
SEC
|
||||
@END: RTS
|
||||
|
||||
|
||||
; Smartport Open and Close commands
|
||||
;
|
||||
; supported for character devices, only
|
||||
;
|
||||
SMOPEN:
|
||||
SMCLOSE: LDA #ERR_BADCMD
|
||||
SEC
|
||||
RTS
|
||||
|
||||
|
||||
; Smartport Read Character and Write Character
|
||||
;
|
||||
; only 512-byte block operations are supported
|
||||
;
|
||||
SMREADCHAR:
|
||||
SMWRITECHAR:
|
||||
LDA #ERR_IOERR
|
||||
SEC
|
||||
RTS
|
||||
|
||||
|
||||
; Required parameter counts for the commands
|
||||
REQPARAMCOUNT:
|
||||
.byt 3 ; 0 = status
|
||||
.byt 3 ; 1 = read block
|
||||
.byt 3 ; 2 = write block
|
||||
.byt 1 ; 3 = format
|
||||
.byt 3 ; 4 = control
|
||||
.byt 1 ; 5 = init
|
||||
.byt 1 ; 6 = open
|
||||
.byt 1 ; 7 = close
|
||||
.byt 4 ; 8 = read char
|
||||
.byt 4 ; 9 = write char
|
||||
|
||||
; Command jump table
|
||||
SPDISPATCH:
|
||||
.word SMSTATUS
|
||||
.word SMREADBLOCK
|
||||
.word SMWRITEBLOCK
|
||||
.word SMFORMAT
|
||||
.word SMCONTROL
|
||||
.word SMINIT
|
||||
.word SMOPEN
|
||||
.word SMCLOSE
|
||||
.word SMREADCHAR
|
||||
.word SMWRITECHAR
|
||||
|
||||
; Status 00 command data
|
||||
STATUS00DATA:
|
||||
.byt $40 ; no interrupts
|
||||
.word $0000 ; unknown vendor
|
||||
.word SMDRIVERVER ; driver version
|
||||
.byt $00, $00 ; reserved
|
||||
.assert(*-STATUS00DATA)=7, error, "STATUS00DATA must be 7 bytes long"
|
||||
|
||||
; Status 3 command data
|
||||
STATUS3DATA:
|
||||
.byt 16, "APPLE][SD " ; ID length and string, padded
|
||||
.byt $02 ; hard disk
|
||||
.byt $00 ; removable hard disk
|
||||
.word SMDRIVERVER ; driver version
|
||||
.assert (*-STATUS3DATA)=21, error, "STATUS3DATA must be 21 bytes long"
|
||||
Binary file not shown.
|
|
@ -1,280 +0,0 @@
|
|||
G75*
|
||||
%MOIN*%
|
||||
%OFA0B0*%
|
||||
%FSLAX25Y25*%
|
||||
%IPPOS*%
|
||||
%LPD*%
|
||||
%AMOC8*
|
||||
5,1,8,0,0,1.08239X$1,22.5*
|
||||
%
|
||||
%ADD10C,0.01000*%
|
||||
%ADD11C,0.00000*%
|
||||
D10*
|
||||
X0306900Y0070642D02*
|
||||
X0306900Y0345445D01*
|
||||
X0701388Y0345445D01*
|
||||
X0701388Y0070642D01*
|
||||
X0663987Y0070642D01*
|
||||
X0663987Y0041902D01*
|
||||
X0661624Y0039540D01*
|
||||
X0407294Y0039540D01*
|
||||
X0404931Y0041902D01*
|
||||
X0404931Y0070642D01*
|
||||
X0306900Y0070642D01*
|
||||
D11*
|
||||
X0674203Y0122886D02*
|
||||
X0674205Y0123047D01*
|
||||
X0674211Y0123207D01*
|
||||
X0674221Y0123368D01*
|
||||
X0674235Y0123528D01*
|
||||
X0674253Y0123688D01*
|
||||
X0674274Y0123847D01*
|
||||
X0674300Y0124006D01*
|
||||
X0674330Y0124164D01*
|
||||
X0674363Y0124321D01*
|
||||
X0674401Y0124478D01*
|
||||
X0674442Y0124633D01*
|
||||
X0674487Y0124787D01*
|
||||
X0674536Y0124940D01*
|
||||
X0674589Y0125092D01*
|
||||
X0674645Y0125243D01*
|
||||
X0674706Y0125392D01*
|
||||
X0674769Y0125540D01*
|
||||
X0674837Y0125686D01*
|
||||
X0674908Y0125830D01*
|
||||
X0674982Y0125972D01*
|
||||
X0675060Y0126113D01*
|
||||
X0675142Y0126251D01*
|
||||
X0675227Y0126388D01*
|
||||
X0675315Y0126522D01*
|
||||
X0675407Y0126654D01*
|
||||
X0675502Y0126784D01*
|
||||
X0675600Y0126912D01*
|
||||
X0675701Y0127037D01*
|
||||
X0675805Y0127159D01*
|
||||
X0675912Y0127279D01*
|
||||
X0676022Y0127396D01*
|
||||
X0676135Y0127511D01*
|
||||
X0676251Y0127622D01*
|
||||
X0676370Y0127731D01*
|
||||
X0676491Y0127836D01*
|
||||
X0676615Y0127939D01*
|
||||
X0676741Y0128039D01*
|
||||
X0676869Y0128135D01*
|
||||
X0677000Y0128228D01*
|
||||
X0677134Y0128318D01*
|
||||
X0677269Y0128405D01*
|
||||
X0677407Y0128488D01*
|
||||
X0677546Y0128568D01*
|
||||
X0677688Y0128644D01*
|
||||
X0677831Y0128717D01*
|
||||
X0677976Y0128786D01*
|
||||
X0678123Y0128852D01*
|
||||
X0678271Y0128914D01*
|
||||
X0678421Y0128972D01*
|
||||
X0678572Y0129027D01*
|
||||
X0678725Y0129078D01*
|
||||
X0678879Y0129125D01*
|
||||
X0679034Y0129168D01*
|
||||
X0679190Y0129207D01*
|
||||
X0679346Y0129243D01*
|
||||
X0679504Y0129274D01*
|
||||
X0679662Y0129302D01*
|
||||
X0679821Y0129326D01*
|
||||
X0679981Y0129346D01*
|
||||
X0680141Y0129362D01*
|
||||
X0680301Y0129374D01*
|
||||
X0680462Y0129382D01*
|
||||
X0680623Y0129386D01*
|
||||
X0680783Y0129386D01*
|
||||
X0680944Y0129382D01*
|
||||
X0681105Y0129374D01*
|
||||
X0681265Y0129362D01*
|
||||
X0681425Y0129346D01*
|
||||
X0681585Y0129326D01*
|
||||
X0681744Y0129302D01*
|
||||
X0681902Y0129274D01*
|
||||
X0682060Y0129243D01*
|
||||
X0682216Y0129207D01*
|
||||
X0682372Y0129168D01*
|
||||
X0682527Y0129125D01*
|
||||
X0682681Y0129078D01*
|
||||
X0682834Y0129027D01*
|
||||
X0682985Y0128972D01*
|
||||
X0683135Y0128914D01*
|
||||
X0683283Y0128852D01*
|
||||
X0683430Y0128786D01*
|
||||
X0683575Y0128717D01*
|
||||
X0683718Y0128644D01*
|
||||
X0683860Y0128568D01*
|
||||
X0683999Y0128488D01*
|
||||
X0684137Y0128405D01*
|
||||
X0684272Y0128318D01*
|
||||
X0684406Y0128228D01*
|
||||
X0684537Y0128135D01*
|
||||
X0684665Y0128039D01*
|
||||
X0684791Y0127939D01*
|
||||
X0684915Y0127836D01*
|
||||
X0685036Y0127731D01*
|
||||
X0685155Y0127622D01*
|
||||
X0685271Y0127511D01*
|
||||
X0685384Y0127396D01*
|
||||
X0685494Y0127279D01*
|
||||
X0685601Y0127159D01*
|
||||
X0685705Y0127037D01*
|
||||
X0685806Y0126912D01*
|
||||
X0685904Y0126784D01*
|
||||
X0685999Y0126654D01*
|
||||
X0686091Y0126522D01*
|
||||
X0686179Y0126388D01*
|
||||
X0686264Y0126251D01*
|
||||
X0686346Y0126113D01*
|
||||
X0686424Y0125972D01*
|
||||
X0686498Y0125830D01*
|
||||
X0686569Y0125686D01*
|
||||
X0686637Y0125540D01*
|
||||
X0686700Y0125392D01*
|
||||
X0686761Y0125243D01*
|
||||
X0686817Y0125092D01*
|
||||
X0686870Y0124940D01*
|
||||
X0686919Y0124787D01*
|
||||
X0686964Y0124633D01*
|
||||
X0687005Y0124478D01*
|
||||
X0687043Y0124321D01*
|
||||
X0687076Y0124164D01*
|
||||
X0687106Y0124006D01*
|
||||
X0687132Y0123847D01*
|
||||
X0687153Y0123688D01*
|
||||
X0687171Y0123528D01*
|
||||
X0687185Y0123368D01*
|
||||
X0687195Y0123207D01*
|
||||
X0687201Y0123047D01*
|
||||
X0687203Y0122886D01*
|
||||
X0687201Y0122725D01*
|
||||
X0687195Y0122565D01*
|
||||
X0687185Y0122404D01*
|
||||
X0687171Y0122244D01*
|
||||
X0687153Y0122084D01*
|
||||
X0687132Y0121925D01*
|
||||
X0687106Y0121766D01*
|
||||
X0687076Y0121608D01*
|
||||
X0687043Y0121451D01*
|
||||
X0687005Y0121294D01*
|
||||
X0686964Y0121139D01*
|
||||
X0686919Y0120985D01*
|
||||
X0686870Y0120832D01*
|
||||
X0686817Y0120680D01*
|
||||
X0686761Y0120529D01*
|
||||
X0686700Y0120380D01*
|
||||
X0686637Y0120232D01*
|
||||
X0686569Y0120086D01*
|
||||
X0686498Y0119942D01*
|
||||
X0686424Y0119800D01*
|
||||
X0686346Y0119659D01*
|
||||
X0686264Y0119521D01*
|
||||
X0686179Y0119384D01*
|
||||
X0686091Y0119250D01*
|
||||
X0685999Y0119118D01*
|
||||
X0685904Y0118988D01*
|
||||
X0685806Y0118860D01*
|
||||
X0685705Y0118735D01*
|
||||
X0685601Y0118613D01*
|
||||
X0685494Y0118493D01*
|
||||
X0685384Y0118376D01*
|
||||
X0685271Y0118261D01*
|
||||
X0685155Y0118150D01*
|
||||
X0685036Y0118041D01*
|
||||
X0684915Y0117936D01*
|
||||
X0684791Y0117833D01*
|
||||
X0684665Y0117733D01*
|
||||
X0684537Y0117637D01*
|
||||
X0684406Y0117544D01*
|
||||
X0684272Y0117454D01*
|
||||
X0684137Y0117367D01*
|
||||
X0683999Y0117284D01*
|
||||
X0683860Y0117204D01*
|
||||
X0683718Y0117128D01*
|
||||
X0683575Y0117055D01*
|
||||
X0683430Y0116986D01*
|
||||
X0683283Y0116920D01*
|
||||
X0683135Y0116858D01*
|
||||
X0682985Y0116800D01*
|
||||
X0682834Y0116745D01*
|
||||
X0682681Y0116694D01*
|
||||
X0682527Y0116647D01*
|
||||
X0682372Y0116604D01*
|
||||
X0682216Y0116565D01*
|
||||
X0682060Y0116529D01*
|
||||
X0681902Y0116498D01*
|
||||
X0681744Y0116470D01*
|
||||
X0681585Y0116446D01*
|
||||
X0681425Y0116426D01*
|
||||
X0681265Y0116410D01*
|
||||
X0681105Y0116398D01*
|
||||
X0680944Y0116390D01*
|
||||
X0680783Y0116386D01*
|
||||
X0680623Y0116386D01*
|
||||
X0680462Y0116390D01*
|
||||
X0680301Y0116398D01*
|
||||
X0680141Y0116410D01*
|
||||
X0679981Y0116426D01*
|
||||
X0679821Y0116446D01*
|
||||
X0679662Y0116470D01*
|
||||
X0679504Y0116498D01*
|
||||
X0679346Y0116529D01*
|
||||
X0679190Y0116565D01*
|
||||
X0679034Y0116604D01*
|
||||
X0678879Y0116647D01*
|
||||
X0678725Y0116694D01*
|
||||
X0678572Y0116745D01*
|
||||
X0678421Y0116800D01*
|
||||
X0678271Y0116858D01*
|
||||
X0678123Y0116920D01*
|
||||
X0677976Y0116986D01*
|
||||
X0677831Y0117055D01*
|
||||
X0677688Y0117128D01*
|
||||
X0677546Y0117204D01*
|
||||
X0677407Y0117284D01*
|
||||
X0677269Y0117367D01*
|
||||
X0677134Y0117454D01*
|
||||
X0677000Y0117544D01*
|
||||
X0676869Y0117637D01*
|
||||
X0676741Y0117733D01*
|
||||
X0676615Y0117833D01*
|
||||
X0676491Y0117936D01*
|
||||
X0676370Y0118041D01*
|
||||
X0676251Y0118150D01*
|
||||
X0676135Y0118261D01*
|
||||
X0676022Y0118376D01*
|
||||
X0675912Y0118493D01*
|
||||
X0675805Y0118613D01*
|
||||
X0675701Y0118735D01*
|
||||
X0675600Y0118860D01*
|
||||
X0675502Y0118988D01*
|
||||
X0675407Y0119118D01*
|
||||
X0675315Y0119250D01*
|
||||
X0675227Y0119384D01*
|
||||
X0675142Y0119521D01*
|
||||
X0675060Y0119659D01*
|
||||
X0674982Y0119800D01*
|
||||
X0674908Y0119942D01*
|
||||
X0674837Y0120086D01*
|
||||
X0674769Y0120232D01*
|
||||
X0674706Y0120380D01*
|
||||
X0674645Y0120529D01*
|
||||
X0674589Y0120680D01*
|
||||
X0674536Y0120832D01*
|
||||
X0674487Y0120985D01*
|
||||
X0674442Y0121139D01*
|
||||
X0674401Y0121294D01*
|
||||
X0674363Y0121451D01*
|
||||
X0674330Y0121608D01*
|
||||
X0674300Y0121766D01*
|
||||
X0674274Y0121925D01*
|
||||
X0674253Y0122084D01*
|
||||
X0674235Y0122244D01*
|
||||
X0674221Y0122404D01*
|
||||
X0674211Y0122565D01*
|
||||
X0674205Y0122725D01*
|
||||
X0674203Y0122886D01*
|
||||
M02*
|
||||
|
|
@ -1,738 +0,0 @@
|
|||
G75*
|
||||
%MOIN*%
|
||||
%OFA0B0*%
|
||||
%FSLAX25Y25*%
|
||||
%IPPOS*%
|
||||
%LPD*%
|
||||
%AMOC8*
|
||||
5,1,8,0,0,1.08239X$1,22.5*
|
||||
%
|
||||
%ADD10R,0.06000X0.25500*%
|
||||
%ADD11C,0.04775*%
|
||||
%ADD12OC8,0.04775*%
|
||||
%ADD13C,0.04775*%
|
||||
%ADD14C,0.05575*%
|
||||
%ADD15OC8,0.06300*%
|
||||
%ADD16C,0.06300*%
|
||||
%ADD17R,0.03937X0.04331*%
|
||||
%ADD18R,0.04331X0.03937*%
|
||||
%ADD19R,0.03937X0.06299*%
|
||||
%ADD20C,0.07874*%
|
||||
%ADD21R,0.06890X0.04724*%
|
||||
%ADD22R,0.06890X0.03937*%
|
||||
%ADD23R,0.04134X0.04252*%
|
||||
%ADD24C,0.01575*%
|
||||
%ADD25C,0.02559*%
|
||||
%ADD26C,0.02362*%
|
||||
D10*
|
||||
X0414400Y0057433D03*
|
||||
X0424400Y0057433D03*
|
||||
X0434400Y0057433D03*
|
||||
X0444400Y0057433D03*
|
||||
X0454400Y0057433D03*
|
||||
X0464400Y0057433D03*
|
||||
X0474400Y0057433D03*
|
||||
X0484400Y0057433D03*
|
||||
X0494400Y0057433D03*
|
||||
X0504400Y0057433D03*
|
||||
X0514400Y0057433D03*
|
||||
X0524400Y0057433D03*
|
||||
X0534400Y0057433D03*
|
||||
X0544400Y0057433D03*
|
||||
X0554400Y0057433D03*
|
||||
X0564400Y0057433D03*
|
||||
X0574400Y0057433D03*
|
||||
X0584400Y0057433D03*
|
||||
X0594400Y0057433D03*
|
||||
X0604400Y0057433D03*
|
||||
X0614400Y0057433D03*
|
||||
X0624400Y0057433D03*
|
||||
X0634400Y0057433D03*
|
||||
X0644400Y0057433D03*
|
||||
X0654400Y0057433D03*
|
||||
D11*
|
||||
X0456821Y0317729D03*
|
||||
D12*
|
||||
X0446821Y0317729D03*
|
||||
X0436821Y0317729D03*
|
||||
X0426821Y0317729D03*
|
||||
X0416821Y0317729D03*
|
||||
X0416821Y0307729D03*
|
||||
X0426821Y0307729D03*
|
||||
X0426821Y0297729D03*
|
||||
X0416821Y0297729D03*
|
||||
X0416821Y0287729D03*
|
||||
X0426821Y0287729D03*
|
||||
X0426821Y0277729D03*
|
||||
X0416821Y0277729D03*
|
||||
X0416821Y0267729D03*
|
||||
X0426821Y0267729D03*
|
||||
X0436821Y0267729D03*
|
||||
X0446821Y0267729D03*
|
||||
X0456821Y0267729D03*
|
||||
X0466821Y0267729D03*
|
||||
X0476821Y0267729D03*
|
||||
X0486821Y0267729D03*
|
||||
X0486821Y0277729D03*
|
||||
X0476821Y0277729D03*
|
||||
X0476821Y0287729D03*
|
||||
X0486821Y0287729D03*
|
||||
X0486821Y0297729D03*
|
||||
X0476821Y0297729D03*
|
||||
X0476821Y0307729D03*
|
||||
X0486821Y0307729D03*
|
||||
X0486821Y0317729D03*
|
||||
X0476821Y0317729D03*
|
||||
X0466821Y0317729D03*
|
||||
X0466821Y0327729D03*
|
||||
X0476821Y0327729D03*
|
||||
X0456821Y0327729D03*
|
||||
X0446821Y0327729D03*
|
||||
X0436821Y0327729D03*
|
||||
X0426821Y0327729D03*
|
||||
X0531743Y0331548D03*
|
||||
X0531743Y0321548D03*
|
||||
X0476821Y0257729D03*
|
||||
X0466821Y0257729D03*
|
||||
X0456821Y0257729D03*
|
||||
X0446821Y0257729D03*
|
||||
X0436821Y0257729D03*
|
||||
X0426821Y0257729D03*
|
||||
D13*
|
||||
X0429144Y0219722D02*
|
||||
X0429144Y0214948D01*
|
||||
X0419144Y0214948D02*
|
||||
X0419144Y0219722D01*
|
||||
X0409144Y0219722D02*
|
||||
X0409144Y0214948D01*
|
||||
X0399144Y0214948D02*
|
||||
X0399144Y0219722D01*
|
||||
X0389144Y0219722D02*
|
||||
X0389144Y0214948D01*
|
||||
X0379144Y0214948D02*
|
||||
X0379144Y0219722D01*
|
||||
X0439144Y0219722D02*
|
||||
X0439144Y0214948D01*
|
||||
X0449144Y0214948D02*
|
||||
X0449144Y0219722D01*
|
||||
X0459144Y0219722D02*
|
||||
X0459144Y0214948D01*
|
||||
X0469144Y0214948D02*
|
||||
X0469144Y0219722D01*
|
||||
X0479144Y0219722D02*
|
||||
X0479144Y0214948D01*
|
||||
X0489144Y0214948D02*
|
||||
X0489144Y0219722D01*
|
||||
X0489144Y0159722D02*
|
||||
X0489144Y0154948D01*
|
||||
X0479144Y0154948D02*
|
||||
X0479144Y0159722D01*
|
||||
X0469144Y0159722D02*
|
||||
X0469144Y0154948D01*
|
||||
X0459144Y0154948D02*
|
||||
X0459144Y0159722D01*
|
||||
X0449144Y0159722D02*
|
||||
X0449144Y0154948D01*
|
||||
X0439144Y0154948D02*
|
||||
X0439144Y0159722D01*
|
||||
X0429144Y0159722D02*
|
||||
X0429144Y0154948D01*
|
||||
X0419144Y0154948D02*
|
||||
X0419144Y0159722D01*
|
||||
X0409144Y0159722D02*
|
||||
X0409144Y0154948D01*
|
||||
X0399144Y0154948D02*
|
||||
X0399144Y0159722D01*
|
||||
X0389144Y0159722D02*
|
||||
X0389144Y0154948D01*
|
||||
X0379144Y0154948D02*
|
||||
X0379144Y0159722D01*
|
||||
X0419302Y0127596D02*
|
||||
X0419302Y0122822D01*
|
||||
X0429302Y0122822D02*
|
||||
X0429302Y0127596D01*
|
||||
X0439302Y0127596D02*
|
||||
X0439302Y0122822D01*
|
||||
X0449302Y0122822D02*
|
||||
X0449302Y0127596D01*
|
||||
X0459302Y0127596D02*
|
||||
X0459302Y0122822D01*
|
||||
X0469302Y0122822D02*
|
||||
X0469302Y0127596D01*
|
||||
X0479302Y0127596D02*
|
||||
X0479302Y0122822D01*
|
||||
X0489302Y0122822D02*
|
||||
X0489302Y0127596D01*
|
||||
X0499302Y0127596D02*
|
||||
X0499302Y0122822D01*
|
||||
X0509302Y0122822D02*
|
||||
X0509302Y0127596D01*
|
||||
X0509302Y0097596D02*
|
||||
X0509302Y0092822D01*
|
||||
X0499302Y0092822D02*
|
||||
X0499302Y0097596D01*
|
||||
X0489302Y0097596D02*
|
||||
X0489302Y0092822D01*
|
||||
X0479302Y0092822D02*
|
||||
X0479302Y0097596D01*
|
||||
X0469302Y0097596D02*
|
||||
X0469302Y0092822D01*
|
||||
X0459302Y0092822D02*
|
||||
X0459302Y0097596D01*
|
||||
X0449302Y0097596D02*
|
||||
X0449302Y0092822D01*
|
||||
X0439302Y0092822D02*
|
||||
X0439302Y0097596D01*
|
||||
X0429302Y0097596D02*
|
||||
X0429302Y0092822D01*
|
||||
X0419302Y0092822D02*
|
||||
X0419302Y0097596D01*
|
||||
D14*
|
||||
X0618916Y0112886D02*
|
||||
X0624491Y0112886D01*
|
||||
X0624491Y0122886D02*
|
||||
X0618916Y0122886D01*
|
||||
X0618916Y0132886D02*
|
||||
X0624491Y0132886D01*
|
||||
X0498987Y0230059D02*
|
||||
X0498987Y0235634D01*
|
||||
X0488987Y0235634D02*
|
||||
X0488987Y0230059D01*
|
||||
X0478987Y0230059D02*
|
||||
X0478987Y0235634D01*
|
||||
X0367758Y0282650D02*
|
||||
X0362183Y0282650D01*
|
||||
X0362183Y0292650D02*
|
||||
X0367758Y0292650D01*
|
||||
X0367758Y0302650D02*
|
||||
X0362183Y0302650D01*
|
||||
X0362183Y0312650D02*
|
||||
X0367758Y0312650D01*
|
||||
X0367758Y0322650D02*
|
||||
X0362183Y0322650D01*
|
||||
X0362183Y0332650D02*
|
||||
X0367758Y0332650D01*
|
||||
D15*
|
||||
X0598858Y0122689D03*
|
||||
D16*
|
||||
X0608858Y0122689D03*
|
||||
D17*
|
||||
X0609420Y0149264D03*
|
||||
X0602727Y0149264D03*
|
||||
X0618475Y0149146D03*
|
||||
X0625168Y0149146D03*
|
||||
X0613396Y0096036D03*
|
||||
X0606703Y0096036D03*
|
||||
D18*
|
||||
X0605128Y0180288D03*
|
||||
X0595286Y0180288D03*
|
||||
X0595286Y0186981D03*
|
||||
X0605128Y0186981D03*
|
||||
X0614971Y0186981D03*
|
||||
X0614971Y0180288D03*
|
||||
X0663396Y0180327D03*
|
||||
X0663396Y0187020D03*
|
||||
X0673042Y0186981D03*
|
||||
X0673042Y0180288D03*
|
||||
X0694695Y0251154D03*
|
||||
X0694695Y0257847D03*
|
||||
X0694695Y0264933D03*
|
||||
X0694695Y0271626D03*
|
||||
X0531624Y0304343D03*
|
||||
X0531624Y0311036D03*
|
||||
D19*
|
||||
X0594794Y0199382D03*
|
||||
X0604636Y0199382D03*
|
||||
X0614479Y0199382D03*
|
||||
X0624321Y0199382D03*
|
||||
X0634164Y0199382D03*
|
||||
X0644006Y0199382D03*
|
||||
X0653849Y0199382D03*
|
||||
X0663691Y0199382D03*
|
||||
X0670187Y0199382D03*
|
||||
D20*
|
||||
X0684459Y0294658D03*
|
||||
X0574420Y0294658D03*
|
||||
D21*
|
||||
X0683376Y0243870D03*
|
||||
D22*
|
||||
X0683376Y0278516D03*
|
||||
X0683376Y0283634D03*
|
||||
D23*
|
||||
X0613494Y0104894D03*
|
||||
X0606605Y0104894D03*
|
||||
D24*
|
||||
X0607097Y0105386D01*
|
||||
X0607097Y0112768D01*
|
||||
X0598858Y0121007D01*
|
||||
X0598858Y0122689D01*
|
||||
X0599223Y0123054D01*
|
||||
X0599223Y0133437D01*
|
||||
X0602727Y0136941D01*
|
||||
X0602727Y0149264D01*
|
||||
X0609420Y0149264D02*
|
||||
X0618357Y0149264D01*
|
||||
X0618475Y0149146D01*
|
||||
X0618475Y0142729D01*
|
||||
X0621861Y0139343D01*
|
||||
X0621861Y0133044D01*
|
||||
X0621703Y0132886D01*
|
||||
X0629026Y0122886D02*
|
||||
X0634459Y0128319D01*
|
||||
X0634459Y0149308D01*
|
||||
X0634297Y0149146D01*
|
||||
X0625168Y0149146D01*
|
||||
X0634459Y0149308D02*
|
||||
X0634459Y0180449D01*
|
||||
X0634621Y0180288D01*
|
||||
X0663435Y0180288D01*
|
||||
X0663396Y0180327D01*
|
||||
X0663435Y0180288D02*
|
||||
X0673042Y0180288D01*
|
||||
X0673042Y0186981D02*
|
||||
X0673042Y0190524D01*
|
||||
X0670187Y0193378D01*
|
||||
X0670187Y0199382D01*
|
||||
X0663691Y0199382D02*
|
||||
X0663691Y0187315D01*
|
||||
X0663396Y0187020D01*
|
||||
X0654341Y0193477D02*
|
||||
X0653849Y0193969D01*
|
||||
X0653849Y0199382D01*
|
||||
X0663199Y0199874D02*
|
||||
X0663199Y0230878D01*
|
||||
X0644006Y0235307D02*
|
||||
X0638593Y0240721D01*
|
||||
X0546073Y0240721D01*
|
||||
X0548042Y0243673D02*
|
||||
X0683180Y0243673D01*
|
||||
X0683376Y0243870D01*
|
||||
X0683573Y0243673D01*
|
||||
X0691743Y0243673D01*
|
||||
X0694695Y0246626D01*
|
||||
X0694695Y0251154D01*
|
||||
X0694695Y0257847D02*
|
||||
X0694695Y0264933D01*
|
||||
X0633840Y0264933D01*
|
||||
X0633672Y0264765D01*
|
||||
X0633672Y0247610D01*
|
||||
X0633672Y0237768D02*
|
||||
X0634164Y0237276D01*
|
||||
X0634164Y0199382D01*
|
||||
X0634656Y0199874D01*
|
||||
X0634164Y0199382D02*
|
||||
X0634459Y0199087D01*
|
||||
X0634459Y0180681D01*
|
||||
X0634459Y0180449D01*
|
||||
X0634621Y0180288D02*
|
||||
X0614971Y0180288D01*
|
||||
X0605128Y0180288D01*
|
||||
X0595286Y0180288D01*
|
||||
X0595286Y0186981D02*
|
||||
X0594794Y0187473D01*
|
||||
X0594794Y0199382D01*
|
||||
X0604636Y0199382D02*
|
||||
X0604636Y0187473D01*
|
||||
X0605128Y0186981D01*
|
||||
X0614479Y0187473D02*
|
||||
X0614971Y0186981D01*
|
||||
X0614479Y0187473D02*
|
||||
X0614479Y0199382D01*
|
||||
X0614479Y0229402D01*
|
||||
X0606113Y0237768D01*
|
||||
X0551979Y0237768D01*
|
||||
X0547057Y0234815D02*
|
||||
X0599223Y0234815D01*
|
||||
X0604636Y0229402D01*
|
||||
X0604636Y0199382D01*
|
||||
X0624321Y0199382D02*
|
||||
X0624321Y0193969D01*
|
||||
X0624813Y0193477D01*
|
||||
X0644006Y0199382D02*
|
||||
X0644006Y0235307D01*
|
||||
X0633840Y0264933D02*
|
||||
X0546776Y0264933D01*
|
||||
X0541152Y0270557D01*
|
||||
X0541152Y0326351D01*
|
||||
X0536231Y0331272D01*
|
||||
X0532018Y0331272D01*
|
||||
X0531743Y0331548D01*
|
||||
X0502491Y0331548D01*
|
||||
X0498829Y0335209D01*
|
||||
X0453554Y0335209D01*
|
||||
X0451585Y0333240D01*
|
||||
X0451585Y0332422D01*
|
||||
X0451357Y0332650D01*
|
||||
X0364971Y0332650D01*
|
||||
X0383672Y0305681D02*
|
||||
X0405325Y0327335D01*
|
||||
X0426428Y0327335D01*
|
||||
X0426821Y0327729D01*
|
||||
X0436821Y0327729D02*
|
||||
X0441743Y0322807D01*
|
||||
X0441743Y0316508D01*
|
||||
X0437806Y0312571D01*
|
||||
X0406309Y0312571D01*
|
||||
X0399144Y0305406D01*
|
||||
X0399144Y0217335D01*
|
||||
X0399420Y0217059D01*
|
||||
X0399420Y0200366D01*
|
||||
X0394498Y0195445D01*
|
||||
X0394498Y0114736D01*
|
||||
X0384656Y0111784D02*
|
||||
X0384656Y0195445D01*
|
||||
X0389577Y0200366D01*
|
||||
X0389577Y0216902D01*
|
||||
X0389144Y0217335D01*
|
||||
X0389144Y0305248D01*
|
||||
X0406309Y0322414D01*
|
||||
X0432136Y0322414D01*
|
||||
X0436821Y0317729D01*
|
||||
X0446821Y0317729D02*
|
||||
X0446821Y0317650D01*
|
||||
X0431900Y0302729D01*
|
||||
X0411231Y0302729D01*
|
||||
X0409262Y0300760D01*
|
||||
X0409262Y0217453D01*
|
||||
X0409144Y0217335D01*
|
||||
X0409262Y0217217D01*
|
||||
X0409262Y0200366D01*
|
||||
X0404341Y0195445D01*
|
||||
X0404341Y0117689D01*
|
||||
X0428947Y0132453D02*
|
||||
X0429144Y0132650D01*
|
||||
X0429144Y0157335D01*
|
||||
X0419144Y0157335D02*
|
||||
X0419144Y0195406D01*
|
||||
X0414183Y0200366D01*
|
||||
X0414183Y0255485D01*
|
||||
X0412215Y0257453D01*
|
||||
X0412215Y0284028D01*
|
||||
X0415916Y0287729D01*
|
||||
X0416821Y0287729D01*
|
||||
X0422057Y0282965D02*
|
||||
X0426821Y0287729D01*
|
||||
X0422057Y0282965D02*
|
||||
X0422057Y0251548D01*
|
||||
X0424026Y0249579D01*
|
||||
X0424026Y0200366D01*
|
||||
X0428947Y0195445D01*
|
||||
X0428947Y0174776D01*
|
||||
X0414400Y0174559D02*
|
||||
X0414183Y0174776D01*
|
||||
X0414400Y0174559D02*
|
||||
X0414400Y0057433D01*
|
||||
X0424400Y0057433D02*
|
||||
X0424400Y0195071D01*
|
||||
X0419105Y0200366D01*
|
||||
X0419105Y0207453D01*
|
||||
X0419144Y0217335D01*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
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|
||||
X0447648Y0306666D01*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
||||
X0500798Y0240721D01*
|
||||
X0496861Y0243673D02*
|
||||
X0496861Y0257689D01*
|
||||
X0486821Y0267729D01*
|
||||
X0486821Y0277729D02*
|
||||
X0491349Y0277729D01*
|
||||
X0500798Y0268280D01*
|
||||
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|
||||
X0476428Y0278122D01*
|
||||
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|
||||
X0436821Y0267729D01*
|
||||
X0441743Y0262374D02*
|
||||
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|
||||
X0446664Y0239736D02*
|
||||
X0446664Y0257571D01*
|
||||
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|
||||
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|
||||
X0433869Y0226941D01*
|
||||
X0433869Y0200366D01*
|
||||
X0439144Y0195091D01*
|
||||
X0439144Y0157335D01*
|
||||
X0399144Y0157335D02*
|
||||
X0399144Y0195170D01*
|
||||
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|
||||
X0404341Y0305248D01*
|
||||
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|
||||
X0416821Y0307729D01*
|
||||
X0416585Y0317492D02*
|
||||
X0406309Y0317492D01*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X0379144Y0157335D02*
|
||||
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|
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|
||||
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|
||||
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|
||||
X0383672Y0305681D01*
|
||||
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|
||||
X0373829Y0291902D01*
|
||||
X0373829Y0166902D01*
|
||||
X0517530Y0091114D02*
|
||||
X0517530Y0249579D01*
|
||||
X0531309Y0240721D02*
|
||||
X0531624Y0241036D01*
|
||||
X0531624Y0304343D01*
|
||||
X0531624Y0311036D02*
|
||||
X0531743Y0311154D01*
|
||||
X0531743Y0321548D01*
|
||||
X0495876Y0313555D02*
|
||||
X0482648Y0313555D01*
|
||||
X0416821Y0317729D02*
|
||||
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|
||||
X0545089Y0279107D02*
|
||||
X0545680Y0278516D01*
|
||||
X0683376Y0278516D01*
|
||||
X0683770Y0278122D01*
|
||||
X0691743Y0278122D01*
|
||||
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|
||||
X0694695Y0271626D01*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
D25*
|
||||
X0373829Y0166902D03*
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
D26*
|
||||
X0517530Y0249579D03*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X0634656Y0074382D03*
|
||||
X0644498Y0074382D03*
|
||||
M02*
|
||||
|
|
@ -1,171 +0,0 @@
|
|||
%
|
||||
M48
|
||||
M72
|
||||
T01C0.01181
|
||||
T02C0.01378
|
||||
T03C0.03200
|
||||
T04C0.04000
|
||||
T05C0.06299
|
||||
T06C0.13000
|
||||
%
|
||||
T01
|
||||
X384656Y111784
|
||||
X394498Y114736
|
||||
X404341Y117689
|
||||
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|
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X520483Y83240
|
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X634656Y74382
|
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|
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|
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X551979Y237768
|
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X546073Y240721
|
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X548042Y243673
|
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|
||||
T02
|
||||
X373829Y166902
|
||||
X414183Y174776
|
||||
X428947Y174776
|
||||
X428947Y132453
|
||||
X499813Y135406
|
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X533278Y125563
|
||||
X530325Y95051
|
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X533278Y90130
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
X379735Y297807
|
||||
T03
|
||||
X416821Y297729
|
||||
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|
||||
X426821Y307729
|
||||
X416821Y307729
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
X449144Y157335
|
||||
X459144Y157335
|
||||
X469144Y157335
|
||||
X479144Y157335
|
||||
X489144Y157335
|
||||
X489302Y125209
|
||||
X499302Y125209
|
||||
X509302Y125209
|
||||
X479302Y125209
|
||||
X469302Y125209
|
||||
X459302Y125209
|
||||
X449302Y125209
|
||||
X439302Y125209
|
||||
X429302Y125209
|
||||
X419302Y125209
|
||||
X419302Y95209
|
||||
X429302Y95209
|
||||
X439302Y95209
|
||||
X449302Y95209
|
||||
X459302Y95209
|
||||
X469302Y95209
|
||||
X479302Y95209
|
||||
X489302Y95209
|
||||
X499302Y95209
|
||||
X509302Y95209
|
||||
X598858Y122689
|
||||
X608858Y122689
|
||||
T04
|
||||
X621703Y122886
|
||||
X621703Y112886
|
||||
X621703Y132886
|
||||
X498987Y232847
|
||||
X488987Y232847
|
||||
X478987Y232847
|
||||
X364971Y282650
|
||||
X364971Y292650
|
||||
X364971Y302650
|
||||
X364971Y312650
|
||||
X364971Y322650
|
||||
X364971Y332650
|
||||
T05
|
||||
X574420Y294658
|
||||
X684459Y294658
|
||||
T06
|
||||
X680703Y122886
|
||||
M30
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
Generated by EAGLE CAM Processor 7.7.0
|
||||
|
||||
Drill Station Info File: //LUDWIG-FS/Vertrieb/TEMP/RZF/AppleIISd/SD_A2.dri
|
||||
|
||||
Date : 18.07.2017 10:20
|
||||
Drills : generated
|
||||
Device : Excellon drill station, coordinate format 2.5 inch
|
||||
|
||||
Parameter settings:
|
||||
|
||||
Tolerance Drill + : 2.50 %
|
||||
Tolerance Drill - : 2.50 %
|
||||
Rotate : no
|
||||
Mirror : no
|
||||
Optimize : yes
|
||||
Auto fit : yes
|
||||
OffsetX : 0inch
|
||||
OffsetY : 0inch
|
||||
Layers : Drills Holes
|
||||
|
||||
Drill File Info:
|
||||
|
||||
Data Mode : Absolute
|
||||
Units : 1/100000 Inch
|
||||
|
||||
Drills used:
|
||||
|
||||
Code Size used
|
||||
|
||||
T01 0.0118inch 12
|
||||
T02 0.0138inch 35
|
||||
T03 0.0320inch 92
|
||||
T04 0.0400inch 12
|
||||
T05 0.0630inch 2
|
||||
T06 0.1300inch 1
|
||||
|
||||
Total number of drills: 154
|
||||
|
||||
Plotfiles:
|
||||
|
||||
//LUDWIG-FS/Vertrieb/TEMP/RZF/AppleIISd/SD_A2.drd
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
Generated by EAGLE CAM Processor 7.7.0
|
||||
|
||||
Photoplotter Info File: //LUDWIG-FS/Vertrieb/TEMP/RZF/AppleIISd/SD_A2.gpi
|
||||
|
||||
Date : 18.07.2017 10:20
|
||||
Plotfile : //LUDWIG-FS/Vertrieb/TEMP/RZF/AppleIISd/SD_A2.sts
|
||||
Apertures : generated:
|
||||
Device : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
|
||||
|
||||
Parameter settings:
|
||||
|
||||
Emulate Apertures : no
|
||||
Tolerance Draw + : 0.00 %
|
||||
Tolerance Draw - : 0.00 %
|
||||
Tolerance Flash + : 0.00 %
|
||||
Tolerance Flash - : 0.00 %
|
||||
Rotate : no
|
||||
Mirror : no
|
||||
Optimize : yes
|
||||
Auto fit : yes
|
||||
OffsetX : 0inch
|
||||
OffsetY : 0inch
|
||||
|
||||
Plotfile Info:
|
||||
|
||||
Coordinate Format : 2.5
|
||||
Coordinate Units : Inch
|
||||
Data Mode : Absolute
|
||||
Zero Suppression : None
|
||||
End Of Block : *
|
||||
|
||||
Apertures used:
|
||||
|
||||
Code Shape Size used
|
||||
|
||||
D10 rectangle 0.0659inch x 0.2609inch 25
|
||||
D11 round 0.0537inch 1
|
||||
D12 octagon 0.0537inch 45
|
||||
D13 draw 0.0537inch 44
|
||||
D14 draw 0.0617inch 12
|
||||
D15 round 0.1359inch 1
|
||||
D16 octagon 0.0689inch 1
|
||||
D17 round 0.0689inch 1
|
||||
D18 round 0.0846inch 2
|
||||
D19 rectangle 0.0472inch x 0.0484inch 4
|
||||
D20 rectangle 0.0484inch x 0.0472inch 12
|
||||
D21 round 0.0315inch 35
|
||||
D22 round 0.0295inch 12
|
||||
|
||||
|
||||
Layers:
|
||||
|
||||
*.cmp Top Layer
|
||||
*.sol Bottom Layer
|
||||
*.M1 Board Outline
|
||||
*.stc Top Soldermask
|
||||
*.sts Bottom Soldermask
|
||||
*.plc Top Silk
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,315 +0,0 @@
|
|||
G75*
|
||||
%MOIN*%
|
||||
%OFA0B0*%
|
||||
%FSLAX25Y25*%
|
||||
%IPPOS*%
|
||||
%LPD*%
|
||||
%AMOC8*
|
||||
5,1,8,0,0,1.08239X$1,22.5*
|
||||
%
|
||||
%ADD10R,0.06591X0.26091*%
|
||||
%ADD11C,0.05365*%
|
||||
%ADD12OC8,0.05365*%
|
||||
%ADD13C,0.05365*%
|
||||
%ADD14C,0.06165*%
|
||||
%ADD15C,0.13591*%
|
||||
%ADD16OC8,0.06891*%
|
||||
%ADD17C,0.06891*%
|
||||
%ADD18R,0.04528X0.04921*%
|
||||
%ADD19R,0.04921X0.04528*%
|
||||
%ADD20R,0.04528X0.06890*%
|
||||
%ADD21C,0.08465*%
|
||||
%ADD22R,0.07480X0.05315*%
|
||||
%ADD23R,0.07480X0.04528*%
|
||||
%ADD24R,0.04724X0.04843*%
|
||||
%ADD25C,0.03150*%
|
||||
%ADD26C,0.02953*%
|
||||
D10*
|
||||
X0414400Y0057433D03*
|
||||
X0424400Y0057433D03*
|
||||
X0434400Y0057433D03*
|
||||
X0444400Y0057433D03*
|
||||
X0454400Y0057433D03*
|
||||
X0464400Y0057433D03*
|
||||
X0474400Y0057433D03*
|
||||
X0484400Y0057433D03*
|
||||
X0494400Y0057433D03*
|
||||
X0504400Y0057433D03*
|
||||
X0514400Y0057433D03*
|
||||
X0524400Y0057433D03*
|
||||
X0534400Y0057433D03*
|
||||
X0544400Y0057433D03*
|
||||
X0554400Y0057433D03*
|
||||
X0564400Y0057433D03*
|
||||
X0574400Y0057433D03*
|
||||
X0584400Y0057433D03*
|
||||
X0594400Y0057433D03*
|
||||
X0604400Y0057433D03*
|
||||
X0614400Y0057433D03*
|
||||
X0624400Y0057433D03*
|
||||
X0634400Y0057433D03*
|
||||
X0644400Y0057433D03*
|
||||
X0654400Y0057433D03*
|
||||
D11*
|
||||
X0456821Y0317729D03*
|
||||
D12*
|
||||
X0446821Y0317729D03*
|
||||
X0436821Y0317729D03*
|
||||
X0426821Y0317729D03*
|
||||
X0416821Y0317729D03*
|
||||
X0416821Y0307729D03*
|
||||
X0426821Y0307729D03*
|
||||
X0426821Y0297729D03*
|
||||
X0416821Y0297729D03*
|
||||
X0416821Y0287729D03*
|
||||
X0426821Y0287729D03*
|
||||
X0426821Y0277729D03*
|
||||
X0416821Y0277729D03*
|
||||
X0416821Y0267729D03*
|
||||
X0426821Y0267729D03*
|
||||
X0436821Y0267729D03*
|
||||
X0446821Y0267729D03*
|
||||
X0456821Y0267729D03*
|
||||
X0466821Y0267729D03*
|
||||
X0476821Y0267729D03*
|
||||
X0486821Y0267729D03*
|
||||
X0486821Y0277729D03*
|
||||
X0476821Y0277729D03*
|
||||
X0476821Y0287729D03*
|
||||
X0486821Y0287729D03*
|
||||
X0486821Y0297729D03*
|
||||
X0476821Y0297729D03*
|
||||
X0476821Y0307729D03*
|
||||
X0486821Y0307729D03*
|
||||
X0486821Y0317729D03*
|
||||
X0476821Y0317729D03*
|
||||
X0466821Y0317729D03*
|
||||
X0466821Y0327729D03*
|
||||
X0476821Y0327729D03*
|
||||
X0456821Y0327729D03*
|
||||
X0446821Y0327729D03*
|
||||
X0436821Y0327729D03*
|
||||
X0426821Y0327729D03*
|
||||
X0531743Y0331548D03*
|
||||
X0531743Y0321548D03*
|
||||
X0476821Y0257729D03*
|
||||
X0466821Y0257729D03*
|
||||
X0456821Y0257729D03*
|
||||
X0446821Y0257729D03*
|
||||
X0436821Y0257729D03*
|
||||
X0426821Y0257729D03*
|
||||
D13*
|
||||
X0429144Y0219722D02*
|
||||
X0429144Y0214948D01*
|
||||
X0419144Y0214948D02*
|
||||
X0419144Y0219722D01*
|
||||
X0409144Y0219722D02*
|
||||
X0409144Y0214948D01*
|
||||
X0399144Y0214948D02*
|
||||
X0399144Y0219722D01*
|
||||
X0389144Y0219722D02*
|
||||
X0389144Y0214948D01*
|
||||
X0379144Y0214948D02*
|
||||
X0379144Y0219722D01*
|
||||
X0439144Y0219722D02*
|
||||
X0439144Y0214948D01*
|
||||
X0449144Y0214948D02*
|
||||
X0449144Y0219722D01*
|
||||
X0459144Y0219722D02*
|
||||
X0459144Y0214948D01*
|
||||
X0469144Y0214948D02*
|
||||
X0469144Y0219722D01*
|
||||
X0479144Y0219722D02*
|
||||
X0479144Y0214948D01*
|
||||
X0489144Y0214948D02*
|
||||
X0489144Y0219722D01*
|
||||
X0489144Y0159722D02*
|
||||
X0489144Y0154948D01*
|
||||
X0479144Y0154948D02*
|
||||
X0479144Y0159722D01*
|
||||
X0469144Y0159722D02*
|
||||
X0469144Y0154948D01*
|
||||
X0459144Y0154948D02*
|
||||
X0459144Y0159722D01*
|
||||
X0449144Y0159722D02*
|
||||
X0449144Y0154948D01*
|
||||
X0439144Y0154948D02*
|
||||
X0439144Y0159722D01*
|
||||
X0429144Y0159722D02*
|
||||
X0429144Y0154948D01*
|
||||
X0419144Y0154948D02*
|
||||
X0419144Y0159722D01*
|
||||
X0409144Y0159722D02*
|
||||
X0409144Y0154948D01*
|
||||
X0399144Y0154948D02*
|
||||
X0399144Y0159722D01*
|
||||
X0389144Y0159722D02*
|
||||
X0389144Y0154948D01*
|
||||
X0379144Y0154948D02*
|
||||
X0379144Y0159722D01*
|
||||
X0419302Y0127596D02*
|
||||
X0419302Y0122822D01*
|
||||
X0429302Y0122822D02*
|
||||
X0429302Y0127596D01*
|
||||
X0439302Y0127596D02*
|
||||
X0439302Y0122822D01*
|
||||
X0449302Y0122822D02*
|
||||
X0449302Y0127596D01*
|
||||
X0459302Y0127596D02*
|
||||
X0459302Y0122822D01*
|
||||
X0469302Y0122822D02*
|
||||
X0469302Y0127596D01*
|
||||
X0479302Y0127596D02*
|
||||
X0479302Y0122822D01*
|
||||
X0489302Y0122822D02*
|
||||
X0489302Y0127596D01*
|
||||
X0499302Y0127596D02*
|
||||
X0499302Y0122822D01*
|
||||
X0509302Y0122822D02*
|
||||
X0509302Y0127596D01*
|
||||
X0509302Y0097596D02*
|
||||
X0509302Y0092822D01*
|
||||
X0499302Y0092822D02*
|
||||
X0499302Y0097596D01*
|
||||
X0489302Y0097596D02*
|
||||
X0489302Y0092822D01*
|
||||
X0479302Y0092822D02*
|
||||
X0479302Y0097596D01*
|
||||
X0469302Y0097596D02*
|
||||
X0469302Y0092822D01*
|
||||
X0459302Y0092822D02*
|
||||
X0459302Y0097596D01*
|
||||
X0449302Y0097596D02*
|
||||
X0449302Y0092822D01*
|
||||
X0439302Y0092822D02*
|
||||
X0439302Y0097596D01*
|
||||
X0429302Y0097596D02*
|
||||
X0429302Y0092822D01*
|
||||
X0419302Y0092822D02*
|
||||
X0419302Y0097596D01*
|
||||
D14*
|
||||
X0618916Y0112886D02*
|
||||
X0624491Y0112886D01*
|
||||
X0624491Y0122886D02*
|
||||
X0618916Y0122886D01*
|
||||
X0618916Y0132886D02*
|
||||
X0624491Y0132886D01*
|
||||
X0498987Y0230059D02*
|
||||
X0498987Y0235634D01*
|
||||
X0488987Y0235634D02*
|
||||
X0488987Y0230059D01*
|
||||
X0478987Y0230059D02*
|
||||
X0478987Y0235634D01*
|
||||
X0367758Y0282650D02*
|
||||
X0362183Y0282650D01*
|
||||
X0362183Y0292650D02*
|
||||
X0367758Y0292650D01*
|
||||
X0367758Y0302650D02*
|
||||
X0362183Y0302650D01*
|
||||
X0362183Y0312650D02*
|
||||
X0367758Y0312650D01*
|
||||
X0367758Y0322650D02*
|
||||
X0362183Y0322650D01*
|
||||
X0362183Y0332650D02*
|
||||
X0367758Y0332650D01*
|
||||
D15*
|
||||
X0680703Y0122886D03*
|
||||
D16*
|
||||
X0598858Y0122689D03*
|
||||
D17*
|
||||
X0608858Y0122689D03*
|
||||
D18*
|
||||
X0609420Y0149264D03*
|
||||
X0602727Y0149264D03*
|
||||
X0618475Y0149146D03*
|
||||
X0625168Y0149146D03*
|
||||
X0613396Y0096036D03*
|
||||
X0606703Y0096036D03*
|
||||
D19*
|
||||
X0605128Y0180288D03*
|
||||
X0595286Y0180288D03*
|
||||
X0595286Y0186981D03*
|
||||
X0605128Y0186981D03*
|
||||
X0614971Y0186981D03*
|
||||
X0614971Y0180288D03*
|
||||
X0663396Y0180327D03*
|
||||
X0663396Y0187020D03*
|
||||
X0673042Y0186981D03*
|
||||
X0673042Y0180288D03*
|
||||
X0694695Y0251154D03*
|
||||
X0694695Y0257847D03*
|
||||
X0694695Y0264933D03*
|
||||
X0694695Y0271626D03*
|
||||
X0531624Y0304343D03*
|
||||
X0531624Y0311036D03*
|
||||
D20*
|
||||
X0594794Y0199382D03*
|
||||
X0604636Y0199382D03*
|
||||
X0614479Y0199382D03*
|
||||
X0624321Y0199382D03*
|
||||
X0634164Y0199382D03*
|
||||
X0644006Y0199382D03*
|
||||
X0653849Y0199382D03*
|
||||
X0663691Y0199382D03*
|
||||
X0670187Y0199382D03*
|
||||
D21*
|
||||
X0684459Y0294658D03*
|
||||
X0574420Y0294658D03*
|
||||
D22*
|
||||
X0683376Y0243870D03*
|
||||
D23*
|
||||
X0683376Y0278516D03*
|
||||
X0683376Y0283634D03*
|
||||
D24*
|
||||
X0613494Y0104894D03*
|
||||
X0606605Y0104894D03*
|
||||
D25*
|
||||
X0373829Y0166902D03*
|
||||
X0414183Y0174776D03*
|
||||
X0428947Y0174776D03*
|
||||
X0428947Y0132453D03*
|
||||
X0499813Y0135406D03*
|
||||
X0533278Y0125563D03*
|
||||
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|
||||
X0533278Y0090130D03*
|
||||
X0533278Y0079303D03*
|
||||
X0554931Y0092099D03*
|
||||
X0559853Y0092099D03*
|
||||
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|
||||
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|
||||
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|
||||
X0654341Y0193477D03*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X0472254Y0262374D03*
|
||||
X0441743Y0262374D03*
|
||||
X0419105Y0262374D03*
|
||||
X0441743Y0242689D03*
|
||||
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|
||||
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|
||||
X0451585Y0301744D03*
|
||||
X0447648Y0306666D03*
|
||||
X0379735Y0297807D03*
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
|
|
@ -1,287 +0,0 @@
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||||
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||||
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||||
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||||
D11*
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||||
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||||
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||||
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||||
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||||
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File diff suppressed because it is too large
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Load Diff
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|
||||
<smd name="1" x="-2.54" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="4" x="-1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="3" x="-1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="6" x="0" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="5" x="0" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="7" x="1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="8" x="1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="10" x="2.54" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="9" x="2.54" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<rectangle x1="-2.54" y1="-0.635" x2="2.54" y2="0.635" layer="41"/>
|
||||
<hole x="-3.81" y="0" drill="0.9906"/>
|
||||
<hole x="3.81" y="1.016" drill="0.9906"/>
|
||||
<hole x="3.81" y="-1.016" drill="0.9906"/>
|
||||
<hole x="-3.81" y="2.54" drill="2.3749"/>
|
||||
<hole x="-3.81" y="-2.54" drill="2.3749"/>
|
||||
<hole x="1.905" y="2.54" drill="2.3749"/>
|
||||
<hole x="1.905" y="-2.54" drill="2.3749"/>
|
||||
<rectangle x1="-4.5847" y1="-5.14985" x2="-3.0353" y2="-2.54" layer="40"/>
|
||||
<rectangle x1="1.1303" y1="-5.14985" x2="2.6797" y2="-2.54" layer="40"/>
|
||||
<rectangle x1="-4.5847" y1="2.54" x2="-3.0353" y2="5.14985" layer="40"/>
|
||||
<rectangle x1="1.1303" y1="2.54" x2="2.6797" y2="5.14985" layer="40"/>
|
||||
<text x="-5.715" y="-2.54" size="1.27" layer="27" rot="R90">>VALUE</text>
|
||||
<text x="6.35" y="-2.54" size="1.27" layer="25" rot="R90">>NAME</text>
|
||||
</package>
|
||||
<package name="TC2050-IDC-NL">
|
||||
<smd name="2" x="-2.54" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="1" x="-2.54" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="4" x="-1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="3" x="-1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="6" x="0" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="5" x="0" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="7" x="1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="8" x="1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="10" x="2.54" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="9" x="2.54" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<rectangle x1="-2.54" y1="-0.635" x2="2.54" y2="0.635" layer="41"/>
|
||||
<hole x="-3.81" y="0" drill="0.9906"/>
|
||||
<hole x="3.81" y="1.016" drill="0.9906"/>
|
||||
<hole x="3.81" y="-1.016" drill="0.9906"/>
|
||||
<text x="-4.445" y="-3.175" size="1.27" layer="27">>VALUE</text>
|
||||
<text x="-4.445" y="1.905" size="1.27" layer="25">>NAME</text>
|
||||
</package>
|
||||
<package name="TC2030-IDC">
|
||||
<smd name="2" x="-1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="1" x="-1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="4" x="0" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="3" x="0" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="6" x="1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="5" x="1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<rectangle x1="-1.27" y1="-0.635" x2="1.27" y2="0.635" layer="41"/>
|
||||
<hole x="-2.54" y="0" drill="0.9906"/>
|
||||
<hole x="2.54" y="1.016" drill="0.9906"/>
|
||||
<hole x="2.54" y="-1.016" drill="0.9906"/>
|
||||
<hole x="-2.54" y="2.54" drill="2.3749"/>
|
||||
<hole x="-2.54" y="-2.54" drill="2.3749"/>
|
||||
<hole x="0.635" y="2.54" drill="2.3749"/>
|
||||
<hole x="0.635" y="-2.54" drill="2.3749"/>
|
||||
<rectangle x1="-3.3147" y1="-5.14985" x2="-1.7653" y2="-2.54" layer="40"/>
|
||||
<rectangle x1="-0.1397" y1="-5.14985" x2="1.4097" y2="-2.54" layer="40"/>
|
||||
<rectangle x1="-3.3147" y1="2.54" x2="-1.7653" y2="5.14985" layer="40"/>
|
||||
<rectangle x1="-0.1397" y1="2.54" x2="1.4097" y2="5.14985" layer="40"/>
|
||||
<text x="-4.445" y="-2.54" size="1.27" layer="27" rot="R90">>VALUE</text>
|
||||
<text x="5.08" y="-2.54" size="1.27" layer="25" rot="R90">>NAME</text>
|
||||
</package>
|
||||
<package name="TC2030-IDC-NL">
|
||||
<smd name="2" x="-1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="1" x="-1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="4" x="0" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="3" x="0" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="6" x="1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="5" x="1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<rectangle x1="-1.27" y1="-0.635" x2="1.27" y2="0.635" layer="41"/>
|
||||
<hole x="-2.54" y="0" drill="0.9906"/>
|
||||
<hole x="2.54" y="1.016" drill="0.9906"/>
|
||||
<hole x="2.54" y="-1.016" drill="0.9906"/>
|
||||
<text x="-3.175" y="1.905" size="1.27" layer="27">>VALUE</text>
|
||||
<text x="-3.175" y="-3.175" size="1.27" layer="25">>NAME</text>
|
||||
</package>
|
||||
</packages>
|
||||
<symbols>
|
||||
<symbol name="TC2030-IDC">
|
||||
<wire x1="3.81" y1="-5.08" x2="-3.81" y2="-5.08" width="0.4064" layer="94"/>
|
||||
<wire x1="-3.81" y1="5.08" x2="-3.81" y2="-5.08" width="0.4064" layer="94"/>
|
||||
<wire x1="3.81" y1="-5.08" x2="3.81" y2="5.08" width="0.4064" layer="94"/>
|
||||
<wire x1="-3.81" y1="5.08" x2="3.81" y2="5.08" width="0.4064" layer="94"/>
|
||||
<wire x1="1.27" y1="2.54" x2="2.54" y2="2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="0" x2="2.54" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="-2.54" x2="2.54" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="2.54" x2="-1.27" y2="2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="0" x2="-1.27" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="-2.54" x2="-1.27" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<text x="-3.81" y="-7.62" size="1.778" layer="96">>VALUE</text>
|
||||
<text x="-3.81" y="5.842" size="1.778" layer="95">>NAME</text>
|
||||
<pin name="1" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="3" x="7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="5" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="2" x="-7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="4" x="-7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="6" x="-7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
</symbol>
|
||||
<symbol name="TC2050-IDC">
|
||||
<wire x1="3.81" y1="-7.62" x2="-3.81" y2="-7.62" width="0.4064" layer="94"/>
|
||||
<wire x1="1.27" y1="0" x2="2.54" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="-2.54" x2="2.54" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="-5.08" x2="2.54" y2="-5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="0" x2="-1.27" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="-2.54" x2="-1.27" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="-5.08" x2="-1.27" y2="-5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="-3.81" y1="7.62" x2="-3.81" y2="-7.62" width="0.4064" layer="94"/>
|
||||
<wire x1="3.81" y1="-7.62" x2="3.81" y2="7.62" width="0.4064" layer="94"/>
|
||||
<wire x1="-3.81" y1="7.62" x2="3.81" y2="7.62" width="0.4064" layer="94"/>
|
||||
<wire x1="1.27" y1="5.08" x2="2.54" y2="5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="2.54" x2="2.54" y2="2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="5.08" x2="-1.27" y2="5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="2.54" x2="-1.27" y2="2.54" width="0.6096" layer="94"/>
|
||||
<text x="-3.81" y="-10.16" size="1.778" layer="96">>VALUE</text>
|
||||
<text x="-3.81" y="8.382" size="1.778" layer="95">>NAME</text>
|
||||
<pin name="1" x="7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="3" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="5" x="7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="2" x="-7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="4" x="-7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="6" x="-7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="7" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="9" x="7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="8" x="-7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="10" x="-7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="TC2050-IDC" prefix="TC">
|
||||
<description>Tag-Connect In Circuit Programming & Debug Cable 10 Pin
|
||||
http://www.tag-connect.com</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="TC2050-IDC" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="TC2050-IDC">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="10" pad="10"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
<connect gate="A" pin="7" pad="7"/>
|
||||
<connect gate="A" pin="8" pad="8"/>
|
||||
<connect gate="A" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="-NL" package="TC2050-IDC-NL">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="10" pad="10"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
<connect gate="A" pin="7" pad="7"/>
|
||||
<connect gate="A" pin="8" pad="8"/>
|
||||
<connect gate="A" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="TC2030-IDC" prefix="TC">
|
||||
<description>Tag-Connect In Circuit Programming & Debug Cable 6 Pin
|
||||
http://www.tag-connect.com</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="TC2030-IDC" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="TC2030-IDC">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="-NL" package="TC2030-IDC-NL">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
|
|
@ -1,12 +1,12 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="7.7.0">
|
||||
<eagle version="7.2.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.05" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
|
||||
<grid distance="25" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
|
|
@ -161,56 +161,56 @@ Dimensions taken from Tech Note #28</description>
|
|||
<wire x1="-25.4" y1="2.54" x2="-25.4" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-105.41" y1="-3.81" x2="-16.51" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-0.127" y1="77.597" x2="-0.127" y2="7.778" width="0.2032" layer="49"/>
|
||||
<smd name="26" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="27" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="28" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="29" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="30" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="31" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="32" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="33" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="34" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="35" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="36" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="37" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="38" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="39" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="40" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="41" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="42" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="43" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="44" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="45" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="46" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="47" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="48" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="49" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="50" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="25" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="24" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="23" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="22" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="21" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="20" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="19" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="18" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="17" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="16" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="15" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="14" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="13" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="12" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="11" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="10" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="09" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="08" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="07" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="06" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="05" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="04" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="03" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="02" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="01" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="26" x="-12.065" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="27" x="-14.605" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="28" x="-17.145" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="29" x="-19.685" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="30" x="-22.225" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="31" x="-24.765" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="32" x="-27.305" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="33" x="-29.845" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="34" x="-32.385" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="35" x="-34.925" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="36" x="-37.465" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="37" x="-40.005" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="38" x="-42.545" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="39" x="-45.085" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="40" x="-47.625" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="41" x="-50.165" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="42" x="-52.705" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="43" x="-55.245" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="44" x="-57.785" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="45" x="-60.325" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="46" x="-62.865" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="47" x="-65.405" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="48" x="-67.945" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="49" x="-70.485" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="50" x="-73.025" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="25" x="-12.065" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="24" x="-14.605" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="23" x="-17.145" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="22" x="-19.685" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="21" x="-22.225" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="20" x="-24.765" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="19" x="-27.305" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="18" x="-29.845" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="17" x="-32.385" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="16" x="-34.925" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="15" x="-37.465" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="14" x="-40.005" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="13" x="-42.545" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="12" x="-45.085" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="11" x="-47.625" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="10" x="-50.165" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="09" x="-52.705" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="08" x="-55.245" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="07" x="-57.785" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="06" x="-60.325" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="05" x="-62.865" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="04" x="-65.405" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="03" x="-67.945" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="02" x="-70.485" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="01" x="-73.025" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<text x="-5.715" y="3.175" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-94.5134" y="2.9718" size="1.778" layer="48">7,87 mm</text>
|
||||
<text x="-40.8432" y="-9.2964" size="1.778" layer="48">74.93 mm
|
||||
|
|
@ -478,14 +478,14 @@ Dimensions taken from Tech Note #28</description>
|
|||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="A2-50PIN" prefix="ST" uservalue="yes">
|
||||
<deviceset name="A2-50PIN">
|
||||
<description><B>Apple ][ Peripheral Card Connector</B>
|
||||
<br />
|
||||
This is the, default, 50-pin connector for slot #1 to #7
|
||||
<br />
|
||||
Pins are laid out as seen from the top of the slot</description>
|
||||
<gates>
|
||||
<gate name="_-12V@2" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
|
||||
<gate name="_+12V" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
|
||||
<gate name="_D0" symbol="ATPIN" x="-5.08" y="-35.56" addlevel="always"/>
|
||||
<gate name="_D1" symbol="ATPIN" x="-5.08" y="-33.02" addlevel="always"/>
|
||||
<gate name="_D2" symbol="ATPIN" x="-5.08" y="-30.48" addlevel="always"/>
|
||||
|
|
@ -494,23 +494,23 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<gate name="_D5" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
|
||||
<gate name="_D6" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
|
||||
<gate name="_D7" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
|
||||
<gate name="_DEVSELECT\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
|
||||
<gate name="_00" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
|
||||
<gate name="_!DEVSELECT" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
|
||||
<gate name="_PHI0" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
|
||||
<gate name="_USER1" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
|
||||
<gate name="_01" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
|
||||
<gate name="_PHI1" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
|
||||
<gate name="_Q3" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
|
||||
<gate name="_7M" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
|
||||
<gate name="_NC@2" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
|
||||
<gate name="_-5V" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
|
||||
<gate name="_-12V@1" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
|
||||
<gate name="_INH\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
|
||||
<gate name="_RES\" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
|
||||
<gate name="_IRQ\" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
|
||||
<gate name="_NMI\" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
|
||||
<gate name="_-12V" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
|
||||
<gate name="_!INH" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
|
||||
<gate name="_!RES" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
|
||||
<gate name="_!IRQ" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
|
||||
<gate name="_!NMI" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
|
||||
<gate name="_INT_IN" symbol="ATPIN" x="-5.08" y="17.78" addlevel="always"/>
|
||||
<gate name="_DMA_IN" symbol="ATPIN" x="-5.08" y="20.32" addlevel="always"/>
|
||||
<gate name="_GND" symbol="ATPIN" x="-5.08" y="22.86" addlevel="always"/>
|
||||
<gate name="_IOSELECT\" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
|
||||
<gate name="_!IOSELECT" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
|
||||
<gate name="_A00" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
|
||||
<gate name="_A01" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
|
||||
<gate name="_A02" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
|
||||
|
|
@ -527,11 +527,11 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<gate name="_A13" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
|
||||
<gate name="_A14" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
|
||||
<gate name="_A15" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
|
||||
<gate name="_RW" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
|
||||
<gate name="_R!W" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
|
||||
<gate name="_NC@1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
|
||||
<gate name="_IOSTR\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
|
||||
<gate name="_!IOSTR" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
|
||||
<gate name="_RDY" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
|
||||
<gate name="_DMA\" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
|
||||
<gate name="_!DMA" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
|
||||
<gate name="_INT_OUT" symbol="ATPIN" x="27.94" y="17.78" addlevel="always"/>
|
||||
<gate name="_DMA_OUT" symbol="ATPIN" x="27.94" y="20.32" addlevel="always"/>
|
||||
<gate name="_+5V" symbol="ATPIN" x="27.94" y="22.86" addlevel="always"/>
|
||||
|
|
@ -539,12 +539,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<devices>
|
||||
<device name="SLOT1-3" package="A2-50PIN-SL1-3">
|
||||
<connects>
|
||||
<connect gate="_!DEVSELECT" pin="P" pad="41"/>
|
||||
<connect gate="_!DMA" pin="P" pad="22"/>
|
||||
<connect gate="_!INH" pin="P" pad="32"/>
|
||||
<connect gate="_!IOSELECT" pin="P" pad="01"/>
|
||||
<connect gate="_!IOSTR" pin="P" pad="20"/>
|
||||
<connect gate="_!IRQ" pin="P" pad="30"/>
|
||||
<connect gate="_!NMI" pin="P" pad="29"/>
|
||||
<connect gate="_!RES" pin="P" pad="31"/>
|
||||
<connect gate="_+12V" pin="P" pad="50"/>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V@1" pin="P" pad="33"/>
|
||||
<connect gate="_-12V@2" pin="P" pad="50"/>
|
||||
<connect gate="_-12V" pin="P" pad="33"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
|
|
@ -570,24 +576,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_PHI0" pin="P" pad="40"/>
|
||||
<connect gate="_PHI1" pin="P" pad="38"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_R!W" pin="P" pad="18"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
|
|
@ -596,12 +596,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
</device>
|
||||
<device name="SLOT4-7" package="A2-50PIN-SL4-7">
|
||||
<connects>
|
||||
<connect gate="_!DEVSELECT" pin="P" pad="41"/>
|
||||
<connect gate="_!DMA" pin="P" pad="22"/>
|
||||
<connect gate="_!INH" pin="P" pad="32"/>
|
||||
<connect gate="_!IOSELECT" pin="P" pad="01"/>
|
||||
<connect gate="_!IOSTR" pin="P" pad="20"/>
|
||||
<connect gate="_!IRQ" pin="P" pad="30"/>
|
||||
<connect gate="_!NMI" pin="P" pad="29"/>
|
||||
<connect gate="_!RES" pin="P" pad="31"/>
|
||||
<connect gate="_+12V" pin="P" pad="50"/>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V@1" pin="P" pad="33"/>
|
||||
<connect gate="_-12V@2" pin="P" pad="50"/>
|
||||
<connect gate="_-12V" pin="P" pad="33"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
|
|
@ -627,24 +633,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_PHI0" pin="P" pad="40"/>
|
||||
<connect gate="_PHI1" pin="P" pad="38"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_R!W" pin="P" pad="18"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -0,0 +1,688 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="8.2.2">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="50" name="dxf" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="53" name="tGND_GNDA" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="54" name="bGND_GNDA" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="56" name="wert" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="100" name="Release" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="101" name="Heatsink" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="102" name="tMarkings" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="103" name="bMarkings" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="104" name="Name" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="105" name="Beschreib" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="106" name="BGA-Top" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="107" name="BD-Top" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="116" name="Patch_BOT" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="121" name="_layer121" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="122" name="_bplace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="150" name="References" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="200" name="200bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="201" name="201bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="202" name="202bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="203" name="203bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="204" name="204bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="205" name="205bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="206" name="206bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="207" name="207bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="208" name="208bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="231" name="Eagle3D_PG1" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="232" name="Eagle3D_PG2" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="233" name="Eagle3D_PG3" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="250" name="Descript" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="251" name="SMDround" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="254" name="OrgLBR" color="7" fill="1" visible="yes" active="yes"/>
|
||||
</layers>
|
||||
<library>
|
||||
<packages>
|
||||
<package name="S44">
|
||||
<description><b>PLCC SOCKET</b></description>
|
||||
<circle x="-2.54" y="2.54" radius="1.27" width="0.1524" layer="21"/>
|
||||
<circle x="2.54" y="2.54" radius="1.27" width="0.1524" layer="21"/>
|
||||
<circle x="-2.54" y="-2.54" radius="1.27" width="0.1524" layer="21"/>
|
||||
<circle x="2.54" y="-2.54" radius="1.27" width="0.1524" layer="21"/>
|
||||
<wire x1="-10.16" y1="11.684" x2="-11.684" y2="10.16" width="0.1524" layer="21"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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<pad name="38" x="6.35" y="3.81" drill="0.8128" shape="octagon"/>
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<description><b>QFP44</b><p>
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||||
</package>
|
||||
</packages>
|
||||
<symbols>
|
||||
<symbol name="SUPPLY">
|
||||
<pin name="GND@0" x="-5.08" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
|
||||
<pin name="GND@1" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
|
||||
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|
||||
<pin name="VCCINT@0" x="-5.08" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
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||||
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|
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||||
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|
||||
<pin name="FB01/14" x="-30.48" y="-2.54" length="middle"/>
|
||||
<pin name="FB01/15" x="-30.48" y="-5.08" length="middle"/>
|
||||
<pin name="FB01/17" x="-30.48" y="-7.62" length="middle"/>
|
||||
<pin name="FB02/02" x="10.16" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/05" x="7.62" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/06" x="5.08" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/08" x="2.54" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/09" x="0" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/11" x="-2.54" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/14" x="-5.08" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/15" x="-7.62" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/17" x="-10.16" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB03/02" x="-10.16" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/05" x="-7.62" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/08" x="-5.08" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/09" x="-2.54" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/11" x="0" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/14" x="2.54" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/15" x="5.08" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/16" x="7.62" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/17" x="10.16" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB04/02" x="30.48" y="-2.54" length="middle" rot="R180"/>
|
||||
<pin name="FB04/05" x="30.48" y="0" length="middle" rot="R180"/>
|
||||
<pin name="FB04/08" x="30.48" y="2.54" length="middle" rot="R180"/>
|
||||
<pin name="FB04/11" x="30.48" y="5.08" length="middle" rot="R180"/>
|
||||
<pin name="FB04/14" x="30.48" y="7.62" length="middle" rot="R180"/>
|
||||
<pin name="FB04/15" x="30.48" y="10.16" length="middle" rot="R180"/>
|
||||
<pin name="FB04/17" x="30.48" y="12.7" length="middle" rot="R180"/>
|
||||
<pin name="TCK" x="30.48" y="-10.16" length="middle" direction="in" rot="R180"/>
|
||||
<pin name="TDI" x="30.48" y="-15.24" length="middle" direction="in" rot="R180"/>
|
||||
<pin name="TDO" x="30.48" y="-12.7" length="middle" direction="out" rot="R180"/>
|
||||
<pin name="TMS" x="30.48" y="-17.78" length="middle" direction="in" rot="R180"/>
|
||||
<text x="-5.08" y="1.27" size="1.778" layer="95">>NAME</text>
|
||||
<text x="-5.08" y="-2.54" size="1.778" layer="96">>VALUE</text>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="XC9572_S44">
|
||||
<gates>
|
||||
<gate name="G$1" symbol="XC9572_PC44" x="0" y="0"/>
|
||||
<gate name="SUPPLY" symbol="SUPPLY" x="58.42" y="-2.54" addlevel="request"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="PLCC" package="S44">
|
||||
<connects>
|
||||
<connect gate="G$1" pin="FB01/02" pad="1"/>
|
||||
<connect gate="G$1" pin="FB01/05" pad="2"/>
|
||||
<connect gate="G$1" pin="FB01/06" pad="3"/>
|
||||
<connect gate="G$1" pin="FB01/08" pad="4"/>
|
||||
<connect gate="G$1" pin="FB01/09" pad="5"/>
|
||||
<connect gate="G$1" pin="FB01/11" pad="6"/>
|
||||
<connect gate="G$1" pin="FB01/14" pad="7"/>
|
||||
<connect gate="G$1" pin="FB01/15" pad="8"/>
|
||||
<connect gate="G$1" pin="FB01/17" pad="9"/>
|
||||
<connect gate="G$1" pin="FB02/02" pad="35"/>
|
||||
<connect gate="G$1" pin="FB02/05" pad="36"/>
|
||||
<connect gate="G$1" pin="FB02/06" pad="37"/>
|
||||
<connect gate="G$1" pin="FB02/08" pad="38"/>
|
||||
<connect gate="G$1" pin="FB02/09" pad="39"/>
|
||||
<connect gate="G$1" pin="FB02/11" pad="40"/>
|
||||
<connect gate="G$1" pin="FB02/14" pad="42"/>
|
||||
<connect gate="G$1" pin="FB02/15" pad="43"/>
|
||||
<connect gate="G$1" pin="FB02/17" pad="44"/>
|
||||
<connect gate="G$1" pin="FB03/02" pad="11"/>
|
||||
<connect gate="G$1" pin="FB03/05" pad="12"/>
|
||||
<connect gate="G$1" pin="FB03/08" pad="13"/>
|
||||
<connect gate="G$1" pin="FB03/09" pad="14"/>
|
||||
<connect gate="G$1" pin="FB03/11" pad="18"/>
|
||||
<connect gate="G$1" pin="FB03/14" pad="19"/>
|
||||
<connect gate="G$1" pin="FB03/15" pad="20"/>
|
||||
<connect gate="G$1" pin="FB03/16" pad="24"/>
|
||||
<connect gate="G$1" pin="FB03/17" pad="22"/>
|
||||
<connect gate="G$1" pin="FB04/02" pad="25"/>
|
||||
<connect gate="G$1" pin="FB04/05" pad="26"/>
|
||||
<connect gate="G$1" pin="FB04/08" pad="27"/>
|
||||
<connect gate="G$1" pin="FB04/11" pad="28"/>
|
||||
<connect gate="G$1" pin="FB04/14" pad="29"/>
|
||||
<connect gate="G$1" pin="FB04/15" pad="33"/>
|
||||
<connect gate="G$1" pin="FB04/17" pad="34"/>
|
||||
<connect gate="G$1" pin="TCK" pad="17"/>
|
||||
<connect gate="G$1" pin="TDI" pad="15"/>
|
||||
<connect gate="G$1" pin="TDO" pad="30"/>
|
||||
<connect gate="G$1" pin="TMS" pad="16"/>
|
||||
<connect gate="SUPPLY" pin="GND@0" pad="10"/>
|
||||
<connect gate="SUPPLY" pin="GND@1" pad="23"/>
|
||||
<connect gate="SUPPLY" pin="GND@2" pad="31"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@0" pad="21"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@1" pad="41"/>
|
||||
<connect gate="SUPPLY" pin="VCCIO" pad="32"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="VQFP" package="SQFP-S-10X10-44">
|
||||
<connects>
|
||||
<connect gate="G$1" pin="FB01/02" pad="39"/>
|
||||
<connect gate="G$1" pin="FB01/05" pad="40"/>
|
||||
<connect gate="G$1" pin="FB01/06" pad="41"/>
|
||||
<connect gate="G$1" pin="FB01/08" pad="42"/>
|
||||
<connect gate="G$1" pin="FB01/09" pad="43"/>
|
||||
<connect gate="G$1" pin="FB01/11" pad="44"/>
|
||||
<connect gate="G$1" pin="FB01/14" pad="1"/>
|
||||
<connect gate="G$1" pin="FB01/15" pad="2"/>
|
||||
<connect gate="G$1" pin="FB01/17" pad="3"/>
|
||||
<connect gate="G$1" pin="FB02/02" pad="29"/>
|
||||
<connect gate="G$1" pin="FB02/05" pad="30"/>
|
||||
<connect gate="G$1" pin="FB02/06" pad="31"/>
|
||||
<connect gate="G$1" pin="FB02/08" pad="32"/>
|
||||
<connect gate="G$1" pin="FB02/09" pad="33"/>
|
||||
<connect gate="G$1" pin="FB02/11" pad="34"/>
|
||||
<connect gate="G$1" pin="FB02/14" pad="36"/>
|
||||
<connect gate="G$1" pin="FB02/15" pad="37"/>
|
||||
<connect gate="G$1" pin="FB02/17" pad="38"/>
|
||||
<connect gate="G$1" pin="FB03/02" pad="5"/>
|
||||
<connect gate="G$1" pin="FB03/05" pad="6"/>
|
||||
<connect gate="G$1" pin="FB03/08" pad="7"/>
|
||||
<connect gate="G$1" pin="FB03/09" pad="8"/>
|
||||
<connect gate="G$1" pin="FB03/11" pad="12"/>
|
||||
<connect gate="G$1" pin="FB03/14" pad="13"/>
|
||||
<connect gate="G$1" pin="FB03/15" pad="14"/>
|
||||
<connect gate="G$1" pin="FB03/16" pad="18"/>
|
||||
<connect gate="G$1" pin="FB03/17" pad="16"/>
|
||||
<connect gate="G$1" pin="FB04/02" pad="19"/>
|
||||
<connect gate="G$1" pin="FB04/05" pad="20"/>
|
||||
<connect gate="G$1" pin="FB04/08" pad="21"/>
|
||||
<connect gate="G$1" pin="FB04/11" pad="22"/>
|
||||
<connect gate="G$1" pin="FB04/14" pad="23"/>
|
||||
<connect gate="G$1" pin="FB04/15" pad="27"/>
|
||||
<connect gate="G$1" pin="FB04/17" pad="28"/>
|
||||
<connect gate="G$1" pin="TCK" pad="11"/>
|
||||
<connect gate="G$1" pin="TDI" pad="9"/>
|
||||
<connect gate="G$1" pin="TDO" pad="24"/>
|
||||
<connect gate="G$1" pin="TMS" pad="10"/>
|
||||
<connect gate="SUPPLY" pin="GND@0" pad="4"/>
|
||||
<connect gate="SUPPLY" pin="GND@1" pad="17"/>
|
||||
<connect gate="SUPPLY" pin="GND@2" pad="25"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@0" pad="15"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@1" pad="35"/>
|
||||
<connect gate="SUPPLY" pin="VCCIO" pad="26"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 189 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 280 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 572 KiB |
103
README.md
103
README.md
|
|
@ -1,23 +1,68 @@
|
|||
# Apple][Sd
|
||||
SD card based ProFile replacement for enhanced Apple IIe computers
|
||||
# AppleIISd
|
||||
SD card based ProFile replacement for enhanced Apple IIe and IIgs computers
|
||||
|
||||
The **Apple][Sd** is a SD card based replaced for the ProFile harddrive. In contrast to other SD card based devices, this card does not replace a Disk II drive. Data is saved directly onto the SD card, not via images on a FAT system, like on other cards. The SD card is accessable with [CiderPress](http://a2ciderpress.com/).
|
||||
The **AppleIISd** is a SD card based replaced for the ProFile harddrive. In contrast to other SD card based devices, this card does not replace a Disk II drive. Data is saved directly onto the SD card, not via images on a FAT system, like on other cards. The SD card is accessable with [CiderPress](http://a2ciderpress.com/).
|
||||
|
||||
A Xilinx CPLD is used as a SPI controller and translates, together with the ROM driver, SD card data to/from the Apple IIe. The VHDL source is based on [SPI65/B](http://www.6502.org/users/andre/spi65b) by André Fachat.
|
||||
|
||||
The assembler sources were written in Merlin-8. The [schematics](AppleIISd.pdf) are available as PDF.
|
||||
The assembler sources are written for CC65. The [schematics](Binary/AppleIISd.pdf) are available as PDF.
|
||||
|
||||
## Features
|
||||
* up to 64MB storage space (2x 65535 blocks)
|
||||
* ProDOS driver in ROM
|
||||
* works with ProDOS and GS/OS
|
||||
* up to 128MB storage space (4x 65535 blocks)
|
||||
* ProDOS and Smartport driver in ROM
|
||||
* Firmware update from ProDOS
|
||||
* Auto boot
|
||||
* Access LED
|
||||
* Card detect and write protect sensing
|
||||
* Skip boot when Open-Apple key is pressed
|
||||
|
||||
## Requirements
|
||||
The Apple][Sd requires and has been tested on an enhanced IIe computer. The ROM code uses some 65c02 opcodes and will therefore not work on a II, II+ or unenhanced IIe. ProDOS versions 1.1 to 2.4.1 seem to work.
|
||||
The AppleIISd requires an enhanced IIe or IIgs computer. The ROM code uses some 65c02 opcodes and will therefore not work on a II, II+ or unenhanced IIe. It has been tested in the following combinations:
|
||||
* Apple IIgs Rom 01, GS/OS 6.0.4
|
||||
* Apple IIgs Rom 01, Prodos 2.4.1
|
||||
* Apple IIgs Rom 01, Prodos 1.9
|
||||
* Apple IIe enhanced, 128k, Prodos 2.4.1
|
||||
* Apple IIe enhanced, 128k, Prodos 1.9
|
||||
* Apple IIe enhanced, 64k, Prodos 1.9
|
||||
|
||||
When a 2732 type ROM is used, the binary image has to be programmed at offset 0x800, because A11 is always high for compatibility with 2716 type ROMs.
|
||||
## Binary distribution
|
||||
The following files in [Binary/](Binary) have been provided to eliminate the need to compile assembler or VHDL sources.
|
||||
|
||||
| File | Purpose |
|
||||
| ---- | ------- |
|
||||
| AppleIISd_xx44.jed | CPLD bitfiles for PC44 and VQ44 formfactors |
|
||||
| AppleIISd.bin | 2k Firmware binary for EPROM |
|
||||
| AppleIISd.hex | Same as above in INTEL-HEX format |
|
||||
| AppleIISd.bom.txt | BOM for the board |
|
||||
| AppleIISd.pdf | Schematic and layout |
|
||||
| Flasher.bin | Flasher program ProDOS binary |
|
||||
| Flasher.dsk | Complete ProDOS disk image with Flasher.bin and AppleIISd.bin |
|
||||
| Gerber_Vx.x.zip | Gerber files for different hw revisions |
|
||||
|
||||
## Smartport drive remapping
|
||||
The AppleIISd features Smartport drivers in ROM to provide more than two drives in both GS/OS and ProDOS.
|
||||
|
||||
As ProDOS supports only two drives per slot, additional drives on a Smartport device are mapped to 'phantom slots'. Version prior to version 2 supported only the remapping of drives when the card was in slot 5. Starting with version 2, the remapping seems to work on all slots. The following list shows the assignments as slot/drive, when no other devices are attached:
|
||||
|
||||
* Slot 7: 7/1, 7/2, 4/1, 4/2
|
||||
* Slot 6: 6/1, 6/2, 4/1, 4/1
|
||||
* Slot 5: 5/1, 5/2, 2/1, 2/1
|
||||
* Slot 4: 4/1, 4/2, 1/1, 1/2
|
||||
* Slot 3: 80 col HW, not usable
|
||||
* Slot 2: 2/1, 2/2, 4/1, 4/2
|
||||
* Slot 1: 1/1, 1/2, 4/1, 4/2
|
||||
|
||||
When more devices are connected, things get a little confusing ;-)
|
||||
|
||||
## Building the sources
|
||||
Be sure to have the newest version of CC65 (V2.16) and some kind of Make instaled, then type one of the following comands:
|
||||
```
|
||||
make # generate binaries
|
||||
make OPTIONS=mapfile,listing # generate mapfile and listing, too
|
||||
make clean # delete binaries
|
||||
```
|
||||
Alternatively use the VisualStudio solution.
|
||||
|
||||
## Timing
|
||||
The clock of the SPI bus *SCK* may be derived from either *Phi0* or the *7M* clock. Additionally, the divisor may be 2 to 8.
|
||||
|
|
@ -53,15 +98,47 @@ LDA $C0C0
|
|||
```
|
||||
|
||||
|
||||
## Registers
|
||||
The control registers of the *AppleIISd* are mapped to the usual I/O space at **$C0n0 - $C0n3**, where n is slot+8. All registers and bits are read/write, except where noted.
|
||||
|
||||
| Address | Function | Default value |
|
||||
| ------- | --------------- | ------------- |
|
||||
| $C0n0 | DATA | - |
|
||||
| $C0n1 | **0:** PGMEN<br>**1:** -<br>**2:** ECE<br>**3:** -<br>**4:** FRX<br>**5:** BSY (R)<br>**6:** -<br>**7:** TC (R) | 0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br> |
|
||||
| $C0n2 | unused | $00 |
|
||||
| $C0n3 | **0:** /SS<br>**1:** -<br>**2:** -<br>**3:** -<br>**4:** SDHC<br>**5:** WP (R)<br>**6:** CD (R)<br>**7:** INIT | 1<br>0<br>0<br>0<br>0<br>-<br>-<br>0 |
|
||||
|
||||
**DATA** SPI data register - Is used for both input and output. When the register is written to, the controller will output the byte on the SPI bus. When it is read from, it reflects the data that was received over the SPI bus.
|
||||
|
||||
**PGMEN** Program Enable - Enable programing of the internal firmware eeprom. Should be reset immediately after writing to the device.
|
||||
|
||||
**ECE** External Clock Enable - This bit enables the the external clock input to the SPI controller. In the *AppleIISd*, this effectively switches the SPI clock between 500kHz (ECE = 0) and 3.5MHz (ECE = 1).
|
||||
|
||||
**FRX** Fast Receive mode - When set to 1, fast receive mode triggers shifting upon reading or writing the SPI Data register. When set to 0, shifting is only triggered by writing the SPI data register.
|
||||
|
||||
**BSY** Busy - This bit is 1 as long as data is shifted out on the SPI bus. *BSY* is read-only.
|
||||
|
||||
**TC** Transfer Complete - This flag is set when the last bit has been shifted out onto the SPI bus and is cleared when *SPI data* is read.
|
||||
|
||||
**/SS** Slave select - Write 0 to this bit to select the SD card.
|
||||
|
||||
**SDHC** This bit is used by the initialization routine in firmware to signalize when a SDHC card was found. Do not write to manually.
|
||||
|
||||
**WP** Write Protect - This read-only bit is 0 when writing to the card is enabled by the switch on the card.
|
||||
|
||||
**CD** Card Detect - This read-only bit is 0 when a card is inserted.
|
||||
|
||||
**INIT** Initialized - This bit is set to 1 when the SD card has been initialized by the firmware. Do not write manually.
|
||||
|
||||
## TODOs
|
||||
* Much more testing
|
||||
* SRAM option (may never work, though)
|
||||
* Find a use for the IRQ pin
|
||||
* Use 28 pin socket to support other EPROMS than 2716 and 2732
|
||||
* Enable more than 4 volumes under GS/OS
|
||||
* Support for 6502 CPUs
|
||||
* Support for CP/M
|
||||
|
||||
## Known Bugs
|
||||
* Does not always boot in slot 7 (may be a faulty connector, though)
|
||||
* Does not work, when a Z80 card is present
|
||||
* Programs not startable from partitions 3 and 4 under ProDOS
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,100 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project DefaultTargets="Build" ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
<ItemGroup Label="ProjectConfigurations">
|
||||
<ProjectConfiguration Include="Debug|Win32">
|
||||
<Configuration>Debug</Configuration>
|
||||
<Platform>Win32</Platform>
|
||||
</ProjectConfiguration>
|
||||
<ProjectConfiguration Include="Release|Win32">
|
||||
<Configuration>Release</Configuration>
|
||||
<Platform>Win32</Platform>
|
||||
</ProjectConfiguration>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<None Include="Flasher.bin.map" />
|
||||
<None Include="makefile" />
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="obj\Flasher.lst" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="src\Flasher.c" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="src\AppleIISd.h" />
|
||||
</ItemGroup>
|
||||
<PropertyGroup Label="Globals">
|
||||
<ProjectGuid>{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}</ProjectGuid>
|
||||
<Keyword>MakeFileProj</Keyword>
|
||||
<ProjectName>Flasher</ProjectName>
|
||||
</PropertyGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
|
||||
<ConfigurationType>Makefile</ConfigurationType>
|
||||
<UseDebugLibraries>true</UseDebugLibraries>
|
||||
<PlatformToolset>v140</PlatformToolset>
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
|
||||
<ConfigurationType>Makefile</ConfigurationType>
|
||||
<UseDebugLibraries>false</UseDebugLibraries>
|
||||
<PlatformToolset>v140</PlatformToolset>
|
||||
</PropertyGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
|
||||
<ImportGroup Label="ExtensionSettings">
|
||||
</ImportGroup>
|
||||
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
|
||||
</ImportGroup>
|
||||
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
|
||||
</ImportGroup>
|
||||
<PropertyGroup Label="UserMacros" />
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<NMakeOutput>
|
||||
</NMakeOutput>
|
||||
<NMakePreprocessorDefinitions>__APPLE2__;__APPLE2ENH__;__fastcall__=__fastcall;_MSC_VER=0;__attribute__</NMakePreprocessorDefinitions>
|
||||
<ExecutablePath>$(PATH);C:\cc65\bin</ExecutablePath>
|
||||
<IncludePath>C:\cc65\include</IncludePath>
|
||||
<LibraryPath>C:\cc65\lib</LibraryPath>
|
||||
<LibraryWPath />
|
||||
<ExcludePath />
|
||||
<NMakeBuildCommandLine>$(MAKE_HOME)\make OPTIONS=mapfile,listing</NMakeBuildCommandLine>
|
||||
<SourcePath>$(ProjectDir)\src</SourcePath>
|
||||
<NMakeReBuildCommandLine>$(MAKE_HOME)\make clean
|
||||
$(MAKE_HOME)\make OPTIONS=mapfile,listing</NMakeReBuildCommandLine>
|
||||
<OutDir>$(SolutionDir)\</OutDir>
|
||||
<NMakeCleanCommandLine>$(MAKE_HOME)\make clean</NMakeCleanCommandLine>
|
||||
<ReferencePath />
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<NMakeOutput>
|
||||
</NMakeOutput>
|
||||
<NMakePreprocessorDefinitions>
|
||||
</NMakePreprocessorDefinitions>
|
||||
<NMakeBuildCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"</NMakeBuildCommandLine>
|
||||
<NMakeReBuildCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make clean -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
$(MAKE_HOME)\make -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"
|
||||
</NMakeReBuildCommandLine>
|
||||
<NMakeCleanCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make clean -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"</NMakeCleanCommandLine>
|
||||
<ExecutablePath>$(PATH);C:\cc65\bin</ExecutablePath>
|
||||
<IncludePath>$(VC_IncludePath);C:\cc65\include</IncludePath>
|
||||
<ReferencePath />
|
||||
<LibraryPath>C:\cc65\lib</LibraryPath>
|
||||
<ExcludePath />
|
||||
<LibraryWPath />
|
||||
<OutDir>$(SolutionDir)$\</OutDir>
|
||||
</PropertyGroup>
|
||||
<ItemDefinitionGroup>
|
||||
</ItemDefinitionGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
|
||||
<ImportGroup Label="ExtensionTargets">
|
||||
</ImportGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
<ItemGroup>
|
||||
<None Include="makefile" />
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="Flasher.bin.map" />
|
||||
<None Include="obj\Flasher.lst" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="src\Flasher.c" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="src\AppleIISd.h" />
|
||||
</ItemGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
# Configuration for ProDOS 8 system programs (allowing for 3KB in LC)
|
||||
|
||||
SYMBOLS {
|
||||
__EXEHDR__: type = import;
|
||||
__FILETYPE__: type = weak, value = $00FF; # ProDOS file type
|
||||
__STACKSIZE__: type = weak, value = $0800; # 2k stack
|
||||
__LCADDR__: type = weak, value = $D400; # Behind quit code
|
||||
__LCSIZE__: type = weak, value = $0C00; # Rest of bank two
|
||||
}
|
||||
MEMORY {
|
||||
ZP: file = "", define = yes, start = $0080, size = $001A;
|
||||
HEADER: file = %O, start = $2000 - $003A, size = $003A;
|
||||
MAIN: file = %O, define = yes, start = $2000, size = $BF00 - $2000;
|
||||
BSS: file = "", start = __ONCE_RUN__, size = $BF00 - __STACKSIZE__ - __ONCE_RUN__;
|
||||
LC: file = "", define = yes, start = __LCADDR__, size = __LCSIZE__;
|
||||
}
|
||||
SEGMENTS {
|
||||
ZEROPAGE: load = ZP, type = zp;
|
||||
EXEHDR: load = HEADER, type = ro, optional = yes;
|
||||
STARTUP: load = MAIN, type = ro;
|
||||
LOWCODE: load = MAIN, type = ro, optional = yes;
|
||||
CODE: load = MAIN, type = ro;
|
||||
RODATA: load = MAIN, type = ro;
|
||||
DATA: load = MAIN, type = rw;
|
||||
INIT: load = MAIN, type = rw;
|
||||
ONCE: load = MAIN, type = ro, define = yes;
|
||||
LC: load = MAIN, run = LC, type = ro, optional = yes;
|
||||
BSS: load = BSS, type = bss, define = yes;
|
||||
}
|
||||
FEATURES {
|
||||
CONDES: type = constructor,
|
||||
label = __CONSTRUCTOR_TABLE__,
|
||||
count = __CONSTRUCTOR_COUNT__,
|
||||
segment = ONCE;
|
||||
CONDES: type = destructor,
|
||||
label = __DESTRUCTOR_TABLE__,
|
||||
count = __DESTRUCTOR_COUNT__,
|
||||
segment = RODATA;
|
||||
CONDES: type = interruptor,
|
||||
label = __INTERRUPTOR_TABLE__,
|
||||
count = __INTERRUPTOR_COUNT__,
|
||||
segment = RODATA,
|
||||
import = __CALLIRQ__;
|
||||
}
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
make clean
|
||||
make
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -d ..\Binary\Flasher.dsk flasher
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -as ..\Binary\Flasher.dsk flasher < Flasher.bin
|
||||
copy Flasher.bin ..\Binary
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/bash
|
||||
|
||||
make clean
|
||||
make
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -d ../Binary/Flasher.dsk flasher
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -as ../Binary/Flasher.dsk flasher < Flasher.bin
|
||||
cp Flasher.bin ../Binary/
|
||||
|
|
@ -0,0 +1,346 @@
|
|||
###############################################################################
|
||||
### Generic Makefile for cc65 projects - full version with abstract options ###
|
||||
### V1.3.0(w) 2010 - 2013 Oliver Schmidt & Patryk "Silver Dream !" ?ogiewa ###
|
||||
###############################################################################
|
||||
|
||||
###############################################################################
|
||||
### In order to override defaults - values can be assigned to the variables ###
|
||||
###############################################################################
|
||||
|
||||
# Space or comma separated list of cc65 supported target platforms to build for.
|
||||
# Default: c64 (lowercase!)
|
||||
TARGETS := apple2enh
|
||||
|
||||
# Name of the final, single-file executable.
|
||||
# Default: name of the current dir with target name appended
|
||||
PROGRAM := Flasher
|
||||
|
||||
# Path(s) to additional libraries required for linking the program
|
||||
# Use only if you don't want to place copies of the libraries in SRCDIR
|
||||
# Default: none
|
||||
LIBS :=
|
||||
|
||||
# Custom linker configuration file
|
||||
# Use only if you don't want to place it in SRCDIR
|
||||
# Default: none
|
||||
CONFIG := apple2enh-system.cfg
|
||||
|
||||
# Additional C compiler flags and options.
|
||||
# Default: none
|
||||
CFLAGS =
|
||||
|
||||
# Additional assembler flags and options.
|
||||
# Default: none
|
||||
ASFLAGS =
|
||||
|
||||
# Additional linker flags and options.
|
||||
# Default: none
|
||||
LDFLAGS =
|
||||
|
||||
# Path to the directory containing C and ASM sources.
|
||||
# Default: src
|
||||
SRCDIR :=
|
||||
|
||||
# Path to the directory where object files are to be stored (inside respective target subdirectories).
|
||||
# Default: obj
|
||||
OBJDIR :=
|
||||
|
||||
# Command used to run the emulator.
|
||||
# Default: depending on target platform. For default (c64) target: x64 -kernal kernal -VICIIdsize -autoload
|
||||
EMUCMD :=
|
||||
|
||||
# Optional commands used before starting the emulation process, and after finishing it.
|
||||
# Default: none
|
||||
# Examples
|
||||
#PREEMUCMD := osascript -e "tell application \"System Events\" to set isRunning to (name of processes) contains \"X11.bin\"" -e "if isRunning is true then tell application \"X11\" to activate"
|
||||
#PREEMUCMD := osascript -e "tell application \"X11\" to activate"
|
||||
#POSTEMUCMD := osascript -e "tell application \"System Events\" to tell process \"X11\" to set visible to false"
|
||||
#POSTEMUCMD := osascript -e "tell application \"Terminal\" to activate"
|
||||
PREEMUCMD :=
|
||||
POSTEMUCMD :=
|
||||
|
||||
# On Windows machines VICE emulators may not be available in the PATH by default.
|
||||
# In such case, please set the variable below to point to directory containing
|
||||
# VICE emulators.
|
||||
#VICE_HOME := "C:\Program Files\WinVICE-2.2-x86\"
|
||||
VICE_HOME :=
|
||||
|
||||
# Options state file name. You should not need to change this, but for those
|
||||
# rare cases when you feel you really need to name it differently - here you are
|
||||
STATEFILE := Makefile.options
|
||||
|
||||
###################################################################################
|
||||
#### DO NOT EDIT BELOW THIS LINE, UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! ####
|
||||
###################################################################################
|
||||
|
||||
###################################################################################
|
||||
### Mapping abstract options to the actual compiler, assembler and linker flags ###
|
||||
### Predefined compiler, assembler and linker flags, used with abstract options ###
|
||||
### valid for 2.14.x. Consult the documentation of your cc65 version before use ###
|
||||
###################################################################################
|
||||
|
||||
# Compiler flags used to tell the compiler to optimise for SPEED
|
||||
define _optspeed_
|
||||
CFLAGS += -Oris
|
||||
endef
|
||||
|
||||
# Compiler flags used to tell the compiler to optimise for SIZE
|
||||
define _optsize_
|
||||
CFLAGS += -Or
|
||||
endef
|
||||
|
||||
# Compiler and assembler flags for generating listings
|
||||
define _listing_
|
||||
CFLAGS += --listing $$(@:.o=.lst) -T
|
||||
ASFLAGS += --listing $$(@:.o=.lst)
|
||||
REMOVES += $(addsuffix .lst,$(basename $(OBJECTS)))
|
||||
endef
|
||||
|
||||
# Linker flags for generating map file
|
||||
define _mapfile_
|
||||
LDFLAGS += --mapfile $$@.map
|
||||
REMOVES += $(PROGRAM).map
|
||||
endef
|
||||
|
||||
# Linker flags for generating VICE label file
|
||||
define _labelfile_
|
||||
LDFLAGS += -Ln $$@.lbl
|
||||
REMOVES += $(PROGRAM).lbl
|
||||
endef
|
||||
|
||||
# Linker flags for generating a debug file
|
||||
define _debugfile_
|
||||
LDFLAGS += -Wl --dbgfile,$$@.dbg
|
||||
REMOVES += $(PROGRAM).dbg
|
||||
endef
|
||||
|
||||
###############################################################################
|
||||
### Defaults to be used if nothing defined in the editable sections above ###
|
||||
###############################################################################
|
||||
|
||||
# Presume the C64 target like the cl65 compile & link utility does.
|
||||
# Set TARGETS to override.
|
||||
ifeq ($(TARGETS),)
|
||||
TARGETS := c64
|
||||
endif
|
||||
|
||||
# Presume we're in a project directory so name the program like the current
|
||||
# directory. Set PROGRAM to override.
|
||||
ifeq ($(PROGRAM),)
|
||||
PROGRAM := $(notdir $(CURDIR))
|
||||
endif
|
||||
|
||||
# Presume the C and asm source files to be located in the subdirectory 'src'.
|
||||
# Set SRCDIR to override.
|
||||
ifeq ($(SRCDIR),)
|
||||
SRCDIR := src
|
||||
endif
|
||||
|
||||
# Presume the object and dependency files to be located in the subdirectory
|
||||
# 'obj' (which will be created). Set OBJDIR to override.
|
||||
ifeq ($(OBJDIR),)
|
||||
OBJDIR := obj
|
||||
endif
|
||||
TARGETOBJDIR := $(OBJDIR)
|
||||
|
||||
# On Windows it is mandatory to have CC65_HOME set. So do not unnecessarily
|
||||
# rely on cl65 being added to the PATH in this scenario.
|
||||
ifdef CC65_HOME
|
||||
CC := $(CC65_HOME)/bin/cl65
|
||||
else
|
||||
CC := cl65
|
||||
endif
|
||||
|
||||
# Default emulator commands and options for particular targets.
|
||||
# Set EMUCMD to override.
|
||||
c64_EMUCMD := $(VICE_HOME)x64 -kernal kernal -VICIIdsize -autoload
|
||||
c128_EMUCMD := $(VICE_HOME)x128 -kernal kernal -VICIIdsize -autoload
|
||||
vic20_EMUCMD := $(VICE_HOME)xvic -kernal kernal -VICdsize -autoload
|
||||
pet_EMUCMD := $(VICE_HOME)xpet -Crtcdsize -autoload
|
||||
plus4_EMUCMD := $(VICE_HOME)xplus4 -TEDdsize -autoload
|
||||
# So far there is no x16 emulator in VICE (why??) so we have to use xplus4 with -memsize option
|
||||
c16_EMUCMD := $(VICE_HOME)xplus4 -ramsize 16 -TEDdsize -autoload
|
||||
cbm510_EMUCMD := $(VICE_HOME)xcbm2 -model 510 -VICIIdsize -autoload
|
||||
cbm610_EMUCMD := $(VICE_HOME)xcbm2 -model 610 -Crtcdsize -autoload
|
||||
atari_EMUCMD := atari800 -windowed -xl -pal -nopatchall -run
|
||||
|
||||
ifeq ($(EMUCMD),)
|
||||
EMUCMD = $($(CC65TARGET)_EMUCMD)
|
||||
endif
|
||||
|
||||
###############################################################################
|
||||
### The magic begins ###
|
||||
###############################################################################
|
||||
|
||||
# The "Native Win32" GNU Make contains quite some workarounds to get along with
|
||||
# cmd.exe as shell. However it does not provide means to determine that it does
|
||||
# actually activate those workarounds. Especially $(SHELL) does NOT contain the
|
||||
# value 'cmd.exe'. So the usual way to determine if cmd.exe is being used is to
|
||||
# execute the command 'echo' without any parameters. Only cmd.exe will return a
|
||||
# non-empty string - saying 'ECHO is on/off'.
|
||||
#
|
||||
# Many "Native Win32" programs accept '/' as directory delimiter just fine. How-
|
||||
# ever the internal commands of cmd.exe generally require '\' to be used.
|
||||
#
|
||||
# cmd.exe has an internal command 'mkdir' that doesn't understand nor require a
|
||||
# '-p' to create parent directories as needed.
|
||||
#
|
||||
# cmd.exe has an internal command 'del' that reports a syntax error if executed
|
||||
# without any file so make sure to call it only if there's an actual argument.
|
||||
ifeq ($(shell echo),)
|
||||
MKDIR = mkdir -p $1
|
||||
RMDIR = rmdir $1
|
||||
RMFILES = $(RM) $1
|
||||
else
|
||||
MKDIR = mkdir $(subst /,\,$1)
|
||||
RMDIR = rmdir $(subst /,\,$1)
|
||||
RMFILES = $(if $1,del /f $(subst /,\,$1))
|
||||
endif
|
||||
COMMA := ,
|
||||
SPACE := $(N/A) $(N/A)
|
||||
define NEWLINE
|
||||
|
||||
|
||||
endef
|
||||
# Note: Do not remove any of the two empty lines above !
|
||||
|
||||
TARGETLIST := $(subst $(COMMA),$(SPACE),$(TARGETS))
|
||||
|
||||
ifeq ($(words $(TARGETLIST)),1)
|
||||
|
||||
# Set PROGRAM to something like 'myprog.c64'.
|
||||
override PROGRAM := $(PROGRAM).bin
|
||||
|
||||
# Set SOURCES to something like 'src/foo.c src/bar.s'.
|
||||
# Use of assembler files with names ending differently than .s is deprecated!
|
||||
SOURCES := $(wildcard $(SRCDIR)/*.c)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.s)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.asm)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.a65)
|
||||
|
||||
# Add to SOURCES something like 'src/c64/me.c src/c64/too.s'.
|
||||
# Use of assembler files with names ending differently than .s is deprecated!
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.c)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.s)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.asm)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.a65)
|
||||
|
||||
# Set OBJECTS to something like 'obj/c64/foo.o obj/c64/bar.o'.
|
||||
OBJECTS := $(addsuffix .o,$(basename $(addprefix $(TARGETOBJDIR)/,$(notdir $(SOURCES)))))
|
||||
|
||||
# Set DEPENDS to something like 'obj/c64/foo.d obj/c64/bar.d'.
|
||||
DEPENDS := $(OBJECTS:.o=.d)
|
||||
|
||||
# Add to LIBS something like 'src/foo.lib src/c64/bar.lib'.
|
||||
LIBS += $(wildcard $(SRCDIR)/*.lib)
|
||||
LIBS += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.lib)
|
||||
|
||||
# Add to CONFIG something like 'src/c64/bar.cfg src/foo.cfg'.
|
||||
CONFIG += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.cfg)
|
||||
CONFIG += $(wildcard $(SRCDIR)/*.cfg)
|
||||
|
||||
# Select CONFIG file to use. Target specific configs have higher priority.
|
||||
ifneq ($(word 2,$(CONFIG)),)
|
||||
CONFIG := $(firstword $(CONFIG))
|
||||
$(info Using config file $(CONFIG) for linking)
|
||||
endif
|
||||
|
||||
.SUFFIXES:
|
||||
.PHONY: all test clean zap love
|
||||
|
||||
all: $(PROGRAM)
|
||||
|
||||
-include $(DEPENDS)
|
||||
-include $(STATEFILE)
|
||||
|
||||
# If OPTIONS are given on the command line then save them to STATEFILE
|
||||
# if (and only if) they have actually changed. But if OPTIONS are not
|
||||
# given on the command line then load them from STATEFILE. Have object
|
||||
# files depend on STATEFILE only if it actually exists.
|
||||
ifeq ($(origin OPTIONS),command line)
|
||||
ifneq ($(OPTIONS),$(_OPTIONS_))
|
||||
ifeq ($(OPTIONS),)
|
||||
$(info Removing OPTIONS)
|
||||
$(shell $(RM) $(STATEFILE))
|
||||
$(eval $(STATEFILE):)
|
||||
else
|
||||
$(info Saving OPTIONS=$(OPTIONS))
|
||||
$(shell echo _OPTIONS_=$(OPTIONS) > $(STATEFILE))
|
||||
endif
|
||||
$(eval $(OBJECTS): $(STATEFILE))
|
||||
endif
|
||||
else
|
||||
ifeq ($(origin _OPTIONS_),file)
|
||||
$(info Using saved OPTIONS=$(_OPTIONS_))
|
||||
OPTIONS = $(_OPTIONS_)
|
||||
$(eval $(OBJECTS): $(STATEFILE))
|
||||
endif
|
||||
endif
|
||||
|
||||
# Transform the abstract OPTIONS to the actual cc65 options.
|
||||
$(foreach o,$(subst $(COMMA),$(SPACE),$(OPTIONS)),$(eval $(_$o_)))
|
||||
|
||||
# Strip potential variant suffix from the actual cc65 target.
|
||||
CC65TARGET := $(firstword $(subst .,$(SPACE),$(TARGETLIST)))
|
||||
|
||||
# The remaining targets.
|
||||
$(TARGETOBJDIR):
|
||||
$(call MKDIR,$@)
|
||||
|
||||
vpath %.c $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.c | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(CFLAGS) -o $@ $<
|
||||
|
||||
vpath %.s $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.s | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
vpath %.asm $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.asm | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
vpath %.a65 $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.a65 | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
$(PROGRAM): $(CONFIG) $(OBJECTS) $(LIBS)
|
||||
$(CC) -t $(CC65TARGET) $(LDFLAGS) -o $@ $(patsubst %.cfg,-C %.cfg,$^)
|
||||
|
||||
test: $(PROGRAM)
|
||||
$(PREEMUCMD)
|
||||
$(EMUCMD) $<
|
||||
$(POSTEMUCMD)
|
||||
|
||||
clean:
|
||||
$(call RMFILES,$(OBJECTS))
|
||||
$(call RMFILES,$(DEPENDS))
|
||||
$(call RMFILES,$(REMOVES))
|
||||
$(call RMFILES,$(PROGRAM))
|
||||
|
||||
else # $(words $(TARGETLIST)),1
|
||||
|
||||
all test clean:
|
||||
$(foreach t,$(TARGETLIST),$(MAKE) TARGETS=$t $@$(NEWLINE))
|
||||
|
||||
endif # $(words $(TARGETLIST)),1
|
||||
|
||||
OBJDIRLIST := $(wildcard $(OBJDIR)/*)
|
||||
|
||||
zap:
|
||||
$(foreach o,$(OBJDIRLIST),-$(call RMFILES,$o/*.o $o/*.d $o/*.lst)$(NEWLINE))
|
||||
$(foreach o,$(OBJDIRLIST),-$(call RMDIR,$o)$(NEWLINE))
|
||||
-$(call RMDIR,$(OBJDIR))
|
||||
-$(call RMFILES,$(basename $(PROGRAM)).* $(STATEFILE))
|
||||
|
||||
love:
|
||||
@echo "Not war, eh?"
|
||||
|
||||
###################################################################
|
||||
### Place your additional targets in the additional Makefiles ###
|
||||
### in the same directory - their names have to end with ".mk"! ###
|
||||
###################################################################
|
||||
-include *.mk
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
#ifndef APPLE_II_SD_H
|
||||
#define APPLE_II_SD_H
|
||||
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned short uint16;
|
||||
typedef unsigned long uint32;
|
||||
typedef unsigned char boolean;
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#define SLOT_IO_START (volatile uint8*)0xC080
|
||||
#define SLOT_ROM_START (volatile uint8*)0xC000
|
||||
#define EXT_ROM_START (volatile uint8*)0xC800
|
||||
|
||||
#define CFFF (volatile uint8*)0xCFFF
|
||||
|
||||
typedef volatile struct
|
||||
{
|
||||
// data register
|
||||
// +0
|
||||
uint8 data;
|
||||
|
||||
// status register
|
||||
// +1
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned pgmen : 1;
|
||||
unsigned : 1;
|
||||
unsigned ece : 1;
|
||||
unsigned : 1;
|
||||
unsigned frx : 1;
|
||||
const unsigned bsy : 1;
|
||||
unsigned : 1;
|
||||
const unsigned tc : 1;
|
||||
};
|
||||
|
||||
uint8 status;
|
||||
} status;
|
||||
|
||||
// clock divisor register, unused
|
||||
// +2
|
||||
uint8 clkDiv;
|
||||
|
||||
// slave select and card state register
|
||||
// +3
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned slaveSel : 1;
|
||||
unsigned : 3;
|
||||
unsigned sdhc : 1;
|
||||
const unsigned wp : 1;
|
||||
const unsigned card : 1;
|
||||
unsigned inited : 1;
|
||||
};
|
||||
|
||||
uint8 ss_card;
|
||||
} ss_card;
|
||||
} APPLE_II_SD_T;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
#include "AppleIISd.h"
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdio.h>
|
||||
#include <errno.h>
|
||||
#include <conio.h>
|
||||
#include <string.h>
|
||||
#include <apple2enh.h>
|
||||
|
||||
// Binary can't be larger than 2k
|
||||
#define BUFFER_SIZE 2048
|
||||
#define BIN_FILE_NAME "AppleIISd.bin"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
STATE_0, // pipe
|
||||
STATE_1, // slash
|
||||
STATE_2, // hyphen
|
||||
STATE_3, // backslash
|
||||
|
||||
STATE_LAST // don't use
|
||||
} STATE_CURSOR_T;
|
||||
|
||||
const char state_char[STATE_LAST] = { '|', '/', '-', '\\' };
|
||||
static uint8 buffer[BUFFER_SIZE];
|
||||
|
||||
static void writeChip(const uint8* pSource, volatile uint8* pDest, uint16 length);
|
||||
static boolean verifyChip(const uint8* pSource, volatile uint8* pDest, uint16 length);
|
||||
static void printStatus(uint8 percentage);
|
||||
|
||||
int main()
|
||||
{
|
||||
int retval = 1;
|
||||
FILE* pFile;
|
||||
char slotNum;
|
||||
boolean erase = FALSE;
|
||||
uint16 fileSize = 0;
|
||||
|
||||
APPLE_II_SD_T* pAIISD;
|
||||
volatile uint8* pSlotRom = SLOT_ROM_START;
|
||||
volatile uint8 dummy;
|
||||
|
||||
videomode(VIDEOMODE_40COL);
|
||||
clrscr();
|
||||
cprintf("AppleIISd firmware flasher V1.2\r\n");
|
||||
cprintf("(c) 2019-2020 Florian Reitz\r\n\r\n");
|
||||
|
||||
// ask for slot
|
||||
cursor(1); // enable blinking cursor
|
||||
cprintf("Slot number (1-7): ");
|
||||
cscanf("%c", &slotNum);
|
||||
slotNum -= 0x30;
|
||||
cursor(0); // disable blinking cursor
|
||||
|
||||
if(slotNum == 0)
|
||||
{
|
||||
// erase device
|
||||
erase = TRUE;
|
||||
// ask for slot
|
||||
cursor(1); // enable blinking cursor
|
||||
cprintf("Erase device in slot number (1-7): ");
|
||||
cscanf("%c", &slotNum);
|
||||
slotNum -= 0x30;
|
||||
cursor(0); // disable blinking cursor
|
||||
}
|
||||
|
||||
// check if slot is valid
|
||||
if((slotNum < 1) || (slotNum > 7))
|
||||
{
|
||||
cprintf("\r\nInvalid slot number!");
|
||||
cgetc();
|
||||
return 1; // failure
|
||||
}
|
||||
|
||||
pAIISD = (APPLE_II_SD_T*)(SLOT_IO_START + (slotNum << 4));
|
||||
pSlotRom += slotNum << 8;
|
||||
|
||||
if(erase)
|
||||
{
|
||||
fileSize = BUFFER_SIZE;
|
||||
memset(buffer, 0, sizeof(buffer));
|
||||
}
|
||||
else
|
||||
{
|
||||
// open file
|
||||
pFile = fopen(BIN_FILE_NAME, "rb");
|
||||
if(pFile)
|
||||
{
|
||||
// read buffer
|
||||
fileSize = fread(buffer, 1, sizeof(buffer), pFile);
|
||||
fclose(pFile);
|
||||
pFile = NULL;
|
||||
|
||||
if(fileSize != BUFFER_SIZE)
|
||||
{
|
||||
cprintf("\r\nWrong file size: %d\r\n", fileSize);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
cprintf("\r\nCan't open %s file\r\n", BIN_FILE_NAME);
|
||||
fileSize = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if(fileSize == BUFFER_SIZE)
|
||||
{
|
||||
// enable write
|
||||
pAIISD->status.pgmen = 1;
|
||||
|
||||
// write to SLOTROM
|
||||
cprintf("\r\n\r\nFlashing SLOTROM: ");
|
||||
writeChip(buffer, pSlotRom, 256);
|
||||
|
||||
cprintf("\r\nVerifying SLOTROM: ");
|
||||
if(verifyChip(buffer, pSlotRom, 256))
|
||||
{
|
||||
// write to EXT_ROM
|
||||
cprintf("\r\n\r\nFlashing EXTROM: ");
|
||||
|
||||
// clear CFFF and dummy read to enable correct EXT_ROM
|
||||
dummy = *CFFF;
|
||||
dummy = *pSlotRom;
|
||||
|
||||
writeChip(buffer + 256, EXT_ROM_START, fileSize - 256);
|
||||
cprintf("\r\nVerifying EXTROM: ");
|
||||
|
||||
dummy = *CFFF;
|
||||
dummy = *pSlotRom;
|
||||
|
||||
if(verifyChip(buffer + 256, EXT_ROM_START, fileSize - 256))
|
||||
{
|
||||
cprintf("\r\n\r\nFlashing finished!\n");
|
||||
retval = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// disable write
|
||||
pAIISD->status.pgmen = 0;
|
||||
}
|
||||
|
||||
cgetc();
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void writeChip(const uint8* pSource, volatile uint8* pDest, uint16 length)
|
||||
{
|
||||
uint32 i;
|
||||
volatile uint8 readData;
|
||||
|
||||
for(i=0; i<length; i++)
|
||||
{
|
||||
pDest[i] = pSource[i];
|
||||
printStatus((i * 100u / length) + 1);
|
||||
|
||||
// wait for write cycle
|
||||
do
|
||||
{
|
||||
readData = pDest[i];
|
||||
}
|
||||
while((readData & 0x80) != (pSource[i] & 0x80));
|
||||
}
|
||||
}
|
||||
|
||||
static boolean verifyChip(const uint8* pSource, volatile uint8* pDest, uint16 length)
|
||||
{
|
||||
uint32 i;
|
||||
|
||||
for(i=0; i<length; i++)
|
||||
{
|
||||
printStatus((i * 100u / length) + 1);
|
||||
|
||||
if(pDest[i] != pSource[i])
|
||||
{
|
||||
// verification not successful
|
||||
cprintf("\r\n\r\n!!! Verification failed at %p !!!\r\n", &pDest[i]);
|
||||
cprintf("Was 0x%02hhX, should be 0x%02hhX\r\n", pDest[i], pSource[i]);
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static void printStatus(uint8 percentage)
|
||||
{
|
||||
static STATE_CURSOR_T state = STATE_0;
|
||||
uint8 wait = 0;
|
||||
uint8 x = wherex();
|
||||
char cState = (percentage < 100) ? state_char[state] : ' ';
|
||||
|
||||
cprintf("% 3hhu%% %c", percentage, cState);
|
||||
gotox(x);
|
||||
|
||||
state++;
|
||||
if(state == STATE_LAST)
|
||||
{
|
||||
state = STATE_0;
|
||||
}
|
||||
}
|
||||
|
|
@ -1 +0,0 @@
|
|||
MODULE AddressDecoder
|
||||
|
|
@ -1,244 +0,0 @@
|
|||
VERSION 6
|
||||
BEGIN SCHEMATIC
|
||||
BEGIN ATTR DeviceFamilyName "xc9500xl"
|
||||
DELETE all:0
|
||||
EDITNAME all:0
|
||||
EDITTRAIT all:0
|
||||
END ATTR
|
||||
BEGIN NETLIST
|
||||
SIGNAL A10
|
||||
SIGNAL A9
|
||||
SIGNAL A8
|
||||
SIGNAL XLXN_10
|
||||
SIGNAL CLK
|
||||
SIGNAL XLXN_14
|
||||
SIGNAL B10
|
||||
SIGNAL B9
|
||||
SIGNAL B8
|
||||
SIGNAL NOE
|
||||
SIGNAL XLXN_29
|
||||
SIGNAL NIO_SEL
|
||||
SIGNAL NIO_STB
|
||||
SIGNAL XLXN_38
|
||||
SIGNAL XLXN_46
|
||||
SIGNAL XLXN_47
|
||||
SIGNAL NDEV_SEL
|
||||
PORT Input A10
|
||||
PORT Input A9
|
||||
PORT Input A8
|
||||
PORT Input CLK
|
||||
PORT Output B10
|
||||
PORT Output B9
|
||||
PORT Output B8
|
||||
PORT Output NOE
|
||||
PORT Input NIO_SEL
|
||||
PORT Input NIO_STB
|
||||
PORT Input NDEV_SEL
|
||||
BEGIN BLOCKDEF fdrs
|
||||
TIMESTAMP 2001 3 9 11 23 0
|
||||
LINE N 0 -128 64 -128
|
||||
LINE N 0 -256 64 -256
|
||||
LINE N 384 -256 320 -256
|
||||
LINE N 0 -32 64 -32
|
||||
LINE N 0 -352 64 -352
|
||||
RECTANGLE N 64 -320 320 -64
|
||||
LINE N 192 -64 192 -32
|
||||
LINE N 192 -32 64 -32
|
||||
LINE N 64 -112 80 -128
|
||||
LINE N 80 -128 64 -144
|
||||
LINE N 192 -320 192 -352
|
||||
LINE N 192 -352 64 -352
|
||||
END BLOCKDEF
|
||||
BEGIN BLOCKDEF inv
|
||||
TIMESTAMP 2001 3 9 11 23 50
|
||||
LINE N 0 -32 64 -32
|
||||
LINE N 224 -32 160 -32
|
||||
LINE N 64 -64 128 -32
|
||||
LINE N 128 -32 64 0
|
||||
LINE N 64 0 64 -64
|
||||
CIRCLE N 128 -48 160 -16
|
||||
END BLOCKDEF
|
||||
BEGIN BLOCKDEF vcc
|
||||
TIMESTAMP 2001 3 9 11 23 11
|
||||
LINE N 96 -64 32 -64
|
||||
LINE N 64 0 64 -32
|
||||
LINE N 64 -32 64 -64
|
||||
END BLOCKDEF
|
||||
BEGIN BLOCKDEF and2
|
||||
TIMESTAMP 2001 5 11 10 41 37
|
||||
LINE N 0 -64 64 -64
|
||||
LINE N 0 -128 64 -128
|
||||
LINE N 256 -96 192 -96
|
||||
ARC N 96 -144 192 -48 144 -48 144 -144
|
||||
LINE N 144 -48 64 -48
|
||||
LINE N 64 -144 144 -144
|
||||
LINE N 64 -48 64 -144
|
||||
END BLOCKDEF
|
||||
BEGIN BLOCKDEF and4
|
||||
TIMESTAMP 2001 5 11 10 43 14
|
||||
LINE N 144 -112 64 -112
|
||||
ARC N 96 -208 192 -112 144 -112 144 -208
|
||||
LINE N 64 -208 144 -208
|
||||
LINE N 64 -64 64 -256
|
||||
LINE N 256 -160 192 -160
|
||||
LINE N 0 -256 64 -256
|
||||
LINE N 0 -192 64 -192
|
||||
LINE N 0 -128 64 -128
|
||||
LINE N 0 -64 64 -64
|
||||
END BLOCKDEF
|
||||
BEGIN BLOCKDEF nand2
|
||||
TIMESTAMP 2001 3 9 11 23 50
|
||||
LINE N 0 -64 64 -64
|
||||
LINE N 0 -128 64 -128
|
||||
LINE N 256 -96 216 -96
|
||||
CIRCLE N 192 -108 216 -84
|
||||
LINE N 64 -48 64 -144
|
||||
LINE N 64 -144 144 -144
|
||||
LINE N 144 -48 64 -48
|
||||
ARC N 96 -144 192 -48 144 -48 144 -144
|
||||
END BLOCKDEF
|
||||
BEGIN BLOCK XLXI_16 fdrs
|
||||
PIN C CLK
|
||||
PIN D XLXN_14
|
||||
PIN R XLXN_10
|
||||
PIN S XLXN_46
|
||||
PIN Q XLXN_47
|
||||
END BLOCK
|
||||
BEGIN BLOCK XLXI_17 vcc
|
||||
PIN P XLXN_14
|
||||
END BLOCK
|
||||
BEGIN BLOCK XLXI_18 and2
|
||||
PIN I0 A10
|
||||
PIN I1 XLXN_38
|
||||
PIN O B10
|
||||
END BLOCK
|
||||
BEGIN BLOCK XLXI_19 and2
|
||||
PIN I0 A9
|
||||
PIN I1 XLXN_38
|
||||
PIN O B9
|
||||
END BLOCK
|
||||
BEGIN BLOCK XLXI_20 and2
|
||||
PIN I0 A8
|
||||
PIN I1 XLXN_38
|
||||
PIN O B8
|
||||
END BLOCK
|
||||
BEGIN BLOCK XLXI_22 inv
|
||||
PIN I NIO_SEL
|
||||
PIN O XLXN_46
|
||||
END BLOCK
|
||||
BEGIN BLOCK XLXI_30 and4
|
||||
PIN I0 A8
|
||||
PIN I1 A9
|
||||
PIN I2 A10
|
||||
PIN I3 XLXN_38
|
||||
PIN O XLXN_10
|
||||
END BLOCK
|
||||
BEGIN BLOCK XLXI_31 inv
|
||||
PIN I NIO_STB
|
||||
PIN O XLXN_38
|
||||
END BLOCK
|
||||
BEGIN BLOCK XLXI_32 nand2
|
||||
PIN I0 XLXN_47
|
||||
PIN I1 NDEV_SEL
|
||||
PIN O NOE
|
||||
END BLOCK
|
||||
END NETLIST
|
||||
BEGIN SHEET 1 3520 2720
|
||||
BEGIN BRANCH A10
|
||||
WIRE 320 704 592 704
|
||||
WIRE 592 704 704 704
|
||||
WIRE 592 704 592 992
|
||||
WIRE 592 992 1088 992
|
||||
END BRANCH
|
||||
BEGIN BRANCH A9
|
||||
WIRE 320 768 528 768
|
||||
WIRE 528 768 704 768
|
||||
WIRE 528 768 528 1136
|
||||
WIRE 528 1136 1088 1136
|
||||
END BRANCH
|
||||
BEGIN BRANCH A8
|
||||
WIRE 320 832 464 832
|
||||
WIRE 464 832 704 832
|
||||
WIRE 464 832 464 1280
|
||||
WIRE 464 1280 1088 1280
|
||||
END BRANCH
|
||||
IOMARKER 320 704 A10 R180 28
|
||||
IOMARKER 320 768 A9 R180 28
|
||||
IOMARKER 320 832 A8 R180 28
|
||||
BEGIN BRANCH CLK
|
||||
WIRE 320 576 912 576
|
||||
WIRE 912 576 912 640
|
||||
WIRE 912 640 992 640
|
||||
END BRANCH
|
||||
BEGIN BRANCH B10
|
||||
WIRE 1344 960 1360 960
|
||||
WIRE 1360 960 1664 960
|
||||
END BRANCH
|
||||
BEGIN BRANCH B9
|
||||
WIRE 1344 1104 1360 1104
|
||||
WIRE 1360 1104 1664 1104
|
||||
END BRANCH
|
||||
BEGIN BRANCH B8
|
||||
WIRE 1344 1248 1360 1248
|
||||
WIRE 1360 1248 1664 1248
|
||||
END BRANCH
|
||||
BEGIN BRANCH NOE
|
||||
WIRE 1680 336 1696 336
|
||||
END BRANCH
|
||||
BEGIN BRANCH NIO_SEL
|
||||
WIRE 320 368 352 368
|
||||
END BRANCH
|
||||
BEGIN BRANCH NIO_STB
|
||||
WIRE 320 640 336 640
|
||||
END BRANCH
|
||||
IOMARKER 320 368 NIO_SEL R180 28
|
||||
IOMARKER 320 640 NIO_STB R180 28
|
||||
INSTANCE XLXI_31 336 672 R0
|
||||
BEGIN BRANCH XLXN_38
|
||||
WIRE 560 640 672 640
|
||||
WIRE 672 640 704 640
|
||||
WIRE 672 640 672 928
|
||||
WIRE 672 928 1088 928
|
||||
WIRE 672 928 672 1072
|
||||
WIRE 672 1072 1088 1072
|
||||
WIRE 672 1072 672 1216
|
||||
WIRE 672 1216 1088 1216
|
||||
END BRANCH
|
||||
INSTANCE XLXI_30 704 896 R0
|
||||
BEGIN BRANCH XLXN_10
|
||||
WIRE 960 736 976 736
|
||||
WIRE 976 736 992 736
|
||||
END BRANCH
|
||||
BEGIN BRANCH XLXN_14
|
||||
WIRE 848 496 848 512
|
||||
WIRE 848 512 992 512
|
||||
END BRANCH
|
||||
IOMARKER 320 576 CLK R180 28
|
||||
INSTANCE XLXI_17 784 496 R0
|
||||
INSTANCE XLXI_22 352 400 R0
|
||||
BEGIN BRANCH XLXN_46
|
||||
WIRE 576 368 592 368
|
||||
WIRE 592 368 992 368
|
||||
WIRE 992 368 992 416
|
||||
END BRANCH
|
||||
INSTANCE XLXI_16 992 768 R0
|
||||
INSTANCE XLXI_18 1088 1056 R0
|
||||
INSTANCE XLXI_19 1088 1200 R0
|
||||
INSTANCE XLXI_20 1088 1344 R0
|
||||
IOMARKER 1664 960 B10 R0 28
|
||||
IOMARKER 1664 1104 B9 R0 28
|
||||
IOMARKER 1664 1248 B8 R0 28
|
||||
INSTANCE XLXI_32 1424 432 R0
|
||||
BEGIN BRANCH XLXN_47
|
||||
WIRE 1376 512 1392 512
|
||||
WIRE 1392 368 1424 368
|
||||
WIRE 1392 368 1392 512
|
||||
END BRANCH
|
||||
IOMARKER 1696 336 NOE R0 28
|
||||
BEGIN BRANCH NDEV_SEL
|
||||
WIRE 320 304 1408 304
|
||||
WIRE 1408 304 1424 304
|
||||
END BRANCH
|
||||
IOMARKER 320 304 NDEV_SEL R180 28
|
||||
END SHEET
|
||||
END SCHEMATIC
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="AddressDecoder">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2017-9-3T12:42:25</timestamp>
|
||||
<pin polarity="Input" x="0" y="-416" name="A10" />
|
||||
<pin polarity="Input" x="0" y="-352" name="A9" />
|
||||
<pin polarity="Input" x="0" y="-288" name="A8" />
|
||||
<pin polarity="Input" x="0" y="-224" name="CLK" />
|
||||
<pin polarity="Input" x="0" y="-160" name="NIO_SEL" />
|
||||
<pin polarity="Input" x="0" y="-96" name="NIO_STB" />
|
||||
<pin polarity="Input" x="0" y="-32" name="NDEV_SEL" />
|
||||
<pin polarity="Output" x="384" y="-416" name="B10" />
|
||||
<pin polarity="Output" x="384" y="-288" name="B9" />
|
||||
<pin polarity="Output" x="384" y="-160" name="B8" />
|
||||
<pin polarity="Output" x="384" y="-32" name="NOE" />
|
||||
<graph>
|
||||
<rect width="256" x="64" y="-448" height="448" />
|
||||
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-456" type="symbol" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin A10" />
|
||||
<line x2="0" y1="-416" y2="-416" x1="64" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin A9" />
|
||||
<line x2="0" y1="-352" y2="-352" x1="64" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin A8" />
|
||||
<line x2="0" y1="-288" y2="-288" x1="64" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin CLK" />
|
||||
<line x2="0" y1="-224" y2="-224" x1="64" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin NIO_SEL" />
|
||||
<line x2="0" y1="-160" y2="-160" x1="64" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin NIO_STB" />
|
||||
<line x2="0" y1="-96" y2="-96" x1="64" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin NDEV_SEL" />
|
||||
<line x2="0" y1="-32" y2="-32" x1="64" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin B10" />
|
||||
<line x2="384" y1="-416" y2="-416" x1="320" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin B9" />
|
||||
<line x2="384" y1="-288" y2="-288" x1="320" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin B8" />
|
||||
<line x2="384" y1="-160" y2="-160" x1="320" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin NOE" />
|
||||
<line x2="384" y1="-32" y2="-32" x1="320" />
|
||||
</graph>
|
||||
</symbol>
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 22:03:22 10/10/2017
|
||||
-- Design Name:
|
||||
-- Module Name: AddressDecoder - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity AddressDecoder is
|
||||
Port ( A : in std_logic_vector (11 downto 8);
|
||||
B : out std_logic_vector (10 downto 8); -- to EEPROM
|
||||
CLK : in std_logic;
|
||||
PHI0 : in std_logic;
|
||||
RNW : in std_logic;
|
||||
NDEV_SEL : in std_logic; -- $C0n0 - $C0nF, CPLD registers
|
||||
NIO_SEL : in std_logic; -- $Cs00 - $CsFF, EEPROM bank 0
|
||||
NIO_STB : in std_logic; -- $C800 - $CFFF, EEPROM banks 1 to 7
|
||||
NRESET : in std_logic;
|
||||
DATA_EN : out std_logic; -- to CPLD
|
||||
PGM_EN : in std_logic; -- from CPLD;
|
||||
NG : out std_logic; -- to bus transceiver
|
||||
NOE : out std_logic; -- to EEPROM
|
||||
NWE : out std_logic); -- to EEPROM
|
||||
end AddressDecoder;
|
||||
|
||||
architecture Behavioral of AddressDecoder is
|
||||
|
||||
signal cfxx : std_logic; -- $C800 - $CFFF disable
|
||||
signal ndev_sel_int : std_logic;
|
||||
signal nio_sel_int : std_logic;
|
||||
signal nio_stb_int : std_logic;
|
||||
signal ncs : std_logic; -- $C800 - $CFFE enabled
|
||||
signal a_int : std_logic_vector (11 downto 8);
|
||||
|
||||
begin
|
||||
|
||||
-- According to Apple IIgs Tech Note #68
|
||||
-- in order to prevent bus fights with video data,
|
||||
-- data from peripheral to CPU shall be valid on the bus
|
||||
-- only from the first rising edge of 7M when any select
|
||||
-- line is low (Phi0 high) to the falling edge of Phi0
|
||||
|
||||
-- $C0xx to $C7xx is mapped to EEPROM bank 0
|
||||
-- $C8xx to $CExx is mapped to banks 1 to 7
|
||||
|
||||
B(8) <= (a_int(11) and not a_int(8))
|
||||
or (a_int(11) and a_int(10) and a_int(9));
|
||||
B(9) <= (a_int(11) and not a_int(9) and a_int(8))
|
||||
or (a_int(11) and a_int(9) and not a_int(8))
|
||||
or (a_int(11) and a_int(10) and a_int(9));
|
||||
B(10) <= (a_int(11) and a_int(10))
|
||||
or (a_int(11) and a_int(9) and a_int(8));
|
||||
|
||||
DATA_EN <= RNW and not NDEV_SEL;
|
||||
NG <= (ndev_sel_int and nio_sel_int and nio_stb_int)
|
||||
or (ndev_sel_int and nio_sel_int and ncs)
|
||||
or not PHI0;
|
||||
NOE <= not RNW
|
||||
or (not NIO_SEL and not NIO_STB)
|
||||
or (NIO_SEL and NIO_STB)
|
||||
or (NIO_SEL and ncs);
|
||||
NWE <= RNW
|
||||
or (not NIO_SEL and not NIO_STB)
|
||||
or (NIO_SEL and NIO_STB)
|
||||
or (NIO_SEL and ncs)
|
||||
or not PGM_EN;
|
||||
|
||||
cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;
|
||||
|
||||
process(NRESET, nio_sel_int, cfxx)
|
||||
begin
|
||||
if (NRESET = '0' or cfxx = '1') then
|
||||
ncs <= '1';
|
||||
elsif falling_edge(nio_sel_int) then
|
||||
ncs <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(NRESET, CLK)
|
||||
begin
|
||||
if(NRESET = '0') then
|
||||
ndev_sel_int <= '1';
|
||||
nio_sel_int <= '1';
|
||||
nio_stb_int <= '1';
|
||||
a_int <= "0000";
|
||||
elsif rising_edge(CLK) then
|
||||
ndev_sel_int <= NDEV_SEL;
|
||||
nio_sel_int <= NIO_SEL;
|
||||
nio_stb_int <= NIO_STB;
|
||||
a_int <= A;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
|
|
@ -0,0 +1,343 @@
|
|||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 23:42:22 10/10/2017
|
||||
-- Design Name:
|
||||
-- Module Name: C:/Git/AppleIISd/VHDL/AddressDecoder_Test.vhd
|
||||
-- Project Name: AppleIISd
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: AddressDecoder
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY AddressDecoder_Test IS
|
||||
END AddressDecoder_Test;
|
||||
|
||||
ARCHITECTURE behavior OF AddressDecoder_Test IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT AddressDecoder
|
||||
PORT(
|
||||
A : IN std_logic_vector(11 downto 8);
|
||||
B : OUT std_logic_vector(10 downto 8);
|
||||
CLK : IN std_logic;
|
||||
PHI0 : IN std_logic;
|
||||
RNW : IN std_logic;
|
||||
NDEV_SEL : IN std_logic;
|
||||
NIO_SEL : IN std_logic;
|
||||
NIO_STB : IN std_logic;
|
||||
NRESET : IN std_logic;
|
||||
DATA_EN : OUT std_logic;
|
||||
PGM_EN : IN std_logic;
|
||||
NG : OUT std_logic;
|
||||
NOE : OUT std_logic;
|
||||
NWE : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal A : std_logic_vector(11 downto 8) := "0101";
|
||||
signal RNW : std_logic := '1';
|
||||
signal NDEV_SEL : std_logic := '1';
|
||||
signal NIO_SEL : std_logic := '1';
|
||||
signal NIO_STB : std_logic := '1';
|
||||
signal NRESET : std_logic := '1';
|
||||
signal CLK : std_logic := '0';
|
||||
signal PHI0 : std_logic := '1';
|
||||
signal PGM_EN : std_logic := '1';
|
||||
|
||||
--Outputs
|
||||
signal B : std_logic_vector(10 downto 8);
|
||||
signal DATA_EN : std_logic;
|
||||
signal NG : std_logic;
|
||||
signal NOE : std_logic;
|
||||
signal NWE : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 142 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: AddressDecoder PORT MAP (
|
||||
A => A,
|
||||
B => B,
|
||||
CLK => CLK,
|
||||
PHI0 => PHI0,
|
||||
RNW => RNW,
|
||||
NDEV_SEL => NDEV_SEL,
|
||||
NIO_SEL => NIO_SEL,
|
||||
NIO_STB => NIO_STB,
|
||||
NRESET => NRESET,
|
||||
DATA_EN => DATA_EN,
|
||||
PGM_EN => PGM_EN,
|
||||
NG => NG,
|
||||
NOE => NOE,
|
||||
NWE => NWE
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
PHI0_process :process(CLK)
|
||||
variable counter : integer range 0 to 7;
|
||||
begin
|
||||
if rising_edge(CLK) or falling_edge(CLK) then
|
||||
counter := counter + 1;
|
||||
if counter = 7 then
|
||||
PHI0 <= not PHI0;
|
||||
counter := 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state.
|
||||
wait for CLK_period * 10;
|
||||
NRESET <= '0';
|
||||
wait for CLK_period * 20;
|
||||
NRESET <= '1';
|
||||
wait for CLK_period * 10;
|
||||
|
||||
-- C0nX access
|
||||
-- NG must be '0"
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
A <= "0000"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
|
||||
-- C0nX access, write
|
||||
-- NG must be '0"
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '0';
|
||||
A <= "0000"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CnXX access, select
|
||||
-- NG must be '0'
|
||||
-- NOE must be '0'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
A <= "0100"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='0') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CnXX access, write, select
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '0'
|
||||
RNW <= '0';
|
||||
A <= "0100"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='0') report "NWE error" severity error;
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CnXX access, write, select, no PGM_EN
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '0';
|
||||
PGM_EN <= '0';
|
||||
A <= "0100"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx access, selected
|
||||
-- NG must be '0'
|
||||
-- NOE must be '0'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
PGM_EN <= '1';
|
||||
A <= "1000"; -- must become "001"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="001") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='0') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx write access, selected
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '0'
|
||||
RNW <= '0';
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='0') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C9xx access, selected
|
||||
-- NG must be '0'
|
||||
-- NOE must be '0'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
A <= "1001"; -- must become "010"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="010") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='0') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C9xx access write, selected
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '0'
|
||||
RNW <= '0';
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='0') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CPLD access
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
A <= "0101"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CFFF access
|
||||
-- NG must be '1'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
A <= "1111"; -- must become "111"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="111") report "Address error" severity error;
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx access, unselected
|
||||
-- NG must be '1'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
A <= "1000"; -- must become "001"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="001") report "Address error" severity error;
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx access write, unselected
|
||||
-- NG must be '1'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '0';
|
||||
A <= "1000"; -- must become "001"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="001") report "Address error" severity error;
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
Binary file not shown.
|
|
@ -1,41 +0,0 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "a10" LOC = "P38" ;
|
||||
NET "a8" LOC = "P36" ;
|
||||
NET "a9" LOC = "P37" ;
|
||||
NET "addr<0>" LOC = "P19" ;
|
||||
NET "addr<1>" LOC = "P18" ;
|
||||
NET "b10" LOC = "P22" ;
|
||||
NET "b8" LOC = "P26" ;
|
||||
NET "b9" LOC = "P27" ;
|
||||
NET "card" LOC = "P33" ;
|
||||
NET "data<0>" LOC = "P3" ;
|
||||
NET "data<1>" LOC = "P4" ;
|
||||
NET "data<2>" LOC = "P5" ;
|
||||
NET "data<3>" LOC = "P6" ;
|
||||
NET "data<4>" LOC = "P7" ;
|
||||
NET "data<5>" LOC = "P9" ;
|
||||
NET "data<6>" LOC = "P11" ;
|
||||
NET "data<7>" LOC = "P13" ;
|
||||
NET "extclk" LOC = "P43" ;
|
||||
NET "led" LOC = "P29" ;
|
||||
NET "ndev_sel" LOC = "P24" ;
|
||||
NET "ng" LOC = "P12" ;
|
||||
NET "nio_sel" LOC = "P14" ;
|
||||
NET "nio_stb" LOC = "P42" ;
|
||||
NET "noe" LOC = "P25" ;
|
||||
NET "nphi2" LOC = "P8" ;
|
||||
NET "nreset" LOC = "P20" ;
|
||||
NET "nrw" LOC = "P1" ;
|
||||
NET "spi_miso" LOC = "P40" ;
|
||||
NET "spi_mosi" LOC = "P35" ;
|
||||
NET "spi_Nsel" LOC = "P28" ;
|
||||
NET "spi_sclk" LOC = "P34" ;
|
||||
NET "wp" LOC = "P39" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -1,421 +1,172 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company: n/a
|
||||
-- Engineer: A. Fachat
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:37:11 05/07/2011
|
||||
-- Design Name: SPI65B
|
||||
-- Module Name: SPI6502B - Behavioral
|
||||
-- Project Name: CS/A NETUSB 2.0
|
||||
-- Target Devices: CS/A NETUSB 2.0
|
||||
-- Create Date: 20:44:25 10/09/2017
|
||||
-- Design Name:
|
||||
-- Module Name: IO - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description: An SPI interface for 6502-based computers (or compatible).
|
||||
-- modelled after the SPI65 interface by Daryl Rictor
|
||||
-- (see http://sbc.rictor.org/io/65spi.html )
|
||||
-- This implementation here, however, is a complete reimplementation
|
||||
-- as the ABEL language of the original implementation is not supported
|
||||
-- by ISE anymore.
|
||||
-- Also I added the interrupt input handling, replacing four of the
|
||||
-- original SPI select outputs with four interrupt inputs
|
||||
-- Also folded out the single MISO input into one input for each of the
|
||||
-- four supported devices, reducing external parts count again by one.
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination,
|
||||
-- to drive up SPI clock to half of input clock (and not one fourth only as before)
|
||||
-- unfortunately that costed one divisor bit to fit into the CPLD
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity AppleIISd is
|
||||
Port (
|
||||
data : inout STD_LOGIC_VECTOR (7 downto 0);
|
||||
nrw : in STD_LOGIC;
|
||||
nirq : out STD_LOGIC;
|
||||
nreset : in STD_LOGIC;
|
||||
addr : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
nphi2 : in STD_LOGIC;
|
||||
ndev_sel : in STD_LOGIC;
|
||||
extclk : in STD_LOGIC;
|
||||
spi_miso: in std_logic;
|
||||
spi_mosi : out STD_LOGIC;
|
||||
spi_sclk : out STD_LOGIC;
|
||||
spi_Nsel : out STD_LOGIC;
|
||||
wp : in STD_LOGIC;
|
||||
card : in STD_LOGIC;
|
||||
led : out STD_LOGIC;
|
||||
|
||||
a8 : in std_logic;
|
||||
a9 : in std_logic;
|
||||
a10 : in std_logic;
|
||||
nio_sel : in std_logic;
|
||||
nio_stb : in std_logic;
|
||||
b8 : out std_logic;
|
||||
b9 : out std_logic;
|
||||
b10 : out std_logic;
|
||||
noe : out std_logic;
|
||||
ng : out std_logic
|
||||
ADD_HIGH : in std_logic_vector(11 downto 8);
|
||||
ADD_LOW : in std_logic_vector(1 downto 0);
|
||||
B : out std_logic_vector(10 downto 8);
|
||||
CARD : in std_logic;
|
||||
DATA : inout std_logic_vector (7 downto 0);
|
||||
CLK : in std_logic;
|
||||
LED : out std_logic;
|
||||
NDEV_SEL : in std_logic;
|
||||
NG : out std_logic;
|
||||
NIO_SEL : in std_logic;
|
||||
NIO_STB : in std_logic;
|
||||
NOE : out std_logic;
|
||||
NWE : out std_logic;
|
||||
PHI0 : in std_logic;
|
||||
NRESET : in std_logic;
|
||||
RNW : in std_logic;
|
||||
MISO : in std_logic;
|
||||
MOSI : out std_logic;
|
||||
NSEL : out std_logic;
|
||||
SCLK : out std_logic;
|
||||
WP : in std_logic
|
||||
|
||||
-- synthesis translate_off
|
||||
;
|
||||
data_dbg : out std_logic_vector (7 downto 0);
|
||||
add_dbg : out std_logic_vector (1 downto 0);
|
||||
data_en_dbg : out std_logic
|
||||
-- synthesis translate_on
|
||||
|
||||
);
|
||||
|
||||
constant DIV_WIDTH : integer := 3;
|
||||
|
||||
end AppleIISd;
|
||||
|
||||
architecture Behavioral of AppleIISd is
|
||||
|
||||
-- interface signals
|
||||
signal selected: std_logic;
|
||||
signal reset: std_logic;
|
||||
signal int_out: std_logic;
|
||||
signal is_read: std_logic;
|
||||
signal int_din: std_logic_vector (7 downto 0);
|
||||
signal int_dout: std_logic_vector (7 downto 0);
|
||||
|
||||
signal int_mosi: std_logic;
|
||||
signal int_miso: std_logic;
|
||||
signal int_sclk: std_logic;
|
||||
|
||||
--------------------------
|
||||
-- internal state
|
||||
signal spidatain: std_logic_vector (7 downto 0);
|
||||
signal spidataout: std_logic_vector (7 downto 0);
|
||||
signal spiint: std_logic; -- spi interrupt state
|
||||
signal inited: std_logic; -- card initialized
|
||||
signal inited_set: std_logic;
|
||||
signal inited_reset: std_logic;
|
||||
signal inited_int: std_logic;
|
||||
signal inited_intff: std_logic;
|
||||
|
||||
-- spi register flags
|
||||
signal tc: std_logic; -- transmission complete; cleared on spi data read
|
||||
signal ier: std_logic; -- enable general SPI interrupts
|
||||
signal bsy: std_logic; -- SPI busy
|
||||
signal frx: std_logic; -- fast receive mode
|
||||
signal tmo: std_logic; -- tri-state mosi
|
||||
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
|
||||
signal cpol: std_logic; -- shift clock polarity; 0=rising edge, 1=falling edge
|
||||
signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge
|
||||
|
||||
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
|
||||
|
||||
signal slavesel: std_logic; -- slave select output (0=selected)
|
||||
signal slaveinten: std_logic; -- slave interrupt enable (1=enabled)
|
||||
|
||||
--------------------------
|
||||
-- helper signals
|
||||
|
||||
-- shift engine
|
||||
signal start_shifting: std_logic; -- shifting data
|
||||
signal shifting2: std_logic; -- shifting data
|
||||
signal shiftdone: std_logic; -- shifting data done
|
||||
signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
|
||||
signal data_in : std_logic_vector (7 downto 0);
|
||||
signal data_out : std_logic_vector (7 downto 0);
|
||||
signal addr_low_int : std_logic_vector (1 downto 0);
|
||||
|
||||
-- spi clock
|
||||
signal clksrc: std_logic; -- clock source (phi2 or extclk)
|
||||
-- TODO divcnt is not used at all??
|
||||
signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
|
||||
signal shiftclk : std_logic;
|
||||
signal data_en : std_logic;
|
||||
signal pgm_en : std_logic;
|
||||
|
||||
component SpiController is
|
||||
Port (
|
||||
data_in : in std_logic_vector (7 downto 0);
|
||||
data_out : out std_logic_vector (7 downto 0);
|
||||
is_read : in std_logic;
|
||||
nreset : in std_logic;
|
||||
addr : in std_logic_vector (1 downto 0);
|
||||
phi0 : in std_logic;
|
||||
ndev_sel : in std_logic;
|
||||
clk : in std_logic;
|
||||
miso: in std_logic;
|
||||
mosi : out std_logic;
|
||||
sclk : out std_logic;
|
||||
nsel : out std_logic;
|
||||
wp : in std_logic;
|
||||
card : in std_logic;
|
||||
led : out std_logic;
|
||||
pgm_en : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component AddressDecoder
|
||||
Port (
|
||||
A : in std_logic_vector (11 downto 8);
|
||||
B : out std_logic_vector (10 downto 8);
|
||||
CLK : in std_logic;
|
||||
PHI0 : in std_logic;
|
||||
RNW : in std_logic;
|
||||
NDEV_SEL : in std_logic;
|
||||
NIO_SEL : in std_logic;
|
||||
NIO_STB : in std_logic;
|
||||
NRESET : in std_logic;
|
||||
DATA_EN : out std_logic;
|
||||
PGM_EN : in std_logic;
|
||||
NG : out std_logic;
|
||||
NOE : out std_logic;
|
||||
NWE : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
component AddressDecoder
|
||||
port (
|
||||
A8 : in std_logic;
|
||||
A9 : in std_logic;
|
||||
A10 : in std_logic;
|
||||
CLK : in std_logic;
|
||||
NDEV_SEL : in std_logic;
|
||||
NIO_SEL : in std_logic;
|
||||
NIO_STB : in std_logic;
|
||||
B8 : out std_logic;
|
||||
B9 : out std_logic;
|
||||
B10 : out std_logic;
|
||||
NOE : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component SR_Latch
|
||||
port (
|
||||
S,R : in std_logic;
|
||||
Q, Q_n : inout std_logic;
|
||||
Reset : in std_logic;
|
||||
Clk : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
add_dec : AddressDecoder
|
||||
port map (
|
||||
A8 => a8,
|
||||
A9 => a9,
|
||||
A10 => a10,
|
||||
CLK => extclk,
|
||||
NDEV_SEL => ndev_sel,
|
||||
NIO_SEL => nio_sel,
|
||||
NIO_STB => nio_stb,
|
||||
B8 => b8,
|
||||
B9 => b9,
|
||||
B10 => b10,
|
||||
NOE => noe);
|
||||
spi: SpiController port map(
|
||||
data_in => data_in,
|
||||
data_out => data_out,
|
||||
is_read => RNW,
|
||||
nreset => NRESET,
|
||||
addr => addr_low_int,
|
||||
phi0 => PHI0,
|
||||
ndev_sel => NDEV_SEL,
|
||||
clk => CLK,
|
||||
miso => MISO,
|
||||
mosi => MOSI,
|
||||
sclk => SCLK,
|
||||
nsel => NSEL,
|
||||
wp => WP,
|
||||
card => CARD,
|
||||
led => LED,
|
||||
pgm_en => pgm_en
|
||||
);
|
||||
|
||||
sr_inited : SR_Latch
|
||||
port map (
|
||||
S => inited_set,
|
||||
R => inited_reset,
|
||||
Q => inited,
|
||||
Q_n => open,
|
||||
Reset => reset,
|
||||
Clk => extclk);
|
||||
addDec: AddressDecoder port map(
|
||||
A => ADD_HIGH,
|
||||
B => B,
|
||||
CLK => CLK,
|
||||
PHI0 => PHI0,
|
||||
RNW => RNW,
|
||||
NDEV_SEL => NDEV_SEL,
|
||||
NIO_SEL => NIO_SEL,
|
||||
NIO_STB => NIO_STB,
|
||||
NRESET => NRESET,
|
||||
DATA_EN => data_en,
|
||||
PGM_EN => pgm_en,
|
||||
NOE => NOE,
|
||||
NWE => NWE,
|
||||
NG => NG
|
||||
);
|
||||
|
||||
led <= not (bsy or not slavesel);
|
||||
ng <= ndev_sel and nio_sel and nio_stb;
|
||||
inited_reset <= card;
|
||||
bsy <= start_shifting or shifting2;
|
||||
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
|
||||
|
||||
process(start_shifting, shiftdone, shiftclk)
|
||||
-- synthesis translate_off
|
||||
data_dbg <= data_in;
|
||||
add_dbg <= addr_low_int;
|
||||
data_en_dbg <= data_en;
|
||||
-- synthesis translate_on
|
||||
|
||||
data_latch: process(CLK)
|
||||
begin
|
||||
if (rising_edge(shiftclk)) then
|
||||
if (shiftdone = '1') then
|
||||
shifting2 <= '0';
|
||||
else
|
||||
shifting2 <= start_shifting;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(shiftcnt, reset, shiftclk)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
shiftdone <= '0';
|
||||
elsif (rising_edge(shiftclk)) then
|
||||
if (shiftcnt = "1111") then
|
||||
shiftdone <= '1';
|
||||
else
|
||||
shiftdone <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(reset, shifting2, shiftcnt, shiftclk)
|
||||
begin
|
||||
if (reset='1') then
|
||||
shiftcnt <= (others => '0');
|
||||
elsif (rising_edge(shiftclk)) then
|
||||
if (shifting2 = '1') then
|
||||
-- count phase
|
||||
shiftcnt <= shiftcnt + 1;
|
||||
else
|
||||
shiftcnt <= (others => '0');
|
||||
if falling_edge(CLK) then
|
||||
addr_low_int <= ADD_LOW;
|
||||
if (NDEV_SEL = '0') then
|
||||
data_in <= DATA;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inproc: process(reset, shifting2, shiftcnt, shiftclk, spidatain, int_miso)
|
||||
begin
|
||||
if (reset='1') then
|
||||
spidatain <= (others => '0');
|
||||
elsif (rising_edge(shiftclk)) then
|
||||
if (shifting2 = '1' and shiftcnt(0) = '1') then
|
||||
-- shift in to input register
|
||||
spidatain (7 downto 1) <= spidatain (6 downto 0);
|
||||
spidatain (0) <= int_miso;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
outproc: process(reset, shifting2, spidataout, cpol, cpha, shiftcnt, shiftclk)
|
||||
begin
|
||||
if (reset='1') then
|
||||
int_mosi <= '1';
|
||||
int_sclk <= cpol;
|
||||
else
|
||||
-- clock is sync'd
|
||||
if (rising_edge(shiftclk)) then
|
||||
if (shifting2='0' or shiftdone = '1') then
|
||||
int_mosi <= '1';
|
||||
int_sclk <= cpol;
|
||||
else
|
||||
-- output data directly from output register
|
||||
case shiftcnt(3 downto 1) is
|
||||
when "000" => int_mosi <= spidataout(7);
|
||||
when "001" => int_mosi <= spidataout(6);
|
||||
when "010" => int_mosi <= spidataout(5);
|
||||
when "011" => int_mosi <= spidataout(4);
|
||||
when "100" => int_mosi <= spidataout(3);
|
||||
when "101" => int_mosi <= spidataout(2);
|
||||
when "110" => int_mosi <= spidataout(1);
|
||||
when "111" => int_mosi <= spidataout(0);
|
||||
when others => int_mosi <= '1';
|
||||
end case;
|
||||
int_sclk <= cpol xor cpha xor shiftcnt(0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- shift operation enable
|
||||
shiften: process(reset, selected, nrw, addr, frx, shiftdone)
|
||||
begin
|
||||
-- start shifting
|
||||
if (reset='1' or shiftdone='1') then
|
||||
start_shifting <= '0';
|
||||
elsif (falling_edge(selected) and addr="00" and (frx='1' or nrw='0')) then
|
||||
-- access to register 00, either write (nrw=0) or fast receive bit set (frx)
|
||||
-- then both types of access (write but also read)
|
||||
start_shifting <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------
|
||||
-- spiclk - spi clock generation
|
||||
-- spiclk is still 2 times the freq. than sclk
|
||||
clksrc <= nphi2 when (ece = '0') else extclk;
|
||||
|
||||
-- is a pulse signal to allow for divisor==0
|
||||
--shiftclk <= clksrc when divcnt = "000000" else '0';
|
||||
shiftclk <= clksrc when bsy = '1' else '0';
|
||||
|
||||
clkgen: process(reset, divisor, clksrc)
|
||||
begin
|
||||
if (reset='1') then
|
||||
divcnt <= divisor;
|
||||
elsif (falling_edge(clksrc)) then
|
||||
if (shiftclk = '1') then
|
||||
divcnt <= divisor;
|
||||
else
|
||||
divcnt <= divcnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------
|
||||
-- interrupt generation
|
||||
int_out <= spiint and slaveinten;
|
||||
|
||||
--------------------------
|
||||
-- interface section
|
||||
-- inputs
|
||||
reset <= not (nreset);
|
||||
selected <= not(ndev_sel);
|
||||
is_read <= selected and nphi2 and nrw;
|
||||
int_din <= data;
|
||||
|
||||
int_miso <= (spi_miso and not slavesel);
|
||||
|
||||
-- outputs
|
||||
data <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
|
||||
nirq <= '0' when (int_out='1') else 'Z'; -- wired-or
|
||||
spi_sclk <= int_sclk;
|
||||
spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state
|
||||
spi_Nsel <= slavesel;
|
||||
|
||||
tc_proc: process (selected, shiftdone)
|
||||
begin
|
||||
if (shiftdone = '1') then
|
||||
tc <= '1';
|
||||
elsif (falling_edge(selected) and addr="00") then
|
||||
tc <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
spiint <= tc and ier;
|
||||
|
||||
|
||||
-- inited_set pulse
|
||||
process(extclk, reset)
|
||||
begin
|
||||
if(reset = '1') then
|
||||
inited_set <= '0';
|
||||
elsif falling_edge(extclk) then
|
||||
inited_intff <= inited_int; -- one cycle delayed version
|
||||
inited_set <= '0'; -- default value
|
||||
if (inited_int = '1') and (inited_intff = '0') then
|
||||
inited_set <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------
|
||||
-- cpu register section
|
||||
-- cpu read
|
||||
cpu_read: process (is_read, addr,
|
||||
spidatain, tc, ier, bsy, frx, tmo, ece, cpol, cpha, divisor,
|
||||
slavesel, slaveinten, wp, card, inited)
|
||||
begin
|
||||
if (is_read = '1') then
|
||||
case addr is
|
||||
when "00" => -- read SPI data in
|
||||
int_dout <= spidatain;
|
||||
when "01" => -- read status register
|
||||
int_dout(0) <= cpha;
|
||||
int_dout(1) <= cpol;
|
||||
int_dout(2) <= ece;
|
||||
int_dout(3) <= tmo;
|
||||
int_dout(4) <= frx;
|
||||
int_dout(5) <= bsy;
|
||||
int_dout(6) <= ier;
|
||||
int_dout(7) <= tc;
|
||||
when "10" => -- read sclk divisor
|
||||
int_dout(DIV_WIDTH-1 downto 0) <= divisor;
|
||||
int_dout(7 downto 3) <= (others => '0');
|
||||
when "11" => -- read slave select / slave interrupt state
|
||||
int_dout(0) <= slavesel;
|
||||
int_dout(3 downto 1) <= (others => '0');
|
||||
int_dout(4) <= slaveinten;
|
||||
int_dout(5) <= wp;
|
||||
int_dout(6) <= card;
|
||||
int_dout(7) <= inited;
|
||||
when others =>
|
||||
int_dout <= (others => '0');
|
||||
end case;
|
||||
else
|
||||
int_dout <= (others => '0');
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- cpu write
|
||||
cpu_write: process(reset, selected, nrw, addr, int_din)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
cpha <= '0';
|
||||
cpol <= '0';
|
||||
ece <= '0';
|
||||
tmo <= '0';
|
||||
frx <= '0';
|
||||
ier <= '0';
|
||||
slavesel <= '1';
|
||||
slaveinten <= '0';
|
||||
divisor <= (others => '0');
|
||||
spidataout <= (others => '1');
|
||||
elsif (falling_edge(selected) and nrw = '0') then
|
||||
case addr is
|
||||
when "00" => -- write SPI data out (see other process above)
|
||||
spidataout <= int_din;
|
||||
when "01" => -- write status register
|
||||
cpha <= int_din(0);
|
||||
cpol <= int_din(1);
|
||||
ece <= int_din(2);
|
||||
tmo <= int_din(3);
|
||||
frx <= int_din(4);
|
||||
-- no bit 5
|
||||
ier <= int_din(6);
|
||||
-- no bit 7;
|
||||
when "10" => -- write divisor
|
||||
divisor <= int_din(DIV_WIDTH-1 downto 0);
|
||||
when "11" => -- write slave select / slave interrupt enable
|
||||
slavesel <= int_din(0);
|
||||
slaveinten <= int_din(4);
|
||||
inited_int <= int_din(7);
|
||||
when others =>
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADD_HIGH<10>" LOC = "P38" ;
|
||||
NET "ADD_HIGH<11>" LOC = "P44" ;
|
||||
NET "ADD_HIGH<8>" LOC = "P36" ;
|
||||
NET "ADD_HIGH<9>" LOC = "P37" ;
|
||||
NET "ADD_LOW<0>" LOC = "P19" ;
|
||||
NET "ADD_LOW<1>" LOC = "P18" ;
|
||||
NET "B<10>" LOC = "P22" ;
|
||||
NET "B<8>" LOC = "P26" ;
|
||||
NET "B<9>" LOC = "P27" ;
|
||||
NET "CARD" LOC = "P33" ;
|
||||
NET "CLK" LOC = "P43" ;
|
||||
NET "DATA<0>" LOC = "P3" ;
|
||||
NET "DATA<1>" LOC = "P4" ;
|
||||
NET "DATA<2>" LOC = "P5" | BUFG = DATA_GATE ;
|
||||
NET "DATA<3>" LOC = "P6" | BUFG = DATA_GATE ;
|
||||
NET "DATA<4>" LOC = "P7" | BUFG = DATA_GATE ;
|
||||
NET "DATA<5>" LOC = "P9" ;
|
||||
NET "DATA<6>" LOC = "P11" ;
|
||||
NET "DATA<7>" LOC = "P13" ;
|
||||
NET "LED" LOC = "P29" ;
|
||||
NET "MISO" LOC = "P40" ;
|
||||
NET "MOSI" LOC = "P35" ;
|
||||
NET "NDEV_SEL" LOC = "P24" ;
|
||||
NET "NG" LOC = "P12" ;
|
||||
NET "NIO_SEL" LOC = "P14" ;
|
||||
NET "NIO_STB" LOC = "P42" ;
|
||||
NET "NOE" LOC = "P25" ;
|
||||
NET "NRESET" LOC = "P20" ;
|
||||
NET "NSEL" LOC = "P28" ;
|
||||
NET "NWE" LOC = "P2" ;
|
||||
NET "PHI0" LOC = "P8" ;
|
||||
NET "RNW" LOC = "P1" ;
|
||||
NET "SCLK" LOC = "P34" ;
|
||||
NET "WP" LOC = "P39" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -15,20 +15,28 @@
|
|||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
|
||||
<file xil_pn:name="AppleIISd_PC44.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="sr_latch.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
|
|
@ -59,12 +67,14 @@
|
|||
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -85,10 +95,13 @@
|
|||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
|
@ -118,19 +131,20 @@
|
|||
<property xil_pn:name="Output File Name" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="AppleIISd_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="AppleIISd_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
|
@ -138,17 +152,18 @@
|
|||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="50 us" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
|
|
@ -170,6 +185,7 @@
|
|||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -182,7 +198,7 @@
|
|||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
|
@ -0,0 +1,357 @@
|
|||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 00:42:59 10/10/2017
|
||||
-- Design Name:
|
||||
-- Module Name: U:/AppleIISd/VHDL/IO_Test.vhd
|
||||
-- Project Name: AppleIISd
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: IO
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY AppleIISd_Test IS
|
||||
END AppleIISd_Test;
|
||||
|
||||
ARCHITECTURE behavior OF AppleIISd_Test IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT AppleIISd
|
||||
PORT(
|
||||
ADD_HIGH : IN std_logic_vector(11 downto 8);
|
||||
ADD_LOW : IN std_logic_vector(1 downto 0);
|
||||
B : OUT std_logic_vector(10 downto 8);
|
||||
CARD : IN std_logic;
|
||||
DATA : INOUT std_logic_vector(7 downto 0);
|
||||
CLK : IN std_logic;
|
||||
LED : OUT std_logic;
|
||||
NDEV_SEL : IN std_logic;
|
||||
NG : OUT std_logic;
|
||||
NIO_SEL : IN std_logic;
|
||||
NIO_STB : IN std_logic;
|
||||
NOE : OUT std_logic;
|
||||
PHI0 : IN std_logic;
|
||||
NRESET : IN std_logic;
|
||||
RNW : IN std_logic;
|
||||
MISO : IN std_logic;
|
||||
MOSI : OUT std_logic;
|
||||
NSEL : OUT std_logic;
|
||||
SCLK : OUT std_logic;
|
||||
WP : IN std_logic;
|
||||
|
||||
data_dbg : out std_logic_vector (7 downto 0);
|
||||
add_dbg : out std_logic_vector (1 downto 0);
|
||||
data_en_dbg : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal ADD_HIGH : std_logic_vector(11 downto 8) := (others => '0');
|
||||
signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U');
|
||||
signal CARD : std_logic := '0';
|
||||
signal CLK : std_logic := '0';
|
||||
signal NDEV_SEL : std_logic := '1';
|
||||
signal NIO_SEL : std_logic := '1';
|
||||
signal NIO_STB : std_logic := '1';
|
||||
signal PHI0 : std_logic := '1';
|
||||
signal NRESET : std_logic := '1';
|
||||
signal RNW : std_logic := '1';
|
||||
signal MISO : std_logic := '1';
|
||||
signal WP : std_logic := '0';
|
||||
|
||||
--BiDirs
|
||||
signal DATA : std_logic_vector(7 downto 0) := (others => 'Z');
|
||||
|
||||
--Outputs
|
||||
signal B : std_logic_vector(10 downto 8);
|
||||
signal LED : std_logic;
|
||||
signal NG : std_logic;
|
||||
signal NOE : std_logic;
|
||||
signal MOSI : std_logic;
|
||||
signal NSEL : std_logic;
|
||||
signal SCLK : std_logic;
|
||||
|
||||
signal data_dbg : std_logic_vector (7 downto 0);
|
||||
signal add_dbg : std_logic_vector (1 downto 0);
|
||||
signal data_en_dbg : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 142 ns;
|
||||
|
||||
-- Bus timings
|
||||
-- worst case
|
||||
constant ADD_valid : time := 300 ns; -- II+
|
||||
constant DATA_valid : time := 200 ns; -- II+
|
||||
constant ADD_hold : time := 15 ns; -- IIgs
|
||||
--best case
|
||||
--constant ADD_valid : time := 100 ns; -- IIgs
|
||||
--constant DATA_valid : time := 30 ns; -- IIgs
|
||||
--constant ADD_hold : time := 15 ns; -- IIgs
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: AppleIISd PORT MAP (
|
||||
ADD_HIGH => ADD_HIGH,
|
||||
ADD_LOW => ADD_LOW,
|
||||
B => B,
|
||||
CARD => CARD,
|
||||
DATA => DATA,
|
||||
CLK => CLK,
|
||||
LED => LED,
|
||||
NDEV_SEL => NDEV_SEL,
|
||||
NG => NG,
|
||||
NIO_SEL => NIO_SEL,
|
||||
NIO_STB => NIO_STB,
|
||||
NOE => NOE,
|
||||
PHI0 => PHI0,
|
||||
NRESET => NRESET,
|
||||
RNW => RNW,
|
||||
MISO => MISO,
|
||||
MOSI => MOSI,
|
||||
NSEL => NSEL,
|
||||
SCLK => SCLK,
|
||||
WP => WP,
|
||||
|
||||
data_dbg => data_dbg,
|
||||
add_dbg => add_dbg,
|
||||
data_en_dbg => data_en_dbg
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
PHI0_process :process(CLK)
|
||||
variable counter : integer range 0 to 7;
|
||||
begin
|
||||
if rising_edge(CLK) or falling_edge(CLK) then
|
||||
counter := counter + 1;
|
||||
if counter = 7 then
|
||||
PHI0 <= not PHI0;
|
||||
counter := 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state.
|
||||
wait for CLK_period * 10;
|
||||
NRESET <= '0';
|
||||
wait for CLK_period * 20;
|
||||
NRESET <= '1';
|
||||
wait for CLK_period * 10;
|
||||
DATA <= (others => 'Z');
|
||||
ADD_LOW <= (others => 'U');
|
||||
|
||||
-- read reg 3
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '1');
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait for ADD_hold;
|
||||
ADD_LOW <= (others => 'U');
|
||||
|
||||
-- select card
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '1');
|
||||
RNW <= '0';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait for DATA_valid;
|
||||
DATA <= X"00";
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait for ADD_hold;
|
||||
--wait for CLK_period;
|
||||
ADD_LOW <= (others => 'U');
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'Z');
|
||||
|
||||
-- send data
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '0');
|
||||
RNW <= '0';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait for DATA_valid;
|
||||
DATA <= X"AA";
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait for ADD_hold;
|
||||
--wait for CLK_period;
|
||||
ADD_LOW <= (others => 'U');
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'Z');
|
||||
wait for 20 us;
|
||||
|
||||
-- deselect card
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '1');
|
||||
RNW <= '0';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait for DATA_valid;
|
||||
DATA <= X"01";
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait for ADD_hold;
|
||||
--wait for CLK_period;
|
||||
ADD_LOW <= (others => 'U');
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'Z');
|
||||
|
||||
-- write ece
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= "01";
|
||||
RNW <= '0';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait for DATA_valid;
|
||||
DATA <= x"04";
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait for ADD_hold;
|
||||
--wait for CLK_period;
|
||||
ADD_LOW <= (others => 'U');
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'Z');
|
||||
|
||||
-- send data
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '0');
|
||||
RNW <= '0';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait for DATA_valid;
|
||||
DATA <= X"AA";
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait for ADD_hold;
|
||||
--wait for CLK_period;
|
||||
ADD_LOW <= (others => 'U');
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'Z');
|
||||
|
||||
-- read eprom low
|
||||
wait for 3 us;
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '0');
|
||||
ADD_HIGH <= "0100"; -- must become "111"
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_SEL <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait until falling_edge(PHI0);
|
||||
NIO_SEL <= '1';
|
||||
wait for ADD_hold;
|
||||
ADD_LOW <= (others => 'U');
|
||||
ADD_HIGH <= (others => 'U');
|
||||
|
||||
-- read eprom high, selected
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '0');
|
||||
ADD_HIGH <= "1001"; -- must become "001"
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait until falling_edge(PHI0);
|
||||
NIO_STB <= '1';
|
||||
wait for ADD_hold;
|
||||
ADD_LOW <= (others => 'U');
|
||||
ADD_HIGH <= (others => 'U');
|
||||
|
||||
-- read $CFFF
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '1');
|
||||
ADD_HIGH <= "1111";
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait until falling_edge(PHI0);
|
||||
NIO_STB <= '1';
|
||||
wait for ADD_hold;
|
||||
ADD_LOW <= (others => 'U');
|
||||
ADD_HIGH <= (others => 'U');
|
||||
|
||||
-- read eprom high, deselected
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '0');
|
||||
ADD_HIGH <= "1101"; -- must become "101"
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait until falling_edge(PHI0);
|
||||
NIO_STB <= '1';
|
||||
wait for ADD_hold;
|
||||
ADD_LOW <= (others => 'U');
|
||||
ADD_HIGH <= (others => 'U');
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADD_HIGH<10>" LOC = "P32" ;
|
||||
NET "ADD_HIGH<11>" LOC = "P38" ;
|
||||
NET "ADD_HIGH<8>" LOC = "P30" ;
|
||||
NET "ADD_HIGH<9>" LOC = "P31" ;
|
||||
NET "ADD_LOW<0>" LOC = "P13" ;
|
||||
NET "ADD_LOW<1>" LOC = "P12" ;
|
||||
NET "B<10>" LOC = "P16" ;
|
||||
NET "B<8>" LOC = "P20" ;
|
||||
NET "B<9>" LOC = "P21" ;
|
||||
NET "CARD" LOC = "P27" ;
|
||||
NET "CLK" LOC = "P37" ;
|
||||
NET "DATA<0>" LOC = "P41" ;
|
||||
NET "DATA<1>" LOC = "P42" ;
|
||||
NET "DATA<2>" LOC = "P43" ;
|
||||
NET "DATA<3>" LOC = "P44" ;
|
||||
NET "DATA<4>" LOC = "P1" ;
|
||||
NET "DATA<5>" LOC = "P3" ;
|
||||
NET "DATA<6>" LOC = "P5" ;
|
||||
NET "DATA<7>" LOC = "P7" ;
|
||||
NET "LED" LOC = "P23" ;
|
||||
NET "MISO" LOC = "P34" ;
|
||||
NET "MOSI" LOC = "P29" ;
|
||||
NET "NDEV_SEL" LOC = "P18" ;
|
||||
NET "NG" LOC = "P6" ;
|
||||
NET "NIO_SEL" LOC = "P8" ;
|
||||
NET "NIO_STB" LOC = "P36" ;
|
||||
NET "NOE" LOC = "P19" ;
|
||||
NET "NRESET" LOC = "P14" ;
|
||||
NET "NSEL" LOC = "P22" ;
|
||||
NET "NWE" LOC = "P40" ;
|
||||
NET "PHI0" LOC = "P2" ;
|
||||
NET "RNW" LOC = "P39" ;
|
||||
NET "SCLK" LOC = "P28" ;
|
||||
NET "WP" LOC = "P33" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd_VQ44.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="_" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AppleIISd|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="AppleIISd.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AppleIISd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="AppleIISd_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="50 us" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="iMPACT Project File" xil_pn:value="AppleIISd_VQ44.ipf" xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-09-03T14:20:38" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="FD3A1F2B88484D658A65860211499755" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -0,0 +1,255 @@
|
|||
----------------------------------------------------------------------------------
|
||||
--
|
||||
-- Spi controller for 6502 systems
|
||||
-- based on a design by A. Fachat
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
|
||||
entity SpiController is
|
||||
Port (
|
||||
data_in : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
data_out : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
is_read : in STD_LOGIC;
|
||||
nreset : in STD_LOGIC;
|
||||
addr : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
phi0 : in STD_LOGIC;
|
||||
ndev_sel : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
miso: in std_logic;
|
||||
mosi : out STD_LOGIC;
|
||||
sclk : out STD_LOGIC;
|
||||
nsel : out STD_LOGIC;
|
||||
wp : in STD_LOGIC;
|
||||
card : in STD_LOGIC;
|
||||
pgm_en : out STD_LOGIC;
|
||||
led : out STD_LOGIC
|
||||
);
|
||||
end SpiController;
|
||||
|
||||
architecture Behavioral of SpiController is
|
||||
|
||||
--------------------------
|
||||
-- internal state
|
||||
signal spidatain: std_logic_vector (7 downto 0);
|
||||
signal spidataout: std_logic_vector (7 downto 0);
|
||||
signal sdhc: std_logic; -- is SDHC card
|
||||
signal inited: std_logic; -- card initialized
|
||||
signal pgmen: std_logic; -- enable EEPROM programming
|
||||
|
||||
-- spi register flags
|
||||
signal tc: std_logic; -- transmission complete; cleared on spi data read
|
||||
signal bsy: std_logic; -- SPI busy
|
||||
signal frx: std_logic; -- fast receive mode
|
||||
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
|
||||
|
||||
signal slavesel: std_logic := '1'; -- slave select output (0=selected)
|
||||
signal int_miso: std_logic;
|
||||
--------------------------
|
||||
-- helper signals
|
||||
|
||||
-- shift engine
|
||||
signal start_shifting: std_logic := '0'; -- shifting data
|
||||
signal shifting2: std_logic := '0'; -- shifting data
|
||||
signal shiftdone: std_logic; -- shifting data done
|
||||
signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
|
||||
|
||||
-- spi clock
|
||||
signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
|
||||
signal shiftclk : std_logic;
|
||||
|
||||
begin
|
||||
led <= not (bsy or not slavesel);
|
||||
bsy <= start_shifting or shifting2;
|
||||
|
||||
process(start_shifting, shiftdone, shiftclk)
|
||||
begin
|
||||
if (rising_edge(shiftclk)) then
|
||||
if (shiftdone = '1') then
|
||||
shifting2 <= '0';
|
||||
else
|
||||
shifting2 <= start_shifting;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(shiftcnt, nreset, shiftclk)
|
||||
begin
|
||||
if (nreset = '0') then
|
||||
shiftdone <= '0';
|
||||
elsif (rising_edge(shiftclk)) then
|
||||
if (shiftcnt = "1111") then
|
||||
shiftdone <= '1';
|
||||
else
|
||||
shiftdone <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(nreset, shifting2, shiftcnt, shiftclk)
|
||||
begin
|
||||
if (nreset = '0') then
|
||||
shiftcnt <= (others => '0');
|
||||
elsif (rising_edge(shiftclk)) then
|
||||
if (shifting2 = '1') then
|
||||
-- count phase
|
||||
shiftcnt <= shiftcnt + 1;
|
||||
else
|
||||
shiftcnt <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inproc: process(nreset, shifting2, shiftcnt, shiftclk, spidatain, miso)
|
||||
begin
|
||||
if (nreset = '0') then
|
||||
spidatain <= (others => '0');
|
||||
elsif (rising_edge(shiftclk)) then
|
||||
if (shifting2 = '1' and shiftcnt(0) = '1') then
|
||||
-- shift in to input register
|
||||
spidatain (7 downto 1) <= spidatain (6 downto 0);
|
||||
spidatain (0) <= int_miso;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
outproc: process(nreset, shifting2, spidataout, shiftcnt, shiftclk)
|
||||
begin
|
||||
if (nreset = '0') then
|
||||
mosi <= '1';
|
||||
sclk <= '1';
|
||||
else
|
||||
-- clock is sync'd
|
||||
if (rising_edge(shiftclk)) then
|
||||
if (shifting2='0' or shiftdone = '1') then
|
||||
mosi <= '1';
|
||||
sclk <= '1';
|
||||
else
|
||||
-- output data directly from output register
|
||||
case shiftcnt(3 downto 1) is
|
||||
when "000" => mosi <= spidataout(7);
|
||||
when "001" => mosi <= spidataout(6);
|
||||
when "010" => mosi <= spidataout(5);
|
||||
when "011" => mosi <= spidataout(4);
|
||||
when "100" => mosi <= spidataout(3);
|
||||
when "101" => mosi <= spidataout(2);
|
||||
when "110" => mosi <= spidataout(1);
|
||||
when "111" => mosi <= spidataout(0);
|
||||
when others => mosi <= '1';
|
||||
end case;
|
||||
sclk <= shiftcnt(0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- shift operation enable
|
||||
shiften: process(nreset, ndev_sel, is_read, addr, frx, shiftdone)
|
||||
begin
|
||||
-- start shifting
|
||||
if (nreset = '0' or shiftdone = '1') then
|
||||
start_shifting <= '0';
|
||||
elsif (rising_edge(ndev_sel) and addr="00" and (frx='1' or is_read='0')) then
|
||||
-- access to register 00, either write (is_read=0) or fast receive bit set (frx)
|
||||
-- then both types of access (write but also read)
|
||||
start_shifting <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------
|
||||
-- spiclk - spi clock generation
|
||||
-- spiclk is still 2 times the freq. than sclk
|
||||
clksrc <= phi0 when (ece = '0') else clk;
|
||||
|
||||
-- is a pulse signal to allow for divisor==0
|
||||
shiftclk <= clksrc when bsy = '1' else '0';
|
||||
|
||||
--------------------------
|
||||
-- interface section
|
||||
-- inputs
|
||||
int_miso <= (miso and not slavesel);
|
||||
|
||||
-- outputs
|
||||
nsel <= slavesel;
|
||||
pgm_en <= pgmen;
|
||||
|
||||
tc_proc: process (ndev_sel, shiftdone)
|
||||
begin
|
||||
if (shiftdone = '1') then
|
||||
tc <= '1';
|
||||
elsif (rising_edge(ndev_sel) and addr="00") then
|
||||
tc <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------
|
||||
-- cpu register section
|
||||
-- cpu read
|
||||
cpu_read: process(addr, spidatain, tc, bsy, frx, pgmen,
|
||||
ece, slavesel, wp, card, sdhc, inited)
|
||||
begin
|
||||
case addr is
|
||||
when "00" => -- read SPI data in
|
||||
data_out <= spidatain;
|
||||
when "01" => -- read status register
|
||||
data_out(0) <= pgmen;
|
||||
data_out(1) <= '0';
|
||||
data_out(2) <= ece;
|
||||
data_out(3) <= '0';
|
||||
data_out(4) <= frx;
|
||||
data_out(5) <= bsy;
|
||||
data_out(6) <= '0';
|
||||
data_out(7) <= tc;
|
||||
-- no register 2
|
||||
when "11" => -- read slave select / slave interrupt state
|
||||
data_out(0) <= slavesel;
|
||||
data_out(3 downto 1) <= (others => '0');
|
||||
data_out(4) <= sdhc;
|
||||
data_out(5) <= wp;
|
||||
data_out(6) <= card;
|
||||
data_out(7) <= inited;
|
||||
when others =>
|
||||
data_out <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- cpu write
|
||||
cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card)
|
||||
begin
|
||||
if (nreset = '0') then
|
||||
ece <= '0';
|
||||
frx <= '0';
|
||||
slavesel <= '1';
|
||||
spidataout <= (others => '1');
|
||||
sdhc <= '0';
|
||||
inited <= '0';
|
||||
pgmen <= '0';
|
||||
elsif (card = '1') then
|
||||
sdhc <= '0';
|
||||
inited <= '0';
|
||||
elsif (rising_edge(ndev_sel) and is_read = '0') then
|
||||
case addr is
|
||||
when "00" => -- write SPI data out (see other process above)
|
||||
spidataout <= data_in;
|
||||
when "01" => -- write status register
|
||||
pgmen <= data_in(0);
|
||||
ece <= data_in(2);
|
||||
frx <= data_in(4);
|
||||
-- no bit 5 - 7
|
||||
-- no register 2
|
||||
when "11" => -- write slave select
|
||||
slavesel <= data_in(0);
|
||||
-- no bit 1 - 3
|
||||
sdhc <= data_in(4);
|
||||
-- no bit 5 - 6
|
||||
inited <= data_in(7);
|
||||
when others =>
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "a10" LOC = "P38" ;
|
||||
NET "a8" LOC = "P36" ;
|
||||
NET "a9" LOC = "P37" ;
|
||||
NET "addr<0>" LOC = "P19" ;
|
||||
NET "addr<1>" LOC = "P18" ;
|
||||
NET "b10" LOC = "P22" ;
|
||||
NET "b8" LOC = "P26" ;
|
||||
NET "b9" LOC = "P27" ;
|
||||
NET "card" LOC = "P33" ;
|
||||
NET "data<0>" LOC = "P3" ;
|
||||
NET "data<1>" LOC = "P5" ;
|
||||
NET "data<2>" LOC = "P4" ;
|
||||
NET "data<3>" LOC = "P6" ;
|
||||
NET "data<4>" LOC = "P7" ;
|
||||
NET "data<5>" LOC = "P9" ;
|
||||
NET "data<6>" LOC = "P11" ;
|
||||
NET "data<7>" LOC = "P13" ;
|
||||
NET "extclk" LOC = "P42" ;
|
||||
NET "led" LOC = "P29" ;
|
||||
NET "ndev_sel" LOC = "P24" ;
|
||||
NET "ng" LOC = "P12" ;
|
||||
NET "nio_sel" LOC = "P14" ;
|
||||
NET "nio_stb" LOC = "P40" ;
|
||||
NET "nirq" LOC = "P2" ;
|
||||
NET "noe" LOC = "P25" ;
|
||||
NET "nphi2" LOC = "P44" ;
|
||||
NET "nreset" LOC = "P20" ;
|
||||
NET "nrw" LOC = "P1" ;
|
||||
NET "spi_miso" LOC = "P43" ;
|
||||
NET "spi_mosi" LOC = "P35" ;
|
||||
NET "spi_Nsel" LOC = "P28" ;
|
||||
NET "spi_sclk" LOC = "P34" ;
|
||||
NET "wp" LOC = "P39" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -1 +0,0 @@
|
|||
sch2hdl,-intstyle,ise,-family,xc9500xl,-verilog,U:/AppleIISd/VHDL/AddressDecoder.vf,-w,U:/AppleIISd/VHDL/AddressDecoder.sch
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 22:26:04 09/09/2017
|
||||
-- Design Name:
|
||||
-- Module Name: sr_latch - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
|
||||
entity SR_Latch is
|
||||
Port ( S,R : in STD_LOGIC;
|
||||
Q : inout STD_LOGIC;
|
||||
Q_n : inout STD_LOGIC;
|
||||
Reset : in STD_LOGIC;
|
||||
Clk : in STD_LOGIC);
|
||||
end SR_Latch;
|
||||
|
||||
architecture SR_Latch_arch of SR_Latch is
|
||||
begin
|
||||
process (S,R,Q,Q_n, Reset, Clk)
|
||||
begin
|
||||
if(rising_edge(Clk)) then
|
||||
if(Reset = '1') then
|
||||
Q <= '0';
|
||||
Q_n <= '1';
|
||||
else
|
||||
Q <= R NOR Q_n;
|
||||
Q_n <= S NOR Q;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end SR_Latch_arch;
|
||||
Loading…
Reference in New Issue