Update GW4205AManual.pdf

This reverts commit 5db5490f52.

.gitignore

@@ -6,6 +6,7 @@
 *.bak
 *.bck
 *.kicad_pcb-bak
+*.sch-bak
 *~
 _autosave-*
 *.tmp
@@ -13,6 +14,7 @@ _autosave-*
 *-save.pro
 *-save.kicad_pcb
 fp-info-cache
+GR8RAM-backups/*
 
 # Netlist files (exported from Eeschema)
 *.net
@@ -21,8 +23,12 @@ fp-info-cache
 *.dsn
 *.ses
 
-# Exported BOM files
-*.xml
-*.csv
-
 *.DS_Store
+*.kicad_prl
+cpld/db/*
+cpld/incremental_db/*
+cpld/GR8RAM.qws
+~GR8RAM.kicad_sch.lck
+*.kicad_prl
+/Hardware/LCMXO2/GR8RAM-backups
+*.lck

Documentation/Flash Map

@@ -0,0 +1,38 @@
+GR8RAM flash memory map
+
+....		-----------------------------
+7FFF		|							|
+....		|     firmware 3 (8 kB)     |
+6000		|							|
+			-----------------------------
+5FFF		|							|
+....		|     firmware 2 (8 kB)     |
+4000		|							|
+			-----------------------------
+3FFF		|							|
+....		|     firmware 1 (8 kB)     |
+2000		|							|
+			-----------------------------
+1FFF		|							|
+....		|     firmware 0 (8 kB)     |
+0000		|							|
+			-----------------------------
+
+Firmware area map (N=$0000, $2000, $4000, $6000)
+			-----------------------------
+N+1FFF		|							|
+....		|    IOSTRB bank 1 (2 kB)   |
+N+1800		|							|
+			-----------------------------
+N+17FF		|							|
+....		|    IOSEL bank 1 (2 kB)    |
+N+1000		|							|
+			-----------------------------
+N+0FFF		|							|
+....		|    IOSTRB bank 0 (2 kB)   |
+N+0800		|							|
+			-----------------------------
+N+07FF		|							|
+....		|    IOSEL bank 0 (2 kB)    |
+N+0000		|							|
+			-----------------------------

Documentation/Initialization Sequence

@@ -0,0 +1,13 @@
+Init sequence
+
+LS				SDRAM					Flash					IS
+-------------------------------------------------------------------
+$0000-$1FCE		Nothing					Nothing					0
+$1FCF			Init: Precharge			Nothing					1
+$1FD0-$1FFA		Init: AREF Pause		SPI Select				4
+$1FFB			Init: AREF Pause		Dual Read (0x3B)		5
+$1FFC			Init: AREF Pause		A[23:16] (0)			5
+$1FFD			Init: AREF Pause		A[15:08] (FW in 14:13)	5
+$1FFE			Init: AREF Pause		A[07:00] (0)			5
+$1FFF			Init: AREF Pause		Dummy					5
+$2000-$3FFF		Init: Write ROM			Shift MISO into WRD		6

Documentation/RAM Map

@@ -0,0 +1,32 @@
+GR8RAM/LibraryCard Slinky RAM memory map
+			-----------------------------
+1 FF FFFF	|							|
+. .. ....	|    reserved (16,376 kB)   |
+1 00 2000	|							|
+			-----------------------------
+1 00 1FFF	|							|
+. .. ....	|      firmware (8 kB)      |
+1 00 0000	|							|
+			-----------------------------
+0 FF FFFF	|							|
+. .. ....	|     Slinky RAM (16 MB)    |
+0 00 0000	|							|
+			-----------------------------
+
+			-----------------------------
+1 00 1FFF	|							|
+....		|    IOSTRB bank 1 (2 kB)   |
+1 00 1800	|							|
+			-----------------------------
+1 00 17FF	|							|
+....		|    IOSEL bank 1 (2 kB)    |
+1 00 1000	|							|
+			-----------------------------
+1 00 0FFF	|							|
+....		|    IOSTRB bank 0 (2 kB)   |
+1 00 0800	|							|
+			-----------------------------
+1 00 07FF	|							|
+....		|    IOSEL bank 0 (2 kB)    |
+1 00 0000	|							|
+			-----------------------------

GR8RAM

@@ -0,0 +1,21 @@
+Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
+C10 C1 C7 C2 C3 C4 C11 ,7,"10u","stdpads:C_0805","~","C15850"
+C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 C5 ,27,"2u2","stdpads:C_0603","~","C23630"
+FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
+H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
+H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
+J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
+J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
+J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
+R22 R31 ,2,"33","stdpads:R_0603","~","C23140"
+R28 R29 ,2,"22k","stdpads:R_0603","~","C31850"
+RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501"
+RN5 ,1,"4x10k","stdpads:R4_0402","~","C25725"
+SW1 ,1,"FW","stdpads:SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm","~","C319052"
+U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041"
+U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088"
+U16 U14 ,2,"74LVC1G125GW","stdpads:SOT-353","","C12519"
+U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246"
+U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C164122"
+U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
+U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446"

GR8RAM-cache.lib

@@ -1,38 +1,38 @@
 EESchema-LIBRARY Version 2.4
 #encoding utf-8
 #
-# Connector_AVR-JTAG-10
+# Connector_Generic_Conn_02x05_Odd_Even
 #
-DEF Connector_AVR-JTAG-10 J 0 40 Y Y 1 F N
-F0 "J" 175 500 50 H V L CNN
-F1 "Connector_AVR-JTAG-10" 100 -500 50 H V L CNN
-F2 "" -150 150 50 V I C CNN
-F3 "" -1275 -550 50 H I C CNN
+DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
+F0 "J" 50 300 50 H V C CNN
+F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
 $FPLIST
- IDC?Header*2x05*
- Pin?Header*2x05*
+ Connector*:*_2x??_*
 $ENDFPLIST
 DRAW
-S -105 450 -95 420 0 1 0 N
-S -5 -420 5 -450 0 1 0 N
-S -5 450 5 420 0 1 0 N
-S 350 -195 320 -205 0 1 0 N
-S 350 -95 320 -105 0 1 0 N
-S 350 5 320 -5 0 1 0 N
-S 350 105 320 95 0 1 0 N
-S 350 205 320 195 0 1 0 N
-S 350 305 320 295 0 1 0 N
-S 350 450 -350 -450 0 1 10 f
-X TCK 1 500 100 150 L 50 50 1 1 P
-X GND 10 0 -600 150 U 50 50 1 1 W
-X GND 2 0 -600 150 U 50 50 1 1 P N
-X TDO 3 500 -100 150 L 50 50 1 1 P
-X VREF 4 -100 600 150 D 50 50 1 1 P
-X TMS 5 500 0 150 L 50 50 1 1 P
-X ~SRST 6 500 300 150 L 50 50 1 1 P
-X VCC 7 0 600 150 D 50 50 1 1 W
-X ~TRST 8 500 200 150 L 50 50 1 1 P
-X TDI 9 500 -200 150 L 50 50 1 1 P
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 205 0 195 1 1 6 N
+S -50 250 150 -250 1 1 10 f
+S 150 -195 100 -205 1 1 6 N
+S 150 -95 100 -105 1 1 6 N
+S 150 5 100 -5 1 1 6 N
+S 150 105 100 95 1 1 6 N
+S 150 205 100 195 1 1 6 N
+X Pin_1 1 -200 200 150 R 50 50 1 1 P
+X Pin_10 10 300 -200 150 L 50 50 1 1 P
+X Pin_2 2 300 200 150 L 50 50 1 1 P
+X Pin_3 3 -200 100 150 R 50 50 1 1 P
+X Pin_4 4 300 100 150 L 50 50 1 1 P
+X Pin_5 5 -200 0 150 R 50 50 1 1 P
+X Pin_6 6 300 0 150 L 50 50 1 1 P
+X Pin_7 7 -200 -100 150 R 50 50 1 1 P
+X Pin_8 8 300 -100 150 L 50 50 1 1 P
+X Pin_9 9 -200 -200 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
@@ -151,26 +151,6 @@ X Pin_9 9 -200 400 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# Device_CP_Small
-#
-DEF Device_CP_Small C 0 10 N N 1 F N
-F0 "C" 10 70 50 H V L CNN
-F1 "Device_CP_Small" 10 -80 50 H V L CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- CP_*
-$ENDFPLIST
-DRAW
-S -60 -12 60 -27 0 1 0 F
-S -60 27 60 12 0 1 0 N
-P 2 0 1 0 -50 60 -30 60 N
-P 2 0 1 0 -40 50 -40 70 N
-X ~ 1 0 100 73 D 50 50 1 1 P
-X ~ 2 0 -100 73 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
 # Device_C_Small
 #
 DEF Device_C_Small C 0 10 N N 1 F N
@@ -189,6 +169,354 @@ X ~ 2 0 -100 80 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# Device_R_Pack04
+#
+DEF Device_R_Pack04 RN 0 0 Y N 1 F N
+F0 "RN" -300 0 50 V V C CNN
+F1 "Device_R_Pack04" 200 0 50 V V C CNN
+F2 "" 275 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP*
+ SOIC*
+$ENDFPLIST
+DRAW
+S -250 -95 150 95 0 1 10 f
+S -225 75 -175 -75 0 1 10 N
+S -125 75 -75 -75 0 1 10 N
+S -25 75 25 -75 0 1 10 N
+S 75 75 125 -75 0 1 10 N
+P 2 0 1 0 -200 -100 -200 -75 N
+P 2 0 1 0 -200 75 -200 100 N
+P 2 0 1 0 -100 -100 -100 -75 N
+P 2 0 1 0 -100 75 -100 100 N
+P 2 0 1 0 0 -100 0 -75 N
+P 2 0 1 0 0 75 0 100 N
+P 2 0 1 0 100 -100 100 -75 N
+P 2 0 1 0 100 75 100 100 N
+X R1.1 1 -200 -200 100 U 50 50 1 1 P
+X R2.1 2 -100 -200 100 U 50 50 1 1 P
+X R3.1 3 0 -200 100 U 50 50 1 1 P
+X R4.1 4 100 -200 100 U 50 50 1 1 P
+X R4.2 5 100 200 100 D 50 50 1 1 P
+X R3.2 6 0 200 100 D 50 50 1 1 P
+X R2.2 7 -100 200 100 D 50 50 1 1 P
+X R1.2 8 -200 200 100 D 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_R_Small
+#
+DEF Device_R_Small R 0 10 N N 1 F N
+F0 "R" 30 20 50 H V L CNN
+F1 "Device_R_Small" 30 -40 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -30 70 30 -70 0 1 8 N
+X ~ 1 0 100 30 D 50 50 1 1 P
+X ~ 2 0 -100 30 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GW_Logic_741G125GW
+#
+DEF GW_Logic_741G125GW U 0 40 Y Y 1 F N
+F0 "U" 0 250 50 H V C CNN
+F1 "GW_Logic_741G125GW" 0 -250 50 H V C CNN
+F2 "stdpads:SOT-353" 0 -300 50 H I C TNN
+F3 "" 0 -200 60 H I C CNN
+DRAW
+S 200 -200 -200 200 0 1 10 f
+X ~OE~ 1 -400 100 200 R 50 50 1 1 I
+X A 2 -400 0 200 R 50 50 1 1 I
+X GND 3 -400 -100 200 R 50 50 1 1 W
+X Y 4 400 -100 200 L 50 50 1 1 O
+X Vcc 5 400 100 200 L 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# GW_Logic_74245
+#
+DEF GW_Logic_74245 U 0 40 Y Y 1 F N
+F0 "U" 0 600 50 H V C CNN
+F1 "GW_Logic_74245" 0 -600 50 H V C CNN
+F2 "" 0 -650 50 H I C TNN
+F3 "" 0 100 60 H I C CNN
+DRAW
+S -200 550 200 -550 0 1 10 f
+X AtoB 1 -400 450 200 R 50 50 1 1 I
+X GND 10 -400 -450 200 R 50 50 1 1 W
+X B7 11 400 -450 200 L 50 50 1 1 B
+X B6 12 400 -350 200 L 50 50 1 1 B
+X B5 13 400 -250 200 L 50 50 1 1 B
+X B4 14 400 -150 200 L 50 50 1 1 B
+X B3 15 400 -50 200 L 50 50 1 1 B
+X B2 16 400 50 200 L 50 50 1 1 B
+X B1 17 400 150 200 L 50 50 1 1 B
+X B0 18 400 250 200 L 50 50 1 1 B
+X ~OE~ 19 400 350 200 L 50 50 1 1 I
+X A0 2 -400 350 200 R 50 50 1 1 B
+X Vcc 20 400 450 200 L 50 50 1 1 W
+X A1 3 -400 250 200 R 50 50 1 1 B
+X A2 4 -400 150 200 R 50 50 1 1 B
+X A3 5 -400 50 200 R 50 50 1 1 B
+X A4 6 -400 -50 200 R 50 50 1 1 B
+X A5 7 -400 -150 200 R 50 50 1 1 B
+X A6 8 -400 -250 200 R 50 50 1 1 B
+X A7 9 -400 -350 200 R 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# GW_Logic_Oscillator_4P
+#
+DEF GW_Logic_Oscillator_4P U 0 40 Y Y 1 F N
+F0 "U" 0 250 50 H V C CNN
+F1 "GW_Logic_Oscillator_4P" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -250 200 250 -100 0 1 10 f
+X EN 1 -350 100 100 R 50 50 1 1 I
+X GND 2 -350 0 100 R 50 50 1 1 W
+X Output 3 350 0 100 L 50 50 1 1 O
+X Vdd 4 350 100 100 L 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# GW_PLD_EPM240T100
+#
+DEF GW_PLD_EPM240T100 U 0 40 Y Y 1 F N
+F0 "U" 0 50 50 H V C CNN
+F1 "GW_PLD_EPM240T100" 0 -50 50 H V C CNN
+F2 "stdpads:TQFP-100_14x14mm_P0.5mm" 0 -100 20 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ *QFP*P0.5mm*
+$ENDFPLIST
+DRAW
+S -800 2200 800 -2200 1 1 10 f
+X IO2_1 1 1000 2100 200 L 50 50 1 1 B
+X GNDIO 10 -200 -2400 200 U 50 50 1 1 W
+X IO2_100 100 1000 -2000 200 L 50 50 1 1 B
+X GNDINT 11 -400 -2400 200 U 50 50 1 1 W
+X IO1_12/GCLK0 12 -1000 1400 200 R 50 50 1 1 B C
+X VCCINT 13 -400 2400 200 D 50 50 1 1 W
+X IO1_14/GCLK1 14 -1000 1300 200 R 50 50 1 1 B C
+X IO1_15 15 -1000 1200 200 R 50 50 1 1 B
+X IO1_16 16 -1000 1100 200 R 50 50 1 1 B
+X IO1_17 17 -1000 1000 200 R 50 50 1 1 B
+X IO1_18 18 -1000 900 200 R 50 50 1 1 B
+X IO1_19 19 -1000 800 200 R 50 50 1 1 B
+X IO1_2 2 -1000 2100 200 R 50 50 1 1 B
+X IO1_20 20 -1000 700 200 R 50 50 1 1 B
+X IO1_21 21 -1000 600 200 R 50 50 1 1 B
+X TMS 22 -1000 -1700 200 R 50 50 1 1 I
+X TDI 23 -1000 -1800 200 R 50 50 1 1 I
+X TCK 24 -1000 -1900 200 R 50 50 1 1 I C
+X TDO 25 -1000 -2000 200 R 50 50 1 1 O
+X IO1_26 26 -1000 500 200 R 50 50 1 1 B
+X IO1_27 27 -1000 400 200 R 50 50 1 1 B
+X IO1_28 28 -1000 300 200 R 50 50 1 1 B
+X IO1_29 29 -1000 200 200 R 50 50 1 1 B
+X IO1_3 3 -1000 2000 200 R 50 50 1 1 B
+X IO1_30 30 -1000 100 200 R 50 50 1 1 B
+X VCCIO1 31 -100 2400 200 D 50 50 1 1 W
+X GNDIO 32 -100 -2400 200 U 50 50 1 1 W
+X IO1_33 33 -1000 0 200 R 50 50 1 1 B
+X IO1_34 34 -1000 -100 200 R 50 50 1 1 B
+X IO1_35 35 -1000 -200 200 R 50 50 1 1 B
+X IO1_36 36 -1000 -300 200 R 50 50 1 1 B
+X IO1_37 37 -1000 -400 200 R 50 50 1 1 B
+X IO1_38 38 -1000 -500 200 R 50 50 1 1 B
+X IO1_39 39 -1000 -600 200 R 50 50 1 1 B
+X IO1_4 4 -1000 1900 200 R 50 50 1 1 B
+X IO1_40 40 -1000 -700 200 R 50 50 1 1 B
+X IO1_41 41 -1000 -800 200 R 50 50 1 1 B
+X IO1_42 42 -1000 -900 200 R 50 50 1 1 B
+X IO1_43/DEV_OE 43 -1000 -1000 200 R 50 50 1 1 B
+X IO1_44/DEV_CLRn 44 -1000 -1100 200 R 50 50 1 1 B
+X VCCIO1 45 0 2400 200 D 50 50 1 1 W
+X GNDIO 46 0 -2400 200 U 50 50 1 1 W
+X IO1_47 47 -1000 -1200 200 R 50 50 1 1 B
+X IO1_48 48 -1000 -1300 200 R 50 50 1 1 B
+X IO1_49 49 -1000 -1400 200 R 50 50 1 1 B
+X IO1_5 5 -1000 1800 200 R 50 50 1 1 B
+X IO1_50 50 -1000 -1500 200 R 50 50 1 1 B
+X IO1_51 51 -1000 -1600 200 R 50 50 1 1 B
+X IO2_52 52 1000 2000 200 L 50 50 1 1 B
+X IO2_53 53 1000 1900 200 L 50 50 1 1 B
+X IO2_54 54 1000 1800 200 L 50 50 1 1 B
+X IO2_55 55 1000 1700 200 L 50 50 1 1 B
+X IO2_56 56 1000 1600 200 L 50 50 1 1 B
+X IO2_57 57 1000 1500 200 L 50 50 1 1 B
+X IO2_58 58 1000 1400 200 L 50 50 1 1 B
+X VCCIO2 59 100 2400 200 D 50 50 1 1 W
+X IO1_6 6 -1000 1700 200 R 50 50 1 1 B
+X GNDIO 60 100 -2400 200 U 50 50 1 1 W
+X IO2_61 61 1000 1300 200 L 50 50 1 1 B
+X IO2_62/GCLK2 62 1000 1200 200 L 50 50 1 1 B C
+X VCCINT 63 -300 2400 200 D 50 50 1 1 W
+X IO2_64/GCLK3 64 1000 1100 200 L 50 50 1 1 B C
+X GNDINT 65 -300 -2400 200 U 50 50 1 1 W
+X IO2_66 66 1000 1000 200 L 50 50 1 1 B
+X IO2_67 67 1000 900 200 L 50 50 1 1 B
+X IO2_68 68 1000 800 200 L 50 50 1 1 B
+X IO2_69 69 1000 700 200 L 50 50 1 1 B
+X IO1_7 7 -1000 1600 200 R 50 50 1 1 B
+X IO2_70 70 1000 600 200 L 50 50 1 1 B
+X IO2_71 71 1000 500 200 L 50 50 1 1 B
+X IO2_72 72 1000 400 200 L 50 50 1 1 B
+X IO2_73 73 1000 300 200 L 50 50 1 1 B
+X IO2_74 74 1000 200 200 L 50 50 1 1 B
+X IO2_75 75 1000 100 200 L 50 50 1 1 B
+X IO2_76 76 1000 0 200 L 50 50 1 1 B
+X IO2_77 77 1000 -100 200 L 50 50 1 1 B
+X IO2_78 78 1000 -200 200 L 50 50 1 1 B
+X GNDIO 79 200 -2400 200 U 50 50 1 1 W
+X IO1_8 8 -1000 1500 200 R 50 50 1 1 B
+X VCCIO2 80 200 2400 200 D 50 50 1 1 W
+X IO2_81 81 1000 -300 200 L 50 50 1 1 B
+X IO2_82 82 1000 -400 200 L 50 50 1 1 B
+X IO2_83 83 1000 -500 200 L 50 50 1 1 B
+X IO2_84 84 1000 -600 200 L 50 50 1 1 B
+X IO2_85 85 1000 -700 200 L 50 50 1 1 B
+X IO2_86 86 1000 -800 200 L 50 50 1 1 B
+X IO2_87 87 1000 -900 200 L 50 50 1 1 B
+X IO2_88 88 1000 -1000 200 L 50 50 1 1 B
+X IO2_89 89 1000 -1100 200 L 50 50 1 1 B
+X VCCIO1 9 -200 2400 200 D 50 50 1 1 W
+X IO2_90 90 1000 -1200 200 L 50 50 1 1 B
+X IO2_91 91 1000 -1300 200 L 50 50 1 1 B
+X IO2_92 92 1000 -1400 200 L 50 50 1 1 B
+X GNDIO 93 300 -2400 200 U 50 50 1 1 W
+X VCCIO2 94 300 2400 200 D 50 50 1 1 W
+X IO2_95 95 1000 -1500 200 L 50 50 1 1 B
+X IO2_96 96 1000 -1600 200 L 50 50 1 1 B
+X IO2_97 97 1000 -1700 200 L 50 50 1 1 B
+X IO2_98 98 1000 -1800 200 L 50 50 1 1 B
+X IO2_99 99 1000 -1900 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# GW_Power_AP2125
+#
+DEF GW_Power_AP2125 U 0 40 Y Y 1 F N
+F0 "U" 0 250 50 H V C CNN
+F1 "GW_Power_AP2125" 0 -250 50 H V C CNN
+F2 "stdpads:SOT-23" 0 -300 50 H I C TNN
+F3 "" 0 -100 60 H I C CNN
+DRAW
+S -250 200 250 -200 0 1 10 f
+X GND 1 -450 -100 200 R 50 50 1 1 W
+X Vout 2 450 100 200 L 50 50 1 1 w
+X Vin 3 -450 100 200 R 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# GW_RAM_SDRAM-16Mx16-TSOP2-54
+#
+DEF GW_RAM_SDRAM-16Mx16-TSOP2-54 U 0 40 Y Y 1 F N
+F0 "U" 0 1150 50 H V C CNN
+F1 "GW_RAM_SDRAM-16Mx16-TSOP2-54" 0 0 50 V V C CNN
+F2 "stdpads:Winbond_TSOPII-54" 0 -1650 50 H I C CIN
+F3 "" 0 -250 50 H I C CNN
+DRAW
+S -300 1100 300 -1400 0 1 10 f
+X VDD 1 -500 1000 200 R 50 50 1 1 W
+X DQ5 10 500 500 200 L 50 50 1 1 B
+X DQ6 11 500 400 200 L 50 50 1 1 B
+X VSSQ 12 -500 -1300 200 R 50 50 1 1 W N
+X DQ7 13 500 300 200 L 50 50 1 1 B
+X VDD 14 -500 1000 200 R 50 50 1 1 W N
+X DQML 15 500 -600 200 L 50 50 1 1 I
+X ~WE~ 16 500 -1100 200 L 50 50 1 1 I
+X ~CAS~ 17 500 -1200 200 L 50 50 1 1 I
+X ~RAS~ 18 500 -1300 200 L 50 50 1 1 I
+X ~CS~ 19 500 -1000 200 L 50 50 1 1 I
+X DQ0 2 500 1000 200 L 50 50 1 1 B
+X BA0 20 -500 -600 200 R 50 50 1 1 I
+X BA1 21 -500 -700 200 R 50 50 1 1 I
+X A10 22 -500 -300 200 R 50 50 1 1 I
+X A0 23 -500 700 200 R 50 50 1 1 I
+X A1 24 -500 600 200 R 50 50 1 1 I
+X A2 25 -500 500 200 R 50 50 1 1 I
+X A3 26 -500 400 200 R 50 50 1 1 I
+X VDD 27 -500 1000 200 R 50 50 1 1 W N
+X VSS 28 -500 -1200 200 R 50 50 1 1 W
+X A4 29 -500 300 200 R 50 50 1 1 I
+X VDDQ 3 -500 900 200 R 50 50 1 1 W
+X A5 30 -500 200 200 R 50 50 1 1 I
+X A6 31 -500 100 200 R 50 50 1 1 I
+X A7 32 -500 0 200 R 50 50 1 1 I
+X A8 33 -500 -100 200 R 50 50 1 1 I
+X A9 34 -500 -200 200 R 50 50 1 1 I
+X A11 35 -500 -400 200 R 50 50 1 1 I
+X A12 36 -500 -500 200 R 50 50 1 1 I
+X CKE 37 -500 -900 200 R 50 50 1 1 I
+X CLK 38 -500 -1000 200 R 50 50 1 1 I
+X DQMH 39 500 -700 200 L 50 50 1 1 I
+X DQ1 4 500 900 200 L 50 50 1 1 B
+X VSS 41 -500 -1200 200 R 50 50 1 1 W N
+X DQ8 42 500 200 200 L 50 50 1 1 B
+X VDDQ 43 -500 900 200 R 50 50 1 1 W N
+X DQ9 44 500 100 200 L 50 50 1 1 B
+X DQ10 45 500 0 200 L 50 50 1 1 B
+X VSSQ 46 -500 -1300 200 R 50 50 1 1 W N
+X DQ11 47 500 -100 200 L 50 50 1 1 B
+X DQ12 48 500 -200 200 L 50 50 1 1 B
+X VDDQ 49 -500 900 200 R 50 50 1 1 W N
+X DQ2 5 500 800 200 L 50 50 1 1 B
+X DQ13 50 500 -300 200 L 50 50 1 1 B
+X DQ14 51 500 -400 200 L 50 50 1 1 B
+X VSSQ 52 -500 -1300 200 R 50 50 1 1 W N
+X DQ15 53 500 -500 200 L 50 50 1 1 B
+X VSS 54 -500 -1200 200 R 50 50 1 1 W N
+X VSSQ 6 -500 -1300 200 R 50 50 1 1 W
+X DQ3 7 500 700 200 L 50 50 1 1 B
+X DQ4 8 500 600 200 L 50 50 1 1 B
+X VDDQ 9 -500 900 200 R 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# GW_RAM_SPIFlash-SO-8
+#
+DEF GW_RAM_SPIFlash-SO-8 U 0 40 Y Y 1 F N
+F0 "U" 0 350 50 H V C CNN
+F1 "GW_RAM_SPIFlash-SO-8" 0 -250 50 H V C CNN
+F2 "stdpads:Hybrid_SPIFlash_SOIC-8_SOIC-16" 0 -300 50 H I C TNN
+F3 "" 0 0 50 H I C TNN
+DRAW
+S -350 300 350 -200 0 1 10 f
+X ~CS~ 1 -550 200 200 R 50 50 1 1 I
+X DO/IO1 2 -550 100 200 R 50 50 1 1 B
+X ~WP~/IO2 3 -550 0 200 R 50 50 1 1 B
+X GND 4 -550 -100 200 R 50 50 1 1 W
+X DI/IO0 5 550 -100 200 L 50 50 1 1 B
+X CLK 6 550 0 200 L 50 50 1 1 I
+X ~HLD~/IO3 7 550 100 200 L 50 50 1 1 B
+X Vcc 8 550 200 200 L 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# Mechanical_Fiducial
+#
+DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
+F0 "FID" 0 200 50 H V C CNN
+F1 "Mechanical_Fiducial" 0 125 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Fiducial*
+$ENDFPLIST
+DRAW
+C 0 0 50 0 1 20 f
+ENDDRAW
+ENDDEF
+#
 # Mechanical_MountingHole
 #
 DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
@@ -220,6 +548,31 @@ X 1 1 0 -100 100 U 50 50 1 1 I
 ENDDRAW
 ENDDEF
 #
+# Switch_SW_DIP_x02
+#
+DEF Switch_SW_DIP_x02 SW 0 0 Y N 1 F N
+F0 "SW" 0 250 50 H V C CNN
+F1 "Switch_SW_DIP_x02" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ SW?DIP?x2*
+$ENDFPLIST
+DRAW
+C -80 0 20 0 0 0 N
+C -80 100 20 0 0 0 N
+C 80 0 20 0 0 0 N
+C 80 100 20 0 0 0 N
+S -150 200 150 -100 0 1 10 f
+P 2 0 0 0 -60 5 93 46 N
+P 2 0 0 0 -60 105 93 146 N
+X ~ 1 -300 100 200 R 50 50 1 1 P
+X ~ 2 -300 0 200 R 50 50 1 1 P
+X ~ 3 300 0 200 L 50 50 1 1 P
+X ~ 4 300 100 200 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # power_+12V
 #
 DEF power_+12V #PWR 0 0 Y Y 1 F P
@@ -235,6 +588,22 @@ X +12V 1 0 0 0 U 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
+# power_+3V3
+#
+DEF power_+3V3 #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+3V3" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS +3.3V
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
 # power_+5V
 #
 DEF power_+5V #PWR 0 0 Y Y 1 F P
@@ -289,194 +658,4 @@ X GND 1 0 0 0 D 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
-# stdparts_39F040
-#
-DEF stdparts_39F040 U 0 20 Y Y 1 F N
-F0 "U" 0 1050 50 H V C CNN
-F1 "stdparts_39F040" 0 0 50 V V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-S -300 1000 300 -1000 0 1 10 f
-X GND 16 500 -900 200 L 50 50 0 0 W
-X VCC 32 500 900 200 L 50 50 0 0 W
-X A18 1 -500 -900 200 R 50 50 1 1 I
-X A2 10 -500 700 200 R 50 50 1 1 I
-X A1 11 -500 800 200 R 50 50 1 1 I
-X A0 12 -500 900 200 R 50 50 1 1 I
-X D0 13 500 700 200 L 50 50 1 1 T
-X D1 14 500 600 200 L 50 50 1 1 T
-X D2 15 500 500 200 L 50 50 1 1 T
-X D3 17 500 400 200 L 50 50 1 1 T
-X D4 18 500 300 200 L 50 50 1 1 T
-X D5 19 500 200 200 L 50 50 1 1 T
-X A16 2 -500 -700 200 R 50 50 1 1 I
-X D6 20 500 100 200 L 50 50 1 1 T
-X D7 21 500 0 200 L 50 50 1 1 T
-X ~CS~ 22 500 -400 200 L 50 50 1 1 I L
-X A10 23 -500 -100 200 R 50 50 1 1 I
-X ~OE~ 24 500 -600 200 L 50 50 1 1 I L
-X A11 25 -500 -200 200 R 50 50 1 1 I
-X A9 26 -500 0 200 R 50 50 1 1 I
-X A8 27 -500 100 200 R 50 50 1 1 I
-X A13 28 -500 -400 200 R 50 50 1 1 I
-X A14 29 -500 -500 200 R 50 50 1 1 I
-X A15 3 -500 -600 200 R 50 50 1 1 I
-X A17 30 -500 -800 200 R 50 50 1 1 I
-X ~WE~ 31 500 -500 200 L 50 50 1 1 I L
-X A12 4 -500 -300 200 R 50 50 1 1 I
-X A7 5 -500 200 200 R 50 50 1 1 I
-X A6 6 -500 300 200 R 50 50 1 1 I
-X A5 7 -500 400 200 R 50 50 1 1 I
-X A4 8 -500 500 200 R 50 50 1 1 I
-X A3 9 -500 600 200 R 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# stdparts_AS4C4M4
-#
-DEF stdparts_AS4C4M4 U 0 20 Y Y 1 F N
-F0 "U" 0 800 50 H V C CNN
-F1 "stdparts_AS4C4M4" 0 0 50 V V C CNN
-F2 "Package_SO:TSOP-II-44_10.16x18.41mm_P0.8mm" 0 -900 50 H I C CNN
-F3 "" 0 -450 50 H I C CNN
-$FPLIST
- SOJ*10.16x23.49mm*P1.27mm*
-$ENDFPLIST
-DRAW
-S -300 750 300 -850 0 1 10 f
-X A4 1 -400 250 100 R 50 50 1 1 I
-X I/O2 11 400 250 100 L 50 50 1 1 B
-X VDD 11 400 650 100 L 50 50 1 1 W
-X GND 12 -400 -750 100 R 50 50 1 1 P N
-X I/O3 12 400 150 100 L 50 50 1 1 B
-X NC 15 -400 -550 100 R 50 50 1 1 N N
-X NC 16 -400 -550 100 R 50 50 1 1 N N
-X ~WE~ 17 400 -650 100 L 50 50 1 1 I
-X A3 2 -400 350 100 R 50 50 1 1 I
-X I/O4 25 400 50 100 L 50 50 1 1 B
-X I/O5 26 400 -50 100 L 50 50 1 1 B
-X A10 27 -400 -350 100 R 50 50 1 1 I
-X A9 28 -400 -250 100 R 50 50 1 1 I
-X I/O6 29 400 -150 100 L 50 50 1 1 B
-X NC 29 -400 -550 100 R 50 50 1 1 N N
-X A2 3 -400 450 100 R 50 50 1 1 I
-X I/O7 30 400 -250 100 L 50 50 1 1 B
-X NC 30 -400 -550 100 R 50 50 1 1 N N
-X VDD 33 400 650 100 L 50 50 1 1 W N
-X GND 34 -400 -750 100 R 50 50 1 1 W
-X NC 37 -400 -550 100 R 50 50 1 1 N N
-X NC 38 -400 -550 100 R 50 50 1 1 N N
-X A8 39 -400 -150 100 R 50 50 1 1 I
-X A1 4 -400 550 100 R 50 50 1 1 I
-X ~RAS~ 40 400 -550 100 L 50 50 1 1 I
-X ~OE~ 41 400 -750 100 L 50 50 1 1 I
-X A7 42 -400 -50 100 R 50 50 1 1 I
-X A6 43 -400 50 100 R 50 50 1 1 I
-X A5 44 -400 150 100 R 50 50 1 1 I
-X A0 5 -400 650 100 R 50 50 1 1 I
-X ~CAS~ 6 400 -450 100 L 50 50 1 1 I
-X I/O0 7 400 450 100 L 50 50 1 1 B
-X NC 7 -400 -550 100 R 50 50 1 1 N N
-X I/O1 8 400 350 100 L 50 50 1 1 B
-X NC 8 -400 -550 100 R 50 50 1 1 N N
-ENDDRAW
-ENDDEF
-#
-# stdparts_EPM7128SL84
-#
-DEF stdparts_EPM7128SL84 U 0 40 Y Y 1 F N
-F0 "U" 0 50 50 H V C CNN
-F1 "stdparts_EPM7128SL84" 0 -50 50 H V C CNN
-F2 "" -150 200 50 H I C CNN
-F3 "" -150 200 50 H I C CNN
-DRAW
-S -600 -1950 600 1850 0 1 10 f
-X ~GClr~ 1 750 900 150 L 50 50 1 1 I
-X I/O 10 750 1600 150 L 50 50 1 1 B
-X I/O 11 750 1700 150 L 50 50 1 1 B
-X I/O 12 -750 1700 150 R 50 50 1 1 B
-X VccIO 13 -350 2000 150 D 50 50 1 1 W
-X TDI 14 -750 1600 150 R 50 50 1 1 B
-X I/O 15 -750 1500 150 R 50 50 1 1 B
-X I/O 16 -750 1400 150 R 50 50 1 1 B
-X I/O 17 -750 1300 150 R 50 50 1 1 B
-X I/O 18 -750 1200 150 R 50 50 1 1 B
-X GND 19 -350 -2100 150 U 50 50 1 1 W
-X OE2/GClk2 2 750 1000 150 L 50 50 1 1 I
-X I/O 20 -750 1100 150 R 50 50 1 1 B
-X I/O 21 -750 1000 150 R 50 50 1 1 B
-X I/O 22 -750 900 150 R 50 50 1 1 B
-X TMS 23 -750 800 150 R 50 50 1 1 B
-X I/O 24 -750 700 150 R 50 50 1 1 B
-X I/O 25 -750 600 150 R 50 50 1 1 B
-X VccIO 26 -250 2000 150 D 50 50 1 1 W
-X I/O 27 -750 500 150 R 50 50 1 1 W
-X I/O 28 -750 400 150 R 50 50 1 1 B
-X I/O 29 -750 300 150 R 50 50 1 1 B
-X VccINT 3 350 2000 150 D 50 50 1 1 W
-X I/O 30 -750 200 150 R 50 50 1 1 B
-X I/O 31 -750 100 150 R 50 50 1 1 B
-X GND 32 -250 -2100 150 U 50 50 1 1 W
-X I/O 33 -750 -100 150 R 50 50 1 1 B
-X I/O 34 -750 -200 150 R 50 50 1 1 B
-X I/O 35 -750 -300 150 R 50 50 1 1 B
-X I/O 36 -750 -400 150 R 50 50 1 1 B
-X I/O 37 -750 -500 150 R 50 50 1 1 B
-X VccIO 38 -150 2000 150 D 50 50 1 1 W
-X I/O/NC 39 -750 -600 150 R 50 50 1 1 B
-X I/O 4 750 1100 150 L 50 50 1 1 B
-X I/O 40 -750 -700 150 R 50 50 1 1 B
-X I/O 41 -750 -800 150 R 50 50 1 1 B
-X GND 42 -150 -2100 150 U 50 50 1 1 W
-X VccINT 43 250 2000 150 D 50 50 1 1 W
-X I/O 44 -750 -900 150 R 50 50 1 1 B
-X I/O 45 -750 -1000 150 R 50 50 1 1 B
-X I/O/NC 46 -750 -1100 150 R 50 50 1 1 B
-X GND 47 -50 -2100 150 U 50 50 1 1 W
-X I/O 48 -750 -1200 150 R 50 50 1 1 B
-X I/O 49 -750 -1300 150 R 50 50 1 1 B
-X I/O 5 750 1200 150 L 50 50 1 1 B
-X I/O 50 -750 -1400 150 R 50 50 1 1 B
-X I/O 51 -750 -1500 150 R 50 50 1 1 B
-X I/O 52 -750 -1600 150 R 50 50 1 1 B
-X VccIO 53 -50 2000 150 D 50 50 1 1 W
-X I/O 54 750 -1800 150 L 50 50 1 1 B
-X I/O 55 750 -1700 150 L 50 50 1 1 B
-X I/O 56 750 -1600 150 L 50 50 1 1 B
-X I/O 57 750 -1500 150 L 50 50 1 1 B
-X I/O 58 750 -1400 150 L 50 50 1 1 B
-X GND 59 50 -2100 150 U 50 50 1 1 W
-X I/O/NC 6 750 1300 150 L 50 50 1 1 B
-X I/O 60 750 -1300 150 L 50 50 1 1 B
-X I/O 61 750 -1200 150 L 50 50 1 1 B
-X TCK 62 750 -1100 150 L 50 50 1 1 B
-X I/O 63 750 -1000 150 L 50 50 1 1 B
-X I/O 64 750 -900 150 L 50 50 1 1 B
-X I/O 65 750 -800 150 L 50 50 1 1 B
-X VccIO 66 50 2000 150 D 50 50 1 1 W
-X I/O 67 750 -700 150 L 50 50 1 1 B
-X I/O 68 750 -600 150 L 50 50 1 1 B
-X I/O 69 750 -500 150 L 50 50 1 1 B
-X GND 7 350 -2100 150 U 50 50 1 1 W
-X I/O 70 750 -400 150 L 50 50 1 1 B
-X TDO 71 750 -300 150 L 50 50 1 1 B
-X GND 72 150 -2100 150 U 50 50 1 1 W
-X I/O 73 750 -200 150 L 50 50 1 1 B
-X I/O 74 750 -100 150 L 50 50 1 1 B
-X I/O 75 750 100 150 L 50 50 1 1 B
-X I/O 76 750 200 150 L 50 50 1 1 B
-X I/O 77 750 300 150 L 50 50 1 1 B
-X VccIO 78 150 2000 150 D 50 50 1 1 W
-X I/O/NC 79 750 400 150 L 50 50 1 1 B
-X I/O 8 750 1400 150 L 50 50 1 1 B
-X I/O 80 750 500 150 L 50 50 1 1 B
-X I/O 81 750 600 150 L 50 50 1 1 B
-X GND 82 250 -2100 150 U 50 50 1 1 W
-X GClk1 83 750 700 150 L 50 50 1 1 I
-X OE1 84 750 800 150 L 50 50 1 1 I
-X I/O 9 750 1500 150 L 50 50 1 1 B
-ENDDRAW
-ENDDEF
-#
 #End Library

GR8RAM.kicad_pro

@@ -0,0 +1,520 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.15,
+        "copper_line_width": 0.15,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.09999999999999999,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.0,
+          "height": 0.4,
+          "width": 0.65
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.15239999999999998
+        }
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "meta": {
+        "filename": "board_design_settings.json",
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint": "error",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "warning",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_edge_clearance": "warning",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_thickness": "warning",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zones_intersect": "error"
+      },
+      "rule_severitieslegacy_courtyards_overlap": true,
+      "rule_severitieslegacy_no_courtyard_defined": false,
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_connection": 0.0,
+        "min_copper_edge_clearance": 0.075,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_resolved_spokes": 2,
+        "min_silk_clearance": 0.0,
+        "min_text_height": 0.7999999999999999,
+        "min_text_thickness": 0.08,
+        "min_through_hole_diameter": 0.19999999999999998,
+        "min_track_width": 0.15,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.5,
+        "solder_mask_to_copper_clearance": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "teardrop_options": [
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 5,
+          "td_on_pad_in_zone": false,
+          "td_onpadsmd": true,
+          "td_onroundshapesonly": false,
+          "td_ontrackend": false,
+          "td_onviapad": true
+        }
+      ],
+      "teardrop_parameters": [
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_round_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_rect_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_track_end",
+          "td_width_to_size_filter_ratio": 0.9
+        }
+      ],
+      "track_widths": [
+        0.0,
+        0.2,
+        0.25,
+        0.3,
+        0.35,
+        0.4,
+        0.45,
+        0.5,
+        0.6,
+        0.762,
+        0.8,
+        1.0,
+        1.27,
+        1.524
+      ],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        },
+        {
+          "diameter": 0.6,
+          "drill": 0.3
+        },
+        {
+          "diameter": 0.8,
+          "drill": 0.4
+        },
+        {
+          "diameter": 1.0,
+          "drill": 0.5
+        },
+        {
+          "diameter": 1.524,
+          "drill": 0.762
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        1,
+        1,
+        1,
+        1,
+        1,
+        0,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
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+      ],
+      [
+        0,
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+      ],
+      [
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+      ],
+      [
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+      ],
+      [
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+        2,
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+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "GR8RAM.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12,
+        "clearance": 0.15,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.15,
+        "via_diameter": 0.5,
+        "via_drill": 0.2,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
+      "version": 3
+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": []
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "GR8RAM.net",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.25,
+      "pin_symbol_size": 0.0,
+      "text_offset_ratio": 0.08
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "Pcbnew",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "a29f8df0-3fae-4edf-8d9c-bd5a875b13e3",
+      ""
+    ],
+    [
+      "00000000-0000-0000-0000-00005d4d21a0",
+      "Docs"
+    ]
+  ],
+  "text_variables": {}
+}

GR8RAM.pro

@@ -1,256 +0,0 @@
-update=Monday, June 10, 2019 at 02:27:25 PM
-version=1
-last_client=kicad
-[general]
-version=1
-RootSch=
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-[cvpcb]
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-[eeschema]
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-[pcbnew]
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-CopperLayerCount=4
-BoardThickness=1.6
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-MinViaDrill=0.3
-MinMicroViaDiameter=0.2
-MinMicroViaDrill=0.09999999999999999
-MinHoleToHole=0.25
-TrackWidth1=0.1524
-TrackWidth2=0.2
-TrackWidth3=0.254
-TrackWidth4=0.508
-TrackWidth5=0.762
-TrackWidth6=1.27
-TrackWidth7=1.524
-ViaDiameter1=0.8
-ViaDrill1=0.4
-ViaDiameter2=1.524
-ViaDrill2=0.762
-dPairWidth1=0.2
-dPairGap1=0.25
-dPairViaGap1=0.25
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-dPairViaGap=0.25

LICENSE

@@ -0,0 +1,20 @@
+Copyright (c) Garrett's Workshop
+
+Rationale
+----------------------------------------
+We at Garrett's Workshop create our products and release their source in
+hopes of encouraging others to contribute and build their own "clones,"
+even selling them and competing with us. One day, GW will be defunct,
+and it would be a shame if our hardware and software die along with GW.
+At the same time, however, we seek to protect our trademark and ensure
+that clones and derivative products do not masquerade as genuine
+Garrett's Workshop products.
+
+License Terms
+----------------------------------------
+This project may be licensed under one of two licenses:
+
+1. You may elect to license this project under CC BY-NC-SA 4.0.
+
+2. You may elect to license this project under CC BY-SA 4.0 ONLY IF
+   you remove all "Garrett's Workshop" trademarks from the project.

cpld/GR8RAM.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+# Date created = 20:42:53  February 16, 2024
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "19.1"
+DATE = "20:42:53  February 16, 2024"
+
+# Revisions
+
+PROJECT_REVISION = "GR8RAM"

cpld/GR8RAM.qsf

@@ -0,0 +1,257 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+# Date created = 20:36:06  February 16, 2024
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		GR8RAM_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX II"
+set_global_assignment -name DEVICE EPM240T100C5
+set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:36:06  FEBRUARY 16, 2024"
+set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name SDC_FILE GR8RAM.sdc
+set_global_assignment -name VERILOG_FILE GR8RAM.v
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
+
+set_location_assignment PIN_2 -to RA[5]
+set_location_assignment PIN_3 -to RA[6]
+set_location_assignment PIN_4 -to RA[3]
+set_location_assignment PIN_5 -to nFCS
+set_location_assignment PIN_6 -to RA[7]
+set_location_assignment PIN_7 -to RA[8]
+set_location_assignment PIN_8 -to RA[9]
+set_location_assignment PIN_12 -to FCK
+set_location_assignment PIN_14 -to RA[10]
+set_location_assignment PIN_15 -to MOSI
+set_location_assignment PIN_16 -to MISO
+set_location_assignment PIN_30 -to nRESout
+set_location_assignment PIN_34 -to RA[11]
+set_location_assignment PIN_35 -to RA[12]
+set_location_assignment PIN_36 -to RA[13]
+set_location_assignment PIN_37 -to RA[14]
+set_location_assignment PIN_38 -to RA[15]
+set_location_assignment PIN_39 -to nIOSEL
+set_location_assignment PIN_42 -to nIOSTRB
+set_location_assignment PIN_40 -to nDEVSEL
+set_location_assignment PIN_41 -to PHI0
+set_location_assignment PIN_43 -to nWE
+set_location_assignment PIN_44 -to nRES
+set_location_assignment PIN_47 -to SD[1]
+set_location_assignment PIN_50 -to SD[0]
+set_location_assignment PIN_51 -to SD[4]
+set_location_assignment PIN_100 -to RA[0]
+set_location_assignment PIN_99 -to RD[7]
+set_location_assignment PIN_52 -to SD[5]
+set_location_assignment PIN_54 -to SD[7]
+set_location_assignment PIN_55 -to SD[3]
+set_location_assignment PIN_56 -to SD[2]
+set_location_assignment PIN_53 -to SD[6]
+set_location_assignment PIN_57 -to DQMH
+set_location_assignment PIN_58 -to nSWE
+set_location_assignment PIN_62 -to nRAS
+set_location_assignment PIN_61 -to nCAS
+set_location_assignment PIN_64 -to C25M
+set_location_assignment PIN_66 -to RCKE
+set_location_assignment PIN_67 -to nRCS
+set_location_assignment PIN_68 -to SA[12]
+set_location_assignment PIN_69 -to SBA[0]
+set_location_assignment PIN_70 -to SA[11]
+set_location_assignment PIN_71 -to SBA[1]
+set_location_assignment PIN_72 -to SA[9]
+set_location_assignment PIN_73 -to SA[10]
+set_location_assignment PIN_74 -to SA[8]
+set_location_assignment PIN_75 -to SA[0]
+set_location_assignment PIN_76 -to SA[4]
+set_location_assignment PIN_77 -to SA[6]
+set_location_assignment PIN_78 -to SA[7]
+set_location_assignment PIN_81 -to SA[1]
+set_location_assignment PIN_82 -to SA[2]
+set_location_assignment PIN_83 -to SA[5]
+set_location_assignment PIN_84 -to SA[3]
+set_location_assignment PIN_85 -to DQML
+set_location_assignment PIN_86 -to RD[0]
+set_location_assignment PIN_87 -to RD[1]
+set_location_assignment PIN_88 -to RD[2]
+set_location_assignment PIN_89 -to RD[3]
+set_location_assignment PIN_90 -to RD[4]
+set_location_assignment PIN_91 -to RD[5]
+set_location_assignment PIN_92 -to RD[6]
+set_location_assignment PIN_97 -to RA[2]
+set_location_assignment PIN_98 -to RA[1]
+set_location_assignment PIN_96 -to SetFW[0]
+set_location_assignment PIN_95 -to SetFW[1]
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nFCS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nFCS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to FCK
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to FCK
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MOSI
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MOSI
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MISO
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MISO
+set_location_assignment PIN_21 -to nDMAout
+set_location_assignment PIN_19 -to RAdir
+set_location_assignment PIN_20 -to INTout
+set_location_assignment PIN_26 -to nNMIout
+set_location_assignment PIN_27 -to nINHout
+set_location_assignment PIN_28 -to nRDYout
+set_location_assignment PIN_29 -to nIRQout
+set_location_assignment PIN_33 -to RWout
+set_location_assignment PIN_48 -to DMAin
+set_location_assignment PIN_49 -to INTin
+set_location_assignment PIN_17 -to RDdir
+set_location_assignment PIN_18 -to DMAout
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAdir
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RAdir
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RAdir
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RAdir
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAdir
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RDdir
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RDdir
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RDdir
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RDdir
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RDdir
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to PHI0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI0
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to PHI0
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nWE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nWE
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nDEVSEL
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDEVSEL
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nDEVSEL
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSEL
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSEL
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSEL
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSTRB
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSTRB
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSTRB
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nRES
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRES
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRES
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRESout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nRESout
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRESout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRESout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRESout
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nFCS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nFCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nFCS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FCK
+set_instance_assignment -name SLOW_SLEW_RATE ON -to FCK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to FCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MOSI
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MOSI
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to C25M
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C25M
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to C25M
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRCS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRCS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRCS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRAS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRAS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCAS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nCAS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nSWE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nSWE
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nSWE
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nSWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSWE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RCKE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCKE
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCKE
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RCKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SBA
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SBA
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SBA
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SBA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SA
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQMH
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQMH
+set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQML
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQML
+set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SetFW
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SetFW
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SetFW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD
+set_location_assignment PIN_1 -to RA[4]
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

cpld/GR8RAM.sdc

@@ -0,0 +1,3 @@
+create_clock -period 40 [get_ports C25M]
+create_clock -period 978 [get_ports PHI0]
+set_clock_groups -asynchronous -group C25M -group PHI0

cpld/GR8RAM.v

@@ -0,0 +1,569 @@
+module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
+			  INTin, INTout, DMAin, DMAout, 
+			  nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout,
+			  RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
+			  SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
+			  nFCS, FCK, MISO, MOSI);
+
+	/* Clock signals */
+	input C25M, PHI0;
+	reg [4:1] PHI0r;
+	always @(posedge C25M) PHI0r[4:1] <= {PHI0r[3:1], PHI0};
+	
+	/* Reset synchronization */
+	input nRES;
+	reg nRESf = 0; always @(posedge C25M) nRESf <= nRES;
+	reg nRESr = 0; always @(posedge C25M) nRESr <= nRESf;
+
+	/* Firmware select */
+	input [1:0] SetFW;
+	reg [1:0] SetFWr;
+	reg SetFWLoaded = 0;
+	always @(posedge C25M) begin
+		if (!SetFWLoaded) begin
+			SetFWLoaded <= 1;
+			SetFWr[1:0] <= SetFW[1:0];
+		end
+	end
+	wire [1:0] SetROM = ~SetFWr[1:0];
+	wire SetEN16MB = SetROM[1:0]==2'b11;
+	wire SetEN24bit = SetROM[1];
+
+	/* State counter from PHI0 rising edge */
+	reg [3:0] PS = 0;
+	wire PSStart = PHI0r[1] && !PHI0r[2];
+	always @(posedge C25M) begin
+		if (PSStart) PS <= 1;
+		else if (PS==0) PS <= 0;
+		else PS <= PS+4'h1;
+	end
+
+	/* Long state counter: counts from 0 to $3FFF */
+	reg [13:0] LS = 0;
+	always @(posedge C25M) begin if (PS==15) LS <= LS+14'h1; end
+
+	/* Init state */
+	output reg nRESout = 0;
+	reg [2:0] IS = 0;
+	always @(posedge C25M) begin
+		if (IS==7) nRESout <= 1;
+		else if (PS==15) begin
+			if (LS==14'h1FCE) IS <= 1; // PC all + load mode
+			else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
+			else if (LS==14'h1FFA) IS <= 5; // SPI flash command
+			else if (LS==14'h1FFF) IS <= 6; // Flash load driver
+			else if (LS==14'h3FFF) IS <= 7; // Operating mode
+		end
+	end
+
+	/* Apple IO area select signals */
+	input nIOSEL, nDEVSEL, nIOSTRB;
+
+	/* Apple address bus */
+	input [15:0] RA; input nWE;
+	reg   [11:0] RAr; reg nWEr;
+	reg CXXXr;
+	always @(posedge PHI0) begin
+		CXXXr <= RA[15:12]==4'hC;
+		RAr[11:0] <= RA[11:0];
+		nWEr <= nWE;
+	end
+
+	/* Apple select signals */
+	wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (!RAr[11]));
+	wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
+	wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
+	wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
+	wire RAMSpecSEL = RAMRegSpecSEL && (!SetEN24bit || SetEN16MB || !Addr[23]);
+	wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
+	wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
+	wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
+	wire BankSEL = REGEN && !nDEVSEL && BankSpecSEL;
+	wire RAMRegSEL = !nDEVSEL && RAMRegSpecSEL;
+	wire RAMSEL = !nDEVSEL && RAMSpecSEL;
+	wire RAMWR = RAMSEL && !nWEr;
+	wire AddrHSEL = REGEN && !nDEVSEL && AddrHSpecSEL;
+	wire AddrMSEL = REGEN && !nDEVSEL && AddrMSpecSEL;
+	wire AddrLSEL = REGEN && !nDEVSEL && AddrLSpecSEL;
+	
+	/* IOROMEN and REGEN control */
+	reg IOROMEN = 0;
+	reg REGEN = 0;
+	always @(posedge C25M) begin
+		if (!nRESr) REGEN <= 0;
+		else if (PS==8 && !nIOSEL) REGEN <= 1;
+	end
+	always @(posedge C25M) begin
+		if (!nRESr) IOROMEN <= 0;
+		else if (PS==8 && !nIOSTRB && RAr[10:0]==11'h7FF) IOROMEN <= 0;
+		else if (PS==8 && !nIOSEL) IOROMEN <= 1;
+	end
+
+	/* Apple and internal data bus */
+	wire DBSEL = nWEr && (!nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN && RAr[10:0]!=11'h7FF));
+	wire RDOE =  DBSEL && PHI0 && PHI0r[4];
+	reg [7:0] RDD;
+	inout [7:0] RD = RDOE ? RDD[7:0] : 8'bZ;
+	output RDdir = !(DBSEL && PHI0r[3]);
+
+	/* Slinky address registers */
+	reg [23:0] Addr = 0;
+	reg AddrIncL = 0;
+	reg AddrIncM = 0;
+	reg AddrIncH = 0;
+	always @(posedge C25M, negedge nRESr) begin
+		if (!nRESr) begin
+			Addr[23:0] <= 24'h000000;
+			AddrIncL <= 0;
+			AddrIncM <= 0;
+			AddrIncH <= 0;
+		end else begin
+			if (PS==8 && RAMRegSEL) AddrIncL <= 1;
+			else AddrIncL <= 0;
+
+			if (PS==8 && AddrLSEL && !nWEr) begin
+				Addr[7:0] <= RD[7:0];
+				AddrIncM <= Addr[7] && !RD[7];
+			end else if (AddrIncL) begin
+				Addr[7:0] <= Addr[7:0]+8'h1;
+				AddrIncM <= Addr[7:0]==8'hFF;
+			end else AddrIncM <= 0;
+
+			if (PS==8 && AddrMSEL && !nWEr) begin
+				Addr[15:8] <= RD[7:0];
+				AddrIncH <= Addr[15] && !RD[7];
+			end else if (AddrIncM) begin
+				Addr[15:8] <= Addr[15:8]+8'h1;
+				AddrIncH <= Addr[15:8]==8'hFF;
+			end else AddrIncH <= 0;
+
+			if (PS==8 && AddrHSEL && !nWEr) begin
+				Addr[23:16] <= RD[7:0];
+			end else if (AddrIncH) begin
+				Addr[23:16] <= Addr[23:16]+8'h1;
+			end
+		end
+	end
+
+	/* ROM bank register */
+	reg Bank = 0;
+	always @(posedge C25M, negedge nRESr) begin
+		if (!nRESr) Bank <= 0;
+		else if (PS==8 && BankSEL && !nWEr) begin
+			Bank <= RD[0];
+		end
+	end
+
+	/* SPI flash control signals */
+	output nFCS = FCKOE ? !FCS : 1'bZ;
+	reg FCS = 0;
+	output FCK = FCKOE ? FCKout : 1'bZ;
+	reg FCKOE = 0;
+	reg FCKout = 0;
+	inout MOSI = MOSIOE ? MOSIout : 1'bZ;
+	reg MOSIOE = 0;
+	input MISO;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 1: begin // ACT
+				FCKout <= !(IS==5 || IS==6);
+			end 2: begin // RD
+				FCKout <= 1'b1;
+			end 3: begin // NOP CKE
+				FCKout <= !(IS==5 || IS==6);
+			end 4: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 5: begin // NOP CKE
+				FCKout <= !(IS==5 || IS==6);
+			end 6: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 7: begin // NOP CKE
+				FCKout <= !(IS==5 || IS==6);
+			end 8: begin // WR AP
+				FCKout <= 1'b1;
+			end 9: begin // NOP CKE
+				FCKout <= !(IS==5);
+			end 10: begin // PC all
+				FCKout <= 1'b1;
+			end 11: begin // AREF
+				FCKout <= !(IS==5);
+			end 12: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 13: begin // NOP CKE
+				FCKout <= !(IS==5);
+			end 14: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 15: begin // NOP CKE
+				FCKout <= !(IS==5);
+			end
+		endcase
+		FCS <= IS==4 || IS==5 || IS==6;
+		MOSIOE <= IS==5;
+		FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
+	end
+
+	/* SPI flash MOSI control */
+	reg MOSIout = 0;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			1: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 7
+					3'h4: MOSIout <= 1'b0; // Address bit 23
+					3'h5: MOSIout <= 1'b0; // Address bit 15
+					3'h6: MOSIout <= 1'b0; // Address bit 7
+					default MOSIout <= 1'b0;
+				endcase
+			end 3: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 6
+					3'h4: MOSIout <= 1'b0; // Address bit 22
+					3'h5: MOSIout <= SetROM[1]; // Address bit 14
+					3'h6: MOSIout <= 1'b0; // Address bit 6
+					default MOSIout <= 1'b0;
+				endcase
+			end 5: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 5
+					3'h4: MOSIout <= 1'b0; // Address bit 21
+					3'h5: MOSIout <= SetROM[0]; // Address bit 13
+					3'h6: MOSIout <= 1'b0; // Address bit 5
+					default MOSIout <= 1'b0;
+				endcase
+			end 7: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 4
+					3'h4: MOSIout <= 1'b0; // Address bit 20
+					3'h5: MOSIout <= 1'b0; // Address bit 12
+					3'h6: MOSIout <= 1'b0; // Address bit 4
+					default MOSIout <= 1'b0;
+				endcase
+			end 9: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 3
+					3'h4: MOSIout <= 1'b0; // Address bit 19
+					3'h5: MOSIout <= 1'b0; // Address bit 11
+					3'h6: MOSIout <= 1'b0; // Address bit 3
+					default MOSIout <= 1'b0;
+				endcase
+			end 11: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 2
+					3'h4: MOSIout <= 1'b0; // Address bit 18
+					3'h5: MOSIout <= 1'b0; // Address bit 10
+					3'h6: MOSIout <= 1'b0; // Address bit 2
+					default MOSIout <= 1'b0;
+				endcase
+			end 13: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 1
+					3'h4: MOSIout <= 1'b0; // Address bit 16
+					3'h5: MOSIout <= 1'b0; // Address bit 9
+					3'h6: MOSIout <= 1'b0; // Address bit 1
+					default MOSIout <= 1'b0;
+				endcase
+			end 15: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 0
+					3'h4: MOSIout <= 1'b0; // Address bit 15
+					3'h5: MOSIout <= 1'b0; // Address bit 7
+					3'h6: MOSIout <= 1'b0; // Address bit 0
+					default MOSIout <= 1'b0;
+				endcase
+			end 
+		endcase
+	end
+
+	/* SDRAM data bus */
+	inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
+	reg [7:0] WRD;
+	reg SDOE = 0;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 1: begin // ACT
+			end 2: begin // RD
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 3: begin // NOP CKE
+			end 4: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 5: begin // NOP CKE
+			end 6: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 7: begin // NOP CKE
+			end 8: begin // WR AP
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 9: begin // NOP CKE
+			end 10: begin // PC all
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 11: begin // AREF
+			end 12: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 13: begin // NOP CKE
+			end 14: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 15: begin // NOP CKE
+			end
+		endcase
+	end
+
+	/* Apple data bus from SDRAM */
+	always @(negedge C25M) begin
+		if (PS==5) begin
+			if (nDEVSEL || RAr[3]) RDD[7:0] <= SD[7:0];
+			else case (RAr[2:0])
+				3'h7: RDD[7:0] <= 8'h10; // Hex 10 (meaning firmware 1.0)
+				3'h6: RDD[7:0] <= 8'h41; // ASCII "A" (meaning rev. A)
+				3'h5: RDD[7:0] <= 8'h05; // Hex 05 (meaning "4205")
+				3'h4: RDD[7:0] <= 8'h47; // ASCII "G" (meaning "GW")
+				3'h3: RDD[7:0] <= SD[7:0];
+				3'h2: RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
+				3'h1: RDD[7:0] <= Addr[15:8];
+				3'h0: RDD[7:0] <= Addr[7:0];
+			endcase
+		end
+	end
+
+	/* SDRAM command */
+	output reg RCKE = 1;
+	output reg nRCS = 1;
+	output reg nRAS = 1;
+	output reg nCAS = 1;
+	output reg nSWE = 1;
+	wire RefReqd = LS[1:0] == 2'b11;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE / NOP CKD
+				RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 1: begin // ACT CKE / NOP CKD (ACT)
+				RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
+				nRCS <= !(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
+				nRAS <= 0;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 2: begin // RD CKE / NOP CKD (RD)
+				RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
+				nRCS <= !(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
+				nRAS <= 1;
+				nCAS <= 0;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 3: begin // NOP CKE / CKD
+				RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 4: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 5: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 6: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 7: begin // NOP CKE / CKD
+				RCKE <= IS==6 || (RAMWR && IS==7);
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 8: begin // WR AP CKE / NOP CKD (WR AP)
+				RCKE <= IS==6 || (RAMWR && IS==7);
+				nRCS <= !(IS==6 || (RAMWR && IS==7));
+				nRAS <= 1;
+				nCAS <= 0;
+				nSWE <= 0;
+				SDOE <= IS==6 || (RAMWR && IS==7);
+			end 9: begin // NOP CKE / NOP CKD
+				RCKE <= 1;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 10: begin // PC all CKE / PC all CKD
+				RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
+				nRCS <= 0;
+				nRAS <= 0;
+				nCAS <= 1;
+				nSWE <= 0;
+				SDOE <= 0;
+			end 11: begin // LDM CKE / AREF CKE / NOP CKD
+				RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
+				nRCS <= !(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
+				nRAS <= 0;
+				nCAS <= 0;
+				nSWE <= !(IS==1);
+				SDOE <= 0;
+			end default: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end
+		endcase
+	end
+
+	/* SDRAM address */
+	output reg DQML = 1;
+	output reg DQMH = 1;
+	output reg [1:0] SBA;
+	output reg [12:0] SA;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 1: begin // ACT
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				if (IS==6) begin
+					SBA[1:0] <= { 2'b10 };
+					SA[12:0] <= { 10'b0011000100, LS[12:10] };
+				end else if (RAMSpecSEL) begin
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
+					SA[9:0] <= Addr[19:10];
+				end else begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
+				end
+			end 2: begin // RD
+				if (RAMSpecSEL) begin
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SA[12:0] <= { 4'b0011, Addr[9:1] };
+					DQML <= Addr[0];
+					DQMH <= !Addr[0];
+				end else begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 4'b0011, RAr[9:1]};
+					DQML <= RAr[0];
+					DQMH <= !RAr[0];
+				end
+			end 3: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 4: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 5: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 6: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 7: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 8: begin // WR AP
+				if (IS==6) begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 4'b0011, LS[9:1] };
+					DQML <= LS[0];
+					DQMH <= !LS[0];
+				end else begin
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SA[12:0] <= { 4'b0011, Addr[9:1] };
+					DQML <= Addr[0];
+					DQMH <= !Addr[0];
+				end
+			end 9: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 10: begin // PC all
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 11: begin // AREF / load mode
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0001000100000;
+			end 12: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 13: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 14: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 15: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end
+		endcase
+	end
+
+	/* DMA/INT in/out */
+	input INTin, DMAin;
+	output INTout = INTin;
+	output DMAout = DMAin;
+
+	/* Unused Pins */
+	output RAdir = 1;
+	output nDMAout = 1;
+	output nNMIout = 1;
+	output nINHout = 1;
+	output nRDYout = 1;
+	output nIRQout = 1;
+	output RWout = 1;
+endmodule

cpld/output_files/GR8RAM.asm.rpt

@@ -0,0 +1,91 @@
+Assembler report for GR8RAM
+Tue May 14 02:45:43 2024
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: /Repos/GR8RAM/CPLD/output_files/GR8RAM.pof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue May 14 02:45:43 2024 ;
+; Revision Name         ; GR8RAM                                ;
+; Top-level Entity Name ; GR8RAM                                ;
+; Family                ; MAX II                                ;
+; Device                ; EPM240T100C5                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++--------------------------------------------+
+; Assembler Generated Files                  ;
++--------------------------------------------+
+; File Name                                  ;
++--------------------------------------------+
+; /Repos/GR8RAM/CPLD/output_files/GR8RAM.pof ;
++--------------------------------------------+
+
+
++----------------------------------------------------------------------+
+; Assembler Device Options: /Repos/GR8RAM/CPLD/output_files/GR8RAM.pof ;
++----------------+-----------------------------------------------------+
+; Option         ; Setting                                             ;
++----------------+-----------------------------------------------------+
+; JTAG usercode  ; 0x00160A1C                                          ;
+; Checksum       ; 0x00160E24                                          ;
++----------------+-----------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Tue May 14 02:45:42 2024
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 13100 megabytes
+    Info: Processing ended: Tue May 14 02:45:43 2024
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+

cpld/output_files/GR8RAM.done

@@ -0,0 +1 @@
+Tue May 14 02:45:47 2024

cpld/output_files/GR8RAM.fit.rpt

@@ -0,0 +1,774 @@
+Fitter report for GR8RAM
+Tue May 14 02:45:40 2024
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. Pin-Out File
+  6. Fitter Resource Usage Summary
+  7. Input Pins
+  8. Output Pins
+  9. Bidir Pins
+ 10. I/O Bank Usage
+ 11. All Package Pins
+ 12. Output Pin Default Load For Reported TCO
+ 13. Fitter Resource Utilization by Entity
+ 14. Delay Chain Summary
+ 15. Control Signals
+ 16. Global & Other Fast Signals
+ 17. Routing Usage Summary
+ 18. LAB Logic Elements
+ 19. LAB-wide Signals
+ 20. LAB Signals Sourced
+ 21. LAB Signals Sourced Out
+ 22. LAB Distinct Inputs
+ 23. Fitter Device Options
+ 24. Fitter Messages
+ 25. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------------+
+; Fitter Summary                                                      ;
++-----------------------+---------------------------------------------+
+; Fitter Status         ; Successful - Tue May 14 02:45:40 2024       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name         ; GR8RAM                                      ;
+; Top-level Entity Name ; GR8RAM                                      ;
+; Family                ; MAX II                                      ;
+; Device                ; EPM240T100C5                                ;
+; Timing Models         ; Final                                       ;
+; Total logic elements  ; 235 / 240 ( 98 % )                          ;
+; Total pins            ; 80 / 80 ( 100 % )                           ;
+; Total virtual pins    ; 0                                           ;
+; UFM blocks            ; 0 / 1 ( 0 % )                               ;
++-----------------------+---------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                      ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option                                                             ; Setting                        ; Default Value                  ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device                                                             ; EPM240T100C5                   ;                                ;
+; Maximum processors allowed for parallel compilation                ; 4                              ;                                ;
+; Minimum Core Junction Temperature                                  ; 0                              ;                                ;
+; Maximum Core Junction Temperature                                  ; 85                             ;                                ;
+; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
+; Fitter Effort                                                      ; Standard Fit                   ; Auto Fit                       ;
+; Use smart compilation                                              ; Off                            ; Off                            ;
+; Enable parallel Assembler and Timing Analyzer during compilation   ; On                             ; On                             ;
+; Enable compact report table                                        ; Off                            ; Off                            ;
+; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
+; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
+; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
+; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
+; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
+; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
+; Power Optimization During Fitting                                  ; Normal compilation             ; Normal compilation             ;
+; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
+; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
+; Regenerate Full Fit Report During ECO Compiles                     ; Off                            ; Off                            ;
+; Optimize IOC Register Placement for Timing                         ; Normal                         ; Normal                         ;
+; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
+; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
+; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
+; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
+; Periphery to Core Placement and Routing Optimization               ; Off                            ; Off                            ;
+; Slow Slew Rate                                                     ; Off                            ; Off                            ;
+; PCI I/O                                                            ; Off                            ; Off                            ;
+; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
+; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
+; Auto Delay Chains                                                  ; On                             ; On                             ;
+; Auto Delay Chains for High Fanout Input Pins                       ; Off                            ; Off                            ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
+; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
+; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
+; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
+; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
+; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
+; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
+; Auto Global Clock                                                  ; On                             ; On                             ;
+; Auto Global Register Control Signals                               ; On                             ; On                             ;
+; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                            ; Off                            ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 4           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.03        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   1.2%      ;
+;     Processors 3-4         ;   1.0%      ;
++----------------------------+-------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /Repos/GR8RAM/CPLD/output_files/GR8RAM.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 235 / 240 ( 98 % )    ;
+;     -- Combinational with no register       ; 113                   ;
+;     -- Register only                        ; 4                     ;
+;     -- Combinational with a register        ; 118                   ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 126                   ;
+;     -- 3 input functions                    ; 36                    ;
+;     -- 2 input functions                    ; 67                    ;
+;     -- 1 input functions                    ; 0                     ;
+;     -- 0 input functions                    ; 2                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 202                   ;
+;     -- arithmetic mode                      ; 33                    ;
+;     -- qfbk mode                            ; 19                    ;
+;     -- register cascade mode                ; 0                     ;
+;     -- synchronous clear/load mode          ; 65                    ;
+;     -- asynchronous clear/load mode         ; 28                    ;
+;                                             ;                       ;
+; Total registers                             ; 122 / 240 ( 51 % )    ;
+; Total LABs                                  ; 24 / 24 ( 100 % )     ;
+; Logic elements in carry chains              ; 37                    ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 80 / 80 ( 100 % )     ;
+;     -- Clock pins                           ; 4 / 4 ( 100 % )       ;
+;                                             ;                       ;
+; UFM blocks                                  ; 0 / 1 ( 0 % )         ;
+;                                             ;                       ;
+;     -- Total Fixed Point DSP Blocks         ; 0                     ;
+;     -- Total Floating Point DSP Blocks      ; 0                     ;
+;                                             ;                       ;
+; Global signals                              ; 3                     ;
+;     -- Global clocks                        ; 3 / 4 ( 75 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 46.7% / 51.7% / 41.5% ;
+; Peak interconnect usage (total/H/V)         ; 46.7% / 51.7% / 41.5% ;
+; Maximum fan-out                             ; 108                   ;
+; Highest non-global fan-out                  ; 53                    ;
+; Total fan-out                               ; 1084                  ;
+; Average fan-out                             ; 3.44                  ;
++---------------------------------------------+-----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                     ;
++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard               ; Location assigned by ; Slow Slew Rate ;
++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
+; C25M     ; 64    ; 2        ; 8            ; 3            ; 4           ; 108                   ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; DMAin    ; 48    ; 1        ; 6            ; 0            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; INTin    ; 49    ; 1        ; 7            ; 0            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; MISO     ; 16    ; 1        ; 1            ; 2            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; PHI0     ; 41    ; 1        ; 5            ; 0            ; 1           ; 16                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; RA[0]    ; 100   ; 2        ; 2            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[10]   ; 14    ; 1        ; 1            ; 2            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[11]   ; 34    ; 1        ; 3            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[12]   ; 35    ; 1        ; 3            ; 0            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[13]   ; 36    ; 1        ; 4            ; 0            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[14]   ; 37    ; 1        ; 4            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[15]   ; 38    ; 1        ; 4            ; 0            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[1]    ; 98    ; 2        ; 2            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[2]    ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[3]    ; 4     ; 1        ; 1            ; 4            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[4]    ; 1     ; 2        ; 2            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[5]    ; 2     ; 1        ; 1            ; 4            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[6]    ; 3     ; 1        ; 1            ; 4            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[7]    ; 6     ; 1        ; 1            ; 3            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[8]    ; 7     ; 1        ; 1            ; 3            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[9]    ; 8     ; 1        ; 1            ; 3            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; SetFW[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; On           ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; SetFW[1] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; On           ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; nDEVSEL  ; 40    ; 1        ; 5            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; nIOSEL   ; 39    ; 1        ; 5            ; 0            ; 3           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; nIOSTRB  ; 42    ; 1        ; 5            ; 0            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; nRES     ; 44    ; 1        ; 6            ; 0            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; nWE      ; 43    ; 1        ; 6            ; 0            ; 3           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                               ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; DMAout  ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; DQMH    ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; DQML    ; 85    ; 2        ; 5            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; FCK     ; 12    ; 1        ; 1            ; 3            ; 3           ; no              ; yes            ; no              ; no         ; yes           ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; INTout  ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RAdir   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RCKE    ; 66    ; 2        ; 8            ; 3            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RDdir   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RWout   ; 33    ; 1        ; 3            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[0]   ; 75    ; 2        ; 7            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[10]  ; 73    ; 2        ; 8            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[11]  ; 70    ; 2        ; 8            ; 4            ; 4           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[12]  ; 68    ; 2        ; 8            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[1]   ; 81    ; 2        ; 6            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[2]   ; 82    ; 2        ; 6            ; 5            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[3]   ; 84    ; 2        ; 6            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[4]   ; 76    ; 2        ; 7            ; 5            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[5]   ; 83    ; 2        ; 6            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[6]   ; 77    ; 2        ; 7            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[7]   ; 78    ; 2        ; 7            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[8]   ; 74    ; 2        ; 8            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[9]   ; 72    ; 2        ; 8            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SBA[0]  ; 69    ; 2        ; 8            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SBA[1]  ; 71    ; 2        ; 8            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nCAS    ; 61    ; 2        ; 8            ; 2            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nDMAout ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nFCS    ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; yes           ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nINHout ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nIRQout ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nNMIout ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRAS    ; 62    ; 2        ; 8            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRCS    ; 67    ; 2        ; 8            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRDYout ; 28    ; 1        ; 2            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRESout ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nSWE    ; 58    ; 2        ; 8            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                    ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; MOSI  ; 15    ; 1        ; 1            ; 2            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; MOSIOE               ; -                   ;
+; RD[0] ; 86    ; 2        ; 5            ; 5            ; 1           ; 5                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
+; RD[1] ; 87    ; 2        ; 5            ; 5            ; 2           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
+; RD[2] ; 88    ; 2        ; 5            ; 5            ; 3           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
+; RD[3] ; 89    ; 2        ; 4            ; 5            ; 0           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
+; RD[4] ; 90    ; 2        ; 4            ; 5            ; 1           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
+; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
+; RD[6] ; 92    ; 2        ; 3            ; 5            ; 0           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
+; RD[7] ; 99    ; 2        ; 2            ; 5            ; 1           ; 6                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
+; SD[0] ; 50    ; 1        ; 7            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; SDOE                 ; -                   ;
+; SD[1] ; 47    ; 1        ; 6            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; SDOE                 ; -                   ;
+; SD[2] ; 56    ; 2        ; 8            ; 1            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; SDOE                 ; -                   ;
+; SD[3] ; 55    ; 2        ; 8            ; 1            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; SDOE                 ; -                   ;
+; SD[4] ; 51    ; 1        ; 7            ; 0            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; SDOE                 ; -                   ;
+; SD[5] ; 52    ; 2        ; 8            ; 1            ; 4           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; SDOE                 ; -                   ;
+; SD[6] ; 53    ; 2        ; 8            ; 1            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; SDOE                 ; -                   ;
+; SD[7] ; 54    ; 2        ; 8            ; 1            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; SDOE                 ; -                   ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+
+
++-------------------------------------------------------------+
+; I/O Bank Usage                                              ;
++----------+-------------------+---------------+--------------+
+; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
++----------+-------------------+---------------+--------------+
+; 1        ; 38 / 38 ( 100 % ) ; 3.3V          ; --           ;
+; 2        ; 42 / 42 ( 100 % ) ; 3.3V          ; --           ;
++----------+-------------------+---------------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                             ;
++----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard               ; Voltage   ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
+; 1        ; 83         ; 2        ; RA[4]          ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 2        ; 0          ; 1        ; RA[5]          ; input  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 3        ; 1          ; 1        ; RA[6]          ; input  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 4        ; 2          ; 1        ; RA[3]          ; input  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 5        ; 3          ; 1        ; nFCS           ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; On           ;
+; 6        ; 4          ; 1        ; RA[7]          ; input  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 7        ; 5          ; 1        ; RA[8]          ; input  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 8        ; 6          ; 1        ; RA[9]          ; input  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 9        ;            ; 1        ; VCCIO1         ; power  ;                            ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 10       ;            ;          ; GNDIO          ; gnd    ;                            ;           ; --         ;                 ; --       ; --           ;
+; 11       ;            ;          ; GNDINT         ; gnd    ;                            ;           ; --         ;                 ; --       ; --           ;
+; 12       ; 7          ; 1        ; FCK            ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; yes      ; Off          ;
+; 13       ;            ;          ; VCCINT         ; power  ;                            ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
+; 14       ; 8          ; 1        ; RA[10]         ; input  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 15       ; 9          ; 1        ; MOSI           ; bidir  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; yes      ; Off          ;
+; 16       ; 10         ; 1        ; MISO           ; input  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; yes      ; Off          ;
+; 17       ; 11         ; 1        ; RDdir          ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; On           ;
+; 18       ; 12         ; 1        ; DMAout         ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 19       ; 13         ; 1        ; RAdir          ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; On           ;
+; 20       ; 14         ; 1        ; INTout         ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 21       ; 15         ; 1        ; nDMAout        ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 22       ; 16         ; 1        ; #TMS           ; input  ;                            ;           ; --         ;                 ; --       ; --           ;
+; 23       ; 17         ; 1        ; #TDI           ; input  ;                            ;           ; --         ;                 ; --       ; --           ;
+; 24       ; 18         ; 1        ; #TCK           ; input  ;                            ;           ; --         ;                 ; --       ; --           ;
+; 25       ; 19         ; 1        ; #TDO           ; output ;                            ;           ; --         ;                 ; --       ; --           ;
+; 26       ; 20         ; 1        ; nNMIout        ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 27       ; 21         ; 1        ; nINHout        ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 28       ; 22         ; 1        ; nRDYout        ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 29       ; 23         ; 1        ; nIRQout        ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 30       ; 24         ; 1        ; nRESout        ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; On           ;
+; 31       ;            ; 1        ; VCCIO1         ; power  ;                            ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 32       ;            ;          ; GNDIO          ; gnd    ;                            ;           ; --         ;                 ; --       ; --           ;
+; 33       ; 25         ; 1        ; RWout          ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 34       ; 26         ; 1        ; RA[11]         ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 35       ; 27         ; 1        ; RA[12]         ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 36       ; 28         ; 1        ; RA[13]         ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 37       ; 29         ; 1        ; RA[14]         ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 38       ; 30         ; 1        ; RA[15]         ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 39       ; 31         ; 1        ; nIOSEL         ; input  ; 3.3V Schmitt Trigger Input ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 40       ; 32         ; 1        ; nDEVSEL        ; input  ; 3.3V Schmitt Trigger Input ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 41       ; 33         ; 1        ; PHI0           ; input  ; 3.3V Schmitt Trigger Input ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 42       ; 34         ; 1        ; nIOSTRB        ; input  ; 3.3V Schmitt Trigger Input ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 43       ; 35         ; 1        ; nWE            ; input  ; 3.3V Schmitt Trigger Input ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 44       ; 36         ; 1        ; nRES           ; input  ; 3.3V Schmitt Trigger Input ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 45       ;            ; 1        ; VCCIO1         ; power  ;                            ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 46       ;            ;          ; GNDIO          ; gnd    ;                            ;           ; --         ;                 ; --       ; --           ;
+; 47       ; 37         ; 1        ; SD[1]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 48       ; 38         ; 1        ; DMAin          ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 49       ; 39         ; 1        ; INTin          ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 50       ; 40         ; 1        ; SD[0]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 51       ; 41         ; 1        ; SD[4]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 52       ; 42         ; 2        ; SD[5]          ; bidir  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 53       ; 43         ; 2        ; SD[6]          ; bidir  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 54       ; 44         ; 2        ; SD[7]          ; bidir  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 55       ; 45         ; 2        ; SD[3]          ; bidir  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 56       ; 46         ; 2        ; SD[2]          ; bidir  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 57       ; 47         ; 2        ; DQMH           ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 58       ; 48         ; 2        ; nSWE           ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 59       ;            ; 2        ; VCCIO2         ; power  ;                            ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 60       ;            ;          ; GNDIO          ; gnd    ;                            ;           ; --         ;                 ; --       ; --           ;
+; 61       ; 49         ; 2        ; nCAS           ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 62       ; 50         ; 2        ; nRAS           ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 63       ;            ;          ; VCCINT         ; power  ;                            ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
+; 64       ; 51         ; 2        ; C25M           ; input  ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 65       ;            ;          ; GNDINT         ; gnd    ;                            ;           ; --         ;                 ; --       ; --           ;
+; 66       ; 52         ; 2        ; RCKE           ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 67       ; 53         ; 2        ; nRCS           ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 68       ; 54         ; 2        ; SA[12]         ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 69       ; 55         ; 2        ; SBA[0]         ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 70       ; 56         ; 2        ; SA[11]         ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 71       ; 57         ; 2        ; SBA[1]         ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 72       ; 58         ; 2        ; SA[9]          ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 73       ; 59         ; 2        ; SA[10]         ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 74       ; 60         ; 2        ; SA[8]          ; output ; 3.3-V LVTTL                ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 75       ; 61         ; 2        ; SA[0]          ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 76       ; 62         ; 2        ; SA[4]          ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 77       ; 63         ; 2        ; SA[6]          ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 78       ; 64         ; 2        ; SA[7]          ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 79       ;            ;          ; GNDIO          ; gnd    ;                            ;           ; --         ;                 ; --       ; --           ;
+; 80       ;            ; 2        ; VCCIO2         ; power  ;                            ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 81       ; 65         ; 2        ; SA[1]          ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 82       ; 66         ; 2        ; SA[2]          ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 83       ; 67         ; 2        ; SA[5]          ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 84       ; 68         ; 2        ; SA[3]          ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 85       ; 69         ; 2        ; DQML           ; output ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 86       ; 70         ; 2        ; RD[0]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 87       ; 71         ; 2        ; RD[1]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 88       ; 72         ; 2        ; RD[2]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 89       ; 73         ; 2        ; RD[3]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 90       ; 74         ; 2        ; RD[4]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 91       ; 75         ; 2        ; RD[5]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 92       ; 76         ; 2        ; RD[6]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 93       ;            ;          ; GNDIO          ; gnd    ;                            ;           ; --         ;                 ; --       ; --           ;
+; 94       ;            ; 2        ; VCCIO2         ; power  ;                            ; 3.3V      ; --         ;                 ; --       ; --           ;
+; 95       ; 77         ; 2        ; SetFW[1]       ; input  ; 3.3V Schmitt Trigger Input ;           ; Column I/O ; Y               ; no       ; On           ;
+; 96       ; 78         ; 2        ; SetFW[0]       ; input  ; 3.3V Schmitt Trigger Input ;           ; Column I/O ; Y               ; no       ; On           ;
+; 97       ; 79         ; 2        ; RA[2]          ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 98       ; 80         ; 2        ; RA[1]          ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 99       ; 81         ; 2        ; RD[7]          ; bidir  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; yes      ; Off          ;
+; 100      ; 82         ; 2        ; RA[0]          ; input  ; 3.3-V LVTTL                ;           ; Column I/O ; Y               ; no       ; Off          ;
++----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO                    ;
++----------------------------+-------+------------------------+
+; I/O Standard               ; Load  ; Termination Resistance ;
++----------------------------+-------+------------------------+
+; 3.3-V LVTTL                ; 10 pF ; Not Available          ;
+; 3.3-V LVCMOS               ; 10 pF ; Not Available          ;
+; 2.5 V                      ; 10 pF ; Not Available          ;
+; 1.8 V                      ; 10 pF ; Not Available          ;
+; 1.5 V                      ; 10 pF ; Not Available          ;
+; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available          ;
+; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available          ;
++----------------------------+-------+------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                              ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
+; |GR8RAM                    ; 235 (235)   ; 122          ; 0          ; 80   ; 0            ; 113 (113)    ; 4 (4)             ; 118 (118)        ; 37 (37)         ; 19 (19)    ; |GR8RAM             ; GR8RAM      ; work         ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------+
+; Delay Chain Summary                 ;
++----------+----------+---------------+
+; Name     ; Pin Type ; Pad to Core 0 ;
++----------+----------+---------------+
+; nRESout  ; Output   ; --            ;
+; INTout   ; Output   ; --            ;
+; DMAout   ; Output   ; --            ;
+; nNMIout  ; Output   ; --            ;
+; nIRQout  ; Output   ; --            ;
+; nRDYout  ; Output   ; --            ;
+; nINHout  ; Output   ; --            ;
+; RWout    ; Output   ; --            ;
+; nDMAout  ; Output   ; --            ;
+; RAdir    ; Output   ; --            ;
+; RDdir    ; Output   ; --            ;
+; SBA[0]   ; Output   ; --            ;
+; SBA[1]   ; Output   ; --            ;
+; SA[0]    ; Output   ; --            ;
+; SA[1]    ; Output   ; --            ;
+; SA[2]    ; Output   ; --            ;
+; SA[3]    ; Output   ; --            ;
+; SA[4]    ; Output   ; --            ;
+; SA[5]    ; Output   ; --            ;
+; SA[6]    ; Output   ; --            ;
+; SA[7]    ; Output   ; --            ;
+; SA[8]    ; Output   ; --            ;
+; SA[9]    ; Output   ; --            ;
+; SA[10]   ; Output   ; --            ;
+; SA[11]   ; Output   ; --            ;
+; SA[12]   ; Output   ; --            ;
+; nRCS     ; Output   ; --            ;
+; nRAS     ; Output   ; --            ;
+; nCAS     ; Output   ; --            ;
+; nSWE     ; Output   ; --            ;
+; DQML     ; Output   ; --            ;
+; DQMH     ; Output   ; --            ;
+; RCKE     ; Output   ; --            ;
+; nFCS     ; Output   ; --            ;
+; FCK      ; Output   ; --            ;
+; RD[0]    ; Bidir    ; (1)           ;
+; RD[1]    ; Bidir    ; (1)           ;
+; RD[2]    ; Bidir    ; (1)           ;
+; RD[3]    ; Bidir    ; (1)           ;
+; RD[4]    ; Bidir    ; (1)           ;
+; RD[5]    ; Bidir    ; (1)           ;
+; RD[6]    ; Bidir    ; (1)           ;
+; RD[7]    ; Bidir    ; (1)           ;
+; SD[0]    ; Bidir    ; (1)           ;
+; SD[1]    ; Bidir    ; (1)           ;
+; SD[2]    ; Bidir    ; (1)           ;
+; SD[3]    ; Bidir    ; (1)           ;
+; SD[4]    ; Bidir    ; (1)           ;
+; SD[5]    ; Bidir    ; (1)           ;
+; SD[6]    ; Bidir    ; (1)           ;
+; SD[7]    ; Bidir    ; (1)           ;
+; MOSI     ; Bidir    ; (1)           ;
+; INTin    ; Input    ; (1)           ;
+; DMAin    ; Input    ; (1)           ;
+; nIOSTRB  ; Input    ; (1)           ;
+; nIOSEL   ; Input    ; (1)           ;
+; nDEVSEL  ; Input    ; (1)           ;
+; C25M     ; Input    ; (0)           ;
+; nWE      ; Input    ; (1)           ;
+; PHI0     ; Input    ; (0)           ;
+; RA[3]    ; Input    ; (1)           ;
+; RA[2]    ; Input    ; (1)           ;
+; RA[0]    ; Input    ; (1)           ;
+; RA[1]    ; Input    ; (1)           ;
+; RA[4]    ; Input    ; (1)           ;
+; RA[5]    ; Input    ; (1)           ;
+; RA[6]    ; Input    ; (1)           ;
+; RA[7]    ; Input    ; (1)           ;
+; RA[8]    ; Input    ; (1)           ;
+; RA[9]    ; Input    ; (1)           ;
+; RA[10]   ; Input    ; (1)           ;
+; RA[11]   ; Input    ; (1)           ;
+; RA[14]   ; Input    ; (1)           ;
+; RA[15]   ; Input    ; (1)           ;
+; RA[12]   ; Input    ; (1)           ;
+; RA[13]   ; Input    ; (1)           ;
+; SetFW[1] ; Input    ; (1)           ;
+; SetFW[0] ; Input    ; (1)           ;
+; nRES     ; Input    ; (1)           ;
+; MISO     ; Input    ; (1)           ;
++----------+----------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                ;
++-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
+; Name        ; Location    ; Fan-Out ; Usage                                 ; Global ; Global Resource Used ; Global Line Name ;
++-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
+; C25M        ; PIN_64      ; 108     ; Clock                                 ; yes    ; Global Clock         ; GCLK3            ;
+; Equal19~1   ; LC_X3_Y2_N5 ; 8       ; Clock enable                          ; no     ; --                   ; --               ;
+; Equal2~1    ; LC_X5_Y4_N5 ; 16      ; Clock enable                          ; no     ; --                   ; --               ;
+; FCKOE       ; LC_X5_Y4_N6 ; 2       ; Output enable                         ; no     ; --                   ; --               ;
+; IS~20       ; LC_X7_Y3_N4 ; 5       ; Clock enable                          ; no     ; --                   ; --               ;
+; MOSIOE      ; LC_X5_Y2_N9 ; 1       ; Output enable                         ; no     ; --                   ; --               ;
+; PHI0        ; PIN_41      ; 16      ; Clock                                 ; yes    ; Global Clock         ; GCLK2            ;
+; PS[0]       ; LC_X2_Y2_N9 ; 52      ; Clock enable, Sync. clear, Sync. load ; no     ; --                   ; --               ;
+; PS[2]       ; LC_X2_Y2_N0 ; 27      ; Sync. clear, Sync. load               ; no     ; --                   ; --               ;
+; RDOE        ; LC_X7_Y1_N6 ; 8       ; Output enable                         ; no     ; --                   ; --               ;
+; SDOE        ; LC_X6_Y2_N9 ; 8       ; Output enable                         ; no     ; --                   ; --               ;
+; SetFWLoaded ; LC_X7_Y1_N5 ; 2       ; Clock enable                          ; no     ; --                   ; --               ;
+; always10~3  ; LC_X2_Y3_N2 ; 8       ; Sync. load                            ; no     ; --                   ; --               ;
+; always10~4  ; LC_X3_Y3_N4 ; 9       ; Sync. load                            ; no     ; --                   ; --               ;
+; always10~5  ; LC_X2_Y3_N5 ; 9       ; Sync. load                            ; no     ; --                   ; --               ;
+; nRESr       ; LC_X6_Y1_N8 ; 30      ; Async. clear, Sync. clear             ; yes    ; Global Clock         ; GCLK1            ;
++-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
+
+
++-------------------------------------------------------------------------+
+; Global & Other Fast Signals                                             ;
++-------+-------------+---------+----------------------+------------------+
+; Name  ; Location    ; Fan-Out ; Global Resource Used ; Global Line Name ;
++-------+-------------+---------+----------------------+------------------+
+; C25M  ; PIN_64      ; 108     ; Global Clock         ; GCLK3            ;
+; PHI0  ; PIN_41      ; 16      ; Global Clock         ; GCLK2            ;
+; nRESr ; LC_X6_Y1_N8 ; 30      ; Global Clock         ; GCLK1            ;
++-------+-------------+---------+----------------------+------------------+
+
+
++--------------------------------------------+
+; Routing Usage Summary                      ;
++-----------------------+--------------------+
+; Routing Resource Type ; Usage              ;
++-----------------------+--------------------+
+; C4s                   ; 252 / 784 ( 32 % ) ;
+; Direct links          ; 56 / 888 ( 6 % )   ;
+; Global clocks         ; 3 / 4 ( 75 % )     ;
+; LAB clocks            ; 13 / 32 ( 41 % )   ;
+; LUT chains            ; 24 / 216 ( 11 % )  ;
+; Local interconnects   ; 452 / 888 ( 51 % ) ;
+; R4s                   ; 280 / 704 ( 40 % ) ;
++-----------------------+--------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++--------------------------------------------+------------------------------+
+; Number of Logic Elements  (Average = 9.79) ; Number of LABs  (Total = 24) ;
++--------------------------------------------+------------------------------+
+; 1                                          ; 0                            ;
+; 2                                          ; 0                            ;
+; 3                                          ; 0                            ;
+; 4                                          ; 0                            ;
+; 5                                          ; 0                            ;
+; 6                                          ; 1                            ;
+; 7                                          ; 0                            ;
+; 8                                          ; 0                            ;
+; 9                                          ; 1                            ;
+; 10                                         ; 22                           ;
++--------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals                                                  ;
++------------------------------------+------------------------------+
+; LAB-wide Signals  (Average = 1.83) ; Number of LABs  (Total = 24) ;
++------------------------------------+------------------------------+
+; 1 Async. clear                     ; 4                            ;
+; 1 Clock                            ; 18                           ;
+; 1 Clock enable                     ; 6                            ;
+; 1 Sync. clear                      ; 6                            ;
+; 1 Sync. load                       ; 4                            ;
+; 2 Clocks                           ; 6                            ;
++------------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                         ;
++----------------------------------------------+------------------------------+
+; Number of Signals Sourced  (Average = 10.54) ; Number of LABs  (Total = 24) ;
++----------------------------------------------+------------------------------+
+; 0                                            ; 0                            ;
+; 1                                            ; 0                            ;
+; 2                                            ; 0                            ;
+; 3                                            ; 0                            ;
+; 4                                            ; 0                            ;
+; 5                                            ; 0                            ;
+; 6                                            ; 0                            ;
+; 7                                            ; 0                            ;
+; 8                                            ; 0                            ;
+; 9                                            ; 2                            ;
+; 10                                           ; 17                           ;
+; 11                                           ; 1                            ;
+; 12                                           ; 1                            ;
+; 13                                           ; 0                            ;
+; 14                                           ; 3                            ;
++----------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                        ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out  (Average = 7.75) ; Number of LABs  (Total = 24) ;
++-------------------------------------------------+------------------------------+
+; 0                                               ; 0                            ;
+; 1                                               ; 0                            ;
+; 2                                               ; 0                            ;
+; 3                                               ; 2                            ;
+; 4                                               ; 1                            ;
+; 5                                               ; 3                            ;
+; 6                                               ; 3                            ;
+; 7                                               ; 2                            ;
+; 8                                               ; 2                            ;
+; 9                                               ; 3                            ;
+; 10                                              ; 5                            ;
+; 11                                              ; 1                            ;
+; 12                                              ; 1                            ;
+; 13                                              ; 1                            ;
++-------------------------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                         ;
++----------------------------------------------+------------------------------+
+; Number of Distinct Inputs  (Average = 16.38) ; Number of LABs  (Total = 24) ;
++----------------------------------------------+------------------------------+
+; 0                                            ; 0                            ;
+; 1                                            ; 0                            ;
+; 2                                            ; 0                            ;
+; 3                                            ; 0                            ;
+; 4                                            ; 0                            ;
+; 5                                            ; 1                            ;
+; 6                                            ; 1                            ;
+; 7                                            ; 0                            ;
+; 8                                            ; 1                            ;
+; 9                                            ; 1                            ;
+; 10                                           ; 0                            ;
+; 11                                           ; 0                            ;
+; 12                                           ; 2                            ;
+; 13                                           ; 3                            ;
+; 14                                           ; 1                            ;
+; 15                                           ; 1                            ;
+; 16                                           ; 2                            ;
+; 17                                           ; 1                            ;
+; 18                                           ; 1                            ;
+; 19                                           ; 0                            ;
+; 20                                           ; 0                            ;
+; 21                                           ; 1                            ;
+; 22                                           ; 4                            ;
+; 23                                           ; 2                            ;
+; 24                                           ; 0                            ;
+; 25                                           ; 1                            ;
+; 26                                           ; 1                            ;
++----------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options                                                   ;
++----------------------------------------------+--------------------------+
+; Option                                       ; Setting                  ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
+; Enable device-wide output enable (DEV_OE)    ; Off                      ;
+; Enable INIT_DONE output                      ; Off                      ;
+; Configuration scheme                         ; Passive Serial           ;
+; Reserve all unused pins                      ; As output driving ground ;
++----------------------------------------------+--------------------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (16303): Aggressive Area optimization mode selected -- logic area will be prioritized at the potential cost of reduced timing performance
+Info (20032): Parallel compilation is enabled and will use up to 4 processors
+Info (119006): Selected device EPM240T100C5 for design "GR8RAM"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EPM240T100I5 is compatible
+    Info (176445): Device EPM240T100A5 is compatible
+    Info (176445): Device EPM570T100C5 is compatible
+    Info (176445): Device EPM570T100I5 is compatible
+    Info (176445): Device EPM570T100A5 is compatible
+Info (332104): Reading SDC File: 'GR8RAM.sdc'
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 2 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):   40.000         C25M
+    Info (332111):  978.000         PHI0
+Info (186079): Completed User Assigned Global Signals Promotion Operation
+Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 9
+Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 9
+    Info (186217): Destination "PHI0r[1]" may be non-global or may not use global clock File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 11
+    Info (186217): Destination "RDOE" may be non-global or may not use global clock File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 104
+Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 9
+Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 16
+    Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 90
+    Info (186217): Destination "REGEN" may be non-global or may not use global clock File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 91
+Info (186079): Completed Auto Global Promotion Operation
+Info (176234): Starting register packing
+Info (186468): Started processing fast register assignments
+Info (186469): Finished processing fast register assignments
+Info (176235): Finished register packing
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
+Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 35% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.31 seconds.
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
+Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
+Info (144001): Generated suppressed messages file /Repos/GR8RAM/CPLD/output_files/GR8RAM.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 2 warnings
+    Info: Peak virtual memory: 13776 megabytes
+    Info: Processing ended: Tue May 14 02:45:40 2024
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:04
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /Repos/GR8RAM/CPLD/output_files/GR8RAM.fit.smsg.
+
+

cpld/output_files/GR8RAM.fit.smsg

@@ -0,0 +1,4 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176244): Moving registers into LUTs to improve timing and density
+Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00

cpld/output_files/GR8RAM.fit.summary

@@ -0,0 +1,11 @@
+Fitter Status : Successful - Tue May 14 02:45:40 2024
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Revision Name : GR8RAM
+Top-level Entity Name : GR8RAM
+Family : MAX II
+Device : EPM240T100C5
+Timing Models : Final
+Total logic elements : 235 / 240 ( 98 % )
+Total pins : 80 / 80 ( 100 % )
+Total virtual pins : 0
+UFM blocks : 0 / 1 ( 0 % )

cpld/output_files/GR8RAM.flow.rpt

@@ -0,0 +1,123 @@
+Flow report for GR8RAM
+Tue May 14 02:45:46 2024
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------------+
+; Flow Summary                                                        ;
++-----------------------+---------------------------------------------+
+; Flow Status           ; Successful - Tue May 14 02:45:43 2024       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name         ; GR8RAM                                      ;
+; Top-level Entity Name ; GR8RAM                                      ;
+; Family                ; MAX II                                      ;
+; Device                ; EPM240T100C5                                ;
+; Timing Models         ; Final                                       ;
+; Total logic elements  ; 235 / 240 ( 98 % )                          ;
+; Total pins            ; 80 / 80 ( 100 % )                           ;
+; Total virtual pins    ; 0                                           ;
+; UFM blocks            ; 0 / 1 ( 0 % )                               ;
++-----------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 05/14/2024 02:45:12 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; GR8RAM              ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                          ;
++---------------------------------------+----------------------------------------+---------------+-------------+------------+
+; Assignment Name                       ; Value                                  ; Default Value ; Entity Name ; Section Id ;
++---------------------------------------+----------------------------------------+---------------+-------------+------------+
+; ALM_REGISTER_PACKING_EFFORT           ; High                                   ; Medium        ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                 ; 121380219419.171566911200836           ; --            ; --          ; --         ;
+; FITTER_EFFORT                         ; Standard Fit                           ; Auto Fit      ; --          ; --         ;
+; IOBANK_VCCIO                          ; -- (Not supported for targeted family) ; --            ; --          ; 1          ;
+; IOBANK_VCCIO                          ; -- (Not supported for targeted family) ; --            ; --          ; 2          ;
+; MAX_CORE_JUNCTION_TEMP                ; 85                                     ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                ; 0                                      ; --            ; --          ; --         ;
+; NUM_PARALLEL_PROCESSORS               ; 4                                      ; --            ; --          ; --         ;
+; OPTIMIZATION_MODE                     ; Aggressive Area                        ; Balanced      ; --          ; --         ;
+; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V                                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION         ; No Heat Sink With Still Air            ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY              ; output_files                           ; --            ; --          ; --         ;
++---------------------------------------+----------------------------------------+---------------+-------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:23     ; 1.0                     ; 13137 MB            ; 00:00:49                           ;
+; Fitter               ; 00:00:03     ; 1.0                     ; 13776 MB            ; 00:00:04                           ;
+; Assembler            ; 00:00:01     ; 1.0                     ; 13096 MB            ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 13095 MB            ; 00:00:01                           ;
+; Total                ; 00:00:29     ; --                      ; --                  ; 00:00:55                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                    ;
++----------------------+------------------+------------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
++----------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
+; Fitter               ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
+; Assembler            ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
+; Timing Analyzer      ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
++----------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
+quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
+quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
+quartus_sta GR8RAM -c GR8RAM
+
+
+

cpld/output_files/GR8RAM.jdi

@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="39dfb56692188ac3d8b2"/>
+  </project>
+  <file_info>
+    <file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>

cpld/output_files/GR8RAM.map.rpt

@@ -0,0 +1,318 @@
+Analysis & Synthesis report for GR8RAM
+Tue May 14 02:45:35 2024
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. State Machine - |GR8RAM|IS
+  9. Registers Removed During Synthesis
+ 10. General Register Statistics
+ 11. Inverted Register Statistics
+ 12. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 13. Analysis & Synthesis Messages
+ 14. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                              ;
++-----------------------------+---------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Tue May 14 02:45:35 2024       ;
+; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name               ; GR8RAM                                      ;
+; Top-level Entity Name       ; GR8RAM                                      ;
+; Family                      ; MAX II                                      ;
+; Total logic elements        ; 254                                         ;
+; Total pins                  ; 80                                          ;
+; Total virtual pins          ; 0                                           ;
+; UFM blocks                  ; 0 / 1 ( 0 % )                               ;
++-----------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                              ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                           ; Setting            ; Default Value      ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                           ; EPM240T100C5       ;                    ;
+; Top-level entity name                                            ; GR8RAM             ; GR8RAM             ;
+; Family name                                                      ; MAX II             ; Cyclone V          ;
+; Maximum processors allowed for parallel compilation              ; 4                  ;                    ;
+; Use smart compilation                                            ; Off                ; Off                ;
+; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                      ; Off                ; Off                ;
+; Restructure Multiplexers                                         ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
+; Preserve fewer node names                                        ; On                 ; On                 ;
+; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
+; Verilog Version                                                  ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                     ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                         ; Auto               ; Auto               ;
+; Safe State Machine                                               ; Off                ; Off                ;
+; Extract Verilog State Machines                                   ; On                 ; On                 ;
+; Extract VHDL State Machines                                      ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
+; Parallel Synthesis                                               ; On                 ; On                 ;
+; NOT Gate Push-Back                                               ; On                 ; On                 ;
+; Power-Up Don't Care                                              ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                     ; Off                ; Off                ;
+; Remove Duplicate Registers                                       ; On                 ; On                 ;
+; Ignore CARRY Buffers                                             ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
+; Ignore LCELL Buffers                                             ; Off                ; Off                ;
+; Ignore SOFT Buffers                                              ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
+; Optimization Technique                                           ; Balanced           ; Balanced           ;
+; Carry Chain Length                                               ; 70                 ; 70                 ;
+; Auto Carry Chains                                                ; On                 ; On                 ;
+; Auto Open-Drain Pins                                             ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
+; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
+; Allow Synchronous Control Signals                                ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
+; Auto Resource Sharing                                            ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
+; Report Parameter Settings                                        ; On                 ; On                 ;
+; Report Source Assignments                                        ; On                 ; On                 ;
+; Report Connectivity Checks                                       ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
+; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
+; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
+; HDL message level                                                ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
+; Clock MUX Protection                                             ; On                 ; On                 ;
+; Block Design Naming                                              ; Auto               ; Auto               ;
+; Synthesis Effort                                                 ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
+; Analysis & Synthesis Message Level                               ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
++------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 4           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                          ;
++----------------------------------+-----------------+------------------------+-----------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path            ; Library ;
++----------------------------------+-----------------+------------------------+-----------------------------------------+---------+
+; GR8RAM.v                         ; yes             ; User Verilog HDL File  ; //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v ;         ;
++----------------------------------+-----------------+------------------------+-----------------------------------------+---------+
+
+
++-----------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary         ;
++---------------------------------------------+-------+
+; Resource                                    ; Usage ;
++---------------------------------------------+-------+
+; Total logic elements                        ; 254   ;
+;     -- Combinational with no register       ; 132   ;
+;     -- Register only                        ; 23    ;
+;     -- Combinational with a register        ; 99    ;
+;                                             ;       ;
+; Logic element usage by number of LUT inputs ;       ;
+;     -- 4 input functions                    ; 126   ;
+;     -- 3 input functions                    ; 36    ;
+;     -- 2 input functions                    ; 67    ;
+;     -- 1 input functions                    ; 0     ;
+;     -- 0 input functions                    ; 2     ;
+;                                             ;       ;
+; Logic elements by mode                      ;       ;
+;     -- normal mode                          ; 221   ;
+;     -- arithmetic mode                      ; 33    ;
+;     -- qfbk mode                            ; 0     ;
+;     -- register cascade mode                ; 0     ;
+;     -- synchronous clear/load mode          ; 46    ;
+;     -- asynchronous clear/load mode         ; 28    ;
+;                                             ;       ;
+; Total registers                             ; 122   ;
+; Total logic cells in carry chains           ; 37    ;
+; I/O pins                                    ; 80    ;
+; Maximum fan-out node                        ; C25M  ;
+; Maximum fan-out                             ; 108   ;
+; Total fan-out                               ; 1089  ;
+; Average fan-out                             ; 3.26  ;
++---------------------------------------------+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
+; |GR8RAM                    ; 254 (254)   ; 122          ; 0          ; 80   ; 0            ; 132 (132)    ; 23 (23)           ; 99 (99)          ; 37 (37)         ; 0 (0)      ; |GR8RAM             ; GR8RAM      ; work         ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------+
+; State Machine - |GR8RAM|IS                                   ;
++--------+--------+--------+--------+--------+--------+--------+
+; Name   ; IS.111 ; IS.110 ; IS.101 ; IS.100 ; IS.001 ; IS.000 ;
++--------+--------+--------+--------+--------+--------+--------+
+; IS.000 ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ;
+; IS.001 ; 0      ; 0      ; 0      ; 0      ; 1      ; 1      ;
+; IS.100 ; 0      ; 0      ; 0      ; 1      ; 0      ; 1      ;
+; IS.101 ; 0      ; 0      ; 1      ; 0      ; 0      ; 1      ;
+; IS.110 ; 0      ; 1      ; 0      ; 0      ; 0      ; 1      ;
+; IS.111 ; 1      ; 0      ; 0      ; 0      ; 0      ; 1      ;
++--------+--------+--------+--------+--------+--------+--------+
+
+
++------------------------------------------------------------+
+; Registers Removed During Synthesis                         ;
++---------------------------------------+--------------------+
+; Register name                         ; Reason for Removal ;
++---------------------------------------+--------------------+
+; IS~8                                  ; Lost fanout        ;
+; IS~9                                  ; Lost fanout        ;
+; IS~10                                 ; Lost fanout        ;
+; Total Number of Removed Registers = 3 ;                    ;
++---------------------------------------+--------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 122   ;
+; Number of registers using Synchronous Clear  ; 13    ;
+; Number of registers using Synchronous Load   ; 33    ;
+; Number of registers using Asynchronous Clear ; 28    ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 29    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; nRCS~reg0                              ; 1       ;
+; nRAS~reg0                              ; 1       ;
+; nCAS~reg0                              ; 1       ;
+; nSWE~reg0                              ; 1       ;
+; DQML~reg0                              ; 1       ;
+; DQMH~reg0                              ; 1       ;
+; RCKE~reg0                              ; 1       ;
+; Total number of inverted registers = 7 ;         ;
++----------------------------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |GR8RAM|PS[0]              ;
+; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; Yes        ; |GR8RAM|SA[12]~reg0        ;
+; 20:1               ; 6 bits    ; 78 LEs        ; 24 LEs               ; 54 LEs                 ; Yes        ; |GR8RAM|SA[6]~reg0         ;
+; 20:1               ; 3 bits    ; 39 LEs        ; 18 LEs               ; 21 LEs                 ; Yes        ; |GR8RAM|SA[2]~reg0         ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |GR8RAM|WRD[7]             ;
+; 9:1                ; 4 bits    ; 24 LEs        ; 20 LEs               ; 4 LEs                  ; Yes        ; |GR8RAM|RDD[1]             ;
+; 10:1               ; 4 bits    ; 24 LEs        ; 20 LEs               ; 4 LEs                  ; Yes        ; |GR8RAM|RDD[4]             ;
+; 18:1               ; 2 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |GR8RAM|DQMH~reg0          ;
+; 7:1                ; 5 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |GR8RAM|IS                 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Tue May 14 02:45:12 2024
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
+Info (16303): Aggressive Area optimization mode selected -- logic area will be prioritized at the potential cost of reduced timing performance
+Info (20032): Parallel compilation is enabled and will use up to 4 processors
+Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
+    Info (12023): Found entity 1: GR8RAM File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 1
+Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "nNMIout" is stuck at VCC File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 564
+    Warning (13410): Pin "nIRQout" is stuck at VCC File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 567
+    Warning (13410): Pin "nRDYout" is stuck at VCC File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 566
+    Warning (13410): Pin "nINHout" is stuck at VCC File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 565
+    Warning (13410): Pin "RWout" is stuck at VCC File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 568
+    Warning (13410): Pin "nDMAout" is stuck at VCC File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 563
+    Warning (13410): Pin "RAdir" is stuck at VCC File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 562
+Info (17049): 3 registers lost all their fanouts during netlist optimizations.
+Info (21057): Implemented 334 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 28 input pins
+    Info (21059): Implemented 35 output pins
+    Info (21060): Implemented 17 bidirectional pins
+    Info (21061): Implemented 254 logic cells
+Info (144001): Generated suppressed messages file /Repos/GR8RAM/CPLD/output_files/GR8RAM.map.smsg
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
+    Info: Peak virtual memory: 13137 megabytes
+    Info: Processing ended: Tue May 14 02:45:35 2024
+    Info: Elapsed time: 00:00:23
+    Info: Total CPU time (on all processors): 00:00:49
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in /Repos/GR8RAM/CPLD/output_files/GR8RAM.map.smsg.
+
+

cpld/output_files/GR8RAM.map.smsg

@@ -0,0 +1,2 @@
+Warning (10273): Verilog HDL warning at GR8RAM.v(106): extended using "x" or "z" File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 106
+Warning (10273): Verilog HDL warning at GR8RAM.v(280): extended using "x" or "z" File: //Mac/iCloud/Repos/GR8RAM/CPLD/GR8RAM.v Line: 280

cpld/output_files/GR8RAM.map.summary

@@ -0,0 +1,9 @@
+Analysis & Synthesis Status : Successful - Tue May 14 02:45:35 2024
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Revision Name : GR8RAM
+Top-level Entity Name : GR8RAM
+Family : MAX II
+Total logic elements : 254
+Total pins : 80
+Total virtual pins : 0
+UFM blocks : 0 / 1 ( 0 % )

cpld/output_files/GR8RAM.pin

@@ -0,0 +1,165 @@
+ -- Copyright (C) 2019  Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions 
+ -- and other software and tools, and any partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Intel Program License 
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors.  Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (2.5V/3.3V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 1:       3.3V
+ --                  Bank 2:       3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+CHIP  "GR8RAM"  ASSIGNED TO AN: EPM240T100C5
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+RA[4]                        : 1         : input  : 3.3-V LVTTL       :         : 2         : Y              
+RA[5]                        : 2         : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[6]                        : 3         : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[3]                        : 4         : input  : 3.3-V LVTTL       :         : 1         : Y              
+nFCS                         : 5         : output : 3.3-V LVTTL       :         : 1         : Y              
+RA[7]                        : 6         : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[8]                        : 7         : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[9]                        : 8         : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
+GNDIO                        : 10        : gnd    :                   :         :           :                
+GNDINT                       : 11        : gnd    :                   :         :           :                
+FCK                          : 12        : output : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : 13        : power  :                   : 2.5V/3.3V :           :                
+RA[10]                       : 14        : input  : 3.3-V LVTTL       :         : 1         : Y              
+MOSI                         : 15        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+MISO                         : 16        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RDdir                        : 17        : output : 3.3-V LVTTL       :         : 1         : Y              
+DMAout                       : 18        : output : 3.3-V LVTTL       :         : 1         : Y              
+RAdir                        : 19        : output : 3.3-V LVTTL       :         : 1         : Y              
+INTout                       : 20        : output : 3.3-V LVTTL       :         : 1         : Y              
+nDMAout                      : 21        : output : 3.3-V LVTTL       :         : 1         : Y              
+TMS                          : 22        : input  :                   :         : 1         :                
+TDI                          : 23        : input  :                   :         : 1         :                
+TCK                          : 24        : input  :                   :         : 1         :                
+TDO                          : 25        : output :                   :         : 1         :                
+nNMIout                      : 26        : output : 3.3-V LVTTL       :         : 1         : Y              
+nINHout                      : 27        : output : 3.3-V LVTTL       :         : 1         : Y              
+nRDYout                      : 28        : output : 3.3-V LVTTL       :         : 1         : Y              
+nIRQout                      : 29        : output : 3.3-V LVTTL       :         : 1         : Y              
+nRESout                      : 30        : output : 3.3-V LVTTL       :         : 1         : Y              
+VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
+GNDIO                        : 32        : gnd    :                   :         :           :                
+RWout                        : 33        : output : 3.3-V LVTTL       :         : 1         : Y              
+RA[11]                       : 34        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[12]                       : 35        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[13]                       : 36        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[14]                       : 37        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[15]                       : 38        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nIOSEL                       : 39        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
+nDEVSEL                      : 40        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
+PHI0                         : 41        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
+nIOSTRB                      : 42        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
+nWE                          : 43        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
+nRES                         : 44        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
+VCCIO1                       : 45        : power  :                   : 3.3V    : 1         :                
+GNDIO                        : 46        : gnd    :                   :         :           :                
+SD[1]                        : 47        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+DMAin                        : 48        : input  : 3.3-V LVTTL       :         : 1         : Y              
+INTin                        : 49        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SD[0]                        : 50        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+SD[4]                        : 51        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+SD[5]                        : 52        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+SD[6]                        : 53        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+SD[7]                        : 54        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+SD[3]                        : 55        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+SD[2]                        : 56        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+DQMH                         : 57        : output : 3.3-V LVTTL       :         : 2         : Y              
+nSWE                         : 58        : output : 3.3-V LVTTL       :         : 2         : Y              
+VCCIO2                       : 59        : power  :                   : 3.3V    : 2         :                
+GNDIO                        : 60        : gnd    :                   :         :           :                
+nCAS                         : 61        : output : 3.3-V LVTTL       :         : 2         : Y              
+nRAS                         : 62        : output : 3.3-V LVTTL       :         : 2         : Y              
+VCCINT                       : 63        : power  :                   : 2.5V/3.3V :           :                
+C25M                         : 64        : input  : 3.3-V LVTTL       :         : 2         : Y              
+GNDINT                       : 65        : gnd    :                   :         :           :                
+RCKE                         : 66        : output : 3.3-V LVTTL       :         : 2         : Y              
+nRCS                         : 67        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[12]                       : 68        : output : 3.3-V LVTTL       :         : 2         : Y              
+SBA[0]                       : 69        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[11]                       : 70        : output : 3.3-V LVTTL       :         : 2         : Y              
+SBA[1]                       : 71        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[9]                        : 72        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[10]                       : 73        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[8]                        : 74        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[0]                        : 75        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[4]                        : 76        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[6]                        : 77        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[7]                        : 78        : output : 3.3-V LVTTL       :         : 2         : Y              
+GNDIO                        : 79        : gnd    :                   :         :           :                
+VCCIO2                       : 80        : power  :                   : 3.3V    : 2         :                
+SA[1]                        : 81        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[2]                        : 82        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[5]                        : 83        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[3]                        : 84        : output : 3.3-V LVTTL       :         : 2         : Y              
+DQML                         : 85        : output : 3.3-V LVTTL       :         : 2         : Y              
+RD[0]                        : 86        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[1]                        : 87        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[2]                        : 88        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[3]                        : 89        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[4]                        : 90        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[5]                        : 91        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[6]                        : 92        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+GNDIO                        : 93        : gnd    :                   :         :           :                
+VCCIO2                       : 94        : power  :                   : 3.3V    : 2         :                
+SetFW[1]                     : 95        : input  : 3.3V Schmitt Trigger Input :         : 2         : Y              
+SetFW[0]                     : 96        : input  : 3.3V Schmitt Trigger Input :         : 2         : Y              
+RA[2]                        : 97        : input  : 3.3-V LVTTL       :         : 2         : Y              
+RA[1]                        : 98        : input  : 3.3-V LVTTL       :         : 2         : Y              
+RD[7]                        : 99        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RA[0]                        : 100       : input  : 3.3-V LVTTL       :         : 2         : Y              

cpld/output_files/GR8RAM.sld

@@ -0,0 +1 @@
+<sld_project_info/>

cpld/output_files/GR8RAM.sta.rpt

@@ -0,0 +1,789 @@
+Timing Analyzer report for GR8RAM
+Tue May 14 02:45:46 2024
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Fmax Summary
+  7. Setup Summary
+  8. Hold Summary
+  9. Recovery Summary
+ 10. Removal Summary
+ 11. Minimum Pulse Width Summary
+ 12. Setup: 'C25M'
+ 13. Hold: 'C25M'
+ 14. Recovery: 'C25M'
+ 15. Removal: 'C25M'
+ 16. Setup Transfers
+ 17. Hold Transfers
+ 18. Recovery Transfers
+ 19. Removal Transfers
+ 20. Report TCCS
+ 21. Report RSKM
+ 22. Unconstrained Paths Summary
+ 23. Clock Status Summary
+ 24. Unconstrained Input Ports
+ 25. Unconstrained Output Ports
+ 26. Unconstrained Input Ports
+ 27. Unconstrained Output Ports
+ 28. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++-----------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                     ;
++-----------------------+-----------------------------------------------------+
+; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                              ;
+; Revision Name         ; GR8RAM                                              ;
+; Device Family         ; MAX II                                              ;
+; Device Name           ; EPM240T100C5                                        ;
+; Timing Models         ; Final                                               ;
+; Delay Model           ; Slow Model                                          ;
+; Rise/Fall Delays      ; Unavailable                                         ;
++-----------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 4           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 2           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------+
+; SDC File List                                     ;
++---------------+--------+--------------------------+
+; SDC File Path ; Status ; Read at                  ;
++---------------+--------+--------------------------+
+; GR8RAM.sdc    ; OK     ; Tue May 14 02:45:45 2024 ;
++---------------+--------+--------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                             ;
++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
+; Clock Name ; Type ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets  ;
++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
+; C25M       ; Base ; 40.000  ; 25.0 MHz  ; 0.000 ; 20.000  ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { C25M } ;
+; PHI0       ; Base ; 978.000 ; 1.02 MHz  ; 0.000 ; 489.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PHI0 } ;
++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
+
+
++-------------------------------------------------+
+; Fmax Summary                                    ;
++-----------+-----------------+------------+------+
+; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
++-----------+-----------------+------------+------+
+; 81.34 MHz ; 81.34 MHz       ; C25M       ;      ;
++-----------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++--------------------------------+
+; Setup Summary                  ;
++-------+--------+---------------+
+; Clock ; Slack  ; End Point TNS ;
++-------+--------+---------------+
+; C25M  ; 13.913 ; 0.000         ;
++-------+--------+---------------+
+
+
++-------------------------------+
+; Hold Summary                  ;
++-------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------+-------+---------------+
+; C25M  ; 1.379 ; 0.000         ;
++-------+-------+---------------+
+
+
++--------------------------------+
+; Recovery Summary               ;
++-------+--------+---------------+
+; Clock ; Slack  ; End Point TNS ;
++-------+--------+---------------+
+; C25M  ; 33.194 ; 0.000         ;
++-------+--------+---------------+
+
+
++-------------------------------+
+; Removal Summary               ;
++-------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------+-------+---------------+
+; C25M  ; 6.252 ; 0.000         ;
++-------+-------+---------------+
+
+
++---------------------------------+
+; Minimum Pulse Width Summary     ;
++-------+---------+---------------+
+; Clock ; Slack   ; End Point TNS ;
++-------+---------+---------------+
+; C25M  ; 19.734  ; 0.000         ;
+; PHI0  ; 488.734 ; 0.000         ;
++-------+---------+---------------+
+
+
++-------------------------------------------------------------------------------------------------------+
+; Setup: 'C25M'                                                                                         ;
++--------+-----------+------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+------------+--------------+-------------+--------------+------------+------------+
+; 13.913 ; PS[2]     ; RDD[3]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.754      ;
+; 13.913 ; PS[2]     ; RDD[6]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.754      ;
+; 13.913 ; PS[2]     ; RDD[7]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.754      ;
+; 13.937 ; PS[2]     ; RDD[4]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.730      ;
+; 13.937 ; PS[2]     ; RDD[5]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.730      ;
+; 14.065 ; PS[2]     ; RDD[0]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.602      ;
+; 14.065 ; PS[2]     ; RDD[1]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.602      ;
+; 14.065 ; PS[2]     ; RDD[2]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.602      ;
+; 14.093 ; PS[1]     ; RDD[3]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.574      ;
+; 14.093 ; PS[1]     ; RDD[6]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.574      ;
+; 14.093 ; PS[1]     ; RDD[7]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.574      ;
+; 14.117 ; PS[1]     ; RDD[4]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.550      ;
+; 14.117 ; PS[1]     ; RDD[5]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.550      ;
+; 14.220 ; PS[0]     ; RDD[3]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.447      ;
+; 14.220 ; PS[0]     ; RDD[6]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.447      ;
+; 14.220 ; PS[0]     ; RDD[7]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.447      ;
+; 14.244 ; PS[0]     ; RDD[4]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.423      ;
+; 14.244 ; PS[0]     ; RDD[5]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.423      ;
+; 14.245 ; PS[1]     ; RDD[0]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.422      ;
+; 14.245 ; PS[1]     ; RDD[1]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.422      ;
+; 14.245 ; PS[1]     ; RDD[2]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.422      ;
+; 14.372 ; PS[0]     ; RDD[0]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.295      ;
+; 14.372 ; PS[0]     ; RDD[1]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.295      ;
+; 14.372 ; PS[0]     ; RDD[2]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.295      ;
+; 14.590 ; PS[3]     ; RDD[3]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.077      ;
+; 14.590 ; PS[3]     ; RDD[6]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.077      ;
+; 14.590 ; PS[3]     ; RDD[7]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.077      ;
+; 14.614 ; PS[3]     ; RDD[4]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.053      ;
+; 14.614 ; PS[3]     ; RDD[5]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.053      ;
+; 14.616 ; Addr[2]   ; RDD[2]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.051      ;
+; 14.639 ; Addr[20]  ; RDD[4]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.028      ;
+; 14.742 ; PS[3]     ; RDD[0]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.925      ;
+; 14.742 ; PS[3]     ; RDD[1]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.925      ;
+; 14.742 ; PS[3]     ; RDD[2]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.925      ;
+; 14.794 ; Addr[22]  ; RDD[6]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.873      ;
+; 14.868 ; Addr[5]   ; RDD[5]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.799      ;
+; 14.875 ; Addr[9]   ; RDD[1]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.792      ;
+; 14.916 ; Addr[1]   ; RDD[1]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.751      ;
+; 15.029 ; Addr[19]  ; RDD[3]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.638      ;
+; 15.052 ; Addr[15]  ; RDD[7]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.615      ;
+; 15.118 ; SetFWr[1] ; RDD[4]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.549      ;
+; 15.192 ; Addr[11]  ; RDD[3]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.475      ;
+; 15.249 ; SetFWr[1] ; RDD[7]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.418      ;
+; 15.332 ; Addr[23]  ; RDD[7]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.335      ;
+; 15.337 ; Addr[18]  ; RDD[2]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.330      ;
+; 15.345 ; SetFWr[1] ; RDD[5]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.322      ;
+; 15.391 ; Addr[3]   ; RDD[3]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.276      ;
+; 15.398 ; Addr[17]  ; RDD[1]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.269      ;
+; 15.424 ; Addr[13]  ; RDD[5]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.243      ;
+; 15.468 ; Addr[0]   ; RDD[0]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.199      ;
+; 15.481 ; Addr[21]  ; RDD[5]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.186      ;
+; 15.552 ; Addr[14]  ; RDD[6]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.115      ;
+; 15.595 ; Addr[16]  ; RDD[0]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.072      ;
+; 15.632 ; Addr[4]   ; RDD[4]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.035      ;
+; 15.675 ; Addr[12]  ; RDD[4]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.992      ;
+; 15.818 ; Addr[6]   ; RDD[6]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.849      ;
+; 15.851 ; Addr[8]   ; RDD[0]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.816      ;
+; 16.177 ; Addr[7]   ; RDD[7]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.490      ;
+; 16.431 ; SetFWr[1] ; RDD[6]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.236      ;
+; 16.699 ; Addr[10]  ; RDD[2]     ; C25M         ; C25M        ; 20.000       ; 0.000      ; 2.968      ;
+; 27.706 ; PS[0]     ; SA[0]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.961     ;
+; 27.987 ; PS[0]     ; SA[1]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.680     ;
+; 28.395 ; Addr[23]  ; SA[0]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.272     ;
+; 28.454 ; Addr[23]  ; RCKE~reg0  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.213     ;
+; 28.597 ; Addr[23]  ; SA[1]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.070     ;
+; 28.812 ; REGEN     ; SA[0]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.855     ;
+; 28.871 ; REGEN     ; RCKE~reg0  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.796     ;
+; 28.960 ; PS[0]     ; SA[2]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.707     ;
+; 29.014 ; REGEN     ; SA[1]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.653     ;
+; 29.129 ; Addr[23]  ; nRCS~reg0  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.538     ;
+; 29.512 ; PS[1]     ; SA[1]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.155     ;
+; 29.546 ; REGEN     ; nRCS~reg0  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.121     ;
+; 29.572 ; Addr[23]  ; SA[2]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.095     ;
+; 29.589 ; Addr[23]  ; SA[5]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.078     ;
+; 29.746 ; SetFWr[1] ; SA[0]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.921      ;
+; 29.751 ; PS[2]     ; AddrIncH   ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.916      ;
+; 29.805 ; SetFWr[1] ; RCKE~reg0  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.862      ;
+; 29.841 ; Addr[23]  ; SA[6]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.826      ;
+; 29.858 ; Addr[23]  ; SA[8]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.809      ;
+; 29.863 ; Addr[23]  ; SA[7]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.804      ;
+; 29.881 ; REGEN     ; AddrIncH   ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.786      ;
+; 29.893 ; LS[1]     ; IS.110     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.774      ;
+; 29.893 ; LS[1]     ; IS.000     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.774      ;
+; 29.893 ; LS[1]     ; IS.001     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.774      ;
+; 29.893 ; LS[1]     ; IS.101     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.774      ;
+; 29.893 ; LS[1]     ; IS.100     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.774      ;
+; 29.913 ; PS[1]     ; AddrIncH   ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.754      ;
+; 29.948 ; SetFWr[1] ; SA[1]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.719      ;
+; 29.974 ; IS.110    ; SA[0]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.693      ;
+; 29.982 ; IS.110    ; SA[1]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.685      ;
+; 29.989 ; REGEN     ; SA[2]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.678      ;
+; 29.993 ; LS[10]    ; IS.110     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.674      ;
+; 29.993 ; LS[10]    ; IS.000     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.674      ;
+; 29.993 ; LS[10]    ; IS.001     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.674      ;
+; 29.993 ; LS[10]    ; IS.101     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.674      ;
+; 29.993 ; LS[10]    ; IS.100     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.674      ;
+; 29.999 ; PS[1]     ; nRCS~reg0  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.668      ;
+; 30.006 ; REGEN     ; SA[5]~reg0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.661      ;
+; 30.044 ; PS[0]     ; AddrIncH   ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.623      ;
+; 30.053 ; LS[7]     ; IS.110     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 9.614      ;
++--------+-----------+------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Hold: 'C25M'                                                                                              ;
++-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node    ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
+; 1.379 ; PHI0r[3]     ; PHI0r[4]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.600      ;
+; 1.397 ; PHI0r[1]     ; PHI0r[2]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.618      ;
+; 1.409 ; WRD[1]       ; WRD[1]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.630      ;
+; 1.416 ; WRD[0]       ; WRD[0]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.637      ;
+; 1.420 ; WRD[2]       ; WRD[2]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.641      ;
+; 1.420 ; WRD[3]       ; WRD[3]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.641      ;
+; 1.422 ; WRD[5]       ; WRD[5]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.643      ;
+; 1.654 ; IS.101       ; FCS          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.875      ;
+; 1.776 ; PHI0r[2]     ; PHI0r[3]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.997      ;
+; 1.783 ; WRD[7]       ; WRD[7]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.004      ;
+; 1.800 ; WRD[6]       ; WRD[6]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.021      ;
+; 1.811 ; WRD[4]       ; WRD[4]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.032      ;
+; 1.909 ; IOROMEN      ; IOROMEN      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.130      ;
+; 1.911 ; nRESf        ; nRESr        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.132      ;
+; 1.915 ; IS.100       ; FCS          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.136      ;
+; 1.920 ; PS[3]        ; PS[3]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.141      ;
+; 1.949 ; PS[2]        ; PS[2]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.170      ;
+; 1.973 ; PS[1]        ; PS[1]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.194      ;
+; 2.063 ; LS[13]       ; LS[13]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.284      ;
+; 2.113 ; IS.110       ; FCS          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.334      ;
+; 2.116 ; Addr[16]     ; Addr[16]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.337      ;
+; 2.116 ; Addr[8]      ; Addr[8]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.337      ;
+; 2.117 ; Addr[23]     ; Addr[23]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; Addr[10]     ; Addr[10]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; Addr[1]      ; Addr[1]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; Addr[2]      ; Addr[2]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; Addr[15]     ; Addr[15]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; Addr[17]     ; Addr[17]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; Addr[18]     ; Addr[18]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; Addr[9]      ; Addr[9]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.125 ; Addr[0]      ; Addr[0]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.346      ;
+; 2.125 ; LS[7]        ; LS[7]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.346      ;
+; 2.126 ; Addr[7]      ; Addr[7]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.347      ;
+; 2.128 ; LS[6]        ; LS[6]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.349      ;
+; 2.142 ; LS[8]        ; LS[8]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.363      ;
+; 2.144 ; LS[4]        ; LS[4]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.365      ;
+; 2.145 ; LS[9]        ; LS[9]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.366      ;
+; 2.157 ; WRD[2]       ; WRD[4]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.378      ;
+; 2.163 ; PS[0]        ; PS[0]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.384      ;
+; 2.165 ; WRD[0]       ; WRD[2]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.386      ;
+; 2.166 ; PS[0]        ; PS[1]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.387      ;
+; 2.198 ; PS[2]        ; PS[0]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.419      ;
+; 2.201 ; PS[1]        ; PS[2]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.422      ;
+; 2.221 ; REGEN        ; REGEN        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.442      ;
+; 2.222 ; nRESout~reg0 ; nRESout~reg0 ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.443      ;
+; 2.222 ; Addr[19]     ; Addr[19]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.443      ;
+; 2.228 ; AddrIncH     ; Addr[16]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.449      ;
+; 2.230 ; Addr[21]     ; Addr[21]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.451      ;
+; 2.231 ; Addr[20]     ; Addr[20]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.452      ;
+; 2.231 ; Addr[22]     ; Addr[22]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.452      ;
+; 2.232 ; Addr[3]      ; Addr[3]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.453      ;
+; 2.241 ; LS[10]       ; LS[10]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.462      ;
+; 2.241 ; Addr[11]     ; Addr[11]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.462      ;
+; 2.242 ; Bank         ; Bank         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.463      ;
+; 2.249 ; Addr[4]      ; Addr[4]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.470      ;
+; 2.249 ; Addr[14]     ; Addr[14]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.470      ;
+; 2.251 ; LS[2]        ; LS[2]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.472      ;
+; 2.251 ; LS[3]        ; LS[3]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.472      ;
+; 2.260 ; LS[11]       ; LS[11]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.481      ;
+; 2.260 ; Addr[13]     ; Addr[13]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.481      ;
+; 2.260 ; LS[5]        ; LS[5]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.481      ;
+; 2.260 ; Addr[5]      ; Addr[5]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.481      ;
+; 2.260 ; WRD[5]       ; WRD[7]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.481      ;
+; 2.262 ; Addr[12]     ; Addr[12]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.483      ;
+; 2.262 ; Addr[6]      ; Addr[6]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.483      ;
+; 2.266 ; WRD[3]       ; WRD[5]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.487      ;
+; 2.273 ; LS[12]       ; LS[12]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.494      ;
+; 2.350 ; IS.111       ; IS.111       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.571      ;
+; 2.509 ; LS[1]        ; LS[1]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.730      ;
+; 2.551 ; WRD[4]       ; WRD[6]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.772      ;
+; 2.616 ; LS[0]        ; LS[0]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.837      ;
+; 2.644 ; LS[0]        ; LS[1]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.865      ;
+; 2.746 ; LS[2]        ; IS.101       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.967      ;
+; 2.854 ; IS.110       ; FCKout       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.075      ;
+; 2.948 ; Addr[16]     ; Addr[17]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.169      ;
+; 2.948 ; Addr[8]      ; Addr[9]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.169      ;
+; 2.949 ; Addr[9]      ; Addr[10]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.949 ; Addr[10]     ; Addr[11]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.949 ; Addr[1]      ; Addr[2]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.949 ; Addr[2]      ; Addr[3]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.949 ; Addr[17]     ; Addr[18]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.949 ; Addr[18]     ; Addr[19]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.957 ; Addr[0]      ; Addr[1]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.178      ;
+; 2.957 ; LS[7]        ; LS[8]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.178      ;
+; 2.974 ; LS[8]        ; LS[9]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.195      ;
+; 2.976 ; LS[4]        ; LS[5]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.197      ;
+; 2.977 ; LS[9]        ; LS[10]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.198      ;
+; 3.059 ; Addr[8]      ; Addr[10]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.280      ;
+; 3.059 ; Addr[16]     ; Addr[18]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.280      ;
+; 3.060 ; Addr[10]     ; Addr[12]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.281      ;
+; 3.060 ; Addr[2]      ; Addr[4]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.281      ;
+; 3.060 ; Addr[18]     ; Addr[20]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.281      ;
+; 3.060 ; Addr[9]      ; Addr[11]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.281      ;
+; 3.060 ; Addr[1]      ; Addr[3]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.281      ;
+; 3.060 ; Addr[17]     ; Addr[19]     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.281      ;
+; 3.068 ; Addr[0]      ; Addr[2]      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.289      ;
+; 3.068 ; LS[7]        ; LS[9]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.289      ;
+; 3.085 ; LS[8]        ; LS[10]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.306      ;
+; 3.087 ; LS[4]        ; LS[6]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.308      ;
+; 3.088 ; LS[9]        ; LS[11]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.309      ;
++-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Recovery: 'C25M'                                                                                    ;
++--------+-----------+----------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+----------+--------------+-------------+--------------+------------+------------+
+; 33.194 ; nRESr     ; Addr[0]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[23] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[10] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[1]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[11] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[2]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[12] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Bank     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[3]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[13] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[4]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[14] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[5]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[15] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[6]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[16] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[7]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[17] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[8]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[18] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[9]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[19] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[20] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[21] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; Addr[22] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; AddrIncH ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; AddrIncM ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
+; 33.194 ; nRESr     ; AddrIncL ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.473      ;
++--------+-----------+----------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Removal: 'C25M'                                                                                    ;
++-------+-----------+----------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+----------+--------------+-------------+--------------+------------+------------+
+; 6.252 ; nRESr     ; Addr[0]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[23] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[10] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[1]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[11] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[2]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[12] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Bank     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[3]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[13] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[4]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[14] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[5]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[15] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[6]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[16] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[7]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[17] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[8]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[18] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[9]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[19] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[20] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[21] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; Addr[22] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; AddrIncH ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; AddrIncM ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
+; 6.252 ; nRESr     ; AddrIncL ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.473      ;
++-------+-----------+----------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------+
+; Setup Transfers                                                         ;
++------------+----------+------------+------------+------------+----------+
+; From Clock ; To Clock ; RR Paths   ; FR Paths   ; RF Paths   ; FF Paths ;
++------------+----------+------------+------------+------------+----------+
+; C25M       ; C25M     ; 1459       ; 0          ; 60         ; 0        ;
+; PHI0       ; C25M     ; false path ; false path ; false path ; 0        ;
++------------+----------+------------+------------+------------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------------+
+; Hold Transfers                                                          ;
++------------+----------+------------+------------+------------+----------+
+; From Clock ; To Clock ; RR Paths   ; FR Paths   ; RF Paths   ; FF Paths ;
++------------+----------+------------+------------+------------+----------+
+; C25M       ; C25M     ; 1459       ; 0          ; 60         ; 0        ;
+; PHI0       ; C25M     ; false path ; false path ; false path ; 0        ;
++------------+----------+------------+------------+------------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Recovery Transfers                                                ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; C25M       ; C25M     ; 28       ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Removal Transfers                                                 ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; C25M       ; C25M     ; 28       ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 44    ; 44   ;
+; Unconstrained Input Port Paths  ; 144   ; 144  ;
+; Unconstrained Output Ports      ; 45    ; 45   ;
+; Unconstrained Output Port Paths ; 216   ; 216  ;
++---------------------------------+-------+------+
+
+
++-------------------------------------+
+; Clock Status Summary                ;
++--------+-------+------+-------------+
+; Target ; Clock ; Type ; Status      ;
++--------+-------+------+-------------+
+; C25M   ; C25M  ; Base ; Constrained ;
+; PHI0   ; PHI0  ; Base ; Constrained ;
++--------+-------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; DMAin      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; INTin      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MISO       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MOSI       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PHI0       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[8]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[9]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[10]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[11]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[12]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[13]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[14]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[15]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SetFW[0]   ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SetFW[1]   ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nDEVSEL    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nIOSEL     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nIOSTRB    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRES       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nWE        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; DMAout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DQMH        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DQML        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; FCK         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; INTout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MOSI        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDdir       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[12]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SBA[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nFCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRESout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nSWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; DMAin      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; INTin      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MISO       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MOSI       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PHI0       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[8]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[9]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[10]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[11]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[12]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[13]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[14]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[15]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SetFW[0]   ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SetFW[1]   ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nDEVSEL    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nIOSEL     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nIOSTRB    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRES       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nWE        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; DMAout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DQMH        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DQML        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; FCK         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; INTout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MOSI        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDdir       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[12]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SBA[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nFCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRESout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nSWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Timing Analyzer
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Tue May 14 02:45:44 2024
+Info: Command: quartus_sta GR8RAM -c GR8RAM
+Info: qsta_default_script.tcl version: #1
+Info (20032): Parallel compilation is enabled and will use up to 4 processors
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332104): Reading SDC File: 'GR8RAM.sdc'
+Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
+Info (332146): Worst-case setup slack is 13.913
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    13.913               0.000 C25M 
+Info (332146): Worst-case hold slack is 1.379
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.379               0.000 C25M 
+Info (332146): Worst-case recovery slack is 33.194
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    33.194               0.000 C25M 
+Info (332146): Worst-case removal slack is 6.252
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     6.252               0.000 C25M 
+Info (332146): Worst-case minimum pulse width slack is 19.734
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    19.734               0.000 C25M 
+    Info (332119):   488.734               0.000 PHI0 
+Info (332001): The selected device family is not supported by the report_metastability command.
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime Timing Analyzer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 13095 megabytes
+    Info: Processing ended: Tue May 14 02:45:46 2024
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+

cpld/output_files/GR8RAM.sta.summary

@@ -0,0 +1,29 @@
+------------------------------------------------------------
+Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Setup 'C25M'
+Slack : 13.913
+TNS   : 0.000
+
+Type  : Hold 'C25M'
+Slack : 1.379
+TNS   : 0.000
+
+Type  : Recovery 'C25M'
+Slack : 33.194
+TNS   : 0.000
+
+Type  : Removal 'C25M'
+Slack : 6.252
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'C25M'
+Slack : 19.734
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'PHI0'
+Slack : 488.734
+TNS   : 0.000
+
+------------------------------------------------------------

gerber/GR8RAM-BOM.csv

@@ -0,0 +1,21 @@
+Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
+C10 C1 C7 C2 C3 C4 C11 ,7,"10u","stdpads:C_0805","~","C15850"
+C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 C5 ,27,"2u2","stdpads:C_0603","~","C23630"
+FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
+H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
+H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
+J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
+J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
+J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
+R22 R31 ,2,"33","stdpads:R_0603","~","C23140"
+R28 R29 ,2,"22k","stdpads:R_0603","~","C31850"
+RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501"
+RN5 ,1,"4x10k","stdpads:R4_0402","~","C25725"
+SW1 ,1,"FW","stdpads:SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm","~","C319052"
+U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041"
+U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088"
+U16 U14 ,2,"74LVC1G125GW","stdpads:SOT-353","","C12519"
+U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246"
+U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C164122"
+U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
+U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446"

gerber/GR8RAM-Edge_Cuts.gm1

@@ -0,0 +1,61 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)*
+G04 #@! TF.CreationDate,2021-04-19T04:27:15-04:00*
+G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,0.9*
+G04 #@! TF.SameCoordinates,Original*
+G04 #@! TF.FileFunction,Profile,NP*
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW (5.1.5-0-10_14)) date 2021-04-19 04:27:15*
+%MOMM*%
+%LPD*%
+G04 APERTURE LIST*
+%ADD10C,0.150000*%
+G04 APERTURE END LIST*
+D10*
+X57785000Y-80391000D02*
+X46101001Y-92074999D01*
+X57785000Y-80391000D02*
+G75*
+G02X59309000Y-79883000I1524000J-2032000D01*
+G01*
+X46101001Y-92074999D02*
+G75*
+G03X45593000Y-93599000I2031999J-1524001D01*
+G01*
+X48133000Y-132080000D02*
+X73914000Y-132080000D01*
+X59309000Y-79883000D02*
+X143002000Y-79883000D01*
+X143002000Y-79883000D02*
+G75*
+G02X145542000Y-82423000I0J-2540000D01*
+G01*
+X138938000Y-139700000D02*
+X74422000Y-139700000D01*
+X145542000Y-129540000D02*
+X145542000Y-82423000D01*
+X74422000Y-139700000D02*
+G75*
+G02X73914000Y-139192000I0J508000D01*
+G01*
+X139446000Y-139192000D02*
+G75*
+G02X138938000Y-139700000I-508000J0D01*
+G01*
+X73914000Y-132080000D02*
+X73914000Y-139192000D01*
+X45593000Y-129540000D02*
+X45593000Y-93599000D01*
+X48133000Y-132080000D02*
+G75*
+G02X45593000Y-129540000I0J2540000D01*
+G01*
+X143002000Y-132080000D02*
+X139446000Y-132080000D01*
+X139446000Y-132080000D02*
+X139446000Y-139192000D01*
+X145542000Y-129540000D02*
+G75*
+G02X143002000Y-132080000I-2540000J0D01*
+G01*
+M02*

gerber/GR8RAM-bottom-pos.csv

@@ -0,0 +1 @@
+Ref,Val,Package,MidX,MidY,Rot,Side

gerber/GR8RAM-bottom.pos

@@ -0,0 +1,6 @@
+### Module positions - created on Monday, April 19, 2021 at 04:27:25 AM ###
+### Printed by Pcbnew version kicad (5.1.5-0-10_14)
+## Unit = mm, Angle = deg.
+## Side : bottom
+# Ref     Val       Package                PosX       PosY       Rot  Side
+## End

gerber/GR8RAM-top-pos.csv

@@ -0,0 +1,60 @@
+Ref,Val,Package,MidX,MidY,Rot,Side
+"C1","10u","C_0805",136.310000,-128.270000,180.000000,top
+"C2","10u","C_0805",119.976000,-128.270000,180.000000,top
+"C3","10u","C_0805",116.244000,-128.270000,0.000000,top
+"C4","10u","C_0805",75.350000,-128.270000,180.000000,top
+"C5","2u2","C_0603",113.650000,-90.750000,180.000000,top
+"C7","10u","C_0805",140.100000,-124.200000,90.000000,top
+"C10","10u","C_0805",132.750000,-124.200000,90.000000,top
+"C11","10u","C_0805",130.350000,-124.200000,90.000000,top
+"C12","2u2","C_0603",123.650000,-90.750000,180.000000,top
+"C13","2u2","C_0603",76.600000,-119.800000,270.000000,top
+"C14","2u2","C_0603",85.800000,-119.800000,270.000000,top
+"C15","2u2","C_0603",95.000000,-119.800000,270.000000,top
+"C16","2u2","C_0603",104.200000,-119.800000,270.000000,top
+"C18","2u2","C_0603",82.800000,-103.551000,90.000000,top
+"C19","2u2","C_0603",84.350000,-98.000000,90.000000,top
+"C20","2u2","C_0603",84.350000,-100.900000,90.000000,top
+"C21","2u2","C_0603",90.800000,-111.100000,0.000000,top
+"C22","2u2","C_0603",97.800000,-111.100000,0.000000,top
+"C23","2u2","C_0603",103.750000,-104.300000,270.000000,top
+"C24","2u2","C_0603",103.750000,-100.900000,90.000000,top
+"C25","2u2","C_0603",97.150000,-91.700000,180.000000,top
+"C26","2u2","C_0603",90.150000,-91.700000,180.000000,top
+"C27","2u2","C_0603",105.950000,-98.750000,270.000000,top
+"C28","2u2","C_0603",123.650000,-115.350000,180.000000,top
+"C29","2u2","C_0603",126.450000,-112.600000,270.000000,top
+"C30","2u2","C_0603",126.450000,-107.800000,270.000000,top
+"C31","2u2","C_0603",126.450000,-103.800000,270.000000,top
+"C32","2u2","C_0603",126.450000,-93.400000,270.000000,top
+"C33","2u2","C_0603",110.800000,-104.050000,90.000000,top
+"C34","2u2","C_0603",110.850000,-108.700000,90.000000,top
+"C35","2u2","C_0603",113.650000,-115.350000,180.000000,top
+"C42","2u2","C_0603",117.800000,-122.100000,90.000000,top
+"C43","2u2","C_0603",104.800000,-112.250000,0.000000,top
+"C44","2u2","C_0603",69.000000,-100.650000,270.000000,top
+"FID1","Fiducial","Fiducial",143.002000,-82.423000,270.000000,top
+"FID2","Fiducial","Fiducial",48.133000,-93.599000,90.000000,top
+"FID3","Fiducial","Fiducial",58.801000,-82.931000,90.000000,top
+"FID4","Fiducial","Fiducial",143.002000,-129.540000,0.000000,top
+"FID5","Fiducial","Fiducial",48.133000,-129.540000,0.000000,top
+"R22","33","R_0603",115.800000,-124.200000,180.000000,top
+"R28","22k","R_0603",70.550000,-110.650000,0.000000,top
+"R29","22k","R_0603",70.550000,-112.100000,180.000000,top
+"R31","33","R_0603",80.950000,-108.500000,90.000000,top
+"RN1","4x33","R4_0402",108.200000,-95.150000,0.000000,top
+"RN2","4x33","R4_0402",108.450000,-106.250000,270.000000,top
+"RN3","4x33","R4_0402",108.450000,-110.650000,270.000000,top
+"RN5","4x10k","R4_0402",69.100000,-96.450000,90.000000,top
+"SW1","FW","SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm",135.763000,-95.885000,0.000000,top
+"U1","EPM240T100C5N","TQFP-100_14x14mm_P0.5mm",94.050000,-101.400000,270.000000,top
+"U2","W9825","TSOP-II-54_22.2x10.16mm_P0.8mm",118.650000,-103.050000,180.000000,top
+"U3","W25Q128JVSIQ","SOIC-8_5.3mm",79.121000,-100.711000,180.000000,top
+"U4","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",90.225000,-122.000000,0.000000,top
+"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",108.625000,-122.000000,0.000000,top
+"U6","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",81.025000,-122.000000,0.000000,top
+"U8","XC6206P332MR","SOT-23",136.250000,-124.200000,180.000000,top
+"U9","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",99.425000,-122.000000,0.000000,top
+"U13","25M","Crystal_SMD_3225-4Pin_3.2x2.5mm",107.100000,-102.500000,0.000000,top
+"U14","74LVC1G125GW","SOT-353",115.650000,-121.850000,90.000000,top
+"U16","74LVC1G125GW","SOT-353",108.200000,-98.850000,270.000000,top

gerber/GR8RAM-top.pos

@@ -0,0 +1,65 @@
+### Module positions - created on Monday, April 19, 2021 at 04:27:25 AM ###
+### Printed by Pcbnew version kicad (5.1.5-0-10_14)
+## Unit = mm, Angle = deg.
+## Side : top
+# Ref     Val            Package                                     PosX       PosY       Rot  Side
+C1        10u            C_0805                                  136.3100  -128.2700  180.0000  top
+C2        10u            C_0805                                  119.9760  -128.2700  180.0000  top
+C3        10u            C_0805                                  116.2440  -128.2700    0.0000  top
+C4        10u            C_0805                                   75.3500  -128.2700  180.0000  top
+C5        2u2            C_0603                                  113.6500   -90.7500  180.0000  top
+C7        10u            C_0805                                  140.1000  -124.2000   90.0000  top
+C10       10u            C_0805                                  132.7500  -124.2000   90.0000  top
+C11       10u            C_0805                                  130.3500  -124.2000   90.0000  top
+C12       2u2            C_0603                                  123.6500   -90.7500  180.0000  top
+C13       2u2            C_0603                                   76.6000  -119.8000  270.0000  top
+C14       2u2            C_0603                                   85.8000  -119.8000  270.0000  top
+C15       2u2            C_0603                                   95.0000  -119.8000  270.0000  top
+C16       2u2            C_0603                                  104.2000  -119.8000  270.0000  top
+C18       2u2            C_0603                                   82.8000  -103.5510   90.0000  top
+C19       2u2            C_0603                                   84.3500   -98.0000   90.0000  top
+C20       2u2            C_0603                                   84.3500  -100.9000   90.0000  top
+C21       2u2            C_0603                                   90.8000  -111.1000    0.0000  top
+C22       2u2            C_0603                                   97.8000  -111.1000    0.0000  top
+C23       2u2            C_0603                                  103.7500  -104.3000  270.0000  top
+C24       2u2            C_0603                                  103.7500  -100.9000   90.0000  top
+C25       2u2            C_0603                                   97.1500   -91.7000  180.0000  top
+C26       2u2            C_0603                                   90.1500   -91.7000  180.0000  top
+C27       2u2            C_0603                                  105.9500   -98.7500  270.0000  top
+C28       2u2            C_0603                                  123.6500  -115.3500  180.0000  top
+C29       2u2            C_0603                                  126.4500  -112.6000  270.0000  top
+C30       2u2            C_0603                                  126.4500  -107.8000  270.0000  top
+C31       2u2            C_0603                                  126.4500  -103.8000  270.0000  top
+C32       2u2            C_0603                                  126.4500   -93.4000  270.0000  top
+C33       2u2            C_0603                                  110.8000  -104.0500   90.0000  top
+C34       2u2            C_0603                                  110.8500  -108.7000   90.0000  top
+C35       2u2            C_0603                                  113.6500  -115.3500  180.0000  top
+C42       2u2            C_0603                                  117.8000  -122.1000   90.0000  top
+C43       2u2            C_0603                                  104.8000  -112.2500    0.0000  top
+C44       2u2            C_0603                                   69.0000  -100.6500  270.0000  top
+FID1      Fiducial       Fiducial                                143.0020   -82.4230  270.0000  top
+FID2      Fiducial       Fiducial                                 48.1330   -93.5990   90.0000  top
+FID3      Fiducial       Fiducial                                 58.8010   -82.9310   90.0000  top
+FID4      Fiducial       Fiducial                                143.0020  -129.5400    0.0000  top
+FID5      Fiducial       Fiducial                                 48.1330  -129.5400    0.0000  top
+R22       33             R_0603                                  115.8000  -124.2000  180.0000  top
+R28       22k            R_0603                                   70.5500  -110.6500    0.0000  top
+R29       22k            R_0603                                   70.5500  -112.1000  180.0000  top
+R31       33             R_0603                                   80.9500  -108.5000   90.0000  top
+RN1       4x33           R4_0402                                 108.2000   -95.1500    0.0000  top
+RN2       4x33           R4_0402                                 108.4500  -106.2500  270.0000  top
+RN3       4x33           R4_0402                                 108.4500  -110.6500  270.0000  top
+RN5       4x10k          R4_0402                                  69.1000   -96.4500   90.0000  top
+SW1       FW             SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm   135.7630   -95.8850    0.0000  top
+U1        EPM240T100C5N  TQFP-100_14x14mm_P0.5mm                  94.0500  -101.4000  270.0000  top
+U2        W9825          TSOP-II-54_22.2x10.16mm_P0.8mm          118.6500  -103.0500  180.0000  top
+U3        W25Q128JVSIQ   SOIC-8_5.3mm                             79.1210  -100.7110  180.0000  top
+U4        74AHC245PW     TSSOP-20_4.4x6.5mm_P0.65mm               90.2250  -122.0000    0.0000  top
+U5        74AHC245PW     TSSOP-20_4.4x6.5mm_P0.65mm              108.6250  -122.0000    0.0000  top
+U6        74AHC245PW     TSSOP-20_4.4x6.5mm_P0.65mm               81.0250  -122.0000    0.0000  top
+U8        XC6206P332MR   SOT-23                                  136.2500  -124.2000  180.0000  top
+U9        74AHC245PW     TSSOP-20_4.4x6.5mm_P0.65mm               99.4250  -122.0000    0.0000  top
+U13       25M            Crystal_SMD_3225-4Pin_3.2x2.5mm         107.1000  -102.5000    0.0000  top
+U14       74LVC1G125GW   SOT-353                                 115.6500  -121.8500   90.0000  top
+U16       74LVC1G125GW   SOT-353                                 108.2000   -98.8500  270.0000  top
+## End

gerber/GR8RAM.drl

@@ -0,0 +1,759 @@
+M48
+; DRILL file {KiCad (5.1.5-0-10_14)} date Monday, April 19, 2021 at 04:27:16 AM
+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2021-04-19T04:27:16-04:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.5-0-10_14)
+FMAT,2
+INCH
+T1C0.0079
+T2C0.0118
+T3C0.0150
+T4C0.0157
+T5C0.0300
+T6C0.0400
+T7C0.0433
+T8C0.0390
+T9C0.0454
+T10C0.0935
+%
+G90
+G05
+T1
+X1.825Y-3.68
+X1.825Y-3.915
+X1.825Y-4.115
+X1.825Y-4.315
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+X1.925Y-3.575
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+X2.2598Y-4.3327
+X2.2598Y-4.878
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+X2.2854Y-4.5354
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+X2.313Y-4.876
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+X2.33Y-3.175
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+X2.4775Y-4.6075
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+X5.4685Y-4.8602
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+T7
+X5.53Y-5.1
+T8
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+X2.665Y-4.655
+X2.665Y-4.735
+X2.365Y-4.695
+X2.665Y-4.655
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+X5.53Y-3.245
+X5.63Y-5.0
+X1.895Y-3.785
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+X2.59Y-4.595
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+X2.365Y-4.595
+X2.365Y-4.795
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+X2.59Y-4.795
+T0
+M30

sym-lib-table

@@ -1,3 +1,6 @@
 (sym_lib_table
-  (lib (name stdparts)(type Legacy)(uri "$(KIPRJMOD)/../stdparts/stdparts.lib")(options "")(descr ""))
+  (lib (name GW_RAM)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_RAM.lib)(options "")(descr ""))
+  (lib (name GW_PLD)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_PLD.lib)(options "")(descr ""))
+  (lib (name GW_Logic)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Logic.lib)(options "")(descr ""))
+  (lib (name GW_Power)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Power.lib)(options "")(descr ""))
 )