2005-11-15 00:40:23 +00:00
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//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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2006-01-16 21:21:29 +00:00
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#include "X86InstrBuilder.h"
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2005-11-15 00:40:23 +00:00
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#include "X86ISelLowering.h"
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#include "X86TargetMachine.h"
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#include "llvm/CallingConv.h"
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2006-01-31 22:28:30 +00:00
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#include "llvm/Constants.h"
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2006-04-28 21:29:37 +00:00
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#include "llvm/DerivedTypes.h"
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2005-11-15 00:40:23 +00:00
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#include "llvm/Function.h"
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2006-04-05 23:38:46 +00:00
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#include "llvm/Intrinsics.h"
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2006-03-13 23:18:16 +00:00
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/Analysis/ScalarEvolutionExpressions.h"
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2005-11-15 00:40:23 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2006-01-11 00:33:36 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2005-11-15 00:40:23 +00:00
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SSARegMap.h"
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2006-01-31 03:14:29 +00:00
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#include "llvm/Support/MathExtras.h"
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2005-11-15 00:40:23 +00:00
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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// FIXME: temporary.
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#include "llvm/Support/CommandLine.h"
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static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
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cl::desc("Enable fastcc on X86"));
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X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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2006-01-27 08:10:46 +00:00
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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X86ScalarSSE = Subtarget->hasSSE2();
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2005-11-15 00:40:23 +00:00
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// Set up the TargetLowering object.
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// X86 is weird, it always uses i8 for shift amounts and setcc results.
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setShiftAmountType(MVT::i8);
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setSetCCResultType(MVT::i8);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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2006-01-25 09:15:17 +00:00
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setSchedulingPreference(SchedulingForRegPressure);
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2005-11-15 00:40:23 +00:00
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setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
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2006-01-13 18:00:54 +00:00
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setStackPointerRegisterToSaveRestore(X86::ESP);
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2006-03-16 21:47:42 +00:00
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2006-03-22 19:22:18 +00:00
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if (!Subtarget->isTargetDarwin())
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2006-03-17 20:31:41 +00:00
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// Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
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setUseUnderscoreSetJmpLongJmp(true);
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2006-03-16 21:47:42 +00:00
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// Add legal addressing mode scale values.
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addLegalAddressScale(8);
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addLegalAddressScale(4);
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addLegalAddressScale(2);
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// Enter the ones which require both scale + index last. These are more
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// expensive.
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addLegalAddressScale(9);
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addLegalAddressScale(5);
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addLegalAddressScale(3);
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2006-01-29 06:26:08 +00:00
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2005-11-15 00:40:23 +00:00
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// Set up the register classes.
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addRegisterClass(MVT::i8, X86::R8RegisterClass);
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addRegisterClass(MVT::i16, X86::R16RegisterClass);
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addRegisterClass(MVT::i32, X86::R32RegisterClass);
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// Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
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// operation.
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setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
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setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
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2006-01-17 02:32:49 +00:00
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if (X86ScalarSSE)
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// No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead.
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setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
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else
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setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
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2005-11-15 00:40:23 +00:00
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// Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
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// this operation.
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setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
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2006-02-17 00:03:04 +00:00
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// SSE has no i16 to fp conversion, only i32
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2006-01-30 22:13:22 +00:00
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if (X86ScalarSSE)
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setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
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2006-02-17 07:01:52 +00:00
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else {
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setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
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setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
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}
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2005-11-15 00:40:23 +00:00
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2006-01-30 08:02:57 +00:00
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// We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64
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// isn't legal.
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setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
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setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
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2006-01-30 22:13:22 +00:00
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// Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
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// this operation.
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setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
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setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
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if (X86ScalarSSE) {
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setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
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} else {
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2005-11-15 00:40:23 +00:00
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setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
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2006-01-30 22:13:22 +00:00
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setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
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2005-11-15 00:40:23 +00:00
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}
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// Handle FP_TO_UINT by promoting the destination to a larger signed
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// conversion.
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setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
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setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
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setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
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2006-02-18 07:26:17 +00:00
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if (X86ScalarSSE && !Subtarget->hasSSE3())
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2006-01-30 22:13:22 +00:00
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// Expand FP_TO_UINT into a select.
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// FIXME: We would like to use a Custom expander here eventually to do
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// the optimal thing for SSE vs. the default expansion in the legalizer.
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
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else
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2006-02-18 07:26:17 +00:00
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// With SSE3 we can use fisttpll to convert to a signed i64.
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2005-11-15 00:40:23 +00:00
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
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2006-01-30 22:13:22 +00:00
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setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
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setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
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2005-12-23 05:15:23 +00:00
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2006-02-17 07:01:52 +00:00
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setOperationAction(ISD::BRCOND , MVT::Other, Custom);
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2006-02-01 07:19:44 +00:00
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setOperationAction(ISD::BR_CC , MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
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2005-11-15 00:40:23 +00:00
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setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
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2005-12-07 17:59:14 +00:00
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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2005-11-15 00:40:23 +00:00
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::FREM , MVT::f64 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
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2005-11-20 21:41:10 +00:00
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setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
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2006-01-14 03:14:10 +00:00
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setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
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2006-01-11 21:21:00 +00:00
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2005-11-15 00:40:23 +00:00
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// These should be promoted to a larger select which is supported.
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setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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setOperationAction(ISD::SELECT , MVT::i8 , Promote);
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2006-02-17 00:03:04 +00:00
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// X86 wants to expand cmov itself.
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2006-02-17 07:01:52 +00:00
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setOperationAction(ISD::SELECT , MVT::i16 , Custom);
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setOperationAction(ISD::SELECT , MVT::i32 , Custom);
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setOperationAction(ISD::SELECT , MVT::f32 , Custom);
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setOperationAction(ISD::SELECT , MVT::f64 , Custom);
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setOperationAction(ISD::SETCC , MVT::i8 , Custom);
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setOperationAction(ISD::SETCC , MVT::i16 , Custom);
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setOperationAction(ISD::SETCC , MVT::i32 , Custom);
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setOperationAction(ISD::SETCC , MVT::f32 , Custom);
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setOperationAction(ISD::SETCC , MVT::f64 , Custom);
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2006-02-17 00:03:04 +00:00
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// X86 ret instruction may pop stack.
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2006-02-17 07:01:52 +00:00
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setOperationAction(ISD::RET , MVT::Other, Custom);
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2006-02-17 00:03:04 +00:00
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// Darwin ABI issue.
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2006-02-18 00:15:05 +00:00
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setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
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2006-04-22 18:53:45 +00:00
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setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
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2006-02-17 07:01:52 +00:00
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setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
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2006-02-23 20:41:18 +00:00
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setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
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2006-02-17 00:03:04 +00:00
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// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
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2006-02-17 07:01:52 +00:00
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setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
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setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
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setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
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2006-02-17 00:03:04 +00:00
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// X86 wants to expand memset / memcpy itself.
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2006-02-17 07:01:52 +00:00
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setOperationAction(ISD::MEMSET , MVT::Other, Custom);
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setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
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2005-11-15 00:40:23 +00:00
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2005-11-29 06:16:21 +00:00
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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2006-01-05 01:47:43 +00:00
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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2006-03-07 02:02:57 +00:00
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// FIXME - use subtarget debug flags
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2006-03-22 19:22:18 +00:00
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if (!Subtarget->isTargetDarwin())
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2006-03-07 02:02:57 +00:00
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setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
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2005-11-29 06:16:21 +00:00
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2006-01-25 18:21:52 +00:00
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex
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setOperationAction(ISD::VASTART , MVT::Other, Custom);
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// Use the default implementation.
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setOperationAction(ISD::VAARG , MVT::Other, Expand);
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setOperationAction(ISD::VACOPY , MVT::Other, Expand);
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setOperationAction(ISD::VAEND , MVT::Other, Expand);
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2006-01-15 09:00:21 +00:00
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
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2006-01-13 02:42:53 +00:00
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2006-03-05 05:08:37 +00:00
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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2005-11-15 00:40:23 +00:00
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if (X86ScalarSSE) {
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// Set up the FP register classes.
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2006-01-12 08:27:59 +00:00
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addRegisterClass(MVT::f32, X86::FR32RegisterClass);
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addRegisterClass(MVT::f64, X86::FR64RegisterClass);
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2005-11-15 00:40:23 +00:00
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2006-01-31 22:28:30 +00:00
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// Use ANDPD to simulate FABS.
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setOperationAction(ISD::FABS , MVT::f64, Custom);
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setOperationAction(ISD::FABS , MVT::f32, Custom);
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// Use XORP to simulate FNEG.
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setOperationAction(ISD::FNEG , MVT::f64, Custom);
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setOperationAction(ISD::FNEG , MVT::f32, Custom);
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2006-02-02 00:28:23 +00:00
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// We don't support sin/cos/fmod
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2005-11-15 00:40:23 +00:00
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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2006-01-29 06:26:08 +00:00
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// Expand FP immediates into loads from the stack, except for the special
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// cases we handle.
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
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2005-11-15 00:40:23 +00:00
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addLegalFPImmediate(+0.0); // xorps / xorpd
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} else {
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// Set up the FP register classes.
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addRegisterClass(MVT::f64, X86::RFPRegisterClass);
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2006-01-29 06:44:22 +00:00
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setOperationAction(ISD::UNDEF, MVT::f64, Expand);
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2005-11-15 00:40:23 +00:00
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if (!UnsafeFPMath) {
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setOperationAction(ISD::FSIN , MVT::f64 , Expand);
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setOperationAction(ISD::FCOS , MVT::f64 , Expand);
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}
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2006-01-29 06:26:08 +00:00
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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2005-11-15 00:40:23 +00:00
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addLegalFPImmediate(+0.0); // FLD0
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addLegalFPImmediate(+1.0); // FLD1
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addLegalFPImmediate(-0.0); // FLD0/FCHS
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addLegalFPImmediate(-1.0); // FLD1/FCHS
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}
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2006-02-22 02:26:30 +00:00
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2006-03-01 01:11:20 +00:00
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// First set operation action for all vector types to expand. Then we
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// will selectively turn on ones that can be effectively codegen'd.
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for (unsigned VT = (unsigned)MVT::Vector + 1;
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VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
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|
|
|
setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
|
|
|
|
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
|
|
|
|
setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
|
|
|
|
setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
|
2006-03-31 19:22:53 +00:00
|
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
|
2006-03-21 20:51:05 +00:00
|
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
|
2006-03-31 19:22:53 +00:00
|
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
|
2006-03-01 01:11:20 +00:00
|
|
|
}
|
|
|
|
|
2006-03-22 19:22:18 +00:00
|
|
|
if (Subtarget->hasMMX()) {
|
2006-02-22 02:26:30 +00:00
|
|
|
addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
|
|
|
|
addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
|
|
|
|
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
|
|
|
|
|
2006-03-01 01:11:20 +00:00
|
|
|
// FIXME: add MMX packed arithmetics
|
2006-03-21 23:01:21 +00:00
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
|
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
|
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
|
2006-02-22 02:26:30 +00:00
|
|
|
}
|
|
|
|
|
2006-03-22 19:22:18 +00:00
|
|
|
if (Subtarget->hasSSE1()) {
|
2006-02-22 02:26:30 +00:00
|
|
|
addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
|
|
|
|
|
2006-04-12 21:21:57 +00:00
|
|
|
setOperationAction(ISD::AND, MVT::v4f32, Legal);
|
|
|
|
setOperationAction(ISD::OR, MVT::v4f32, Legal);
|
|
|
|
setOperationAction(ISD::XOR, MVT::v4f32, Legal);
|
2006-04-10 07:23:14 +00:00
|
|
|
setOperationAction(ISD::ADD, MVT::v4f32, Legal);
|
|
|
|
setOperationAction(ISD::SUB, MVT::v4f32, Legal);
|
|
|
|
setOperationAction(ISD::MUL, MVT::v4f32, Legal);
|
|
|
|
setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
|
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
|
|
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
|
2006-04-03 20:53:28 +00:00
|
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
|
2006-04-10 07:23:14 +00:00
|
|
|
setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
|
2006-02-22 02:26:30 +00:00
|
|
|
}
|
|
|
|
|
2006-03-22 19:22:18 +00:00
|
|
|
if (Subtarget->hasSSE2()) {
|
2006-02-22 02:26:30 +00:00
|
|
|
addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
|
|
|
|
addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
|
|
|
|
addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
|
|
|
|
addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
|
|
|
|
addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
|
|
|
|
|
2006-04-10 07:23:14 +00:00
|
|
|
setOperationAction(ISD::ADD, MVT::v2f64, Legal);
|
|
|
|
setOperationAction(ISD::ADD, MVT::v16i8, Legal);
|
|
|
|
setOperationAction(ISD::ADD, MVT::v8i16, Legal);
|
|
|
|
setOperationAction(ISD::ADD, MVT::v4i32, Legal);
|
|
|
|
setOperationAction(ISD::SUB, MVT::v2f64, Legal);
|
|
|
|
setOperationAction(ISD::SUB, MVT::v16i8, Legal);
|
|
|
|
setOperationAction(ISD::SUB, MVT::v8i16, Legal);
|
|
|
|
setOperationAction(ISD::SUB, MVT::v4i32, Legal);
|
2006-04-13 05:10:25 +00:00
|
|
|
setOperationAction(ISD::MUL, MVT::v8i16, Legal);
|
2006-04-10 07:23:14 +00:00
|
|
|
setOperationAction(ISD::MUL, MVT::v2f64, Legal);
|
2006-04-12 21:21:57 +00:00
|
|
|
|
2006-04-10 07:23:14 +00:00
|
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
|
|
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
|
2006-04-12 21:21:57 +00:00
|
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
|
2006-04-17 22:04:06 +00:00
|
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
|
|
|
|
// Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
|
|
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
|
2006-04-12 21:21:57 +00:00
|
|
|
|
|
|
|
// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
|
|
|
|
for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
|
|
|
|
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
|
|
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
|
|
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
|
|
|
|
}
|
2006-04-10 07:23:14 +00:00
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
|
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
|
|
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
|
|
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
|
2006-04-03 20:53:28 +00:00
|
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
|
2006-04-12 21:21:57 +00:00
|
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
|
|
|
|
|
|
|
|
// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
|
|
|
|
for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
|
|
|
|
setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
|
|
|
|
AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
|
|
|
|
setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
|
|
|
|
AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
|
|
|
|
setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
|
|
|
|
AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
|
2006-04-12 17:12:36 +00:00
|
|
|
setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
|
|
|
|
AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
|
2006-04-12 21:21:57 +00:00
|
|
|
setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
|
|
|
|
AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
|
2006-04-10 07:23:14 +00:00
|
|
|
}
|
2006-04-12 21:21:57 +00:00
|
|
|
|
|
|
|
// Custom lower v2i64 and v2f64 selects.
|
|
|
|
setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
|
2006-04-12 17:12:36 +00:00
|
|
|
setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
|
2006-04-10 07:23:14 +00:00
|
|
|
setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
|
2006-04-12 21:21:57 +00:00
|
|
|
setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
|
2006-02-22 02:26:30 +00:00
|
|
|
}
|
|
|
|
|
2006-04-05 23:38:46 +00:00
|
|
|
// We want to custom lower some of our intrinsics.
|
|
|
|
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
|
|
|
|
|
2005-11-15 00:40:23 +00:00
|
|
|
computeRegisterProperties();
|
|
|
|
|
2006-02-14 08:25:08 +00:00
|
|
|
// FIXME: These should be based on subtarget info. Plus, the values should
|
|
|
|
// be smaller when we are in optimizing for size mode.
|
2006-02-14 08:38:30 +00:00
|
|
|
maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
|
|
|
|
maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
|
|
|
|
maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
|
2005-11-15 00:40:23 +00:00
|
|
|
allowUnalignedMemoryAccesses = true; // x86 supports it!
|
|
|
|
}
|
|
|
|
|
|
|
|
std::vector<SDOperand>
|
|
|
|
X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
|
2006-04-26 01:20:17 +00:00
|
|
|
std::vector<SDOperand> Args = TargetLowering::LowerArguments(F, DAG);
|
|
|
|
|
|
|
|
FormalArgs.clear();
|
2006-04-27 01:32:22 +00:00
|
|
|
FormalArgLocs.clear();
|
|
|
|
|
2006-04-26 01:20:17 +00:00
|
|
|
// This sets BytesToPopOnReturn, BytesCallerReserves, etc. which have to be set
|
|
|
|
// before the rest of the function can be lowered.
|
2005-11-15 00:40:23 +00:00
|
|
|
if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
|
2006-04-27 01:32:22 +00:00
|
|
|
PreprocessFastCCArguments(Args, F, DAG);
|
2006-04-26 01:20:17 +00:00
|
|
|
else
|
2006-04-27 01:32:22 +00:00
|
|
|
PreprocessCCCArguments(Args, F, DAG);
|
2006-04-26 01:20:17 +00:00
|
|
|
return Args;
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
std::pair<SDOperand, SDOperand>
|
|
|
|
X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
|
|
|
|
bool isVarArg, unsigned CallingConv,
|
|
|
|
bool isTailCall,
|
|
|
|
SDOperand Callee, ArgListTy &Args,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
assert((!isVarArg || CallingConv == CallingConv::C) &&
|
|
|
|
"Only C takes varargs!");
|
2006-01-06 00:43:03 +00:00
|
|
|
|
|
|
|
// If the callee is a GlobalAddress node (quite common, every direct call is)
|
|
|
|
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
|
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
|
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
|
2006-01-11 06:09:51 +00:00
|
|
|
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
|
|
|
|
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
|
2006-01-06 00:43:03 +00:00
|
|
|
|
2005-11-15 00:40:23 +00:00
|
|
|
if (CallingConv == CallingConv::Fast && EnableFastCC)
|
|
|
|
return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
|
|
|
|
return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// C Calling Convention implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2006-04-27 05:35:28 +00:00
|
|
|
/// AddLiveIn - This helper function adds the specified physical register to the
|
|
|
|
/// MachineFunction as a live in value. It also creates a corresponding virtual
|
|
|
|
/// register for it.
|
|
|
|
static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
|
|
|
|
TargetRegisterClass *RC) {
|
|
|
|
assert(RC->contains(PReg) && "Not the correct regclass!");
|
|
|
|
unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
|
|
|
|
MF.addLiveIn(PReg, VReg);
|
|
|
|
return VReg;
|
|
|
|
}
|
|
|
|
|
2006-04-27 08:31:10 +00:00
|
|
|
/// HowToPassCCCArgument - Returns how an formal argument of the specified type
|
|
|
|
/// should be passed. If it is through stack, returns the size of the stack
|
|
|
|
/// frame; if it is through XMM register, returns the number of XMM registers
|
|
|
|
/// are needed.
|
|
|
|
static void
|
|
|
|
HowToPassCCCArgument(MVT::ValueType ObjectVT, unsigned NumXMMRegs,
|
|
|
|
unsigned &ObjSize, unsigned &ObjXMMRegs) {
|
2006-04-27 01:32:22 +00:00
|
|
|
switch (ObjectVT) {
|
|
|
|
default: assert(0 && "Unhandled argument type!");
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8: ObjSize = 1; break;
|
|
|
|
case MVT::i16: ObjSize = 2; break;
|
|
|
|
case MVT::i32: ObjSize = 4; break;
|
|
|
|
case MVT::i64: ObjSize = 8; break;
|
|
|
|
case MVT::f32: ObjSize = 4; break;
|
|
|
|
case MVT::f64: ObjSize = 8; break;
|
2006-04-27 08:31:10 +00:00
|
|
|
case MVT::v16i8:
|
|
|
|
case MVT::v8i16:
|
|
|
|
case MVT::v4i32:
|
|
|
|
case MVT::v2i64:
|
|
|
|
case MVT::v4f32:
|
|
|
|
case MVT::v2f64:
|
|
|
|
if (NumXMMRegs < 3)
|
|
|
|
ObjXMMRegs = 1;
|
|
|
|
else
|
|
|
|
ObjSize = 16;
|
|
|
|
break;
|
2006-04-27 01:32:22 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-27 05:35:28 +00:00
|
|
|
/// getFormalArgObjects - Returns itself if Op is a FORMAL_ARGUMENTS, otherwise
|
|
|
|
/// returns the FORMAL_ARGUMENTS node(s) that made up parts of the node.
|
2006-04-27 01:32:22 +00:00
|
|
|
static std::vector<SDOperand> getFormalArgObjects(SDOperand Op) {
|
|
|
|
unsigned Opc = Op.getOpcode();
|
|
|
|
std::vector<SDOperand> Objs;
|
|
|
|
if (Opc == ISD::TRUNCATE) {
|
|
|
|
Op = Op.getOperand(0);
|
|
|
|
assert(Op.getOpcode() == ISD::AssertSext ||
|
|
|
|
Op.getOpcode() == ISD::AssertZext);
|
|
|
|
Objs.push_back(Op.getOperand(0));
|
2006-04-28 05:25:15 +00:00
|
|
|
} else if (Opc == ISD::FP_ROUND || Opc == ISD::VBIT_CONVERT) {
|
2006-04-27 01:32:22 +00:00
|
|
|
Objs.push_back(Op.getOperand(0));
|
|
|
|
} else if (Opc == ISD::BUILD_PAIR) {
|
|
|
|
Objs.push_back(Op.getOperand(0));
|
|
|
|
Objs.push_back(Op.getOperand(1));
|
|
|
|
} else {
|
|
|
|
Objs.push_back(Op);
|
|
|
|
}
|
|
|
|
return Objs;
|
|
|
|
}
|
|
|
|
|
|
|
|
void X86TargetLowering::PreprocessCCCArguments(std::vector<SDOperand>Args,
|
|
|
|
Function &F, SelectionDAG &DAG) {
|
|
|
|
unsigned NumArgs = Args.size();
|
2006-04-26 01:20:17 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
|
2006-04-27 01:32:22 +00:00
|
|
|
// Add DAG nodes to load the arguments... On entry to a function on the X86,
|
|
|
|
// the stack frame looks like this:
|
|
|
|
//
|
|
|
|
// [ESP] -- return address
|
|
|
|
// [ESP + 4] -- first argument (leftmost lexically)
|
|
|
|
// [ESP + 8] -- second argument, if first argument is four bytes in size
|
|
|
|
// ...
|
|
|
|
//
|
2006-04-26 01:20:17 +00:00
|
|
|
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
|
2006-04-27 08:31:10 +00:00
|
|
|
unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
|
|
|
|
unsigned XMMArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
|
2006-04-26 01:20:17 +00:00
|
|
|
for (unsigned i = 0; i < NumArgs; ++i) {
|
2006-04-27 01:32:22 +00:00
|
|
|
SDOperand Op = Args[i];
|
|
|
|
std::vector<SDOperand> Objs = getFormalArgObjects(Op);
|
|
|
|
for (std::vector<SDOperand>::iterator I = Objs.begin(), E = Objs.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
SDOperand Obj = *I;
|
|
|
|
MVT::ValueType ObjectVT = Obj.getValueType();
|
|
|
|
unsigned ArgIncrement = 4;
|
2006-04-27 08:31:10 +00:00
|
|
|
unsigned ObjSize = 0;
|
|
|
|
unsigned ObjXMMRegs = 0;
|
|
|
|
HowToPassCCCArgument(ObjectVT, NumXMMRegs, ObjSize, ObjXMMRegs);
|
|
|
|
if (ObjSize >= 8)
|
|
|
|
ArgIncrement = ObjSize;
|
|
|
|
|
|
|
|
if (ObjXMMRegs) {
|
|
|
|
// Passed in a XMM register.
|
|
|
|
unsigned Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
|
|
|
|
X86::VR128RegisterClass);
|
|
|
|
std::pair<FALocInfo, FALocInfo> Loc =
|
|
|
|
std::make_pair(FALocInfo(FALocInfo::LiveInRegLoc, Reg, ObjectVT),
|
|
|
|
FALocInfo());
|
|
|
|
FormalArgLocs.push_back(Loc);
|
|
|
|
NumXMMRegs += ObjXMMRegs;
|
|
|
|
} else {
|
|
|
|
// Create the frame index object for this incoming parameter...
|
|
|
|
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
|
|
|
|
std::pair<FALocInfo, FALocInfo> Loc =
|
|
|
|
std::make_pair(FALocInfo(FALocInfo::StackFrameLoc, FI), FALocInfo());
|
|
|
|
FormalArgLocs.push_back(Loc);
|
|
|
|
ArgOffset += ArgIncrement; // Move on to the next argument...
|
|
|
|
}
|
2006-04-26 01:20:17 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the function takes variable number of arguments, make a frame index for
|
|
|
|
// the start of the first vararg value... for expansion of llvm.va_start.
|
|
|
|
if (F.isVarArg())
|
|
|
|
VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
|
|
|
|
ReturnAddrIndex = 0; // No return address slot generated yet.
|
|
|
|
BytesToPopOnReturn = 0; // Callee pops nothing.
|
|
|
|
BytesCallerReserves = ArgOffset;
|
|
|
|
}
|
2005-11-15 00:40:23 +00:00
|
|
|
|
2006-04-26 01:20:17 +00:00
|
|
|
void X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
unsigned NumArgs = Op.Val->getNumValues();
|
2005-11-15 00:40:23 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
|
2006-04-26 01:20:17 +00:00
|
|
|
for (unsigned i = 0; i < NumArgs; ++i) {
|
2006-04-27 08:31:10 +00:00
|
|
|
std::pair<FALocInfo, FALocInfo> Loc = FormalArgLocs[i];
|
|
|
|
SDOperand ArgValue;
|
|
|
|
if (Loc.first.Kind == FALocInfo::StackFrameLoc) {
|
|
|
|
// Create the SelectionDAG nodes corresponding to a load from this parameter
|
|
|
|
unsigned FI = FormalArgLocs[i].first.Loc;
|
|
|
|
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
|
|
|
|
ArgValue = DAG.getLoad(Op.Val->getValueType(i),
|
|
|
|
DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
|
|
|
|
} else {
|
|
|
|
// Must be a CopyFromReg
|
|
|
|
ArgValue= DAG.getCopyFromReg(DAG.getEntryNode(), Loc.first.Loc,
|
|
|
|
Loc.first.Typ);
|
|
|
|
}
|
2006-04-26 01:20:17 +00:00
|
|
|
FormalArgs.push_back(ArgValue);
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
std::pair<SDOperand, SDOperand>
|
|
|
|
X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
|
|
|
|
bool isVarArg, bool isTailCall,
|
|
|
|
SDOperand Callee, ArgListTy &Args,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
// Count how many bytes are to be pushed on the stack.
|
|
|
|
unsigned NumBytes = 0;
|
|
|
|
|
2006-04-28 21:29:37 +00:00
|
|
|
// Keep track of the number of XMM regs passed so far.
|
|
|
|
unsigned NumXMMRegs = 0;
|
|
|
|
unsigned XMMArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
|
|
|
|
|
|
|
|
std::vector<SDOperand> RegValuesToPass;
|
2005-11-15 00:40:23 +00:00
|
|
|
if (Args.empty()) {
|
|
|
|
// Save zero bytes.
|
2006-02-13 09:00:43 +00:00
|
|
|
Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(0, getPointerTy()));
|
2005-11-15 00:40:23 +00:00
|
|
|
} else {
|
|
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i)
|
|
|
|
switch (getValueType(Args[i].second)) {
|
|
|
|
default: assert(0 && "Unknown value type!");
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
case MVT::i32:
|
|
|
|
case MVT::f32:
|
|
|
|
NumBytes += 4;
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
case MVT::f64:
|
|
|
|
NumBytes += 8;
|
|
|
|
break;
|
2006-04-28 21:29:37 +00:00
|
|
|
case MVT::Vector:
|
|
|
|
if (NumXMMRegs < 3)
|
|
|
|
++NumXMMRegs;
|
|
|
|
else
|
|
|
|
NumBytes += 16;
|
|
|
|
break;
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
|
|
|
|
2006-02-13 09:00:43 +00:00
|
|
|
Chain = DAG.getCALLSEQ_START(Chain,
|
|
|
|
DAG.getConstant(NumBytes, getPointerTy()));
|
2005-11-15 00:40:23 +00:00
|
|
|
|
|
|
|
// Arguments go on the stack in reverse order, as specified by the ABI.
|
|
|
|
unsigned ArgOffset = 0;
|
2006-04-28 21:29:37 +00:00
|
|
|
NumXMMRegs = 0;
|
2006-01-11 06:09:51 +00:00
|
|
|
SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
|
2005-11-15 00:40:23 +00:00
|
|
|
std::vector<SDOperand> Stores;
|
|
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
|
|
|
switch (getValueType(Args[i].second)) {
|
|
|
|
default: assert(0 && "Unexpected ValueType for argument!");
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
// Promote the integer to 32 bits. If the input type is signed use a
|
|
|
|
// sign extend, otherwise use a zero extend.
|
|
|
|
if (Args[i].second->isSigned())
|
|
|
|
Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
|
|
|
|
else
|
|
|
|
Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
|
|
|
|
|
|
|
|
// FALL THROUGH
|
|
|
|
case MVT::i32:
|
2006-04-28 21:29:37 +00:00
|
|
|
case MVT::f32: {
|
|
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
2005-11-15 00:40:23 +00:00
|
|
|
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
|
|
Args[i].first, PtrOff,
|
|
|
|
DAG.getSrcValue(NULL)));
|
|
|
|
ArgOffset += 4;
|
|
|
|
break;
|
2006-04-28 21:29:37 +00:00
|
|
|
}
|
2005-11-15 00:40:23 +00:00
|
|
|
case MVT::i64:
|
2006-04-28 21:29:37 +00:00
|
|
|
case MVT::f64: {
|
|
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
2005-11-15 00:40:23 +00:00
|
|
|
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
|
|
Args[i].first, PtrOff,
|
|
|
|
DAG.getSrcValue(NULL)));
|
|
|
|
ArgOffset += 8;
|
|
|
|
break;
|
|
|
|
}
|
2006-04-28 21:29:37 +00:00
|
|
|
case MVT::Vector:
|
|
|
|
if (NumXMMRegs < 3) {
|
|
|
|
RegValuesToPass.push_back(Args[i].first);
|
|
|
|
NumXMMRegs++;
|
|
|
|
} else {
|
|
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
|
|
|
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
|
|
Args[i].first, PtrOff,
|
|
|
|
DAG.getSrcValue(NULL)));
|
|
|
|
ArgOffset += 16;
|
|
|
|
}
|
|
|
|
}
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
2006-04-28 21:29:37 +00:00
|
|
|
if (!Stores.empty())
|
2005-11-15 00:40:23 +00:00
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
|
|
|
|
}
|
|
|
|
|
|
|
|
std::vector<MVT::ValueType> RetVals;
|
|
|
|
MVT::ValueType RetTyVT = getValueType(RetTy);
|
|
|
|
RetVals.push_back(MVT::Other);
|
|
|
|
|
|
|
|
// The result values produced have to be legal. Promote the result.
|
|
|
|
switch (RetTyVT) {
|
|
|
|
case MVT::isVoid: break;
|
|
|
|
default:
|
|
|
|
RetVals.push_back(RetTyVT);
|
|
|
|
break;
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
RetVals.push_back(MVT::i32);
|
|
|
|
break;
|
|
|
|
case MVT::f32:
|
|
|
|
if (X86ScalarSSE)
|
|
|
|
RetVals.push_back(MVT::f32);
|
|
|
|
else
|
|
|
|
RetVals.push_back(MVT::f64);
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
RetVals.push_back(MVT::i32);
|
|
|
|
RetVals.push_back(MVT::i32);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2006-04-28 21:29:37 +00:00
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
|
|
|
// and flag operands which copy the outgoing args into registers.
|
|
|
|
SDOperand InFlag;
|
|
|
|
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
|
|
|
|
unsigned CCReg = XMMArgRegs[i];
|
|
|
|
SDOperand RegToPass = RegValuesToPass[i];
|
|
|
|
assert(RegToPass.getValueType() == MVT::Vector);
|
|
|
|
unsigned NumElems = cast<ConstantSDNode>(*(RegToPass.Val->op_end()-2))->getValue();
|
|
|
|
MVT::ValueType EVT = cast<VTSDNode>(*(RegToPass.Val->op_end()-1))->getVT();
|
|
|
|
MVT::ValueType PVT = getVectorType(EVT, NumElems);
|
|
|
|
SDOperand CCRegNode = DAG.getRegister(CCReg, PVT);
|
|
|
|
RegToPass = DAG.getNode(ISD::VBIT_CONVERT, PVT, RegToPass);
|
|
|
|
Chain = DAG.getCopyToReg(Chain, CCRegNode, RegToPass, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2006-02-17 00:03:04 +00:00
|
|
|
std::vector<MVT::ValueType> NodeTys;
|
|
|
|
NodeTys.push_back(MVT::Other); // Returns a chain
|
|
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(Callee);
|
2006-04-28 21:29:37 +00:00
|
|
|
if (InFlag.Val)
|
|
|
|
Ops.push_back(InFlag);
|
2006-02-17 00:03:04 +00:00
|
|
|
|
|
|
|
// FIXME: Do not generate X86ISD::TAILCALL for now.
|
|
|
|
Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
|
2006-04-28 21:29:37 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
2006-02-17 00:03:04 +00:00
|
|
|
|
|
|
|
NodeTys.clear();
|
|
|
|
NodeTys.push_back(MVT::Other); // Returns a chain
|
|
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
|
|
|
|
Ops.push_back(DAG.getConstant(0, getPointerTy()));
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
|
|
|
SDOperand RetVal;
|
|
|
|
if (RetTyVT != MVT::isVoid) {
|
2006-01-05 00:27:02 +00:00
|
|
|
switch (RetTyVT) {
|
2006-02-17 00:03:04 +00:00
|
|
|
default: assert(0 && "Unknown value type to return!");
|
2006-01-05 00:27:02 +00:00
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
2006-02-17 00:03:04 +00:00
|
|
|
RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
|
|
|
|
Chain = RetVal.getValue(1);
|
|
|
|
if (RetTyVT == MVT::i1)
|
|
|
|
RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
|
|
|
|
break;
|
2006-01-05 00:27:02 +00:00
|
|
|
case MVT::i16:
|
2006-02-17 00:03:04 +00:00
|
|
|
RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
|
|
|
|
Chain = RetVal.getValue(1);
|
2006-01-05 00:27:02 +00:00
|
|
|
break;
|
2006-02-17 00:03:04 +00:00
|
|
|
case MVT::i32:
|
|
|
|
RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
|
|
|
|
Chain = RetVal.getValue(1);
|
2006-01-05 00:27:02 +00:00
|
|
|
break;
|
2006-02-17 00:03:04 +00:00
|
|
|
case MVT::i64: {
|
|
|
|
SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
|
|
|
|
SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
|
|
|
|
Lo.getValue(2));
|
|
|
|
RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
|
|
|
|
Chain = Hi.getValue(1);
|
2006-01-05 00:27:02 +00:00
|
|
|
break;
|
|
|
|
}
|
2006-02-17 00:03:04 +00:00
|
|
|
case MVT::f32:
|
|
|
|
case MVT::f64: {
|
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
Tys.push_back(MVT::f64);
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
|
|
|
|
Chain = RetVal.getValue(1);
|
|
|
|
InFlag = RetVal.getValue(2);
|
|
|
|
if (X86ScalarSSE) {
|
|
|
|
// FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
|
|
|
|
// shouldn't be necessary except that RFP cannot be live across
|
|
|
|
// multiple blocks. When stackifier is fixed, they can be uncoupled.
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
|
|
|
|
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
|
|
Tys.clear();
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(RetVal);
|
|
|
|
Ops.push_back(StackSlot);
|
|
|
|
Ops.push_back(DAG.getValueType(RetTyVT));
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
|
|
|
|
RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
Chain = RetVal.getValue(1);
|
|
|
|
}
|
2006-01-05 00:27:02 +00:00
|
|
|
|
2006-02-17 00:03:04 +00:00
|
|
|
if (RetTyVT == MVT::f32 && !X86ScalarSSE)
|
|
|
|
// FIXME: we would really like to remember that this FP_ROUND
|
|
|
|
// operation is okay to eliminate if we allow excess FP precision.
|
|
|
|
RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
|
|
|
|
break;
|
|
|
|
}
|
2006-04-28 21:29:37 +00:00
|
|
|
case MVT::Vector: {
|
|
|
|
const PackedType *PTy = cast<PackedType>(RetTy);
|
|
|
|
MVT::ValueType EVT;
|
|
|
|
MVT::ValueType LVT;
|
|
|
|
unsigned NumRegs = getPackedTypeBreakdown(PTy, EVT, LVT);
|
|
|
|
assert(NumRegs == 1 && "Unsupported type!");
|
|
|
|
RetVal = DAG.getCopyFromReg(Chain, X86::XMM0, EVT, InFlag);
|
|
|
|
Chain = RetVal.getValue(1);
|
|
|
|
break;
|
|
|
|
}
|
2006-02-17 00:03:04 +00:00
|
|
|
}
|
2006-01-05 00:27:02 +00:00
|
|
|
}
|
2006-02-17 00:03:04 +00:00
|
|
|
|
|
|
|
return std::make_pair(RetVal, Chain);
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Fast Calling Convention implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// The X86 'fast' calling convention passes up to two integer arguments in
|
|
|
|
// registers (an appropriate portion of EAX/EDX), passes arguments in C order,
|
|
|
|
// and requires that the callee pop its arguments off the stack (allowing proper
|
|
|
|
// tail calls), and has the same return value conventions as C calling convs.
|
|
|
|
//
|
|
|
|
// This calling convention always arranges for the callee pop value to be 8n+4
|
|
|
|
// bytes, which is needed for tail recursion elimination and stack alignment
|
|
|
|
// reasons.
|
|
|
|
//
|
|
|
|
// Note that this can be enhanced in the future to pass fp vals in registers
|
|
|
|
// (when we have a global fp allocator) and do other tricks.
|
|
|
|
//
|
|
|
|
|
2006-03-17 17:27:47 +00:00
|
|
|
// FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments
|
|
|
|
// to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and
|
|
|
|
// EDX". Anything more is illegal.
|
|
|
|
//
|
|
|
|
// FIXME: The linscan register allocator currently has problem with
|
2006-03-24 07:12:19 +00:00
|
|
|
// coalescing. At the time of this writing, whenever it decides to coalesce
|
2006-03-17 17:27:47 +00:00
|
|
|
// a physreg with a virtreg, this increases the size of the physreg's live
|
|
|
|
// range, and the live range cannot ever be reduced. This causes problems if
|
2006-03-24 07:12:19 +00:00
|
|
|
// too many physregs are coaleced with virtregs, which can cause the register
|
2006-03-17 17:27:47 +00:00
|
|
|
// allocator to wedge itself.
|
|
|
|
//
|
|
|
|
// This code triggers this problem more often if we pass args in registers,
|
|
|
|
// so disable it until this is fixed.
|
|
|
|
//
|
|
|
|
// NOTE: this isn't marked const, so that GCC doesn't emit annoying warnings
|
|
|
|
// about code being dead.
|
|
|
|
//
|
|
|
|
static unsigned FASTCC_NUM_INT_ARGS_INREGS = 0;
|
2006-03-17 05:10:20 +00:00
|
|
|
|
2005-11-15 00:40:23 +00:00
|
|
|
|
2006-04-27 08:31:10 +00:00
|
|
|
/// HowToPassFastCCArgument - Returns how an formal argument of the specified
|
|
|
|
/// type should be passed. If it is through stack, returns the size of the stack
|
|
|
|
/// frame; if it is through integer or XMM register, returns the number of
|
|
|
|
/// integer or XMM registers are needed.
|
2006-04-27 01:32:22 +00:00
|
|
|
static void
|
2006-04-27 08:31:10 +00:00
|
|
|
HowToPassFastCCArgument(MVT::ValueType ObjectVT,
|
|
|
|
unsigned NumIntRegs, unsigned NumXMMRegs,
|
|
|
|
unsigned &ObjSize, unsigned &ObjIntRegs,
|
|
|
|
unsigned &ObjXMMRegs) {
|
2006-04-27 01:32:22 +00:00
|
|
|
ObjSize = 0;
|
|
|
|
NumIntRegs = 0;
|
|
|
|
|
|
|
|
switch (ObjectVT) {
|
|
|
|
default: assert(0 && "Unhandled argument type!");
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
|
2006-04-27 05:35:28 +00:00
|
|
|
ObjIntRegs = 1;
|
2006-04-27 01:32:22 +00:00
|
|
|
else
|
|
|
|
ObjSize = 1;
|
|
|
|
break;
|
|
|
|
case MVT::i16:
|
|
|
|
if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
|
2006-04-27 05:35:28 +00:00
|
|
|
ObjIntRegs = 1;
|
2006-04-27 01:32:22 +00:00
|
|
|
else
|
|
|
|
ObjSize = 2;
|
|
|
|
break;
|
|
|
|
case MVT::i32:
|
|
|
|
if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
|
2006-04-27 05:35:28 +00:00
|
|
|
ObjIntRegs = 1;
|
2006-04-27 01:32:22 +00:00
|
|
|
else
|
|
|
|
ObjSize = 4;
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) {
|
2006-04-27 05:35:28 +00:00
|
|
|
ObjIntRegs = 2;
|
2006-04-27 01:32:22 +00:00
|
|
|
} else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) {
|
2006-04-27 05:35:28 +00:00
|
|
|
ObjIntRegs = 1;
|
2006-04-27 01:32:22 +00:00
|
|
|
ObjSize = 4;
|
|
|
|
} else
|
|
|
|
ObjSize = 8;
|
|
|
|
case MVT::f32:
|
|
|
|
ObjSize = 4;
|
|
|
|
break;
|
|
|
|
case MVT::f64:
|
|
|
|
ObjSize = 8;
|
|
|
|
break;
|
2006-04-27 08:31:10 +00:00
|
|
|
case MVT::v16i8:
|
|
|
|
case MVT::v8i16:
|
|
|
|
case MVT::v4i32:
|
|
|
|
case MVT::v2i64:
|
|
|
|
case MVT::v4f32:
|
|
|
|
case MVT::v2f64:
|
|
|
|
if (NumXMMRegs < 3)
|
|
|
|
ObjXMMRegs = 1;
|
|
|
|
else
|
|
|
|
ObjSize = 16;
|
|
|
|
break;
|
2006-04-27 01:32:22 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-26 01:20:17 +00:00
|
|
|
void
|
2006-04-27 01:32:22 +00:00
|
|
|
X86TargetLowering::PreprocessFastCCArguments(std::vector<SDOperand>Args,
|
|
|
|
Function &F, SelectionDAG &DAG) {
|
|
|
|
unsigned NumArgs = Args.size();
|
2006-04-26 01:20:17 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
|
2006-04-27 01:32:22 +00:00
|
|
|
// Add DAG nodes to load the arguments... On entry to a function the stack
|
|
|
|
// frame looks like this:
|
|
|
|
//
|
|
|
|
// [ESP] -- return address
|
|
|
|
// [ESP + 4] -- first nonreg argument (leftmost lexically)
|
|
|
|
// [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
|
|
|
|
// ...
|
2006-04-26 01:20:17 +00:00
|
|
|
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
|
|
|
|
|
|
|
|
// Keep track of the number of integer regs passed so far. This can be either
|
|
|
|
// 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
|
|
|
|
// used).
|
|
|
|
unsigned NumIntRegs = 0;
|
2006-04-27 08:31:10 +00:00
|
|
|
unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
|
|
|
|
unsigned XMMArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
|
2006-04-26 01:20:17 +00:00
|
|
|
|
|
|
|
for (unsigned i = 0; i < NumArgs; ++i) {
|
2006-04-27 01:32:22 +00:00
|
|
|
SDOperand Op = Args[i];
|
|
|
|
std::vector<SDOperand> Objs = getFormalArgObjects(Op);
|
|
|
|
for (std::vector<SDOperand>::iterator I = Objs.begin(), E = Objs.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
SDOperand Obj = *I;
|
|
|
|
MVT::ValueType ObjectVT = Obj.getValueType();
|
|
|
|
unsigned ArgIncrement = 4;
|
|
|
|
unsigned ObjSize = 0;
|
2006-04-27 05:35:28 +00:00
|
|
|
unsigned ObjIntRegs = 0;
|
2006-04-27 08:31:10 +00:00
|
|
|
unsigned ObjXMMRegs = 0;
|
2006-04-27 01:32:22 +00:00
|
|
|
|
2006-04-27 08:31:10 +00:00
|
|
|
HowToPassFastCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
|
|
|
|
ObjSize, ObjIntRegs, ObjXMMRegs);
|
|
|
|
if (ObjSize >= 8)
|
|
|
|
ArgIncrement = ObjSize;
|
2006-04-27 01:32:22 +00:00
|
|
|
|
|
|
|
unsigned Reg;
|
|
|
|
std::pair<FALocInfo,FALocInfo> Loc = std::make_pair(FALocInfo(),
|
|
|
|
FALocInfo());
|
2006-04-27 05:35:28 +00:00
|
|
|
if (ObjIntRegs) {
|
|
|
|
switch (ObjectVT) {
|
|
|
|
default: assert(0 && "Unhandled argument type!");
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
Reg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
|
|
|
|
X86::R8RegisterClass);
|
|
|
|
Loc.first.Kind = FALocInfo::LiveInRegLoc;
|
|
|
|
Loc.first.Loc = Reg;
|
|
|
|
Loc.first.Typ = MVT::i8;
|
|
|
|
break;
|
|
|
|
case MVT::i16:
|
|
|
|
Reg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
|
|
|
|
X86::R16RegisterClass);
|
|
|
|
Loc.first.Kind = FALocInfo::LiveInRegLoc;
|
|
|
|
Loc.first.Loc = Reg;
|
|
|
|
Loc.first.Typ = MVT::i16;
|
|
|
|
break;
|
|
|
|
case MVT::i32:
|
|
|
|
Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
|
|
|
|
X86::R32RegisterClass);
|
|
|
|
Loc.first.Kind = FALocInfo::LiveInRegLoc;
|
|
|
|
Loc.first.Loc = Reg;
|
|
|
|
Loc.first.Typ = MVT::i32;
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
|
|
|
|
X86::R32RegisterClass);
|
|
|
|
Loc.first.Kind = FALocInfo::LiveInRegLoc;
|
|
|
|
Loc.first.Loc = Reg;
|
|
|
|
Loc.first.Typ = MVT::i32;
|
|
|
|
if (ObjIntRegs == 2) {
|
|
|
|
Reg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
|
|
|
|
Loc.second.Kind = FALocInfo::LiveInRegLoc;
|
|
|
|
Loc.second.Loc = Reg;
|
|
|
|
Loc.second.Typ = MVT::i32;
|
|
|
|
}
|
|
|
|
break;
|
2006-04-27 08:31:10 +00:00
|
|
|
case MVT::v16i8:
|
|
|
|
case MVT::v8i16:
|
|
|
|
case MVT::v4i32:
|
|
|
|
case MVT::v2i64:
|
|
|
|
case MVT::v4f32:
|
|
|
|
case MVT::v2f64:
|
|
|
|
Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
|
|
|
|
Loc.first.Kind = FALocInfo::LiveInRegLoc;
|
|
|
|
Loc.first.Loc = Reg;
|
|
|
|
Loc.first.Typ = ObjectVT;
|
|
|
|
break;
|
2006-04-27 05:35:28 +00:00
|
|
|
}
|
2006-04-27 05:44:50 +00:00
|
|
|
NumIntRegs += ObjIntRegs;
|
2006-04-27 08:31:10 +00:00
|
|
|
NumXMMRegs += ObjXMMRegs;
|
2006-04-26 01:20:17 +00:00
|
|
|
}
|
2006-04-27 01:32:22 +00:00
|
|
|
if (ObjSize) {
|
|
|
|
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
|
2006-04-27 05:35:28 +00:00
|
|
|
if (ObjectVT == MVT::i64 && ObjIntRegs) {
|
2006-04-27 01:32:22 +00:00
|
|
|
Loc.second.Kind = FALocInfo::StackFrameLoc;
|
|
|
|
Loc.second.Loc = FI;
|
|
|
|
} else {
|
|
|
|
Loc.first.Kind = FALocInfo::StackFrameLoc;
|
|
|
|
Loc.first.Loc = FI;
|
|
|
|
}
|
|
|
|
ArgOffset += ArgIncrement; // Move on to the next argument.
|
2006-04-26 01:20:17 +00:00
|
|
|
}
|
|
|
|
|
2006-04-27 01:32:22 +00:00
|
|
|
FormalArgLocs.push_back(Loc);
|
|
|
|
}
|
2006-04-26 01:20:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
|
|
|
|
// arguments and the arguments after the retaddr has been pushed are aligned.
|
|
|
|
if ((ArgOffset & 7) == 0)
|
|
|
|
ArgOffset += 4;
|
2005-11-15 00:40:23 +00:00
|
|
|
|
2006-04-26 01:20:17 +00:00
|
|
|
VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
|
|
|
|
ReturnAddrIndex = 0; // No return address slot generated yet.
|
|
|
|
BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
|
|
|
|
BytesCallerReserves = 0;
|
|
|
|
|
|
|
|
// Finally, inform the code generator which regs we return values in.
|
|
|
|
switch (getValueType(F.getReturnType())) {
|
|
|
|
default: assert(0 && "Unknown type!");
|
|
|
|
case MVT::isVoid: break;
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
case MVT::i32:
|
|
|
|
MF.addLiveOut(X86::EAX);
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
MF.addLiveOut(X86::EAX);
|
|
|
|
MF.addLiveOut(X86::EDX);
|
|
|
|
break;
|
|
|
|
case MVT::f32:
|
|
|
|
case MVT::f64:
|
|
|
|
MF.addLiveOut(X86::ST0);
|
|
|
|
break;
|
2006-04-28 21:29:37 +00:00
|
|
|
case MVT::Vector: {
|
|
|
|
const PackedType *PTy = cast<PackedType>(F.getReturnType());
|
|
|
|
MVT::ValueType EVT;
|
|
|
|
MVT::ValueType LVT;
|
|
|
|
unsigned NumRegs = getPackedTypeBreakdown(PTy, EVT, LVT);
|
|
|
|
assert(NumRegs == 1 && "Unsupported type!");
|
|
|
|
MF.addLiveOut(X86::XMM0);
|
|
|
|
break;
|
|
|
|
}
|
2006-04-26 01:20:17 +00:00
|
|
|
}
|
|
|
|
}
|
2006-04-28 21:29:37 +00:00
|
|
|
|
2006-04-26 01:20:17 +00:00
|
|
|
void
|
|
|
|
X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
unsigned NumArgs = Op.Val->getNumValues();
|
2005-11-15 00:40:23 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
|
2006-04-26 01:20:17 +00:00
|
|
|
for (unsigned i = 0; i < NumArgs; ++i) {
|
2006-04-27 01:32:22 +00:00
|
|
|
MVT::ValueType VT = Op.Val->getValueType(i);
|
|
|
|
std::pair<FALocInfo, FALocInfo> Loc = FormalArgLocs[i];
|
2005-11-15 00:40:23 +00:00
|
|
|
SDOperand ArgValue;
|
2006-04-27 01:32:22 +00:00
|
|
|
if (Loc.first.Kind == FALocInfo::StackFrameLoc) {
|
|
|
|
// Create the SelectionDAG nodes corresponding to a load from this parameter
|
|
|
|
SDOperand FIN = DAG.getFrameIndex(Loc.first.Loc, MVT::i32);
|
|
|
|
ArgValue = DAG.getLoad(Op.Val->getValueType(i),DAG.getEntryNode(), FIN,
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
} else {
|
|
|
|
// Must be a CopyFromReg
|
2006-04-27 08:31:10 +00:00
|
|
|
ArgValue= DAG.getCopyFromReg(DAG.getEntryNode(), Loc.first.Loc,
|
|
|
|
Loc.first.Typ);
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
|
|
|
|
2006-04-27 01:32:22 +00:00
|
|
|
if (Loc.second.Kind != FALocInfo::None) {
|
|
|
|
SDOperand ArgValue2;
|
|
|
|
if (Loc.second.Kind == FALocInfo::StackFrameLoc) {
|
|
|
|
// Create the SelectionDAG nodes corresponding to a load from this parameter
|
|
|
|
SDOperand FIN = DAG.getFrameIndex(Loc.second.Loc, MVT::i32);
|
|
|
|
ArgValue2 = DAG.getLoad(Op.Val->getValueType(i),DAG.getEntryNode(), FIN,
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
} else {
|
|
|
|
// Must be a CopyFromReg
|
2006-04-27 08:31:10 +00:00
|
|
|
ArgValue2 = DAG.getCopyFromReg(DAG.getEntryNode(),
|
2006-04-27 01:32:22 +00:00
|
|
|
Loc.second.Loc, Loc.second.Typ);
|
|
|
|
}
|
|
|
|
ArgValue = DAG.getNode(ISD::BUILD_PAIR, VT, ArgValue, ArgValue2);
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
2006-04-26 01:20:17 +00:00
|
|
|
FormalArgs.push_back(ArgValue);
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
std::pair<SDOperand, SDOperand>
|
|
|
|
X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
|
|
|
|
bool isTailCall, SDOperand Callee,
|
|
|
|
ArgListTy &Args, SelectionDAG &DAG) {
|
|
|
|
// Count how many bytes are to be pushed on the stack.
|
|
|
|
unsigned NumBytes = 0;
|
|
|
|
|
|
|
|
// Keep track of the number of integer regs passed so far. This can be either
|
|
|
|
// 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
|
|
|
|
// used).
|
|
|
|
unsigned NumIntRegs = 0;
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i)
|
|
|
|
switch (getValueType(Args[i].second)) {
|
|
|
|
default: assert(0 && "Unknown value type!");
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
case MVT::i32:
|
2006-03-17 05:10:20 +00:00
|
|
|
if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
|
2005-11-15 00:40:23 +00:00
|
|
|
++NumIntRegs;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// fall through
|
|
|
|
case MVT::f32:
|
|
|
|
NumBytes += 4;
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
2006-03-17 05:10:20 +00:00
|
|
|
if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) {
|
|
|
|
NumIntRegs += 2;
|
2005-11-15 00:40:23 +00:00
|
|
|
break;
|
2006-03-17 05:10:20 +00:00
|
|
|
} else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) {
|
|
|
|
NumIntRegs = FASTCC_NUM_INT_ARGS_INREGS;
|
2005-11-15 00:40:23 +00:00
|
|
|
NumBytes += 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// fall through
|
|
|
|
case MVT::f64:
|
|
|
|
NumBytes += 8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
|
|
|
|
// arguments and the arguments after the retaddr has been pushed are aligned.
|
|
|
|
if ((NumBytes & 7) == 0)
|
|
|
|
NumBytes += 4;
|
|
|
|
|
2006-02-13 09:00:43 +00:00
|
|
|
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
|
2005-11-15 00:40:23 +00:00
|
|
|
|
|
|
|
// Arguments go on the stack in reverse order, as specified by the ABI.
|
|
|
|
unsigned ArgOffset = 0;
|
2006-01-24 06:14:44 +00:00
|
|
|
SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
|
2005-11-15 00:40:23 +00:00
|
|
|
NumIntRegs = 0;
|
|
|
|
std::vector<SDOperand> Stores;
|
|
|
|
std::vector<SDOperand> RegValuesToPass;
|
|
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
|
|
|
switch (getValueType(Args[i].second)) {
|
|
|
|
default: assert(0 && "Unexpected ValueType for argument!");
|
|
|
|
case MVT::i1:
|
2005-12-27 03:02:18 +00:00
|
|
|
Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
|
|
|
|
// Fall through.
|
2005-11-15 00:40:23 +00:00
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
case MVT::i32:
|
2006-03-17 05:10:20 +00:00
|
|
|
if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
|
2005-11-15 00:40:23 +00:00
|
|
|
RegValuesToPass.push_back(Args[i].first);
|
|
|
|
++NumIntRegs;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Fall through
|
|
|
|
case MVT::f32: {
|
|
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
|
|
|
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
|
|
Args[i].first, PtrOff,
|
|
|
|
DAG.getSrcValue(NULL)));
|
|
|
|
ArgOffset += 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case MVT::i64:
|
2006-03-17 05:10:20 +00:00
|
|
|
// Can pass (at least) part of it in regs?
|
|
|
|
if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
|
2005-11-15 00:40:23 +00:00
|
|
|
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
|
|
|
|
Args[i].first, DAG.getConstant(1, MVT::i32));
|
|
|
|
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
|
|
|
|
Args[i].first, DAG.getConstant(0, MVT::i32));
|
|
|
|
RegValuesToPass.push_back(Lo);
|
|
|
|
++NumIntRegs;
|
2006-03-17 05:10:20 +00:00
|
|
|
|
|
|
|
// Pass both parts in regs?
|
|
|
|
if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
|
2005-11-15 00:40:23 +00:00
|
|
|
RegValuesToPass.push_back(Hi);
|
|
|
|
++NumIntRegs;
|
|
|
|
} else {
|
|
|
|
// Pass the high part in memory.
|
|
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
|
|
|
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
|
|
Hi, PtrOff, DAG.getSrcValue(NULL)));
|
|
|
|
ArgOffset += 4;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Fall through
|
|
|
|
case MVT::f64:
|
|
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
|
|
|
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
|
|
Args[i].first, PtrOff,
|
|
|
|
DAG.getSrcValue(NULL)));
|
|
|
|
ArgOffset += 8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!Stores.empty())
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
|
|
|
|
|
|
|
|
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
|
|
|
|
// arguments and the arguments after the retaddr has been pushed are aligned.
|
|
|
|
if ((ArgOffset & 7) == 0)
|
|
|
|
ArgOffset += 4;
|
|
|
|
|
|
|
|
std::vector<MVT::ValueType> RetVals;
|
|
|
|
MVT::ValueType RetTyVT = getValueType(RetTy);
|
|
|
|
|
|
|
|
RetVals.push_back(MVT::Other);
|
|
|
|
|
|
|
|
// The result values produced have to be legal. Promote the result.
|
|
|
|
switch (RetTyVT) {
|
|
|
|
case MVT::isVoid: break;
|
|
|
|
default:
|
|
|
|
RetVals.push_back(RetTyVT);
|
|
|
|
break;
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
RetVals.push_back(MVT::i32);
|
|
|
|
break;
|
|
|
|
case MVT::f32:
|
|
|
|
if (X86ScalarSSE)
|
|
|
|
RetVals.push_back(MVT::f32);
|
|
|
|
else
|
|
|
|
RetVals.push_back(MVT::f64);
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
RetVals.push_back(MVT::i32);
|
|
|
|
RetVals.push_back(MVT::i32);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2006-02-17 00:03:04 +00:00
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
|
|
|
// and flag operands which copy the outgoing args into registers.
|
|
|
|
SDOperand InFlag;
|
|
|
|
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
|
|
|
|
unsigned CCReg;
|
|
|
|
SDOperand RegToPass = RegValuesToPass[i];
|
|
|
|
switch (RegToPass.getValueType()) {
|
|
|
|
default: assert(0 && "Bad thing to pass in regs");
|
|
|
|
case MVT::i8:
|
|
|
|
CCReg = (i == 0) ? X86::AL : X86::DL;
|
|
|
|
break;
|
|
|
|
case MVT::i16:
|
|
|
|
CCReg = (i == 0) ? X86::AX : X86::DX;
|
|
|
|
break;
|
|
|
|
case MVT::i32:
|
|
|
|
CCReg = (i == 0) ? X86::EAX : X86::EDX;
|
|
|
|
break;
|
2006-01-06 00:43:03 +00:00
|
|
|
}
|
2005-11-15 00:40:23 +00:00
|
|
|
|
2006-02-17 00:03:04 +00:00
|
|
|
Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
|
2006-01-06 00:43:03 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
2006-02-17 00:03:04 +00:00
|
|
|
}
|
2005-11-15 00:40:23 +00:00
|
|
|
|
2006-02-17 00:03:04 +00:00
|
|
|
std::vector<MVT::ValueType> NodeTys;
|
|
|
|
NodeTys.push_back(MVT::Other); // Returns a chain
|
|
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(Callee);
|
|
|
|
if (InFlag.Val)
|
2006-01-24 05:17:12 +00:00
|
|
|
Ops.push_back(InFlag);
|
2006-01-06 00:43:03 +00:00
|
|
|
|
2006-02-17 00:03:04 +00:00
|
|
|
// FIXME: Do not generate X86ISD::TAILCALL for now.
|
2006-04-27 08:40:39 +00:00
|
|
|
Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, NodeTys, Ops);
|
2006-02-17 00:03:04 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
|
|
|
NodeTys.clear();
|
|
|
|
NodeTys.push_back(MVT::Other); // Returns a chain
|
|
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
|
|
|
|
Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
|
|
|
SDOperand RetVal;
|
|
|
|
if (RetTyVT != MVT::isVoid) {
|
2006-01-06 00:43:03 +00:00
|
|
|
switch (RetTyVT) {
|
2006-02-17 00:03:04 +00:00
|
|
|
default: assert(0 && "Unknown value type to return!");
|
2006-01-06 00:43:03 +00:00
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
2006-02-17 00:03:04 +00:00
|
|
|
RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
|
|
|
|
Chain = RetVal.getValue(1);
|
|
|
|
if (RetTyVT == MVT::i1)
|
|
|
|
RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
|
|
|
|
break;
|
2006-01-06 00:43:03 +00:00
|
|
|
case MVT::i16:
|
2006-02-17 00:03:04 +00:00
|
|
|
RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
|
|
|
|
Chain = RetVal.getValue(1);
|
2006-01-06 00:43:03 +00:00
|
|
|
break;
|
2006-02-17 00:03:04 +00:00
|
|
|
case MVT::i32:
|
|
|
|
RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
|
|
|
|
Chain = RetVal.getValue(1);
|
2006-01-06 00:43:03 +00:00
|
|
|
break;
|
2006-02-17 00:03:04 +00:00
|
|
|
case MVT::i64: {
|
|
|
|
SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
|
|
|
|
SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
|
|
|
|
Lo.getValue(2));
|
|
|
|
RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
|
|
|
|
Chain = Hi.getValue(1);
|
2006-01-06 00:43:03 +00:00
|
|
|
break;
|
|
|
|
}
|
2006-02-17 00:03:04 +00:00
|
|
|
case MVT::f32:
|
|
|
|
case MVT::f64: {
|
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
Tys.push_back(MVT::f64);
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
|
|
|
|
Chain = RetVal.getValue(1);
|
|
|
|
InFlag = RetVal.getValue(2);
|
|
|
|
if (X86ScalarSSE) {
|
|
|
|
// FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
|
|
|
|
// shouldn't be necessary except that RFP cannot be live across
|
|
|
|
// multiple blocks. When stackifier is fixed, they can be uncoupled.
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
|
|
|
|
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
|
|
Tys.clear();
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(RetVal);
|
|
|
|
Ops.push_back(StackSlot);
|
|
|
|
Ops.push_back(DAG.getValueType(RetTyVT));
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
|
|
|
|
RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
Chain = RetVal.getValue(1);
|
|
|
|
}
|
2006-01-06 00:43:03 +00:00
|
|
|
|
2006-02-17 00:03:04 +00:00
|
|
|
if (RetTyVT == MVT::f32 && !X86ScalarSSE)
|
|
|
|
// FIXME: we would really like to remember that this FP_ROUND
|
|
|
|
// operation is okay to eliminate if we allow excess FP precision.
|
|
|
|
RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2006-01-06 00:43:03 +00:00
|
|
|
}
|
2006-02-17 00:03:04 +00:00
|
|
|
|
|
|
|
return std::make_pair(RetVal, Chain);
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
|
|
|
|
if (ReturnAddrIndex == 0) {
|
|
|
|
// Set up a frame object for the return address.
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
|
|
|
|
}
|
|
|
|
|
|
|
|
return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
std::pair<SDOperand, SDOperand> X86TargetLowering::
|
|
|
|
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
SDOperand Result;
|
|
|
|
if (Depth) // Depths > 0 not supported yet!
|
|
|
|
Result = DAG.getConstant(0, getPointerTy());
|
|
|
|
else {
|
|
|
|
SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
|
|
|
|
if (!isFrameAddress)
|
|
|
|
// Just load the return address
|
|
|
|
Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
else
|
|
|
|
Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
|
|
|
|
DAG.getConstant(4, MVT::i32));
|
|
|
|
}
|
|
|
|
return std::make_pair(Result, Chain);
|
|
|
|
}
|
|
|
|
|
2006-01-11 00:33:36 +00:00
|
|
|
/// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
|
|
|
|
/// which corresponds to the condition code.
|
|
|
|
static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
|
|
|
|
switch (X86CC) {
|
|
|
|
default: assert(0 && "Unknown X86 conditional code!");
|
|
|
|
case X86ISD::COND_A: return X86::JA;
|
|
|
|
case X86ISD::COND_AE: return X86::JAE;
|
|
|
|
case X86ISD::COND_B: return X86::JB;
|
|
|
|
case X86ISD::COND_BE: return X86::JBE;
|
|
|
|
case X86ISD::COND_E: return X86::JE;
|
|
|
|
case X86ISD::COND_G: return X86::JG;
|
|
|
|
case X86ISD::COND_GE: return X86::JGE;
|
|
|
|
case X86ISD::COND_L: return X86::JL;
|
|
|
|
case X86ISD::COND_LE: return X86::JLE;
|
|
|
|
case X86ISD::COND_NE: return X86::JNE;
|
|
|
|
case X86ISD::COND_NO: return X86::JNO;
|
|
|
|
case X86ISD::COND_NP: return X86::JNP;
|
|
|
|
case X86ISD::COND_NS: return X86::JNS;
|
|
|
|
case X86ISD::COND_O: return X86::JO;
|
|
|
|
case X86ISD::COND_P: return X86::JP;
|
|
|
|
case X86ISD::COND_S: return X86::JS;
|
|
|
|
}
|
|
|
|
}
|
2005-11-15 00:40:23 +00:00
|
|
|
|
2006-01-30 23:41:35 +00:00
|
|
|
/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
|
|
|
|
/// specific condition code. It returns a false if it cannot do a direct
|
|
|
|
/// translation. X86CC is the translated CondCode. Flip is set to true if the
|
|
|
|
/// the order of comparison operands should be flipped.
|
2006-04-05 23:38:46 +00:00
|
|
|
static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
|
|
|
|
unsigned &X86CC, bool &Flip) {
|
2006-01-30 23:41:35 +00:00
|
|
|
Flip = false;
|
|
|
|
X86CC = X86ISD::COND_INVALID;
|
2006-01-06 00:43:03 +00:00
|
|
|
if (!isFP) {
|
|
|
|
switch (SetCCOpcode) {
|
|
|
|
default: break;
|
|
|
|
case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
|
|
|
|
case ISD::SETGT: X86CC = X86ISD::COND_G; break;
|
|
|
|
case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
|
|
|
|
case ISD::SETLT: X86CC = X86ISD::COND_L; break;
|
|
|
|
case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
|
|
|
|
case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
|
|
|
|
case ISD::SETULT: X86CC = X86ISD::COND_B; break;
|
|
|
|
case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
|
|
|
|
case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
|
|
|
|
case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// On a floating point condition, the flags are set as follows:
|
|
|
|
// ZF PF CF op
|
|
|
|
// 0 | 0 | 0 | X > Y
|
|
|
|
// 0 | 0 | 1 | X < Y
|
|
|
|
// 1 | 0 | 0 | X == Y
|
|
|
|
// 1 | 1 | 1 | unordered
|
|
|
|
switch (SetCCOpcode) {
|
|
|
|
default: break;
|
|
|
|
case ISD::SETUEQ:
|
|
|
|
case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
|
2006-04-17 07:24:10 +00:00
|
|
|
case ISD::SETOLT: Flip = true; // Fallthrough
|
2006-01-06 00:43:03 +00:00
|
|
|
case ISD::SETOGT:
|
|
|
|
case ISD::SETGT: X86CC = X86ISD::COND_A; break;
|
2006-04-17 07:24:10 +00:00
|
|
|
case ISD::SETOLE: Flip = true; // Fallthrough
|
2006-01-06 00:43:03 +00:00
|
|
|
case ISD::SETOGE:
|
|
|
|
case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
|
2006-04-17 07:24:10 +00:00
|
|
|
case ISD::SETUGT: Flip = true; // Fallthrough
|
2006-01-06 00:43:03 +00:00
|
|
|
case ISD::SETULT:
|
|
|
|
case ISD::SETLT: X86CC = X86ISD::COND_B; break;
|
2006-04-17 07:24:10 +00:00
|
|
|
case ISD::SETUGE: Flip = true; // Fallthrough
|
2006-01-06 00:43:03 +00:00
|
|
|
case ISD::SETULE:
|
|
|
|
case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
|
|
|
|
case ISD::SETONE:
|
|
|
|
case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
|
|
|
|
case ISD::SETUO: X86CC = X86ISD::COND_P; break;
|
|
|
|
case ISD::SETO: X86CC = X86ISD::COND_NP; break;
|
|
|
|
}
|
|
|
|
}
|
2006-01-30 23:41:35 +00:00
|
|
|
|
|
|
|
return X86CC != X86ISD::COND_INVALID;
|
2006-01-06 00:43:03 +00:00
|
|
|
}
|
|
|
|
|
2006-04-05 23:38:46 +00:00
|
|
|
static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC,
|
|
|
|
bool &Flip) {
|
|
|
|
return translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC, Flip);
|
|
|
|
}
|
|
|
|
|
2006-01-11 00:33:36 +00:00
|
|
|
/// hasFPCMov - is there a floating point cmov for the specific X86 condition
|
|
|
|
/// code. Current x86 isa includes the following FP cmov instructions:
|
2006-01-10 20:26:56 +00:00
|
|
|
/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
|
2006-01-11 00:33:36 +00:00
|
|
|
static bool hasFPCMov(unsigned X86CC) {
|
2006-01-10 20:26:56 +00:00
|
|
|
switch (X86CC) {
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
case X86ISD::COND_B:
|
|
|
|
case X86ISD::COND_BE:
|
|
|
|
case X86ISD::COND_E:
|
|
|
|
case X86ISD::COND_P:
|
|
|
|
case X86ISD::COND_A:
|
|
|
|
case X86ISD::COND_AE:
|
|
|
|
case X86ISD::COND_NE:
|
|
|
|
case X86ISD::COND_NP:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-01-11 00:33:36 +00:00
|
|
|
MachineBasicBlock *
|
|
|
|
X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *BB) {
|
2006-01-16 21:21:29 +00:00
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default: assert(false && "Unexpected instr type to insert");
|
|
|
|
case X86::CMOV_FR32:
|
2006-04-10 07:23:14 +00:00
|
|
|
case X86::CMOV_FR64:
|
|
|
|
case X86::CMOV_V4F32:
|
|
|
|
case X86::CMOV_V2F64:
|
|
|
|
case X86::CMOV_V2I64: {
|
2006-01-31 19:43:35 +00:00
|
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the
|
|
|
|
// diamond control-flow pattern. The incoming instruction knows the
|
|
|
|
// destination vreg to set, the condition code register to branch on, the
|
|
|
|
// true/false values to select between, and a branch opcode to use.
|
2006-01-16 21:21:29 +00:00
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
ilist<MachineBasicBlock>::iterator It = BB;
|
|
|
|
++It;
|
2006-01-11 00:33:36 +00:00
|
|
|
|
2006-01-16 21:21:29 +00:00
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// TrueVal = ...
|
|
|
|
// cmpTY ccX, r1, r2
|
|
|
|
// bCC copy1MBB
|
|
|
|
// fallthrough --> copy0MBB
|
|
|
|
MachineBasicBlock *thisMBB = BB;
|
|
|
|
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
|
|
|
|
unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
|
|
|
|
BuildMI(BB, Opc, 1).addMBB(sinkMBB);
|
|
|
|
MachineFunction *F = BB->getParent();
|
|
|
|
F->getBasicBlockList().insert(It, copy0MBB);
|
|
|
|
F->getBasicBlockList().insert(It, sinkMBB);
|
2006-03-27 01:32:24 +00:00
|
|
|
// Update machine-CFG edges by first adding all successors of the current
|
|
|
|
// block to the new block which will contain the Phi node for the select.
|
|
|
|
for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
|
|
|
|
e = BB->succ_end(); i != e; ++i)
|
|
|
|
sinkMBB->addSuccessor(*i);
|
|
|
|
// Next, remove all successors of the current block, and add the true
|
|
|
|
// and fallthrough blocks as its successors.
|
|
|
|
while(!BB->succ_empty())
|
|
|
|
BB->removeSuccessor(BB->succ_begin());
|
2006-01-16 21:21:29 +00:00
|
|
|
BB->addSuccessor(copy0MBB);
|
|
|
|
BB->addSuccessor(sinkMBB);
|
2006-01-11 00:33:36 +00:00
|
|
|
|
2006-01-16 21:21:29 +00:00
|
|
|
// copy0MBB:
|
|
|
|
// %FalseValue = ...
|
|
|
|
// # fallthrough to sinkMBB
|
|
|
|
BB = copy0MBB;
|
2006-01-11 00:33:36 +00:00
|
|
|
|
2006-01-16 21:21:29 +00:00
|
|
|
// Update machine-CFG edges
|
|
|
|
BB->addSuccessor(sinkMBB);
|
2006-01-11 00:33:36 +00:00
|
|
|
|
2006-01-16 21:21:29 +00:00
|
|
|
// sinkMBB:
|
|
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
|
|
// ...
|
|
|
|
BB = sinkMBB;
|
|
|
|
BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
|
|
|
|
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
|
|
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
|
|
|
|
|
|
|
|
delete MI; // The pseudo instruction is gone now.
|
|
|
|
return BB;
|
|
|
|
}
|
|
|
|
|
|
|
|
case X86::FP_TO_INT16_IN_MEM:
|
|
|
|
case X86::FP_TO_INT32_IN_MEM:
|
|
|
|
case X86::FP_TO_INT64_IN_MEM: {
|
|
|
|
// Change the floating point control register to use "round towards zero"
|
|
|
|
// mode when truncating to an integer value.
|
|
|
|
MachineFunction *F = BB->getParent();
|
|
|
|
int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
|
|
|
|
addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
|
|
|
|
|
|
|
|
// Load the old value of the high byte of the control word...
|
|
|
|
unsigned OldCW =
|
|
|
|
F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass);
|
|
|
|
addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
|
|
|
|
|
|
|
|
// Set the high part to be round to zero...
|
|
|
|
addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
|
|
|
|
|
|
|
|
// Reload the modified control word now...
|
|
|
|
addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
|
|
|
|
|
|
|
|
// Restore the memory image of control word to original value
|
|
|
|
addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
|
|
|
|
|
|
|
|
// Get the X86 opcode to use.
|
|
|
|
unsigned Opc;
|
|
|
|
switch (MI->getOpcode()) {
|
2006-01-28 10:34:47 +00:00
|
|
|
default: assert(0 && "illegal opcode!");
|
2006-01-16 21:21:29 +00:00
|
|
|
case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
|
|
|
|
case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
|
|
|
|
case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
|
|
|
|
}
|
|
|
|
|
|
|
|
X86AddressMode AM;
|
|
|
|
MachineOperand &Op = MI->getOperand(0);
|
|
|
|
if (Op.isRegister()) {
|
|
|
|
AM.BaseType = X86AddressMode::RegBase;
|
|
|
|
AM.Base.Reg = Op.getReg();
|
|
|
|
} else {
|
|
|
|
AM.BaseType = X86AddressMode::FrameIndexBase;
|
|
|
|
AM.Base.FrameIndex = Op.getFrameIndex();
|
|
|
|
}
|
|
|
|
Op = MI->getOperand(1);
|
|
|
|
if (Op.isImmediate())
|
|
|
|
AM.Scale = Op.getImmedValue();
|
|
|
|
Op = MI->getOperand(2);
|
|
|
|
if (Op.isImmediate())
|
|
|
|
AM.IndexReg = Op.getImmedValue();
|
|
|
|
Op = MI->getOperand(3);
|
|
|
|
if (Op.isGlobalAddress()) {
|
|
|
|
AM.GV = Op.getGlobal();
|
|
|
|
} else {
|
|
|
|
AM.Disp = Op.getImmedValue();
|
|
|
|
}
|
|
|
|
addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
|
|
|
|
|
|
|
|
// Reload the original control word now.
|
|
|
|
addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
|
|
|
|
|
|
|
|
delete MI; // The pseudo instruction is gone now.
|
|
|
|
return BB;
|
|
|
|
}
|
|
|
|
}
|
2006-01-11 00:33:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// X86 Custom Lowering Hooks
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2006-03-13 23:18:16 +00:00
|
|
|
/// DarwinGVRequiresExtraLoad - true if accessing the GV requires an extra
|
|
|
|
/// load. For Darwin, external and weak symbols are indirect, loading the value
|
|
|
|
/// at address GV rather then the value of GV itself. This means that the
|
|
|
|
/// GlobalAddress must be in the base or index register of the address, not the
|
|
|
|
/// GV offset field.
|
|
|
|
static bool DarwinGVRequiresExtraLoad(GlobalValue *GV) {
|
|
|
|
return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
|
|
|
|
(GV->isExternal() && !GV->hasNotBeenReadFromBytecode()));
|
|
|
|
}
|
|
|
|
|
2006-04-06 23:23:56 +00:00
|
|
|
/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
|
2006-04-07 21:53:05 +00:00
|
|
|
/// true if Op is undef or if its value falls within the specified range (L, H].
|
2006-04-06 23:23:56 +00:00
|
|
|
static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
|
|
|
|
if (Op.getOpcode() == ISD::UNDEF)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Op)->getValue();
|
2006-04-07 21:53:05 +00:00
|
|
|
return (Val >= Low && Val < Hi);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
|
|
|
|
/// true if Op is undef or if its value equal to the specified value.
|
|
|
|
static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
|
|
|
|
if (Op.getOpcode() == ISD::UNDEF)
|
|
|
|
return true;
|
|
|
|
return cast<ConstantSDNode>(Op)->getValue() == Val;
|
2006-04-06 23:23:56 +00:00
|
|
|
}
|
|
|
|
|
2006-03-22 18:59:22 +00:00
|
|
|
/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a shuffle of elements that is suitable for input to PSHUFD.
|
|
|
|
bool X86::isPSHUFDMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
if (N->getNumOperands() != 4)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Check if the value doesn't reference the second vector.
|
2006-03-29 23:07:14 +00:00
|
|
|
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
|
2006-03-31 00:30:29 +00:00
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
|
|
|
if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
|
2006-03-29 23:07:14 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
|
2006-04-05 01:47:37 +00:00
|
|
|
/// specifies a shuffle of elements that is suitable for input to PSHUFHW.
|
2006-03-29 23:07:14 +00:00
|
|
|
bool X86::isPSHUFHWMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
if (N->getNumOperands() != 8)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Lower quadword copied in order.
|
|
|
|
for (unsigned i = 0; i != 4; ++i) {
|
2006-03-31 00:30:29 +00:00
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
|
|
|
if (cast<ConstantSDNode>(Arg)->getValue() != i)
|
2006-03-29 23:07:14 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Upper quadword shuffled.
|
|
|
|
for (unsigned i = 4; i != 8; ++i) {
|
2006-03-31 00:30:29 +00:00
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
|
2006-03-29 23:07:14 +00:00
|
|
|
if (Val < 4 || Val > 7)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
|
2006-04-05 01:47:37 +00:00
|
|
|
/// specifies a shuffle of elements that is suitable for input to PSHUFLW.
|
2006-03-29 23:07:14 +00:00
|
|
|
bool X86::isPSHUFLWMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
if (N->getNumOperands() != 8)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Upper quadword copied in order.
|
2006-04-07 21:53:05 +00:00
|
|
|
for (unsigned i = 4; i != 8; ++i)
|
|
|
|
if (!isUndefOrEqual(N->getOperand(i), i))
|
2006-03-29 23:07:14 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Lower quadword shuffled.
|
2006-04-07 21:53:05 +00:00
|
|
|
for (unsigned i = 0; i != 4; ++i)
|
|
|
|
if (!isUndefOrInRange(N->getOperand(i), 0, 4))
|
2006-03-29 23:07:14 +00:00
|
|
|
return false;
|
2006-03-24 01:18:28 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a shuffle of elements that is suitable for input to SHUFP*.
|
2006-04-20 08:58:49 +00:00
|
|
|
static bool isSHUFPMask(std::vector<SDOperand> &N) {
|
|
|
|
unsigned NumElems = N.size();
|
|
|
|
if (NumElems != 2 && NumElems != 4) return false;
|
2006-03-24 01:18:28 +00:00
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
unsigned Half = NumElems / 2;
|
|
|
|
for (unsigned i = 0; i < Half; ++i)
|
|
|
|
if (!isUndefOrInRange(N[i], 0, NumElems))
|
|
|
|
return false;
|
|
|
|
for (unsigned i = Half; i < NumElems; ++i)
|
|
|
|
if (!isUndefOrInRange(N[i], NumElems, NumElems*2))
|
|
|
|
return false;
|
2006-03-24 02:58:06 +00:00
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
return true;
|
|
|
|
}
|
2006-03-24 01:18:28 +00:00
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
bool X86::isSHUFPMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
|
|
|
|
return ::isSHUFPMask(Ops);
|
|
|
|
}
|
2006-03-22 18:59:22 +00:00
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
/// isCommutedSHUFP - Returns true if the shuffle mask is except
|
|
|
|
/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
|
|
|
|
/// half elements to come from vector 1 (which would equal the dest.) and
|
|
|
|
/// the upper half to come from vector 2.
|
|
|
|
static bool isCommutedSHUFP(std::vector<SDOperand> &Ops) {
|
|
|
|
unsigned NumElems = Ops.size();
|
|
|
|
if (NumElems != 2 && NumElems != 4) return false;
|
|
|
|
|
|
|
|
unsigned Half = NumElems / 2;
|
|
|
|
for (unsigned i = 0; i < Half; ++i)
|
|
|
|
if (!isUndefOrInRange(Ops[i], NumElems, NumElems*2))
|
|
|
|
return false;
|
|
|
|
for (unsigned i = Half; i < NumElems; ++i)
|
|
|
|
if (!isUndefOrInRange(Ops[i], 0, NumElems))
|
|
|
|
return false;
|
2006-03-22 18:59:22 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
static bool isCommutedSHUFP(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
|
|
|
|
return isCommutedSHUFP(Ops);
|
|
|
|
}
|
|
|
|
|
2006-03-24 02:58:06 +00:00
|
|
|
/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
|
|
|
|
bool X86::isMOVHLPSMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
2006-03-28 06:50:32 +00:00
|
|
|
if (N->getNumOperands() != 4)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
|
2006-04-07 21:53:05 +00:00
|
|
|
return isUndefOrEqual(N->getOperand(0), 6) &&
|
|
|
|
isUndefOrEqual(N->getOperand(1), 7) &&
|
|
|
|
isUndefOrEqual(N->getOperand(2), 2) &&
|
|
|
|
isUndefOrEqual(N->getOperand(3), 3);
|
2006-03-28 06:50:32 +00:00
|
|
|
}
|
|
|
|
|
2006-04-06 23:23:56 +00:00
|
|
|
/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
|
|
|
|
bool X86::isMOVLPMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
unsigned NumElems = N->getNumOperands();
|
|
|
|
if (NumElems != 2 && NumElems != 4)
|
|
|
|
return false;
|
|
|
|
|
2006-04-07 21:53:05 +00:00
|
|
|
for (unsigned i = 0; i < NumElems/2; ++i)
|
|
|
|
if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
|
|
|
|
return false;
|
2006-04-06 23:23:56 +00:00
|
|
|
|
2006-04-07 21:53:05 +00:00
|
|
|
for (unsigned i = NumElems/2; i < NumElems; ++i)
|
|
|
|
if (!isUndefOrEqual(N->getOperand(i), i))
|
|
|
|
return false;
|
2006-04-06 23:23:56 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
|
2006-04-19 20:35:22 +00:00
|
|
|
/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
|
|
|
|
/// and MOVLHPS.
|
2006-04-06 23:23:56 +00:00
|
|
|
bool X86::isMOVHPMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
unsigned NumElems = N->getNumOperands();
|
|
|
|
if (NumElems != 2 && NumElems != 4)
|
|
|
|
return false;
|
|
|
|
|
2006-04-07 21:53:05 +00:00
|
|
|
for (unsigned i = 0; i < NumElems/2; ++i)
|
|
|
|
if (!isUndefOrEqual(N->getOperand(i), i))
|
|
|
|
return false;
|
2006-04-06 23:23:56 +00:00
|
|
|
|
|
|
|
for (unsigned i = 0; i < NumElems/2; ++i) {
|
|
|
|
SDOperand Arg = N->getOperand(i + NumElems/2);
|
2006-04-07 21:53:05 +00:00
|
|
|
if (!isUndefOrEqual(Arg, i + NumElems))
|
|
|
|
return false;
|
2006-04-06 23:23:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-03-28 02:43:26 +00:00
|
|
|
/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a shuffle of elements that is suitable for input to UNPCKL.
|
2006-04-20 08:58:49 +00:00
|
|
|
bool static isUNPCKLMask(std::vector<SDOperand> &N, bool V2IsSplat = false) {
|
|
|
|
unsigned NumElems = N.size();
|
2006-03-28 02:43:26 +00:00
|
|
|
if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
|
2006-03-24 02:58:06 +00:00
|
|
|
return false;
|
|
|
|
|
2006-03-28 02:43:26 +00:00
|
|
|
for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
|
2006-04-20 08:58:49 +00:00
|
|
|
SDOperand BitI = N[i];
|
|
|
|
SDOperand BitI1 = N[i+1];
|
2006-04-07 21:53:05 +00:00
|
|
|
if (!isUndefOrEqual(BitI, j))
|
|
|
|
return false;
|
2006-04-20 08:58:49 +00:00
|
|
|
if (V2IsSplat) {
|
|
|
|
if (isUndefOrEqual(BitI1, NumElems))
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
if (!isUndefOrEqual(BitI1, j + NumElems))
|
|
|
|
return false;
|
|
|
|
}
|
2006-03-28 02:43:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
2006-03-24 02:58:06 +00:00
|
|
|
}
|
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
|
2006-03-28 00:39:58 +00:00
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
2006-04-20 08:58:49 +00:00
|
|
|
std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
|
|
|
|
return ::isUNPCKLMask(Ops, V2IsSplat);
|
|
|
|
}
|
2006-03-28 00:39:58 +00:00
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a shuffle of elements that is suitable for input to UNPCKH.
|
|
|
|
bool static isUNPCKHMask(std::vector<SDOperand> &N, bool V2IsSplat = false) {
|
|
|
|
unsigned NumElems = N.size();
|
2006-03-28 00:39:58 +00:00
|
|
|
if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
|
2006-04-20 08:58:49 +00:00
|
|
|
SDOperand BitI = N[i];
|
|
|
|
SDOperand BitI1 = N[i+1];
|
2006-04-07 21:53:05 +00:00
|
|
|
if (!isUndefOrEqual(BitI, j + NumElems/2))
|
|
|
|
return false;
|
2006-04-20 08:58:49 +00:00
|
|
|
if (V2IsSplat) {
|
|
|
|
if (isUndefOrEqual(BitI1, NumElems))
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
if (!isUndefOrEqual(BitI1, j + NumElems/2 + NumElems))
|
|
|
|
return false;
|
|
|
|
}
|
2006-03-28 00:39:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
|
|
|
|
return ::isUNPCKHMask(Ops, V2IsSplat);
|
|
|
|
}
|
|
|
|
|
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27437 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 07:20:06 +00:00
|
|
|
/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
|
|
|
|
/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
|
|
|
|
/// <0, 0, 1, 1>
|
|
|
|
bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
unsigned NumElems = N->getNumOperands();
|
|
|
|
if (NumElems != 4 && NumElems != 8 && NumElems != 16)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
|
|
|
|
SDOperand BitI = N->getOperand(i);
|
|
|
|
SDOperand BitI1 = N->getOperand(i+1);
|
|
|
|
|
2006-04-07 21:53:05 +00:00
|
|
|
if (!isUndefOrEqual(BitI, j))
|
|
|
|
return false;
|
|
|
|
if (!isUndefOrEqual(BitI1, j))
|
|
|
|
return false;
|
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27437 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 07:20:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a shuffle of elements that is suitable for input to MOVSS,
|
|
|
|
/// MOVSD, and MOVD, i.e. setting the lowest element.
|
|
|
|
static bool isMOVLMask(std::vector<SDOperand> &N) {
|
2006-04-20 08:58:49 +00:00
|
|
|
unsigned NumElems = N.size();
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
|
2006-04-20 08:58:49 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!isUndefOrEqual(N[0], NumElems))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
for (unsigned i = 1; i < NumElems; ++i) {
|
|
|
|
SDOperand Arg = N[i];
|
|
|
|
if (!isUndefOrEqual(Arg, i))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
bool X86::isMOVLMask(SDNode *N) {
|
2006-04-11 00:19:04 +00:00
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
2006-04-20 08:58:49 +00:00
|
|
|
std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
return ::isMOVLMask(Ops);
|
2006-04-20 08:58:49 +00:00
|
|
|
}
|
2006-04-11 00:19:04 +00:00
|
|
|
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
|
|
|
|
/// of what x86 movss want. X86 movs requires the lowest element to be lowest
|
2006-04-20 08:58:49 +00:00
|
|
|
/// element of vector 2 and the other elements to come from vector 1 in order.
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false) {
|
2006-04-20 08:58:49 +00:00
|
|
|
unsigned NumElems = Ops.size();
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
|
2006-04-11 00:19:04 +00:00
|
|
|
return false;
|
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
if (!isUndefOrEqual(Ops[0], 0))
|
2006-04-11 00:19:04 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
for (unsigned i = 1; i < NumElems; ++i) {
|
2006-04-20 08:58:49 +00:00
|
|
|
SDOperand Arg = Ops[i];
|
|
|
|
if (V2IsSplat) {
|
|
|
|
if (!isUndefOrEqual(Arg, NumElems))
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
if (!isUndefOrEqual(Arg, i+NumElems))
|
|
|
|
return false;
|
|
|
|
}
|
2006-04-11 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27437 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 07:20:06 +00:00
|
|
|
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false) {
|
2006-04-20 08:58:49 +00:00
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
return isCommutedMOVL(Ops, V2IsSplat);
|
2006-04-20 08:58:49 +00:00
|
|
|
}
|
|
|
|
|
2006-04-14 21:59:03 +00:00
|
|
|
/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
|
|
|
|
bool X86::isMOVSHDUPMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
if (N->getNumOperands() != 4)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Expect 1, 1, 3, 3
|
|
|
|
for (unsigned i = 0; i < 2; ++i) {
|
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
|
|
|
|
if (Val != 1) return false;
|
|
|
|
}
|
2006-04-15 05:37:34 +00:00
|
|
|
|
|
|
|
bool HasHi = false;
|
2006-04-14 21:59:03 +00:00
|
|
|
for (unsigned i = 2; i < 4; ++i) {
|
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
|
|
|
|
if (Val != 3) return false;
|
2006-04-15 05:37:34 +00:00
|
|
|
HasHi = true;
|
2006-04-14 21:59:03 +00:00
|
|
|
}
|
2006-04-15 03:13:24 +00:00
|
|
|
|
2006-04-15 05:37:34 +00:00
|
|
|
// Don't use movshdup if it can be done with a shufps.
|
|
|
|
return HasHi;
|
2006-04-14 21:59:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
|
|
|
|
bool X86::isMOVSLDUPMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
if (N->getNumOperands() != 4)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Expect 0, 0, 2, 2
|
|
|
|
for (unsigned i = 0; i < 2; ++i) {
|
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
|
|
|
|
if (Val != 0) return false;
|
|
|
|
}
|
2006-04-15 05:37:34 +00:00
|
|
|
|
|
|
|
bool HasHi = false;
|
2006-04-14 21:59:03 +00:00
|
|
|
for (unsigned i = 2; i < 4; ++i) {
|
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
|
|
|
|
if (Val != 2) return false;
|
2006-04-15 05:37:34 +00:00
|
|
|
HasHi = true;
|
2006-04-14 21:59:03 +00:00
|
|
|
}
|
2006-04-15 03:13:24 +00:00
|
|
|
|
2006-04-15 05:37:34 +00:00
|
|
|
// Don't use movshdup if it can be done with a shufps.
|
|
|
|
return HasHi;
|
2006-04-14 21:59:03 +00:00
|
|
|
}
|
|
|
|
|
2006-03-22 02:53:00 +00:00
|
|
|
/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
|
|
|
|
/// a splat of a single element.
|
2006-04-17 20:43:08 +00:00
|
|
|
static bool isSplatMask(SDNode *N) {
|
2006-03-22 02:53:00 +00:00
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
// This is a splat operation if each element of the permute is the same, and
|
|
|
|
// if the value doesn't reference the second vector.
|
2006-04-19 23:28:59 +00:00
|
|
|
unsigned NumElems = N->getNumOperands();
|
|
|
|
SDOperand ElementBase;
|
|
|
|
unsigned i = 0;
|
|
|
|
for (; i != NumElems; ++i) {
|
|
|
|
SDOperand Elt = N->getOperand(i);
|
|
|
|
if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) {
|
|
|
|
ElementBase = Elt;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!ElementBase.Val)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
for (; i != NumElems; ++i) {
|
2006-03-31 00:30:29 +00:00
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
2006-04-19 23:28:59 +00:00
|
|
|
if (Arg != ElementBase) return false;
|
2006-03-22 02:53:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Make sure it is a splat of the first vector operand.
|
2006-04-19 23:28:59 +00:00
|
|
|
return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
|
2006-03-22 02:53:00 +00:00
|
|
|
}
|
|
|
|
|
2006-04-17 20:43:08 +00:00
|
|
|
/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
|
|
|
|
/// a splat of a single element and it's a 2 or 4 element mask.
|
|
|
|
bool X86::isSplatMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
2006-04-19 23:28:59 +00:00
|
|
|
// We can only splat 64-bit, and 32-bit quantities with a single instruction.
|
2006-04-17 20:43:08 +00:00
|
|
|
if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
|
|
|
|
return false;
|
|
|
|
return ::isSplatMask(N);
|
|
|
|
}
|
|
|
|
|
2006-03-22 08:01:21 +00:00
|
|
|
/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
|
|
|
|
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
|
|
|
|
/// instructions.
|
|
|
|
unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
|
2006-03-22 02:53:00 +00:00
|
|
|
unsigned NumOperands = N->getNumOperands();
|
|
|
|
unsigned Shift = (NumOperands == 4) ? 2 : 1;
|
|
|
|
unsigned Mask = 0;
|
2006-03-28 23:41:33 +00:00
|
|
|
for (unsigned i = 0; i < NumOperands; ++i) {
|
2006-03-31 00:30:29 +00:00
|
|
|
unsigned Val = 0;
|
|
|
|
SDOperand Arg = N->getOperand(NumOperands-i-1);
|
|
|
|
if (Arg.getOpcode() != ISD::UNDEF)
|
|
|
|
Val = cast<ConstantSDNode>(Arg)->getValue();
|
2006-03-24 01:18:28 +00:00
|
|
|
if (Val >= NumOperands) Val -= NumOperands;
|
2006-03-22 08:01:21 +00:00
|
|
|
Mask |= Val;
|
2006-03-28 23:41:33 +00:00
|
|
|
if (i != NumOperands - 1)
|
|
|
|
Mask <<= Shift;
|
|
|
|
}
|
2006-03-22 08:01:21 +00:00
|
|
|
|
|
|
|
return Mask;
|
|
|
|
}
|
|
|
|
|
2006-03-29 23:07:14 +00:00
|
|
|
/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
|
|
|
|
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
|
|
|
|
/// instructions.
|
|
|
|
unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
|
|
|
|
unsigned Mask = 0;
|
|
|
|
// 8 nodes, but we only care about the last 4.
|
|
|
|
for (unsigned i = 7; i >= 4; --i) {
|
2006-03-31 00:30:29 +00:00
|
|
|
unsigned Val = 0;
|
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() != ISD::UNDEF)
|
|
|
|
Val = cast<ConstantSDNode>(Arg)->getValue();
|
2006-03-29 23:07:14 +00:00
|
|
|
Mask |= (Val - 4);
|
|
|
|
if (i != 4)
|
|
|
|
Mask <<= 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
return Mask;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
|
|
|
|
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
|
|
|
|
/// instructions.
|
|
|
|
unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
|
|
|
|
unsigned Mask = 0;
|
|
|
|
// 8 nodes, but we only care about the first 4.
|
|
|
|
for (int i = 3; i >= 0; --i) {
|
2006-03-31 00:30:29 +00:00
|
|
|
unsigned Val = 0;
|
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() != ISD::UNDEF)
|
|
|
|
Val = cast<ConstantSDNode>(Arg)->getValue();
|
2006-03-29 23:07:14 +00:00
|
|
|
Mask |= Val;
|
|
|
|
if (i != 0)
|
|
|
|
Mask <<= 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
return Mask;
|
|
|
|
}
|
|
|
|
|
2006-04-05 01:47:37 +00:00
|
|
|
/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a 8 element shuffle that can be broken into a pair of
|
|
|
|
/// PSHUFHW and PSHUFLW.
|
|
|
|
static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
|
|
|
|
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
if (N->getNumOperands() != 8)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Lower quadword shuffled.
|
|
|
|
for (unsigned i = 0; i != 4; ++i) {
|
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
|
|
|
|
if (Val > 4)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Upper quadword shuffled.
|
|
|
|
for (unsigned i = 4; i != 8; ++i) {
|
|
|
|
SDOperand Arg = N->getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
|
|
|
|
if (Val < 4 || Val > 7)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-04-06 23:23:56 +00:00
|
|
|
/// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
|
|
|
|
/// values in ther permute mask.
|
|
|
|
static SDOperand CommuteVectorShuffle(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
SDOperand V1 = Op.getOperand(0);
|
|
|
|
SDOperand V2 = Op.getOperand(1);
|
|
|
|
SDOperand Mask = Op.getOperand(2);
|
|
|
|
MVT::ValueType VT = Op.getValueType();
|
|
|
|
MVT::ValueType MaskVT = Mask.getValueType();
|
|
|
|
MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
|
|
|
|
unsigned NumElems = Mask.getNumOperands();
|
|
|
|
std::vector<SDOperand> MaskVec;
|
|
|
|
|
|
|
|
for (unsigned i = 0; i != NumElems; ++i) {
|
|
|
|
SDOperand Arg = Mask.getOperand(i);
|
2006-04-19 22:48:17 +00:00
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) {
|
|
|
|
MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
|
|
|
|
continue;
|
|
|
|
}
|
2006-04-06 23:23:56 +00:00
|
|
|
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
|
|
|
|
if (Val < NumElems)
|
|
|
|
MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
|
|
|
|
else
|
|
|
|
MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
|
|
|
|
}
|
|
|
|
|
|
|
|
Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask);
|
|
|
|
}
|
|
|
|
|
2006-04-19 20:35:22 +00:00
|
|
|
/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
|
|
|
|
/// match movhlps. The lower half elements should come from upper half of
|
|
|
|
/// V1 (and in order), and the upper half elements should come from the upper
|
|
|
|
/// half of V2 (and in order).
|
|
|
|
static bool ShouldXformToMOVHLPS(SDNode *Mask) {
|
|
|
|
unsigned NumElems = Mask->getNumOperands();
|
|
|
|
if (NumElems != 4)
|
|
|
|
return false;
|
|
|
|
for (unsigned i = 0, e = 2; i != e; ++i)
|
|
|
|
if (!isUndefOrEqual(Mask->getOperand(i), i+2))
|
|
|
|
return false;
|
|
|
|
for (unsigned i = 2; i != 4; ++i)
|
|
|
|
if (!isUndefOrEqual(Mask->getOperand(i), i+4))
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-04-06 23:23:56 +00:00
|
|
|
/// isScalarLoadToVector - Returns true if the node is a scalar load that
|
|
|
|
/// is promoted to a vector.
|
2006-04-19 20:35:22 +00:00
|
|
|
static inline bool isScalarLoadToVector(SDNode *N) {
|
|
|
|
if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
|
|
|
|
N = N->getOperand(0).Val;
|
|
|
|
return (N->getOpcode() == ISD::LOAD);
|
2006-04-06 23:23:56 +00:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-04-19 20:35:22 +00:00
|
|
|
/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
|
|
|
|
/// match movlp{s|d}. The lower half elements should come from lower half of
|
|
|
|
/// V1 (and in order), and the upper half elements should come from the upper
|
|
|
|
/// half of V2 (and in order). And since V1 will become the source of the
|
|
|
|
/// MOVLP, it must be either a vector load or a scalar load to vector.
|
|
|
|
static bool ShouldXformToMOVLP(SDNode *V1, SDNode *Mask) {
|
|
|
|
if (V1->getOpcode() != ISD::LOAD && !isScalarLoadToVector(V1))
|
|
|
|
return false;
|
2006-04-06 23:23:56 +00:00
|
|
|
|
2006-04-19 20:35:22 +00:00
|
|
|
unsigned NumElems = Mask->getNumOperands();
|
|
|
|
if (NumElems != 2 && NumElems != 4)
|
|
|
|
return false;
|
|
|
|
for (unsigned i = 0, e = NumElems/2; i != e; ++i)
|
|
|
|
if (!isUndefOrEqual(Mask->getOperand(i), i))
|
|
|
|
return false;
|
|
|
|
for (unsigned i = NumElems/2; i != NumElems; ++i)
|
|
|
|
if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
|
|
|
|
return false;
|
|
|
|
return true;
|
2006-04-06 23:23:56 +00:00
|
|
|
}
|
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
|
|
|
|
/// all the same.
|
|
|
|
static bool isSplatVector(SDNode *N) {
|
|
|
|
if (N->getOpcode() != ISD::BUILD_VECTOR)
|
|
|
|
return false;
|
2006-04-06 23:23:56 +00:00
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
SDOperand SplatValue = N->getOperand(0);
|
|
|
|
for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
|
|
|
|
if (N->getOperand(i) != SplatValue)
|
2006-04-06 23:23:56 +00:00
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
|
|
|
|
/// that point to V2 points to its first element.
|
|
|
|
static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
|
|
|
|
assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
|
|
|
|
|
|
|
|
bool Changed = false;
|
|
|
|
std::vector<SDOperand> MaskVec;
|
|
|
|
unsigned NumElems = Mask.getNumOperands();
|
|
|
|
for (unsigned i = 0; i != NumElems; ++i) {
|
|
|
|
SDOperand Arg = Mask.getOperand(i);
|
|
|
|
if (Arg.getOpcode() != ISD::UNDEF) {
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
|
|
|
|
if (Val > NumElems) {
|
|
|
|
Arg = DAG.getConstant(NumElems, Arg.getValueType());
|
|
|
|
Changed = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
MaskVec.push_back(Arg);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Changed)
|
|
|
|
Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), MaskVec);
|
|
|
|
return Mask;
|
|
|
|
}
|
|
|
|
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
|
|
|
|
/// operation of specified width.
|
|
|
|
static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
|
2006-04-20 08:58:49 +00:00
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
|
|
|
|
MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
|
|
|
|
|
|
|
|
std::vector<SDOperand> MaskVec;
|
|
|
|
MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
|
|
|
|
for (unsigned i = 1; i != NumElems; ++i)
|
|
|
|
MaskVec.push_back(DAG.getConstant(i, BaseVT));
|
|
|
|
return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
|
|
|
|
}
|
|
|
|
|
2006-04-17 20:43:08 +00:00
|
|
|
/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
|
|
|
|
/// of specified width.
|
|
|
|
static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
|
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
|
|
|
|
MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
|
|
|
|
std::vector<SDOperand> MaskVec;
|
|
|
|
for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
|
|
|
|
MaskVec.push_back(DAG.getConstant(i, BaseVT));
|
|
|
|
MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
|
|
|
|
}
|
|
|
|
return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
|
|
|
|
}
|
|
|
|
|
2006-04-20 08:58:49 +00:00
|
|
|
/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
|
|
|
|
/// of specified width.
|
|
|
|
static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
|
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
|
|
|
|
MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
|
|
|
|
unsigned Half = NumElems/2;
|
|
|
|
std::vector<SDOperand> MaskVec;
|
|
|
|
for (unsigned i = 0; i != Half; ++i) {
|
|
|
|
MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
|
|
|
|
MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
|
|
|
|
}
|
|
|
|
return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
|
|
|
|
}
|
|
|
|
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
/// getZeroVector - Returns a vector of specified type with all zero elements.
|
|
|
|
///
|
|
|
|
static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
|
|
|
|
assert(MVT::isVector(VT) && "Expected a vector type");
|
|
|
|
unsigned NumElems = getVectorNumElements(VT);
|
|
|
|
MVT::ValueType EVT = MVT::getVectorBaseType(VT);
|
|
|
|
bool isFP = MVT::isFloatingPoint(EVT);
|
|
|
|
SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
|
|
|
|
std::vector<SDOperand> ZeroVec(NumElems, Zero);
|
|
|
|
return DAG.getNode(ISD::BUILD_VECTOR, VT, ZeroVec);
|
|
|
|
}
|
|
|
|
|
2006-04-17 20:43:08 +00:00
|
|
|
/// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
|
|
|
|
///
|
|
|
|
static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
SDOperand V1 = Op.getOperand(0);
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
SDOperand Mask = Op.getOperand(2);
|
2006-04-17 20:43:08 +00:00
|
|
|
MVT::ValueType VT = Op.getValueType();
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
unsigned NumElems = Mask.getNumOperands();
|
|
|
|
Mask = getUnpacklMask(NumElems, DAG);
|
2006-04-17 20:43:08 +00:00
|
|
|
while (NumElems != 4) {
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
|
2006-04-17 20:43:08 +00:00
|
|
|
NumElems >>= 1;
|
|
|
|
}
|
|
|
|
V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
|
|
|
|
|
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
Mask = getZeroVector(MaskVT, DAG);
|
2006-04-17 20:43:08 +00:00
|
|
|
SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
|
2006-04-17 20:43:08 +00:00
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
|
|
|
|
}
|
|
|
|
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
/// isZeroNode - Returns true if Elt is a constant zero or a floating point
|
|
|
|
/// constant +0.0.
|
|
|
|
static inline bool isZeroNode(SDOperand Elt) {
|
|
|
|
return ((isa<ConstantSDNode>(Elt) &&
|
|
|
|
cast<ConstantSDNode>(Elt)->getValue() == 0) ||
|
|
|
|
(isa<ConstantFPSDNode>(Elt) &&
|
|
|
|
cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
|
|
|
|
}
|
|
|
|
|
Revamp build_vector lowering to take advantage of movss and movd instructions.
movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27939 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 23:03:30 +00:00
|
|
|
/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
|
|
|
|
/// vector and zero or undef vector.
|
|
|
|
static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
unsigned NumElems, unsigned Idx,
|
Revamp build_vector lowering to take advantage of movss and movd instructions.
movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27939 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 23:03:30 +00:00
|
|
|
bool isZero, SelectionDAG &DAG) {
|
|
|
|
SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
|
|
|
|
MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
|
|
|
|
SDOperand Zero = DAG.getConstant(0, EVT);
|
|
|
|
std::vector<SDOperand> MaskVec(NumElems, Zero);
|
|
|
|
MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
|
|
|
|
SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
|
Revamp build_vector lowering to take advantage of movss and movd instructions.
movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27939 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 23:03:30 +00:00
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
}
|
|
|
|
|
2006-04-24 18:01:45 +00:00
|
|
|
/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
|
|
|
|
///
|
|
|
|
static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
|
|
|
|
unsigned NumNonZero, unsigned NumZero,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
if (NumNonZero > 8)
|
|
|
|
return SDOperand();
|
|
|
|
|
|
|
|
SDOperand V(0, 0);
|
|
|
|
bool First = true;
|
|
|
|
for (unsigned i = 0; i < 16; ++i) {
|
|
|
|
bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
|
|
|
|
if (ThisIsNonZero && First) {
|
|
|
|
if (NumZero)
|
|
|
|
V = getZeroVector(MVT::v8i16, DAG);
|
|
|
|
else
|
|
|
|
V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
|
|
|
|
First = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((i & 1) != 0) {
|
|
|
|
SDOperand ThisElt(0, 0), LastElt(0, 0);
|
|
|
|
bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
|
|
|
|
if (LastIsNonZero) {
|
|
|
|
LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
|
|
|
|
}
|
|
|
|
if (ThisIsNonZero) {
|
|
|
|
ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
|
|
|
|
ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
|
|
|
|
ThisElt, DAG.getConstant(8, MVT::i8));
|
|
|
|
if (LastIsNonZero)
|
|
|
|
ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
|
|
|
|
} else
|
|
|
|
ThisElt = LastElt;
|
|
|
|
|
|
|
|
if (ThisElt.Val)
|
|
|
|
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
|
|
|
|
DAG.getConstant(i/2, MVT::i32));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16.
|
|
|
|
///
|
|
|
|
static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
|
|
|
|
unsigned NumNonZero, unsigned NumZero,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
if (NumNonZero > 4)
|
|
|
|
return SDOperand();
|
|
|
|
|
|
|
|
SDOperand V(0, 0);
|
|
|
|
bool First = true;
|
|
|
|
for (unsigned i = 0; i < 8; ++i) {
|
|
|
|
bool isNonZero = (NonZeros & (1 << i)) != 0;
|
|
|
|
if (isNonZero) {
|
|
|
|
if (First) {
|
|
|
|
if (NumZero)
|
|
|
|
V = getZeroVector(MVT::v8i16, DAG);
|
|
|
|
else
|
|
|
|
V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
|
|
|
|
First = false;
|
|
|
|
}
|
|
|
|
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
|
|
|
|
DAG.getConstant(i, MVT::i32));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return V;
|
|
|
|
}
|
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
// All zero's are handled with pxor.
|
|
|
|
if (ISD::isBuildVectorAllZeros(Op.Val))
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
// All one's are handled with pcmpeqd.
|
|
|
|
if (ISD::isBuildVectorAllOnes(Op.Val))
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
MVT::ValueType VT = Op.getValueType();
|
|
|
|
MVT::ValueType EVT = MVT::getVectorBaseType(VT);
|
|
|
|
unsigned EVTBits = MVT::getSizeInBits(EVT);
|
|
|
|
|
|
|
|
unsigned NumElems = Op.getNumOperands();
|
|
|
|
unsigned NumZero = 0;
|
|
|
|
unsigned NumNonZero = 0;
|
|
|
|
unsigned NonZeros = 0;
|
|
|
|
std::set<SDOperand> Values;
|
|
|
|
for (unsigned i = 0; i < NumElems; ++i) {
|
|
|
|
SDOperand Elt = Op.getOperand(i);
|
|
|
|
if (Elt.getOpcode() != ISD::UNDEF) {
|
|
|
|
Values.insert(Elt);
|
|
|
|
if (isZeroNode(Elt))
|
|
|
|
NumZero++;
|
|
|
|
else {
|
|
|
|
NonZeros |= (1 << i);
|
|
|
|
NumNonZero++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (NumNonZero == 0)
|
|
|
|
// Must be a mix of zero and undef. Return a zero vector.
|
|
|
|
return getZeroVector(VT, DAG);
|
|
|
|
|
|
|
|
// Splat is obviously ok. Let legalizer expand it to a shuffle.
|
|
|
|
if (Values.size() == 1)
|
|
|
|
return SDOperand();
|
|
|
|
|
|
|
|
// Special case for single non-zero element.
|
|
|
|
if (NumNonZero == 1) {
|
|
|
|
unsigned Idx = CountTrailingZeros_32(NonZeros);
|
|
|
|
SDOperand Item = Op.getOperand(Idx);
|
|
|
|
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
|
|
|
|
if (Idx == 0)
|
|
|
|
// Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
|
|
|
|
return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
|
|
|
|
NumZero > 0, DAG);
|
|
|
|
|
|
|
|
if (EVTBits == 32) {
|
|
|
|
// Turn it into a shuffle of zero and zero-extended scalar to vector.
|
|
|
|
Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
|
|
|
|
DAG);
|
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
|
|
|
|
MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
|
|
|
|
std::vector<SDOperand> MaskVec;
|
|
|
|
for (unsigned i = 0; i < NumElems; i++)
|
|
|
|
MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
|
|
|
|
SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
|
|
|
|
DAG.getNode(ISD::UNDEF, VT), Mask);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Let legalizer expand 2-widde build_vector's.
|
|
|
|
if (EVTBits == 64)
|
|
|
|
return SDOperand();
|
|
|
|
|
|
|
|
// If element VT is < 32 bits, convert it to inserts into a zero vector.
|
|
|
|
if (EVTBits == 8) {
|
|
|
|
SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG);
|
|
|
|
if (V.Val) return V;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (EVTBits == 16) {
|
|
|
|
SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG);
|
|
|
|
if (V.Val) return V;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If element VT is == 32 bits, turn it into a number of shuffles.
|
|
|
|
std::vector<SDOperand> V(NumElems);
|
|
|
|
if (NumElems == 4 && NumZero > 0) {
|
|
|
|
for (unsigned i = 0; i < 4; ++i) {
|
|
|
|
bool isZero = !(NonZeros & (1 << i));
|
|
|
|
if (isZero)
|
|
|
|
V[i] = getZeroVector(VT, DAG);
|
|
|
|
else
|
|
|
|
V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < 2; ++i) {
|
|
|
|
switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
|
|
|
|
default: break;
|
|
|
|
case 0:
|
|
|
|
V[i] = V[i*2]; // Must be a zero vector.
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
|
|
|
|
getMOVLMask(NumElems, DAG));
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
|
|
|
|
getMOVLMask(NumElems, DAG));
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
|
|
|
|
getUnpacklMask(NumElems, DAG));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Take advantage of the fact R32 to VR128 scalar_to_vector (i.e. movd)
|
|
|
|
// clears the upper bits.
|
|
|
|
// FIXME: we can do the same for v4f32 case when we know both parts of
|
|
|
|
// the lower half come from scalar_to_vector (loadf32). We should do
|
|
|
|
// that in post legalizer dag combiner with target specific hooks.
|
|
|
|
if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
|
|
|
|
return V[0];
|
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
|
|
|
|
MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
|
|
|
|
std::vector<SDOperand> MaskVec;
|
|
|
|
bool Reverse = (NonZeros & 0x3) == 2;
|
|
|
|
for (unsigned i = 0; i < 2; ++i)
|
|
|
|
if (Reverse)
|
|
|
|
MaskVec.push_back(DAG.getConstant(1-i, EVT));
|
|
|
|
else
|
|
|
|
MaskVec.push_back(DAG.getConstant(i, EVT));
|
|
|
|
Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
|
|
|
|
for (unsigned i = 0; i < 2; ++i)
|
|
|
|
if (Reverse)
|
|
|
|
MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
|
|
|
|
else
|
|
|
|
MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
|
|
|
|
SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Values.size() > 2) {
|
|
|
|
// Expand into a number of unpckl*.
|
|
|
|
// e.g. for v4f32
|
|
|
|
// Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
|
|
|
|
// : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
|
|
|
|
// Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
|
|
|
|
SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
|
|
|
|
for (unsigned i = 0; i < NumElems; ++i)
|
|
|
|
V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
|
|
|
|
NumElems >>= 1;
|
|
|
|
while (NumElems != 0) {
|
|
|
|
for (unsigned i = 0; i < NumElems; ++i)
|
|
|
|
V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
|
|
|
|
UnpckMask);
|
|
|
|
NumElems >>= 1;
|
|
|
|
}
|
|
|
|
return V[0];
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
SDOperand V1 = Op.getOperand(0);
|
|
|
|
SDOperand V2 = Op.getOperand(1);
|
|
|
|
SDOperand PermMask = Op.getOperand(2);
|
|
|
|
MVT::ValueType VT = Op.getValueType();
|
|
|
|
unsigned NumElems = PermMask.getNumOperands();
|
|
|
|
bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
|
|
|
|
bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
|
|
|
|
|
|
|
|
if (isSplatMask(PermMask.Val)) {
|
|
|
|
if (NumElems <= 4) return Op;
|
|
|
|
// Promote it to a v4i32 splat.
|
|
|
|
return PromoteSplat(Op, DAG);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (X86::isMOVLMask(PermMask.Val))
|
|
|
|
return (V1IsUndef) ? V2 : Op;
|
|
|
|
|
|
|
|
if (X86::isMOVSHDUPMask(PermMask.Val) ||
|
|
|
|
X86::isMOVSLDUPMask(PermMask.Val) ||
|
|
|
|
X86::isMOVHLPSMask(PermMask.Val) ||
|
|
|
|
X86::isMOVHPMask(PermMask.Val) ||
|
|
|
|
X86::isMOVLPMask(PermMask.Val))
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
if (ShouldXformToMOVHLPS(PermMask.Val) ||
|
|
|
|
ShouldXformToMOVLP(V1.Val, PermMask.Val))
|
|
|
|
return CommuteVectorShuffle(Op, DAG);
|
|
|
|
|
|
|
|
bool V1IsSplat = isSplatVector(V1.Val) || V1.getOpcode() == ISD::UNDEF;
|
|
|
|
bool V2IsSplat = isSplatVector(V2.Val) || V2.getOpcode() == ISD::UNDEF;
|
|
|
|
if (V1IsSplat && !V2IsSplat) {
|
|
|
|
Op = CommuteVectorShuffle(Op, DAG);
|
|
|
|
V1 = Op.getOperand(0);
|
|
|
|
V2 = Op.getOperand(1);
|
|
|
|
PermMask = Op.getOperand(2);
|
|
|
|
V2IsSplat = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (isCommutedMOVL(PermMask.Val, V2IsSplat)) {
|
|
|
|
if (V2IsUndef) return V1;
|
|
|
|
Op = CommuteVectorShuffle(Op, DAG);
|
|
|
|
V1 = Op.getOperand(0);
|
|
|
|
V2 = Op.getOperand(1);
|
|
|
|
PermMask = Op.getOperand(2);
|
|
|
|
if (V2IsSplat) {
|
|
|
|
// V2 is a splat, so the mask may be malformed. That is, it may point
|
|
|
|
// to any V2 element. The instruction selectior won't like this. Get
|
|
|
|
// a corrected mask and commute to form a proper MOVS{S|D}.
|
|
|
|
SDOperand NewMask = getMOVLMask(NumElems, DAG);
|
|
|
|
if (NewMask.Val != PermMask.Val)
|
|
|
|
Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
|
|
|
|
}
|
|
|
|
return Op;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
|
|
|
|
X86::isUNPCKLMask(PermMask.Val) ||
|
|
|
|
X86::isUNPCKHMask(PermMask.Val))
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
if (V2IsSplat) {
|
|
|
|
// Normalize mask so all entries that point to V2 points to its first
|
|
|
|
// element then try to match unpck{h|l} again. If match, return a
|
|
|
|
// new vector_shuffle with the corrected mask.
|
|
|
|
SDOperand NewMask = NormalizeMask(PermMask, DAG);
|
|
|
|
if (NewMask.Val != PermMask.Val) {
|
|
|
|
if (X86::isUNPCKLMask(PermMask.Val, true)) {
|
|
|
|
SDOperand NewMask = getUnpacklMask(NumElems, DAG);
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
|
|
|
|
} else if (X86::isUNPCKHMask(PermMask.Val, true)) {
|
|
|
|
SDOperand NewMask = getUnpackhMask(NumElems, DAG);
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Normalize the node to match x86 shuffle ops if needed
|
|
|
|
if (V2.getOpcode() != ISD::UNDEF)
|
|
|
|
if (isCommutedSHUFP(PermMask.Val)) {
|
|
|
|
Op = CommuteVectorShuffle(Op, DAG);
|
|
|
|
V1 = Op.getOperand(0);
|
|
|
|
V2 = Op.getOperand(1);
|
|
|
|
PermMask = Op.getOperand(2);
|
|
|
|
}
|
|
|
|
|
|
|
|
// If VT is integer, try PSHUF* first, then SHUFP*.
|
|
|
|
if (MVT::isInteger(VT)) {
|
|
|
|
if (X86::isPSHUFDMask(PermMask.Val) ||
|
|
|
|
X86::isPSHUFHWMask(PermMask.Val) ||
|
|
|
|
X86::isPSHUFLWMask(PermMask.Val)) {
|
|
|
|
if (V2.getOpcode() != ISD::UNDEF)
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
|
|
|
|
DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
|
|
|
|
return Op;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (X86::isSHUFPMask(PermMask.Val))
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
// Handle v8i16 shuffle high / low shuffle node pair.
|
|
|
|
if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
|
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
|
|
|
|
MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
|
|
|
|
std::vector<SDOperand> MaskVec;
|
|
|
|
for (unsigned i = 0; i != 4; ++i)
|
|
|
|
MaskVec.push_back(PermMask.getOperand(i));
|
|
|
|
for (unsigned i = 4; i != 8; ++i)
|
|
|
|
MaskVec.push_back(DAG.getConstant(i, BaseVT));
|
|
|
|
SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
|
|
|
|
V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
|
|
|
|
MaskVec.clear();
|
|
|
|
for (unsigned i = 0; i != 4; ++i)
|
|
|
|
MaskVec.push_back(DAG.getConstant(i, BaseVT));
|
|
|
|
for (unsigned i = 4; i != 8; ++i)
|
|
|
|
MaskVec.push_back(PermMask.getOperand(i));
|
|
|
|
Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// Floating point cases in the other order.
|
|
|
|
if (X86::isSHUFPMask(PermMask.Val))
|
|
|
|
return Op;
|
|
|
|
if (X86::isPSHUFDMask(PermMask.Val) ||
|
|
|
|
X86::isPSHUFHWMask(PermMask.Val) ||
|
|
|
|
X86::isPSHUFLWMask(PermMask.Val)) {
|
|
|
|
if (V2.getOpcode() != ISD::UNDEF)
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
|
|
|
|
DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
|
|
|
|
return Op;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (NumElems == 4) {
|
|
|
|
MVT::ValueType MaskVT = PermMask.getValueType();
|
|
|
|
MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
|
Implement four-wide shuffle with 2 shufps if no more than two elements come
from each vector. e.g.
shuffle(G1, G2, 7, 1, 5, 2)
==>
movaps _G2, %xmm0
shufps $151, _G1, %xmm0
shufps $216, %xmm0, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28011 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 07:03:38 +00:00
|
|
|
std::vector<std::pair<int, int> > Locs;
|
|
|
|
Locs.reserve(NumElems);
|
|
|
|
std::vector<SDOperand> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
|
|
|
|
std::vector<SDOperand> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
|
|
|
|
unsigned NumHi = 0;
|
|
|
|
unsigned NumLo = 0;
|
|
|
|
// If no more than two elements come from either vector. This can be
|
|
|
|
// implemented with two shuffles. First shuffle gather the elements.
|
|
|
|
// The second shuffle, which takes the first shuffle as both of its
|
|
|
|
// vector operands, put the elements into the right order.
|
|
|
|
for (unsigned i = 0; i != NumElems; ++i) {
|
|
|
|
SDOperand Elt = PermMask.getOperand(i);
|
|
|
|
if (Elt.getOpcode() == ISD::UNDEF) {
|
|
|
|
Locs[i] = std::make_pair(-1, -1);
|
|
|
|
} else {
|
|
|
|
unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
|
|
|
|
if (Val < NumElems) {
|
|
|
|
Locs[i] = std::make_pair(0, NumLo);
|
|
|
|
Mask1[NumLo] = Elt;
|
|
|
|
NumLo++;
|
|
|
|
} else {
|
|
|
|
Locs[i] = std::make_pair(1, NumHi);
|
|
|
|
if (2+NumHi < NumElems)
|
|
|
|
Mask1[2+NumHi] = Elt;
|
|
|
|
NumHi++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (NumLo <= 2 && NumHi <= 2) {
|
|
|
|
V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
|
|
|
|
DAG.getNode(ISD::BUILD_VECTOR, MaskVT, Mask1));
|
|
|
|
for (unsigned i = 0; i != NumElems; ++i) {
|
|
|
|
if (Locs[i].first == -1)
|
|
|
|
continue;
|
|
|
|
else {
|
|
|
|
unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
|
|
|
|
Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
|
|
|
|
Mask2[i] = DAG.getConstant(Idx, MaskEVT);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
|
|
|
|
DAG.getNode(ISD::BUILD_VECTOR, MaskVT, Mask2));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Break it into (shuffle shuffle_hi, shuffle_lo).
|
|
|
|
Locs.clear();
|
2006-04-25 20:13:52 +00:00
|
|
|
std::vector<SDOperand> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
|
|
|
|
std::vector<SDOperand> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
|
|
|
|
std::vector<SDOperand> *MaskPtr = &LoMask;
|
|
|
|
unsigned MaskIdx = 0;
|
|
|
|
unsigned LoIdx = 0;
|
|
|
|
unsigned HiIdx = NumElems/2;
|
|
|
|
for (unsigned i = 0; i != NumElems; ++i) {
|
|
|
|
if (i == NumElems/2) {
|
|
|
|
MaskPtr = &HiMask;
|
|
|
|
MaskIdx = 1;
|
|
|
|
LoIdx = 0;
|
|
|
|
HiIdx = NumElems/2;
|
|
|
|
}
|
|
|
|
SDOperand Elt = PermMask.getOperand(i);
|
|
|
|
if (Elt.getOpcode() == ISD::UNDEF) {
|
|
|
|
Locs[i] = std::make_pair(-1, -1);
|
|
|
|
} else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
|
|
|
|
Locs[i] = std::make_pair(MaskIdx, LoIdx);
|
|
|
|
(*MaskPtr)[LoIdx] = Elt;
|
|
|
|
LoIdx++;
|
|
|
|
} else {
|
|
|
|
Locs[i] = std::make_pair(MaskIdx, HiIdx);
|
|
|
|
(*MaskPtr)[HiIdx] = Elt;
|
|
|
|
HiIdx++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
|
|
|
|
DAG.getNode(ISD::BUILD_VECTOR, MaskVT, LoMask));
|
|
|
|
SDOperand HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
|
|
|
|
DAG.getNode(ISD::BUILD_VECTOR, MaskVT, HiMask));
|
|
|
|
std::vector<SDOperand> MaskOps;
|
|
|
|
for (unsigned i = 0; i != NumElems; ++i) {
|
|
|
|
if (Locs[i].first == -1) {
|
|
|
|
MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
|
|
|
|
} else {
|
|
|
|
unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
|
|
|
|
MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
|
|
|
|
DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskOps));
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
if (!isa<ConstantSDNode>(Op.getOperand(1)))
|
|
|
|
return SDOperand();
|
|
|
|
|
|
|
|
MVT::ValueType VT = Op.getValueType();
|
|
|
|
// TODO: handle v16i8.
|
|
|
|
if (MVT::getSizeInBits(VT) == 16) {
|
|
|
|
// Transform it so it match pextrw which produces a 32-bit result.
|
|
|
|
MVT::ValueType EVT = (MVT::ValueType)(VT+1);
|
|
|
|
SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
|
|
|
|
Op.getOperand(0), Op.getOperand(1));
|
|
|
|
SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
|
|
|
|
DAG.getValueType(VT));
|
|
|
|
return DAG.getNode(ISD::TRUNCATE, VT, Assert);
|
|
|
|
} else if (MVT::getSizeInBits(VT) == 32) {
|
|
|
|
SDOperand Vec = Op.getOperand(0);
|
|
|
|
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
|
|
|
if (Idx == 0)
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
// SHUFPS the element to the lowest double word, then movss.
|
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
|
|
|
|
SDOperand IdxNode = DAG.getConstant((Idx < 2) ? Idx : Idx+4,
|
|
|
|
MVT::getVectorBaseType(MaskVT));
|
|
|
|
std::vector<SDOperand> IdxVec;
|
|
|
|
IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
|
|
|
|
IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
|
|
|
|
IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
|
|
|
|
IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
|
|
|
|
SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec);
|
|
|
|
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
|
|
|
|
Vec, Vec, Mask);
|
|
|
|
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
|
|
|
|
DAG.getConstant(0, MVT::i32));
|
|
|
|
} else if (MVT::getSizeInBits(VT) == 64) {
|
|
|
|
SDOperand Vec = Op.getOperand(0);
|
|
|
|
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
|
|
|
if (Idx == 0)
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
// UNPCKHPD the element to the lowest double word, then movsd.
|
|
|
|
// Note if the lower 64 bits of the result of the UNPCKHPD is then stored
|
|
|
|
// to a f64mem, the whole operation is folded into a single MOVHPDmr.
|
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
|
|
|
|
std::vector<SDOperand> IdxVec;
|
|
|
|
IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
|
|
|
|
IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
|
|
|
|
SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec);
|
|
|
|
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
|
|
|
|
Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
|
|
|
|
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
|
|
|
|
DAG.getConstant(0, MVT::i32));
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
// Transform it so it match pinsrw which expects a 16-bit value in a R32
|
|
|
|
// as its second argument.
|
|
|
|
MVT::ValueType VT = Op.getValueType();
|
|
|
|
MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
|
|
|
|
SDOperand N0 = Op.getOperand(0);
|
|
|
|
SDOperand N1 = Op.getOperand(1);
|
|
|
|
SDOperand N2 = Op.getOperand(2);
|
|
|
|
if (MVT::getSizeInBits(BaseVT) == 16) {
|
|
|
|
if (N1.getValueType() != MVT::i32)
|
|
|
|
N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
|
|
|
|
if (N2.getValueType() != MVT::i32)
|
|
|
|
N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
|
|
|
|
return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
|
|
|
|
} else if (MVT::getSizeInBits(BaseVT) == 32) {
|
|
|
|
unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
|
|
|
|
if (Idx == 0) {
|
|
|
|
// Use a movss.
|
|
|
|
N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
|
|
|
|
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
|
|
|
|
MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
|
|
|
|
std::vector<SDOperand> MaskVec;
|
|
|
|
MaskVec.push_back(DAG.getConstant(4, BaseVT));
|
|
|
|
for (unsigned i = 1; i <= 3; ++i)
|
|
|
|
MaskVec.push_back(DAG.getConstant(i, BaseVT));
|
|
|
|
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
|
|
|
|
DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec));
|
|
|
|
} else {
|
|
|
|
// Use two pinsrw instructions to insert a 32 bit value.
|
|
|
|
Idx <<= 1;
|
|
|
|
if (MVT::isFloatingPoint(N1.getValueType())) {
|
|
|
|
if (N1.getOpcode() == ISD::LOAD) {
|
|
|
|
// Just load directly from f32mem to R32.
|
|
|
|
N1 = DAG.getLoad(MVT::i32, N1.getOperand(0), N1.getOperand(1),
|
|
|
|
N1.getOperand(2));
|
|
|
|
} else {
|
|
|
|
N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
|
|
|
|
N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
|
|
|
|
N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
|
|
|
|
DAG.getConstant(0, MVT::i32));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
|
|
|
|
N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
|
|
|
|
DAG.getConstant(Idx, MVT::i32));
|
|
|
|
N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
|
|
|
|
N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
|
|
|
|
DAG.getConstant(Idx+1, MVT::i32));
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
|
|
|
|
return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
|
|
|
|
}
|
|
|
|
|
|
|
|
// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
|
|
|
|
// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
|
|
|
|
// one of the above mentioned nodes. It has to be wrapped because otherwise
|
|
|
|
// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
|
|
|
|
// be used to form addressing mode. These wrapped nodes will be selected
|
|
|
|
// into MOV32ri.
|
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
|
|
|
|
SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
|
|
|
|
DAG.getTargetConstantPool(CP->get(), getPointerTy(),
|
|
|
|
CP->getAlignment()));
|
|
|
|
if (Subtarget->isTargetDarwin()) {
|
|
|
|
// With PIC, the address is actually $g + Offset.
|
|
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC)
|
|
|
|
Result = DAG.getNode(ISD::ADD, getPointerTy(),
|
|
|
|
DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
|
|
|
|
}
|
|
|
|
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
|
|
SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
|
|
|
|
DAG.getTargetGlobalAddress(GV, getPointerTy()));
|
|
|
|
if (Subtarget->isTargetDarwin()) {
|
|
|
|
// With PIC, the address is actually $g + Offset.
|
|
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC)
|
|
|
|
Result = DAG.getNode(ISD::ADD, getPointerTy(),
|
|
|
|
DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
|
|
|
|
|
|
|
|
// For Darwin, external and weak symbols are indirect, so we want to load
|
|
|
|
// the value at address GV, not the value of GV itself. This means that
|
|
|
|
// the GlobalAddress must be in the base or index register of the address,
|
|
|
|
// not the GV offset field.
|
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::Static &&
|
|
|
|
DarwinGVRequiresExtraLoad(GV))
|
|
|
|
Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
|
|
|
|
Result, DAG.getSrcValue(NULL));
|
|
|
|
}
|
|
|
|
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
|
|
|
|
SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
|
|
|
|
DAG.getTargetExternalSymbol(Sym, getPointerTy()));
|
|
|
|
if (Subtarget->isTargetDarwin()) {
|
|
|
|
// With PIC, the address is actually $g + Offset.
|
|
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC)
|
|
|
|
Result = DAG.getNode(ISD::ADD, getPointerTy(),
|
|
|
|
DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
|
|
|
|
}
|
|
|
|
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
|
2006-01-09 18:33:28 +00:00
|
|
|
assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
|
|
|
|
"Not an i64 shift!");
|
|
|
|
bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
|
|
|
|
SDOperand ShOpLo = Op.getOperand(0);
|
|
|
|
SDOperand ShOpHi = Op.getOperand(1);
|
|
|
|
SDOperand ShAmt = Op.getOperand(2);
|
|
|
|
SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
|
2006-01-18 09:26:46 +00:00
|
|
|
DAG.getConstant(31, MVT::i8))
|
2006-01-09 18:33:28 +00:00
|
|
|
: DAG.getConstant(0, MVT::i32);
|
|
|
|
|
|
|
|
SDOperand Tmp2, Tmp3;
|
|
|
|
if (Op.getOpcode() == ISD::SHL_PARTS) {
|
|
|
|
Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
|
|
|
|
Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
|
|
|
|
} else {
|
|
|
|
Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
|
2006-01-19 01:46:14 +00:00
|
|
|
Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
|
2006-01-09 18:33:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
|
|
|
|
ShAmt, DAG.getConstant(32, MVT::i8));
|
|
|
|
|
|
|
|
SDOperand Hi, Lo;
|
2006-01-09 20:49:21 +00:00
|
|
|
SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
|
2006-01-09 18:33:28 +00:00
|
|
|
|
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
Tys.push_back(MVT::i32);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
if (Op.getOpcode() == ISD::SHL_PARTS) {
|
|
|
|
Ops.push_back(Tmp2);
|
|
|
|
Ops.push_back(Tmp3);
|
|
|
|
Ops.push_back(CC);
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
|
|
|
|
InFlag = Hi.getValue(1);
|
|
|
|
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(Tmp3);
|
|
|
|
Ops.push_back(Tmp1);
|
|
|
|
Ops.push_back(CC);
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
|
|
|
|
} else {
|
|
|
|
Ops.push_back(Tmp2);
|
|
|
|
Ops.push_back(Tmp3);
|
|
|
|
Ops.push_back(CC);
|
2006-01-09 22:29:54 +00:00
|
|
|
Ops.push_back(InFlag);
|
2006-01-09 18:33:28 +00:00
|
|
|
Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
|
|
|
|
InFlag = Lo.getValue(1);
|
|
|
|
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(Tmp3);
|
|
|
|
Ops.push_back(Tmp1);
|
|
|
|
Ops.push_back(CC);
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
Tys.clear();
|
|
|
|
Tys.push_back(MVT::i32);
|
|
|
|
Tys.push_back(MVT::i32);
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(Lo);
|
|
|
|
Ops.push_back(Hi);
|
|
|
|
return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
|
2006-04-25 20:13:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
|
|
|
|
Op.getOperand(0).getValueType() >= MVT::i16 &&
|
|
|
|
"Unknown SINT_TO_FP to lower!");
|
2006-01-12 22:54:21 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
SDOperand Result;
|
|
|
|
MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
|
|
|
|
unsigned Size = MVT::getSizeInBits(SrcVT)/8;
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
|
|
|
|
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
|
|
SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other,
|
|
|
|
DAG.getEntryNode(), Op.getOperand(0),
|
|
|
|
StackSlot, DAG.getSrcValue(NULL));
|
|
|
|
|
|
|
|
// Build the FILD
|
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
Tys.push_back(MVT::f64);
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
if (X86ScalarSSE) Tys.push_back(MVT::Flag);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(StackSlot);
|
|
|
|
Ops.push_back(DAG.getValueType(SrcVT));
|
|
|
|
Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
|
|
|
|
Tys, Ops);
|
|
|
|
|
|
|
|
if (X86ScalarSSE) {
|
|
|
|
Chain = Result.getValue(1);
|
|
|
|
SDOperand InFlag = Result.getValue(2);
|
|
|
|
|
|
|
|
// FIXME: Currently the FST is flagged to the FILD_FLAG. This
|
|
|
|
// shouldn't be necessary except that RFP cannot be live across
|
|
|
|
// multiple blocks. When stackifier is fixed, they can be uncoupled.
|
2005-11-15 00:40:23 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2006-04-25 20:13:52 +00:00
|
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
|
2005-11-15 00:40:23 +00:00
|
|
|
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
2006-01-12 22:54:21 +00:00
|
|
|
std::vector<MVT::ValueType> Tys;
|
2006-01-30 08:02:57 +00:00
|
|
|
Tys.push_back(MVT::Other);
|
2005-11-15 00:40:23 +00:00
|
|
|
std::vector<SDOperand> Ops;
|
2006-01-12 22:54:21 +00:00
|
|
|
Ops.push_back(Chain);
|
2006-04-25 20:13:52 +00:00
|
|
|
Ops.push_back(Result);
|
2005-11-15 00:40:23 +00:00
|
|
|
Ops.push_back(StackSlot);
|
2006-04-25 20:13:52 +00:00
|
|
|
Ops.push_back(DAG.getValueType(Op.getValueType()));
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
|
|
|
|
Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
|
|
|
|
DAG.getSrcValue(NULL));
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
|
|
|
|
"Unknown FP_TO_SINT to lower!");
|
|
|
|
// We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
|
|
|
|
// stack slot.
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
|
|
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
|
|
|
|
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
|
|
|
|
|
|
unsigned Opc;
|
|
|
|
switch (Op.getValueType()) {
|
2005-11-15 00:40:23 +00:00
|
|
|
default: assert(0 && "Invalid FP_TO_SINT to lower!");
|
|
|
|
case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
|
|
|
|
case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
|
|
|
|
case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
|
|
|
|
}
|
2006-04-25 20:13:52 +00:00
|
|
|
|
|
|
|
SDOperand Chain = DAG.getEntryNode();
|
|
|
|
SDOperand Value = Op.getOperand(0);
|
|
|
|
if (X86ScalarSSE) {
|
|
|
|
assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
|
|
|
|
Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, StackSlot,
|
|
|
|
DAG.getSrcValue(0));
|
2005-11-20 22:01:40 +00:00
|
|
|
std::vector<MVT::ValueType> Tys;
|
2006-04-25 20:13:52 +00:00
|
|
|
Tys.push_back(MVT::f64);
|
2005-11-20 22:01:40 +00:00
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
std::vector<SDOperand> Ops;
|
2006-04-25 20:13:52 +00:00
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(StackSlot);
|
|
|
|
Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType()));
|
|
|
|
Value = DAG.getNode(X86ISD::FLD, Tys, Ops);
|
|
|
|
Chain = Value.getValue(1);
|
|
|
|
SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
|
|
|
|
StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
2005-11-20 21:41:10 +00:00
|
|
|
}
|
2006-01-06 00:43:03 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
// Build the FP_TO_INT*_IN_MEM
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(Value);
|
|
|
|
Ops.push_back(StackSlot);
|
|
|
|
SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
|
|
|
|
|
|
|
|
// Load the result.
|
|
|
|
return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
MVT::ValueType VT = Op.getValueType();
|
|
|
|
const Type *OpNTy = MVT::getTypeForValueType(VT);
|
|
|
|
std::vector<Constant*> CV;
|
|
|
|
if (VT == MVT::f64) {
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, 0.0));
|
|
|
|
} else {
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, 0.0));
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, 0.0));
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, 0.0));
|
|
|
|
}
|
|
|
|
Constant *CS = ConstantStruct::get(CV);
|
|
|
|
SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
|
|
|
|
SDOperand Mask
|
|
|
|
= DAG.getNode(X86ISD::LOAD_PACK,
|
|
|
|
VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
|
|
|
|
return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
MVT::ValueType VT = Op.getValueType();
|
|
|
|
const Type *OpNTy = MVT::getTypeForValueType(VT);
|
|
|
|
std::vector<Constant*> CV;
|
|
|
|
if (VT == MVT::f64) {
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, 0.0));
|
|
|
|
} else {
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, 0.0));
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, 0.0));
|
|
|
|
CV.push_back(ConstantFP::get(OpNTy, 0.0));
|
|
|
|
}
|
|
|
|
Constant *CS = ConstantStruct::get(CV);
|
|
|
|
SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
|
|
|
|
SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK,
|
|
|
|
VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
|
|
|
|
return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
|
|
|
|
SDOperand Cond;
|
|
|
|
SDOperand CC = Op.getOperand(2);
|
|
|
|
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
|
|
|
|
bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
|
|
|
|
bool Flip;
|
|
|
|
unsigned X86CC;
|
|
|
|
if (translateX86CC(CC, isFP, X86CC, Flip)) {
|
|
|
|
if (Flip)
|
|
|
|
Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
|
|
|
|
Op.getOperand(1), Op.getOperand(0));
|
|
|
|
else
|
2006-01-30 23:41:35 +00:00
|
|
|
Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
|
|
|
|
Op.getOperand(0), Op.getOperand(1));
|
2006-04-25 20:13:52 +00:00
|
|
|
return DAG.getNode(X86ISD::SETCC, MVT::i8,
|
|
|
|
DAG.getConstant(X86CC, MVT::i8), Cond);
|
|
|
|
} else {
|
|
|
|
assert(isFP && "Illegal integer SetCC!");
|
|
|
|
|
|
|
|
Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
|
|
|
|
Op.getOperand(0), Op.getOperand(1));
|
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
switch (SetCCOpcode) {
|
2006-01-06 00:43:03 +00:00
|
|
|
default: assert(false && "Illegal floating point SetCC!");
|
|
|
|
case ISD::SETOEQ: { // !PF & ZF
|
|
|
|
Tys.push_back(MVT::i8);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
|
|
|
|
Ops.push_back(Cond);
|
|
|
|
SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
|
|
|
|
SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
|
|
|
|
DAG.getConstant(X86ISD::COND_E, MVT::i8),
|
|
|
|
Tmp1.getValue(1));
|
|
|
|
return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
|
|
|
|
}
|
|
|
|
case ISD::SETUNE: { // PF | !ZF
|
|
|
|
Tys.push_back(MVT::i8);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
|
|
|
|
Ops.push_back(Cond);
|
|
|
|
SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
|
|
|
|
SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
|
|
|
|
DAG.getConstant(X86ISD::COND_NE, MVT::i8),
|
|
|
|
Tmp1.getValue(1));
|
|
|
|
return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
|
|
|
|
}
|
|
|
|
}
|
2005-12-21 20:21:51 +00:00
|
|
|
}
|
2006-04-25 20:13:52 +00:00
|
|
|
}
|
2006-01-26 02:13:10 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
MVT::ValueType VT = Op.getValueType();
|
|
|
|
bool isFPStack = MVT::isFloatingPoint(VT) && !X86ScalarSSE;
|
|
|
|
bool addTest = false;
|
|
|
|
SDOperand Op0 = Op.getOperand(0);
|
|
|
|
SDOperand Cond, CC;
|
|
|
|
if (Op0.getOpcode() == ISD::SETCC)
|
|
|
|
Op0 = LowerOperation(Op0, DAG);
|
|
|
|
|
|
|
|
if (Op0.getOpcode() == X86ISD::SETCC) {
|
|
|
|
// If condition flag is set by a X86ISD::CMP, then make a copy of it
|
|
|
|
// (since flag operand cannot be shared). If the X86ISD::SETCC does not
|
|
|
|
// have another use it will be eliminated.
|
|
|
|
// If the X86ISD::SETCC has more than one use, then it's probably better
|
|
|
|
// to use a test instead of duplicating the X86ISD::CMP (for register
|
|
|
|
// pressure reason).
|
|
|
|
unsigned CmpOpc = Op0.getOperand(1).getOpcode();
|
|
|
|
if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI ||
|
|
|
|
CmpOpc == X86ISD::UCOMI) {
|
|
|
|
if (!Op0.hasOneUse()) {
|
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
|
|
|
|
Tys.push_back(Op0.Val->getValueType(i));
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
|
|
|
|
Ops.push_back(Op0.getOperand(i));
|
|
|
|
Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
CC = Op0.getOperand(0);
|
|
|
|
Cond = Op0.getOperand(1);
|
|
|
|
// Make a copy as flag result cannot be used by more than one.
|
|
|
|
Cond = DAG.getNode(CmpOpc, MVT::Flag,
|
|
|
|
Cond.getOperand(0), Cond.getOperand(1));
|
|
|
|
addTest =
|
|
|
|
isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
|
2006-01-13 01:03:02 +00:00
|
|
|
} else
|
|
|
|
addTest = true;
|
2006-04-25 20:13:52 +00:00
|
|
|
} else
|
|
|
|
addTest = true;
|
2006-01-10 20:26:56 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
if (addTest) {
|
|
|
|
CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
|
|
|
|
Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
|
|
|
|
}
|
2006-01-09 18:33:28 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
Tys.push_back(Op.getValueType());
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
|
|
|
|
// condition is true.
|
|
|
|
Ops.push_back(Op.getOperand(2));
|
|
|
|
Ops.push_back(Op.getOperand(1));
|
|
|
|
Ops.push_back(CC);
|
|
|
|
Ops.push_back(Cond);
|
|
|
|
return DAG.getNode(X86ISD::CMOV, Tys, Ops);
|
|
|
|
}
|
2006-01-26 02:13:10 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
bool addTest = false;
|
|
|
|
SDOperand Cond = Op.getOperand(1);
|
|
|
|
SDOperand Dest = Op.getOperand(2);
|
|
|
|
SDOperand CC;
|
|
|
|
if (Cond.getOpcode() == ISD::SETCC)
|
|
|
|
Cond = LowerOperation(Cond, DAG);
|
|
|
|
|
|
|
|
if (Cond.getOpcode() == X86ISD::SETCC) {
|
|
|
|
// If condition flag is set by a X86ISD::CMP, then make a copy of it
|
|
|
|
// (since flag operand cannot be shared). If the X86ISD::SETCC does not
|
|
|
|
// have another use it will be eliminated.
|
|
|
|
// If the X86ISD::SETCC has more than one use, then it's probably better
|
|
|
|
// to use a test instead of duplicating the X86ISD::CMP (for register
|
|
|
|
// pressure reason).
|
|
|
|
unsigned CmpOpc = Cond.getOperand(1).getOpcode();
|
|
|
|
if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI ||
|
|
|
|
CmpOpc == X86ISD::UCOMI) {
|
|
|
|
if (!Cond.hasOneUse()) {
|
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
|
|
|
|
Tys.push_back(Cond.Val->getValueType(i));
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
|
|
|
|
Ops.push_back(Cond.getOperand(i));
|
|
|
|
Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
CC = Cond.getOperand(0);
|
|
|
|
Cond = Cond.getOperand(1);
|
|
|
|
// Make a copy as flag result cannot be used by more than one.
|
|
|
|
Cond = DAG.getNode(CmpOpc, MVT::Flag,
|
|
|
|
Cond.getOperand(0), Cond.getOperand(1));
|
2006-01-13 01:03:02 +00:00
|
|
|
} else
|
|
|
|
addTest = true;
|
2006-04-25 20:13:52 +00:00
|
|
|
} else
|
|
|
|
addTest = true;
|
2006-01-13 01:03:02 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
if (addTest) {
|
|
|
|
CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
|
|
|
|
Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
|
|
|
|
}
|
|
|
|
return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
|
|
|
|
Op.getOperand(0), Op.getOperand(2), CC, Cond);
|
|
|
|
}
|
2006-02-16 00:21:07 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
|
|
|
|
SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
|
|
|
|
DAG.getTargetJumpTable(JT->getIndex(),
|
|
|
|
getPointerTy()));
|
|
|
|
if (Subtarget->isTargetDarwin()) {
|
|
|
|
// With PIC, the address is actually $g + Offset.
|
|
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC)
|
|
|
|
Result = DAG.getNode(ISD::ADD, getPointerTy(),
|
|
|
|
DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
|
2006-02-18 00:15:05 +00:00
|
|
|
}
|
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
return Result;
|
|
|
|
}
|
2006-02-23 20:41:18 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
SDOperand Copy;
|
2006-01-27 21:09:22 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
switch(Op.getNumOperands()) {
|
2006-01-27 21:09:22 +00:00
|
|
|
default:
|
|
|
|
assert(0 && "Do not know how to return this many arguments!");
|
|
|
|
abort();
|
2006-04-17 20:32:50 +00:00
|
|
|
case 1: // ret void.
|
2006-01-27 21:09:22 +00:00
|
|
|
return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
|
2006-04-25 20:13:52 +00:00
|
|
|
DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
|
2006-01-27 21:09:22 +00:00
|
|
|
case 2: {
|
|
|
|
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
|
2006-04-17 20:32:50 +00:00
|
|
|
|
|
|
|
if (MVT::isVector(ArgVT)) {
|
|
|
|
// Integer or FP vector result -> XMM0.
|
|
|
|
if (DAG.getMachineFunction().liveout_empty())
|
|
|
|
DAG.getMachineFunction().addLiveOut(X86::XMM0);
|
|
|
|
Copy = DAG.getCopyToReg(Op.getOperand(0), X86::XMM0, Op.getOperand(1),
|
|
|
|
SDOperand());
|
|
|
|
} else if (MVT::isInteger(ArgVT)) {
|
|
|
|
// Integer result -> EAX
|
|
|
|
if (DAG.getMachineFunction().liveout_empty())
|
|
|
|
DAG.getMachineFunction().addLiveOut(X86::EAX);
|
|
|
|
|
2006-01-27 21:09:22 +00:00
|
|
|
Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1),
|
|
|
|
SDOperand());
|
2006-04-17 20:32:50 +00:00
|
|
|
} else if (!X86ScalarSSE) {
|
|
|
|
// FP return with fp-stack value.
|
|
|
|
if (DAG.getMachineFunction().liveout_empty())
|
|
|
|
DAG.getMachineFunction().addLiveOut(X86::ST0);
|
|
|
|
|
2006-01-27 21:09:22 +00:00
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Op.getOperand(0));
|
|
|
|
Ops.push_back(Op.getOperand(1));
|
|
|
|
Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
|
|
|
|
} else {
|
2006-04-17 20:32:50 +00:00
|
|
|
// FP return with ScalarSSE (return on fp-stack).
|
|
|
|
if (DAG.getMachineFunction().liveout_empty())
|
|
|
|
DAG.getMachineFunction().addLiveOut(X86::ST0);
|
|
|
|
|
2006-02-01 00:20:21 +00:00
|
|
|
SDOperand MemLoc;
|
|
|
|
SDOperand Chain = Op.getOperand(0);
|
2006-01-31 23:19:54 +00:00
|
|
|
SDOperand Value = Op.getOperand(1);
|
|
|
|
|
2006-02-01 01:19:32 +00:00
|
|
|
if (Value.getOpcode() == ISD::LOAD &&
|
|
|
|
(Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
|
2006-01-31 23:19:54 +00:00
|
|
|
Chain = Value.getOperand(0);
|
|
|
|
MemLoc = Value.getOperand(1);
|
|
|
|
} else {
|
|
|
|
// Spill the value to memory and reload it into top of stack.
|
|
|
|
unsigned Size = MVT::getSizeInBits(ArgVT)/8;
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
|
|
|
|
MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
|
|
Chain = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
|
|
|
|
Value, MemLoc, DAG.getSrcValue(0));
|
|
|
|
}
|
2006-01-27 21:09:22 +00:00
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
Tys.push_back(MVT::f64);
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Chain);
|
2006-01-31 23:19:54 +00:00
|
|
|
Ops.push_back(MemLoc);
|
2006-01-27 21:09:22 +00:00
|
|
|
Ops.push_back(DAG.getValueType(ArgVT));
|
|
|
|
Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
|
|
|
|
Tys.clear();
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(Copy.getValue(1));
|
|
|
|
Ops.push_back(Copy);
|
|
|
|
Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 3:
|
2006-04-17 20:32:50 +00:00
|
|
|
if (DAG.getMachineFunction().liveout_empty()) {
|
|
|
|
DAG.getMachineFunction().addLiveOut(X86::EAX);
|
|
|
|
DAG.getMachineFunction().addLiveOut(X86::EDX);
|
|
|
|
}
|
|
|
|
|
2006-01-27 21:09:22 +00:00
|
|
|
Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2),
|
|
|
|
SDOperand());
|
|
|
|
Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
|
|
|
|
break;
|
2006-04-25 20:13:52 +00:00
|
|
|
}
|
|
|
|
return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
|
|
|
|
Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
|
|
|
|
Copy.getValue(1));
|
|
|
|
}
|
2006-04-19 22:48:17 +00:00
|
|
|
|
2006-04-26 01:20:17 +00:00
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
if (FormalArgs.size() == 0) {
|
|
|
|
unsigned CC = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
|
|
|
|
if (CC == CallingConv::Fast && EnableFastCC)
|
|
|
|
LowerFastCCArguments(Op, DAG);
|
|
|
|
else
|
|
|
|
LowerCCCArguments(Op, DAG);
|
|
|
|
}
|
|
|
|
return FormalArgs[Op.ResNo];
|
|
|
|
}
|
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
SDOperand InFlag(0, 0);
|
|
|
|
SDOperand Chain = Op.getOperand(0);
|
|
|
|
unsigned Align =
|
|
|
|
(unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
|
|
|
|
if (Align == 0) Align = 1;
|
|
|
|
|
|
|
|
ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
|
|
|
|
// If not DWORD aligned, call memset if size is less than the threshold.
|
|
|
|
// It knows how to align to the right boundary first.
|
|
|
|
if ((Align & 3) != 0 ||
|
|
|
|
(I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
|
|
|
|
MVT::ValueType IntPtr = getPointerTy();
|
2006-05-03 01:29:57 +00:00
|
|
|
const Type *IntPtrTy = getTargetData()->getIntPtrType();
|
2006-04-25 20:13:52 +00:00
|
|
|
std::vector<std::pair<SDOperand, const Type*> > Args;
|
|
|
|
Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
|
|
|
|
// Extend the ubyte argument to be an int value for the call.
|
|
|
|
SDOperand Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
|
|
|
|
Args.push_back(std::make_pair(Val, IntPtrTy));
|
|
|
|
Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
|
|
|
|
std::pair<SDOperand,SDOperand> CallResult =
|
|
|
|
LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
|
|
|
|
DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
|
|
|
|
return CallResult.second;
|
|
|
|
}
|
|
|
|
|
|
|
|
MVT::ValueType AVT;
|
|
|
|
SDOperand Count;
|
|
|
|
ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
|
|
|
|
unsigned BytesLeft = 0;
|
|
|
|
bool TwoRepStos = false;
|
|
|
|
if (ValC) {
|
|
|
|
unsigned ValReg;
|
|
|
|
unsigned Val = ValC->getValue() & 255;
|
|
|
|
|
|
|
|
// If the value is a constant, then we can potentially use larger sets.
|
|
|
|
switch (Align & 3) {
|
|
|
|
case 2: // WORD aligned
|
|
|
|
AVT = MVT::i16;
|
|
|
|
Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
|
|
|
|
BytesLeft = I->getValue() % 2;
|
|
|
|
Val = (Val << 8) | Val;
|
|
|
|
ValReg = X86::AX;
|
|
|
|
break;
|
|
|
|
case 0: // DWORD aligned
|
|
|
|
AVT = MVT::i32;
|
|
|
|
if (I) {
|
|
|
|
Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
|
|
|
|
BytesLeft = I->getValue() % 4;
|
2006-04-19 22:48:17 +00:00
|
|
|
} else {
|
2006-04-25 20:13:52 +00:00
|
|
|
Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
|
|
|
|
DAG.getConstant(2, MVT::i8));
|
|
|
|
TwoRepStos = true;
|
2006-04-19 22:48:17 +00:00
|
|
|
}
|
2006-04-25 20:13:52 +00:00
|
|
|
Val = (Val << 8) | Val;
|
|
|
|
Val = (Val << 16) | Val;
|
|
|
|
ValReg = X86::EAX;
|
|
|
|
break;
|
|
|
|
default: // Byte aligned
|
|
|
|
AVT = MVT::i8;
|
|
|
|
Count = Op.getOperand(3);
|
|
|
|
ValReg = X86::AL;
|
|
|
|
break;
|
2006-04-19 22:48:17 +00:00
|
|
|
}
|
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
|
|
|
|
InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
} else {
|
|
|
|
AVT = MVT::i8;
|
|
|
|
Count = Op.getOperand(3);
|
|
|
|
Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
2006-03-22 02:53:00 +00:00
|
|
|
}
|
2006-03-27 07:00:16 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
2006-04-24 22:58:52 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(DAG.getValueType(AVT));
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(X86ISD::REP_STOS, Tys, Ops);
|
Revamp build_vector lowering to take advantage of movss and movd instructions.
movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27939 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 23:03:30 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
if (TwoRepStos) {
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
Count = Op.getOperand(3);
|
|
|
|
MVT::ValueType CVT = Count.getValueType();
|
|
|
|
SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
|
|
|
|
DAG.getConstant(3, CVT));
|
|
|
|
Chain = DAG.getCopyToReg(Chain, X86::ECX, Left, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
Tys.clear();
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(DAG.getValueType(MVT::i8));
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(X86ISD::REP_STOS, Tys, Ops);
|
|
|
|
} else if (BytesLeft) {
|
|
|
|
// Issue stores for the last 1 - 3 bytes.
|
|
|
|
SDOperand Value;
|
|
|
|
unsigned Val = ValC->getValue() & 255;
|
|
|
|
unsigned Offset = I->getValue() - BytesLeft;
|
|
|
|
SDOperand DstAddr = Op.getOperand(1);
|
|
|
|
MVT::ValueType AddrVT = DstAddr.getValueType();
|
|
|
|
if (BytesLeft >= 2) {
|
|
|
|
Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
|
|
|
|
Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
|
|
|
|
DAG.getNode(ISD::ADD, AddrVT, DstAddr,
|
|
|
|
DAG.getConstant(Offset, AddrVT)),
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
BytesLeft -= 2;
|
|
|
|
Offset += 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (BytesLeft == 1) {
|
|
|
|
Value = DAG.getConstant(Val, MVT::i8);
|
|
|
|
Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
|
|
|
|
DAG.getNode(ISD::ADD, AddrVT, DstAddr,
|
|
|
|
DAG.getConstant(Offset, AddrVT)),
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return Chain;
|
|
|
|
}
|
Revamp build_vector lowering to take advantage of movss and movd instructions.
movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27939 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 23:03:30 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
SDOperand Chain = Op.getOperand(0);
|
|
|
|
unsigned Align =
|
|
|
|
(unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
|
|
|
|
if (Align == 0) Align = 1;
|
|
|
|
|
|
|
|
ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
|
|
|
|
// If not DWORD aligned, call memcpy if size is less than the threshold.
|
|
|
|
// It knows how to align to the right boundary first.
|
|
|
|
if ((Align & 3) != 0 ||
|
|
|
|
(I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
|
|
|
|
MVT::ValueType IntPtr = getPointerTy();
|
2006-05-03 01:29:57 +00:00
|
|
|
const Type *IntPtrTy = getTargetData()->getIntPtrType();
|
2006-04-25 20:13:52 +00:00
|
|
|
std::vector<std::pair<SDOperand, const Type*> > Args;
|
|
|
|
Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
|
|
|
|
Args.push_back(std::make_pair(Op.getOperand(2), IntPtrTy));
|
|
|
|
Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
|
|
|
|
std::pair<SDOperand,SDOperand> CallResult =
|
|
|
|
LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
|
|
|
|
DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
|
|
|
|
return CallResult.second;
|
|
|
|
}
|
|
|
|
|
|
|
|
MVT::ValueType AVT;
|
|
|
|
SDOperand Count;
|
|
|
|
unsigned BytesLeft = 0;
|
|
|
|
bool TwoRepMovs = false;
|
|
|
|
switch (Align & 3) {
|
|
|
|
case 2: // WORD aligned
|
|
|
|
AVT = MVT::i16;
|
|
|
|
Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
|
|
|
|
BytesLeft = I->getValue() % 2;
|
|
|
|
break;
|
|
|
|
case 0: // DWORD aligned
|
|
|
|
AVT = MVT::i32;
|
|
|
|
if (I) {
|
|
|
|
Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
|
|
|
|
BytesLeft = I->getValue() % 4;
|
|
|
|
} else {
|
|
|
|
Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
|
|
|
|
DAG.getConstant(2, MVT::i8));
|
|
|
|
TwoRepMovs = true;
|
Revamp build_vector lowering to take advantage of movss and movd instructions.
movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27939 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 23:03:30 +00:00
|
|
|
}
|
2006-04-25 20:13:52 +00:00
|
|
|
break;
|
|
|
|
default: // Byte aligned
|
|
|
|
AVT = MVT::i8;
|
|
|
|
Count = Op.getOperand(3);
|
|
|
|
break;
|
|
|
|
}
|
Revamp build_vector lowering to take advantage of movss and movd instructions.
movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27939 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 23:03:30 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
SDOperand InFlag(0, 0);
|
|
|
|
Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(DAG.getValueType(AVT));
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, Ops);
|
2006-03-24 07:29:27 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
if (TwoRepMovs) {
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
Count = Op.getOperand(3);
|
|
|
|
MVT::ValueType CVT = Count.getValueType();
|
|
|
|
SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
|
|
|
|
DAG.getConstant(3, CVT));
|
|
|
|
Chain = DAG.getCopyToReg(Chain, X86::ECX, Left, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
Tys.clear();
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(DAG.getValueType(MVT::i8));
|
|
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, Ops);
|
|
|
|
} else if (BytesLeft) {
|
|
|
|
// Issue loads and stores for the last 1 - 3 bytes.
|
|
|
|
unsigned Offset = I->getValue() - BytesLeft;
|
|
|
|
SDOperand DstAddr = Op.getOperand(1);
|
|
|
|
MVT::ValueType DstVT = DstAddr.getValueType();
|
|
|
|
SDOperand SrcAddr = Op.getOperand(2);
|
|
|
|
MVT::ValueType SrcVT = SrcAddr.getValueType();
|
|
|
|
SDOperand Value;
|
|
|
|
if (BytesLeft >= 2) {
|
|
|
|
Value = DAG.getLoad(MVT::i16, Chain,
|
|
|
|
DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
|
|
|
|
DAG.getConstant(Offset, SrcVT)),
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
Chain = Value.getValue(1);
|
|
|
|
Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
|
|
|
|
DAG.getNode(ISD::ADD, DstVT, DstAddr,
|
|
|
|
DAG.getConstant(Offset, DstVT)),
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
BytesLeft -= 2;
|
|
|
|
Offset += 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (BytesLeft == 1) {
|
|
|
|
Value = DAG.getLoad(MVT::i8, Chain,
|
|
|
|
DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
|
|
|
|
DAG.getConstant(Offset, SrcVT)),
|
|
|
|
DAG.getSrcValue(NULL));
|
|
|
|
Chain = Value.getValue(1);
|
|
|
|
Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
|
|
|
|
DAG.getNode(ISD::ADD, DstVT, DstAddr,
|
|
|
|
DAG.getConstant(Offset, DstVT)),
|
|
|
|
DAG.getSrcValue(NULL));
|
2006-03-25 09:37:23 +00:00
|
|
|
}
|
2006-03-24 07:29:27 +00:00
|
|
|
}
|
2006-03-31 19:22:53 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
return Chain;
|
|
|
|
}
|
2006-03-31 19:22:53 +00:00
|
|
|
|
2006-04-25 20:13:52 +00:00
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
std::vector<MVT::ValueType> Tys;
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
Tys.push_back(MVT::Flag);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(Op.getOperand(0));
|
|
|
|
SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
|
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
|
|
|
|
Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
|
|
|
|
MVT::i32, Ops[0].getValue(2)));
|
|
|
|
Ops.push_back(Ops[1].getValue(1));
|
|
|
|
Tys[0] = Tys[1] = MVT::i32;
|
|
|
|
Tys.push_back(MVT::Other);
|
|
|
|
return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
|
|
// memory location argument.
|
|
|
|
// FIXME: Replace MVT::i32 with PointerTy
|
|
|
|
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
|
|
|
|
return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
|
|
|
|
Op.getOperand(1), Op.getOperand(2));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand
|
|
|
|
X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
|
|
|
|
switch (IntNo) {
|
|
|
|
default: return SDOperand(); // Don't custom lower most intrinsics.
|
2006-04-05 23:38:46 +00:00
|
|
|
// Comparison intrinsics.
|
2006-04-25 20:13:52 +00:00
|
|
|
case Intrinsic::x86_sse_comieq_ss:
|
|
|
|
case Intrinsic::x86_sse_comilt_ss:
|
|
|
|
case Intrinsic::x86_sse_comile_ss:
|
|
|
|
case Intrinsic::x86_sse_comigt_ss:
|
|
|
|
case Intrinsic::x86_sse_comige_ss:
|
|
|
|
case Intrinsic::x86_sse_comineq_ss:
|
|
|
|
case Intrinsic::x86_sse_ucomieq_ss:
|
|
|
|
case Intrinsic::x86_sse_ucomilt_ss:
|
|
|
|
case Intrinsic::x86_sse_ucomile_ss:
|
|
|
|
case Intrinsic::x86_sse_ucomigt_ss:
|
|
|
|
case Intrinsic::x86_sse_ucomige_ss:
|
|
|
|
case Intrinsic::x86_sse_ucomineq_ss:
|
|
|
|
case Intrinsic::x86_sse2_comieq_sd:
|
|
|
|
case Intrinsic::x86_sse2_comilt_sd:
|
|
|
|
case Intrinsic::x86_sse2_comile_sd:
|
|
|
|
case Intrinsic::x86_sse2_comigt_sd:
|
|
|
|
case Intrinsic::x86_sse2_comige_sd:
|
|
|
|
case Intrinsic::x86_sse2_comineq_sd:
|
|
|
|
case Intrinsic::x86_sse2_ucomieq_sd:
|
|
|
|
case Intrinsic::x86_sse2_ucomilt_sd:
|
|
|
|
case Intrinsic::x86_sse2_ucomile_sd:
|
|
|
|
case Intrinsic::x86_sse2_ucomigt_sd:
|
|
|
|
case Intrinsic::x86_sse2_ucomige_sd:
|
|
|
|
case Intrinsic::x86_sse2_ucomineq_sd: {
|
|
|
|
unsigned Opc = 0;
|
|
|
|
ISD::CondCode CC = ISD::SETCC_INVALID;
|
|
|
|
switch (IntNo) {
|
|
|
|
default: break;
|
|
|
|
case Intrinsic::x86_sse_comieq_ss:
|
|
|
|
case Intrinsic::x86_sse2_comieq_sd:
|
|
|
|
Opc = X86ISD::COMI;
|
|
|
|
CC = ISD::SETEQ;
|
|
|
|
break;
|
2006-04-05 23:38:46 +00:00
|
|
|
case Intrinsic::x86_sse_comilt_ss:
|
|
|
|
case Intrinsic::x86_sse2_comilt_sd:
|
2006-04-25 20:13:52 +00:00
|
|
|
Opc = X86ISD::COMI;
|
|
|
|
CC = ISD::SETLT;
|
|
|
|
break;
|
|
|
|
case Intrinsic::x86_sse_comile_ss:
|
2006-04-05 23:38:46 +00:00
|
|
|
case Intrinsic::x86_sse2_comile_sd:
|
2006-04-25 20:13:52 +00:00
|
|
|
Opc = X86ISD::COMI;
|
|
|
|
CC = ISD::SETLE;
|
|
|
|
break;
|
|
|
|
case Intrinsic::x86_sse_comigt_ss:
|
2006-04-05 23:38:46 +00:00
|
|
|
case Intrinsic::x86_sse2_comigt_sd:
|
2006-04-25 20:13:52 +00:00
|
|
|
Opc = X86ISD::COMI;
|
|
|
|
CC = ISD::SETGT;
|
|
|
|
break;
|
|
|
|
case Intrinsic::x86_sse_comige_ss:
|
2006-04-05 23:38:46 +00:00
|
|
|
case Intrinsic::x86_sse2_comige_sd:
|
2006-04-25 20:13:52 +00:00
|
|
|
Opc = X86ISD::COMI;
|
|
|
|
CC = ISD::SETGE;
|
|
|
|
break;
|
|
|
|
case Intrinsic::x86_sse_comineq_ss:
|
2006-04-05 23:38:46 +00:00
|
|
|
case Intrinsic::x86_sse2_comineq_sd:
|
2006-04-25 20:13:52 +00:00
|
|
|
Opc = X86ISD::COMI;
|
|
|
|
CC = ISD::SETNE;
|
|
|
|
break;
|
|
|
|
case Intrinsic::x86_sse_ucomieq_ss:
|
2006-04-05 23:38:46 +00:00
|
|
|
case Intrinsic::x86_sse2_ucomieq_sd:
|
2006-04-25 20:13:52 +00:00
|
|
|
Opc = X86ISD::UCOMI;
|
|
|
|
CC = ISD::SETEQ;
|
|
|
|
break;
|
|
|
|
case Intrinsic::x86_sse_ucomilt_ss:
|
2006-04-05 23:38:46 +00:00
|
|
|
case Intrinsic::x86_sse2_ucomilt_sd:
|
2006-04-25 20:13:52 +00:00
|
|
|
Opc = X86ISD::UCOMI;
|
|
|
|
CC = ISD::SETLT;
|
|
|
|
break;
|
|
|
|
case Intrinsic::x86_sse_ucomile_ss:
|
2006-04-05 23:38:46 +00:00
|
|
|
case Intrinsic::x86_sse2_ucomile_sd:
|
2006-04-25 20:13:52 +00:00
|
|
|
Opc = X86ISD::UCOMI;
|
|
|
|
CC = ISD::SETLE;
|
|
|
|
break;
|
|
|
|
case Intrinsic::x86_sse_ucomigt_ss:
|
2006-04-05 23:38:46 +00:00
|
|
|
case Intrinsic::x86_sse2_ucomigt_sd:
|
2006-04-25 20:13:52 +00:00
|
|
|
Opc = X86ISD::UCOMI;
|
|
|
|
CC = ISD::SETGT;
|
|
|
|
break;
|
|
|
|
case Intrinsic::x86_sse_ucomige_ss:
|
2006-04-05 23:38:46 +00:00
|
|
|
case Intrinsic::x86_sse2_ucomige_sd:
|
2006-04-25 20:13:52 +00:00
|
|
|
Opc = X86ISD::UCOMI;
|
|
|
|
CC = ISD::SETGE;
|
|
|
|
break;
|
|
|
|
case Intrinsic::x86_sse_ucomineq_ss:
|
|
|
|
case Intrinsic::x86_sse2_ucomineq_sd:
|
|
|
|
Opc = X86ISD::UCOMI;
|
|
|
|
CC = ISD::SETNE;
|
|
|
|
break;
|
2006-04-05 23:38:46 +00:00
|
|
|
}
|
2006-04-25 20:13:52 +00:00
|
|
|
bool Flip;
|
|
|
|
unsigned X86CC;
|
|
|
|
translateX86CC(CC, true, X86CC, Flip);
|
|
|
|
SDOperand Cond = DAG.getNode(Opc, MVT::Flag, Op.getOperand(Flip?2:1),
|
|
|
|
Op.getOperand(Flip?1:2));
|
|
|
|
SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
|
|
|
|
DAG.getConstant(X86CC, MVT::i8), Cond);
|
|
|
|
return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
|
|
|
|
}
|
2006-04-05 23:38:46 +00:00
|
|
|
}
|
2006-04-25 20:13:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
|
|
|
///
|
|
|
|
SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|
|
|
switch (Op.getOpcode()) {
|
|
|
|
default: assert(0 && "Should not custom lower this!");
|
|
|
|
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
|
|
|
|
case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
|
|
|
|
case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
|
|
|
|
case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
|
|
|
|
case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
|
|
|
|
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
|
|
|
|
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
|
|
|
|
case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
|
|
|
|
case ISD::SHL_PARTS:
|
|
|
|
case ISD::SRA_PARTS:
|
|
|
|
case ISD::SRL_PARTS: return LowerShift(Op, DAG);
|
|
|
|
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
|
|
|
|
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
|
|
|
|
case ISD::FABS: return LowerFABS(Op, DAG);
|
|
|
|
case ISD::FNEG: return LowerFNEG(Op, DAG);
|
|
|
|
case ISD::SETCC: return LowerSETCC(Op, DAG);
|
|
|
|
case ISD::SELECT: return LowerSELECT(Op, DAG);
|
|
|
|
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
|
|
|
|
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
|
|
|
|
case ISD::RET: return LowerRET(Op, DAG);
|
2006-04-26 01:20:17 +00:00
|
|
|
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
|
2006-04-25 20:13:52 +00:00
|
|
|
case ISD::MEMSET: return LowerMEMSET(Op, DAG);
|
|
|
|
case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
|
|
|
|
case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
|
|
|
|
case ISD::VASTART: return LowerVASTART(Op, DAG);
|
|
|
|
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
|
2005-12-23 07:31:11 +00:00
|
|
|
}
|
2005-11-15 00:40:23 +00:00
|
|
|
}
|
2005-12-20 06:22:03 +00:00
|
|
|
|
|
|
|
const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
|
|
switch (Opcode) {
|
|
|
|
default: return NULL;
|
2006-01-09 18:33:28 +00:00
|
|
|
case X86ISD::SHLD: return "X86ISD::SHLD";
|
|
|
|
case X86ISD::SHRD: return "X86ISD::SHRD";
|
2006-01-31 03:14:29 +00:00
|
|
|
case X86ISD::FAND: return "X86ISD::FAND";
|
2006-01-31 22:28:30 +00:00
|
|
|
case X86ISD::FXOR: return "X86ISD::FXOR";
|
2006-01-12 22:54:21 +00:00
|
|
|
case X86ISD::FILD: return "X86ISD::FILD";
|
2006-02-04 02:20:30 +00:00
|
|
|
case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
|
2005-12-20 06:22:03 +00:00
|
|
|
case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
|
|
|
|
case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
|
|
|
|
case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
|
2005-12-21 02:39:21 +00:00
|
|
|
case X86ISD::FLD: return "X86ISD::FLD";
|
2006-01-05 00:27:02 +00:00
|
|
|
case X86ISD::FST: return "X86ISD::FST";
|
|
|
|
case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
|
2005-12-21 02:39:21 +00:00
|
|
|
case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
|
2005-12-20 06:22:03 +00:00
|
|
|
case X86ISD::CALL: return "X86ISD::CALL";
|
|
|
|
case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
|
|
|
|
case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
|
|
|
|
case X86ISD::CMP: return "X86ISD::CMP";
|
|
|
|
case X86ISD::TEST: return "X86ISD::TEST";
|
2006-04-05 23:38:46 +00:00
|
|
|
case X86ISD::COMI: return "X86ISD::COMI";
|
|
|
|
case X86ISD::UCOMI: return "X86ISD::UCOMI";
|
2005-12-21 20:21:51 +00:00
|
|
|
case X86ISD::SETCC: return "X86ISD::SETCC";
|
2005-12-20 06:22:03 +00:00
|
|
|
case X86ISD::CMOV: return "X86ISD::CMOV";
|
|
|
|
case X86ISD::BRCOND: return "X86ISD::BRCOND";
|
2005-12-21 02:39:21 +00:00
|
|
|
case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
|
2006-03-04 01:12:00 +00:00
|
|
|
case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
|
|
|
|
case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
|
2006-01-31 22:28:30 +00:00
|
|
|
case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
|
2006-02-18 00:15:05 +00:00
|
|
|
case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
|
2006-02-23 20:41:18 +00:00
|
|
|
case X86ISD::Wrapper: return "X86ISD::Wrapper";
|
2006-03-24 23:15:12 +00:00
|
|
|
case X86ISD::S2VEC: return "X86ISD::S2VEC";
|
2006-03-31 19:22:53 +00:00
|
|
|
case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
|
2006-03-31 21:55:24 +00:00
|
|
|
case X86ISD::PINSRW: return "X86ISD::PINSRW";
|
2005-12-20 06:22:03 +00:00
|
|
|
}
|
|
|
|
}
|
2005-12-21 23:05:39 +00:00
|
|
|
|
2006-02-16 21:11:51 +00:00
|
|
|
void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
|
|
|
|
uint64_t Mask,
|
|
|
|
uint64_t &KnownZero,
|
|
|
|
uint64_t &KnownOne,
|
|
|
|
unsigned Depth) const {
|
2005-12-21 23:05:39 +00:00
|
|
|
unsigned Opc = Op.getOpcode();
|
2006-04-05 06:11:20 +00:00
|
|
|
assert((Opc >= ISD::BUILTIN_OP_END ||
|
|
|
|
Opc == ISD::INTRINSIC_WO_CHAIN ||
|
|
|
|
Opc == ISD::INTRINSIC_W_CHAIN ||
|
|
|
|
Opc == ISD::INTRINSIC_VOID) &&
|
|
|
|
"Should use MaskedValueIsZero if you don't know whether Op"
|
|
|
|
" is a target node!");
|
2005-12-21 23:05:39 +00:00
|
|
|
|
2006-04-05 06:11:20 +00:00
|
|
|
KnownZero = KnownOne = 0; // Don't know anything.
|
2005-12-21 23:05:39 +00:00
|
|
|
switch (Opc) {
|
2006-04-05 06:11:20 +00:00
|
|
|
default: break;
|
2006-02-16 21:11:51 +00:00
|
|
|
case X86ISD::SETCC:
|
|
|
|
KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
|
|
|
|
break;
|
2005-12-21 23:05:39 +00:00
|
|
|
}
|
|
|
|
}
|
2006-01-31 19:43:35 +00:00
|
|
|
|
|
|
|
std::vector<unsigned> X86TargetLowering::
|
2006-02-22 00:56:39 +00:00
|
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
|
|
|
MVT::ValueType VT) const {
|
2006-01-31 19:43:35 +00:00
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
// FIXME: not handling fp-stack yet!
|
|
|
|
// FIXME: not handling MMX registers yet ('y' constraint).
|
|
|
|
switch (Constraint[0]) { // GCC X86 Constraint Letters
|
|
|
|
default: break; // Unknown constriant letter
|
|
|
|
case 'r': // GENERAL_REGS
|
|
|
|
case 'R': // LEGACY_REGS
|
2006-05-06 00:29:37 +00:00
|
|
|
if (VT == MVT::i32)
|
|
|
|
return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
|
|
|
|
X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
|
|
|
|
else if (VT == MVT::i16)
|
|
|
|
return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
|
|
|
|
X86::SI, X86::DI, X86::BP, X86::SP, 0);
|
|
|
|
else if (VT == MVT::i8)
|
|
|
|
return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
|
|
|
|
break;
|
2006-01-31 19:43:35 +00:00
|
|
|
case 'l': // INDEX_REGS
|
2006-05-06 00:29:37 +00:00
|
|
|
if (VT == MVT::i32)
|
|
|
|
return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
|
|
|
|
X86::ESI, X86::EDI, X86::EBP, 0);
|
|
|
|
else if (VT == MVT::i16)
|
|
|
|
return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
|
|
|
|
X86::SI, X86::DI, X86::BP, 0);
|
|
|
|
else if (VT == MVT::i8)
|
|
|
|
return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
|
|
|
|
break;
|
2006-01-31 19:43:35 +00:00
|
|
|
case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
|
|
|
|
case 'Q': // Q_REGS
|
2006-05-06 00:29:37 +00:00
|
|
|
if (VT == MVT::i32)
|
|
|
|
return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
|
|
|
|
else if (VT == MVT::i16)
|
|
|
|
return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
|
|
|
|
else if (VT == MVT::i8)
|
|
|
|
return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
|
|
|
|
break;
|
2006-01-31 19:43:35 +00:00
|
|
|
case 'x': // SSE_REGS if SSE1 allowed
|
|
|
|
if (Subtarget->hasSSE1())
|
|
|
|
return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
|
|
|
|
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
|
|
|
|
0);
|
|
|
|
return std::vector<unsigned>();
|
|
|
|
case 'Y': // SSE_REGS if SSE2 allowed
|
|
|
|
if (Subtarget->hasSSE2())
|
|
|
|
return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
|
|
|
|
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
|
|
|
|
0);
|
|
|
|
return std::vector<unsigned>();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-02-22 00:56:39 +00:00
|
|
|
return std::vector<unsigned>();
|
2006-01-31 19:43:35 +00:00
|
|
|
}
|
2006-03-13 23:18:16 +00:00
|
|
|
|
|
|
|
/// isLegalAddressImmediate - Return true if the integer value or
|
|
|
|
/// GlobalValue can be used as the offset of the target addressing mode.
|
|
|
|
bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const {
|
|
|
|
// X86 allows a sign-extended 32-bit immediate field.
|
|
|
|
return (V > -(1LL << 32) && V < (1LL << 32)-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
|
2006-03-22 19:22:18 +00:00
|
|
|
if (Subtarget->isTargetDarwin()) {
|
2006-03-13 23:18:16 +00:00
|
|
|
Reloc::Model RModel = getTargetMachine().getRelocationModel();
|
|
|
|
if (RModel == Reloc::Static)
|
|
|
|
return true;
|
|
|
|
else if (RModel == Reloc::DynamicNoPIC)
|
2006-03-16 22:02:48 +00:00
|
|
|
return !DarwinGVRequiresExtraLoad(GV);
|
2006-03-13 23:18:16 +00:00
|
|
|
else
|
|
|
|
return false;
|
|
|
|
} else
|
|
|
|
return true;
|
|
|
|
}
|
2006-03-22 18:59:22 +00:00
|
|
|
|
|
|
|
/// isShuffleMaskLegal - Targets can use this to indicate that they only
|
|
|
|
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
|
|
|
|
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
|
|
|
|
/// are assumed to be legal.
|
2006-03-22 22:07:06 +00:00
|
|
|
bool
|
|
|
|
X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
|
|
|
|
// Only do shuffles on 128-bit vector types for now.
|
|
|
|
if (MVT::getSizeInBits(VT) == 64) return false;
|
2006-04-19 22:48:17 +00:00
|
|
|
return (Mask.Val->getNumOperands() <= 4 ||
|
2006-04-17 20:43:08 +00:00
|
|
|
isSplatMask(Mask.Val) ||
|
2006-04-05 01:47:37 +00:00
|
|
|
isPSHUFHW_PSHUFLWMask(Mask.Val) ||
|
2006-03-28 08:27:15 +00:00
|
|
|
X86::isUNPCKLMask(Mask.Val) ||
|
Handle canonical form of e.g.
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27437 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 07:20:06 +00:00
|
|
|
X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
|
2006-03-28 10:17:11 +00:00
|
|
|
X86::isUNPCKHMask(Mask.Val));
|
2006-03-22 18:59:22 +00:00
|
|
|
}
|
2006-04-20 08:58:49 +00:00
|
|
|
|
|
|
|
bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
|
|
|
|
MVT::ValueType EVT,
|
|
|
|
SelectionDAG &DAG) const {
|
|
|
|
unsigned NumElts = BVOps.size();
|
|
|
|
// Only do shuffles on 128-bit vector types for now.
|
|
|
|
if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
|
|
|
|
if (NumElts == 2) return true;
|
|
|
|
if (NumElts == 4) {
|
Now generating perfect (I think) code for "vector set" with a single non-zero
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27923 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 01:05:10 +00:00
|
|
|
return (isMOVLMask(BVOps) || isCommutedMOVL(BVOps, true) ||
|
2006-04-20 08:58:49 +00:00
|
|
|
isSHUFPMask(BVOps) || isCommutedSHUFP(BVOps));
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|