2012-02-28 07:46:26 +00:00
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//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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// Describe MIPS instructions format
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//
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2008-06-08 01:39:36 +00:00
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// CPU INSTRUCTION FORMATS
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2007-06-06 07:42:06 +00:00
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//
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// opcode - operation code.
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// rs - src reg.
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// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
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// rd - dst reg, only used on 3 regs instr.
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// shamt - only used on shift instructions, contains the shift amount.
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// funct - combined with opcode field give us an operation code.
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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2011-10-18 17:50:36 +00:00
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<4> val> {
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bits<4> Value = val;
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}
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def Pseudo : Format<0>;
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def FrmR : Format<1>;
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def FrmI : Format<2>;
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def FrmJ : Format<3>;
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def FrmFR : Format<4>;
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def FrmFI : Format<5>;
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def FrmOther : Format<6>; // Instruction w/ a custom format
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2013-04-19 19:03:11 +00:00
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class MMRel;
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def Std2MicroMips : InstrMapping {
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let FilterClass = "MMRel";
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// Instructions with the same BaseOpcode and isNVStore values form a row.
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let RowFields = ["BaseOpcode"];
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// Instructions with the same predicate sense form a column.
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let ColFields = ["Arch"];
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// The key column is the unpredicated instructions.
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let KeyCol = ["se"];
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// Value columns are PredSense=true and PredSense=false
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let ValueCols = [["se"], ["micromips"]];
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}
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class StdArch {
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string Arch = "se";
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}
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2007-06-06 07:42:06 +00:00
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// Generic Mips Format
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2012-07-31 19:13:07 +00:00
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class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format f>: Instruction
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2007-06-06 07:42:06 +00:00
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{
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field bits<32> Inst;
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2011-10-18 17:50:36 +00:00
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Format Form = f;
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2007-06-06 07:42:06 +00:00
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let Namespace = "Mips";
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2012-04-17 18:03:21 +00:00
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let Size = 4;
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2011-10-18 17:50:36 +00:00
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bits<6> Opcode = 0;
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2007-06-06 07:42:06 +00:00
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2011-10-18 17:50:36 +00:00
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// Top 6 bits are the 'opcode' field
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let Inst{31-26} = Opcode;
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2011-03-04 17:51:39 +00:00
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2011-10-18 17:50:36 +00:00
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let OutOperandList = outs;
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let InOperandList = ins;
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2007-08-18 02:01:28 +00:00
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2007-06-06 07:42:06 +00:00
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let AsmString = asmstr;
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let Pattern = pattern;
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2007-08-21 16:06:45 +00:00
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let Itinerary = itin;
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2011-10-18 17:50:36 +00:00
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//
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// Attributes specific to Mips instructions...
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//
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bits<4> FormBits = Form.Value;
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// TSFlags layout should be kept in sync with MipsInstrInfo.h.
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let TSFlags{3-0} = FormBits;
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2012-04-17 18:03:21 +00:00
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let DecoderNamespace = "Mips";
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field bits<32> SoftFail = 0;
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2012-07-31 19:13:07 +00:00
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}
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2012-05-22 03:10:09 +00:00
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2012-07-31 19:13:07 +00:00
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// Mips32/64 Instruction Format
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class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
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2013-04-19 19:03:11 +00:00
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InstrItinClass itin, Format f, string opstr = ""> :
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2014-05-07 10:27:09 +00:00
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MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
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let EncodingPredicates = [HasStdEnc];
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2013-04-19 19:03:11 +00:00
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string BaseOpcode = opstr;
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string Arch;
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2007-06-06 07:42:06 +00:00
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}
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2007-10-09 02:55:31 +00:00
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// Mips Pseudo Instructions Format
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2012-12-20 04:20:09 +00:00
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class MipsPseudo<dag outs, dag ins, list<dag> pattern,
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InstrItinClass itin = IIPseudo> :
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MipsInst<outs, ins, "", pattern, itin, Pseudo> {
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2011-10-18 17:50:36 +00:00
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let isCodeGenOnly = 1;
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2011-09-27 04:57:54 +00:00
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let isPseudo = 1;
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}
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2007-06-06 07:42:06 +00:00
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2012-07-31 19:13:07 +00:00
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// Mips32/64 Pseudo Instruction Format
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2012-12-20 04:20:09 +00:00
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class PseudoSE<dag outs, dag ins, list<dag> pattern,
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2014-05-07 10:27:09 +00:00
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InstrItinClass itin = IIPseudo> :
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MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
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let EncodingPredicates = [HasStdEnc];
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2012-07-31 19:13:07 +00:00
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}
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Implement methods that enable expansion of load immediate
macro instruction (li) in the assembler.
We have identified three possible expansions depending on
the size of immediate operand:
1) for 0 ≤ j ≤ 65535.
li d,j =>
ori d,$zero,j
2) for −32768 ≤ j < 0.
li d,j =>
addiu d,$zero,j
3) for any other value of j that is representable as a 32-bit integer.
li d,j =>
lui d,hi16(j)
ori d,d,lo16(j)
All of the above have been implemented in ths patch.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 04:03:53 +00:00
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// Pseudo-instructions for alternate assembly syntax (never used by codegen).
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// These are aliases that require C++ handling to convert to the target
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// instruction, while InstAliases can be handled directly by tblgen.
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class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
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MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
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let isPseudo = 1;
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let Pattern = [];
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}
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
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2007-08-18 02:01:28 +00:00
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list<dag> pattern, InstrItinClass itin>:
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2012-07-31 18:55:01 +00:00
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InstSE<outs, ins, asmstr, pattern, itin, FrmR>
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2007-06-06 07:42:06 +00:00
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{
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<5> shamt;
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bits<6> funct;
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2011-10-18 17:50:36 +00:00
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let Opcode = op;
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2007-06-06 07:42:06 +00:00
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let funct = _funct;
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let Inst{25-21} = rs;
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2011-03-04 17:51:39 +00:00
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let Inst{20-16} = rt;
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2007-06-06 07:42:06 +00:00
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let Inst{15-11} = rd;
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let Inst{10-6} = shamt;
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let Inst{5-0} = funct;
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}
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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2007-08-18 02:01:28 +00:00
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class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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2012-07-31 18:55:01 +00:00
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InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
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2007-06-06 07:42:06 +00:00
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{
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bits<5> rt;
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bits<5> rs;
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bits<16> imm16;
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2011-10-18 17:50:36 +00:00
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let Opcode = op;
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2007-06-06 07:42:06 +00:00
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let Inst{25-21} = rs;
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2011-03-04 17:51:39 +00:00
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let Inst{20-16} = rt;
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2007-06-06 07:42:06 +00:00
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let Inst{15-0} = imm16;
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}
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2011-12-06 03:34:48 +00:00
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class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
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2011-10-11 18:49:17 +00:00
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list<dag> pattern, InstrItinClass itin>:
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2012-07-31 18:55:01 +00:00
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InstSE<outs, ins, asmstr, pattern, itin, FrmI>
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2011-10-11 18:49:17 +00:00
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{
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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2011-10-18 17:50:36 +00:00
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let Opcode = op;
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2011-10-11 18:49:17 +00:00
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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// Format J instruction class in Mips : <|opcode|address|>
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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2013-10-29 16:38:59 +00:00
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class FJ<bits<6> op> : StdArch
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2007-06-06 07:42:06 +00:00
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{
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2012-12-21 23:03:50 +00:00
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bits<26> target;
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2007-06-06 07:42:06 +00:00
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2012-12-21 23:03:50 +00:00
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bits<32> Inst;
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2011-03-04 17:51:39 +00:00
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2012-12-21 23:03:50 +00:00
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let Inst{31-26} = op;
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let Inst{25-0} = target;
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2007-06-06 07:42:06 +00:00
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}
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2007-10-09 02:55:31 +00:00
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2013-01-04 19:38:05 +00:00
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//===----------------------------------------------------------------------===//
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2012-10-06 01:17:37 +00:00
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// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
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//===----------------------------------------------------------------------===//
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2013-01-04 19:13:49 +00:00
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class MFC3OP_FM<bits<6> op, bits<5> mfmt>
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2012-10-06 01:17:37 +00:00
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{
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bits<5> rt;
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bits<5> rd;
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bits<3> sel;
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2013-01-04 19:13:49 +00:00
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bits<32> Inst;
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2012-10-06 01:17:37 +00:00
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2013-01-04 19:13:49 +00:00
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let Inst{31-26} = op;
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2012-10-06 01:17:37 +00:00
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let Inst{25-21} = mfmt;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-3} = 0;
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let Inst{2-0} = sel;
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}
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2013-04-19 19:03:11 +00:00
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class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
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2012-12-20 03:34:05 +00:00
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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2013-04-19 19:03:11 +00:00
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class ADDI_FM<bits<6> op> : StdArch {
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2012-12-20 03:40:03 +00:00
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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2013-04-25 01:11:15 +00:00
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class SRA_FM<bits<6> funct, bit rotate> : StdArch {
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2012-12-20 03:44:41 +00:00
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bits<5> rd;
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bits<5> rt;
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bits<5> shamt;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-22} = 0;
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let Inst{21} = rotate;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = shamt;
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let Inst{5-0} = funct;
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}
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2013-04-25 01:11:15 +00:00
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class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
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2012-12-20 03:48:24 +00:00
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bits<5> rd;
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bits<5> rt;
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-7} = 0;
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let Inst{6} = rotate;
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let Inst{5-0} = funct;
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}
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2013-11-04 14:53:22 +00:00
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class BEQ_FM<bits<6> op> : StdArch {
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2012-12-20 04:10:13 +00:00
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bits<5> rs;
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
|
|
|
|
let Inst{15-0} = offset;
|
|
|
|
}
|
|
|
|
|
2013-11-04 14:53:22 +00:00
|
|
|
class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
|
2012-12-20 04:13:23 +00:00
|
|
|
bits<5> rs;
|
|
|
|
bits<16> offset;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = op;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = funct;
|
|
|
|
let Inst{15-0} = offset;
|
|
|
|
}
|
|
|
|
|
2013-04-19 19:03:11 +00:00
|
|
|
class SLTI_FM<bits<6> op> : StdArch {
|
2012-12-20 04:27:52 +00:00
|
|
|
bits<5> rt;
|
|
|
|
bits<5> rs;
|
|
|
|
bits<16> imm16;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = op;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-0} = imm16;
|
|
|
|
}
|
|
|
|
|
2013-09-06 12:53:21 +00:00
|
|
|
class MFLO_FM<bits<6> funct> : StdArch {
|
2012-12-21 22:39:17 +00:00
|
|
|
bits<5> rd;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0;
|
|
|
|
let Inst{25-16} = 0;
|
|
|
|
let Inst{15-11} = rd;
|
|
|
|
let Inst{10-6} = 0;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
2013-09-06 12:53:21 +00:00
|
|
|
class MTLO_FM<bits<6> funct> : StdArch {
|
2012-12-21 22:39:17 +00:00
|
|
|
bits<5> rs;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-6} = 0;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
2013-09-14 06:49:25 +00:00
|
|
|
class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
|
2012-12-21 22:41:52 +00:00
|
|
|
bits<5> rd;
|
|
|
|
bits<5> rt;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x1f;
|
|
|
|
let Inst{25-21} = 0;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = rd;
|
|
|
|
let Inst{10-6} = funct;
|
2012-12-21 23:21:32 +00:00
|
|
|
let Inst{5-0} = funct2;
|
2012-12-21 22:41:52 +00:00
|
|
|
}
|
|
|
|
|
2013-09-14 06:49:25 +00:00
|
|
|
class CLO_FM<bits<6> funct> : StdArch {
|
2012-12-21 22:43:58 +00:00
|
|
|
bits<5> rd;
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> rt;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x1c;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = rd;
|
|
|
|
let Inst{10-6} = 0;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
let rt = rd;
|
|
|
|
}
|
|
|
|
|
2013-09-14 07:35:41 +00:00
|
|
|
class LUI_FM : StdArch {
|
2012-12-21 22:46:07 +00:00
|
|
|
bits<5> rt;
|
|
|
|
bits<16> imm16;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0xf;
|
|
|
|
let Inst{25-21} = 0;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-0} = imm16;
|
|
|
|
}
|
|
|
|
|
2014-03-20 10:18:24 +00:00
|
|
|
class JALR_FM {
|
2013-02-07 19:48:00 +00:00
|
|
|
bits<5> rd;
|
2012-12-21 23:03:50 +00:00
|
|
|
bits<5> rs;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = 0;
|
2013-02-07 19:48:00 +00:00
|
|
|
let Inst{15-11} = rd;
|
2012-12-21 23:03:50 +00:00
|
|
|
let Inst{10-6} = 0;
|
|
|
|
let Inst{5-0} = 9;
|
|
|
|
}
|
|
|
|
|
2013-11-04 14:53:22 +00:00
|
|
|
class BGEZAL_FM<bits<5> funct> : StdArch {
|
2012-12-21 23:15:59 +00:00
|
|
|
bits<5> rs;
|
|
|
|
bits<16> offset;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 1;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = funct;
|
|
|
|
let Inst{15-0} = offset;
|
|
|
|
}
|
|
|
|
|
2013-12-19 16:25:00 +00:00
|
|
|
class SYNC_FM : StdArch {
|
2012-12-21 23:17:36 +00:00
|
|
|
bits<5> stype;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0;
|
|
|
|
let Inst{10-6} = stype;
|
|
|
|
let Inst{5-0} = 0xf;
|
|
|
|
}
|
|
|
|
|
2013-04-19 19:03:11 +00:00
|
|
|
class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
|
2012-12-21 23:17:36 +00:00
|
|
|
bits<5> rs;
|
|
|
|
bits<5> rt;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = op;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-6} = 0;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
2013-09-14 06:49:25 +00:00
|
|
|
class EXT_FM<bits<6> funct> : StdArch {
|
2012-12-21 23:21:32 +00:00
|
|
|
bits<5> rt;
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> pos;
|
|
|
|
bits<5> size;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x1f;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = size;
|
|
|
|
let Inst{10-6} = pos;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
|
|
|
class RDHWR_FM {
|
|
|
|
bits<5> rt;
|
|
|
|
bits<5> rd;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x1f;
|
|
|
|
let Inst{25-21} = 0;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = rd;
|
|
|
|
let Inst{10-6} = 0;
|
|
|
|
let Inst{5-0} = 0x3b;
|
|
|
|
}
|
|
|
|
|
2013-11-07 14:35:24 +00:00
|
|
|
class TEQ_FM<bits<6> funct> : StdArch {
|
2013-05-20 18:07:43 +00:00
|
|
|
bits<5> rs;
|
|
|
|
bits<5> rt;
|
|
|
|
bits<10> code_;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-6} = code_;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
2013-11-13 13:15:03 +00:00
|
|
|
class TEQI_FM<bits<5> funct> : StdArch {
|
2013-08-26 10:02:40 +00:00
|
|
|
bits<5> rs;
|
|
|
|
bits<16> imm16;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 1;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = funct;
|
|
|
|
let Inst{15-0} = imm16;
|
|
|
|
}
|
2013-12-19 16:25:00 +00:00
|
|
|
|
|
|
|
class WAIT_FM : StdArch {
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x10;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-6} = 0;
|
|
|
|
let Inst{5-0} = 0x20;
|
|
|
|
}
|
|
|
|
|
2014-04-02 18:40:43 +00:00
|
|
|
class EXTS_FM<bits<6> funct> : StdArch {
|
|
|
|
bits<5> rt;
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> pos;
|
|
|
|
bits<5> lenm1;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x1c;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = lenm1;
|
|
|
|
let Inst{10-6} = pos;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
2014-04-01 18:35:26 +00:00
|
|
|
class MTMR_FM<bits<6> funct> : StdArch {
|
|
|
|
bits<5> rs;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x1c;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-6} = 0;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
2014-03-20 11:51:58 +00:00
|
|
|
class POP_FM<bits<6> funct> : StdArch {
|
|
|
|
bits<5> rd;
|
|
|
|
bits<5> rs;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x1c;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = 0;
|
|
|
|
let Inst{15-11} = rd;
|
|
|
|
let Inst{10-6} = 0;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
|
|
|
class SEQ_FM<bits<6> funct> : StdArch {
|
|
|
|
bits<5> rd;
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> rt;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x1c;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = rd;
|
|
|
|
let Inst{10-6} = 0;
|
|
|
|
let Inst{5-0} = funct;
|
2014-04-04 16:21:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
class SEQI_FM<bits<6> funct> : StdArch {
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> rt;
|
|
|
|
bits<10> imm10;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x1c;
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-6} = imm10;
|
|
|
|
let Inst{5-0} = funct;
|
2014-03-20 11:51:58 +00:00
|
|
|
}
|
|
|
|
|
2013-07-12 09:25:35 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// System calls format <op|code_|funct>
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2013-12-19 16:25:00 +00:00
|
|
|
class SYS_FM<bits<6> funct> : StdArch
|
2013-07-12 09:25:35 +00:00
|
|
|
{
|
|
|
|
bits<20> code_;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x0;
|
|
|
|
let Inst{25-6} = code_;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Break instruction format <op|code_1|funct>
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2013-12-19 16:25:00 +00:00
|
|
|
class BRK_FM<bits<6> funct> : StdArch
|
2013-07-12 09:25:35 +00:00
|
|
|
{
|
|
|
|
bits<10> code_1;
|
|
|
|
bits<10> code_2;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x0;
|
|
|
|
let Inst{25-16} = code_1;
|
|
|
|
let Inst{15-6} = code_2;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2013-07-17 14:05:19 +00:00
|
|
|
// Exception return format <Cop0|1|0|funct>
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2013-12-19 16:25:00 +00:00
|
|
|
class ER_FM<bits<6> funct> : StdArch
|
2013-07-17 14:05:19 +00:00
|
|
|
{
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x10;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-6} = 0;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
2013-08-12 13:07:23 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2013-12-19 16:25:00 +00:00
|
|
|
class EI_FM<bits<1> sc> : StdArch
|
2013-08-12 13:07:23 +00:00
|
|
|
{
|
|
|
|
bits<32> Inst;
|
|
|
|
bits<5> rt;
|
|
|
|
let Inst{31-26} = 0x10;
|
|
|
|
let Inst{25-21} = 0xb;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = 0xc;
|
|
|
|
let Inst{10-6} = 0;
|
|
|
|
let Inst{5} = sc;
|
|
|
|
let Inst{4-0} = 0;
|
|
|
|
}
|
|
|
|
|
2013-07-17 14:05:19 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2008-06-08 01:39:36 +00:00
|
|
|
//
|
2008-07-09 04:45:36 +00:00
|
|
|
// FLOATING POINT INSTRUCTION FORMATS
|
2008-06-08 01:39:36 +00:00
|
|
|
//
|
|
|
|
// opcode - operation code.
|
|
|
|
// fs - src reg.
|
|
|
|
// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
|
|
|
|
// fd - dst reg, only used on 3 regs instr.
|
|
|
|
// fmt - double or single precision.
|
|
|
|
// funct - combined with opcode field give us an operation code.
|
|
|
|
//
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2008-06-08 01:39:36 +00:00
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2008-06-08 01:39:36 +00:00
|
|
|
|
2011-03-04 17:51:39 +00:00
|
|
|
class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
|
2012-07-31 18:55:01 +00:00
|
|
|
InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
|
2008-06-08 01:39:36 +00:00
|
|
|
{
|
|
|
|
bits<5> ft;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
bits<5> base;
|
2008-06-08 01:39:36 +00:00
|
|
|
bits<16> imm16;
|
|
|
|
|
2011-10-18 17:50:36 +00:00
|
|
|
let Opcode = op;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
|
|
|
let Inst{25-21} = base;
|
2011-03-04 17:51:39 +00:00
|
|
|
let Inst{20-16} = ft;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
let Inst{15-0} = imm16;
|
|
|
|
}
|
|
|
|
|
2013-12-20 15:44:08 +00:00
|
|
|
class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
|
2012-12-13 01:07:37 +00:00
|
|
|
bits<5> fd;
|
|
|
|
bits<5> fs;
|
|
|
|
bits<5> ft;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
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|
|
|
let Inst{31-26} = 0x11;
|
|
|
|
let Inst{25-21} = fmt;
|
|
|
|
let Inst{20-16} = ft;
|
|
|
|
let Inst{15-11} = fs;
|
|
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|
let Inst{10-6} = fd;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
2012-12-13 01:14:07 +00:00
|
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|
|
2013-12-20 15:44:08 +00:00
|
|
|
class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
|
2012-12-13 01:14:07 +00:00
|
|
|
bits<5> fd;
|
|
|
|
bits<5> fs;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
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|
|
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|
let Inst{31-26} = 0x11;
|
|
|
|
let Inst{25-21} = fmt;
|
|
|
|
let Inst{20-16} = 0;
|
|
|
|
let Inst{15-11} = fs;
|
|
|
|
let Inst{10-6} = fd;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
2012-12-13 01:16:49 +00:00
|
|
|
|
2013-12-25 10:09:27 +00:00
|
|
|
class MFC1_FM<bits<5> funct> : StdArch {
|
2012-12-13 01:16:49 +00:00
|
|
|
bits<5> rt;
|
|
|
|
bits<5> fs;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
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|
let Inst{31-26} = 0x11;
|
|
|
|
let Inst{25-21} = funct;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = fs;
|
|
|
|
let Inst{10-0} = 0;
|
|
|
|
}
|
2012-12-13 01:24:00 +00:00
|
|
|
|
2013-04-25 01:21:25 +00:00
|
|
|
class LW_FM<bits<6> op> : StdArch {
|
2012-12-13 01:24:00 +00:00
|
|
|
bits<5> rt;
|
|
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|
bits<21> addr;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
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|
let Inst{31-26} = op;
|
|
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|
let Inst{25-21} = addr{20-16};
|
|
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|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-0} = addr{15-0};
|
|
|
|
}
|
2012-12-13 01:27:48 +00:00
|
|
|
|
2013-12-20 15:44:08 +00:00
|
|
|
class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
|
2012-12-13 01:27:48 +00:00
|
|
|
bits<5> fd;
|
|
|
|
bits<5> fr;
|
|
|
|
bits<5> fs;
|
|
|
|
bits<5> ft;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x13;
|
|
|
|
let Inst{25-21} = fr;
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|
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|
let Inst{20-16} = ft;
|
|
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|
let Inst{15-11} = fs;
|
|
|
|
let Inst{10-6} = fd;
|
|
|
|
let Inst{5-3} = funct;
|
|
|
|
let Inst{2-0} = fmt;
|
|
|
|
}
|
2012-12-13 01:30:49 +00:00
|
|
|
|
2013-12-20 15:44:08 +00:00
|
|
|
class LWXC1_FM<bits<6> funct> : StdArch {
|
2012-12-13 01:30:49 +00:00
|
|
|
bits<5> fd;
|
|
|
|
bits<5> base;
|
|
|
|
bits<5> index;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x13;
|
|
|
|
let Inst{25-21} = base;
|
|
|
|
let Inst{20-16} = index;
|
|
|
|
let Inst{15-11} = 0;
|
|
|
|
let Inst{10-6} = fd;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
2013-12-20 15:44:08 +00:00
|
|
|
class SWXC1_FM<bits<6> funct> : StdArch {
|
2012-12-13 01:30:49 +00:00
|
|
|
bits<5> fs;
|
|
|
|
bits<5> base;
|
|
|
|
bits<5> index;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x13;
|
|
|
|
let Inst{25-21} = base;
|
|
|
|
let Inst{20-16} = index;
|
|
|
|
let Inst{15-11} = fs;
|
|
|
|
let Inst{10-6} = 0;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
2012-12-13 01:32:36 +00:00
|
|
|
|
2013-12-20 15:44:08 +00:00
|
|
|
class BC1F_FM<bit nd, bit tf> : StdArch {
|
2013-07-26 20:13:47 +00:00
|
|
|
bits<3> fcc;
|
2012-12-13 01:32:36 +00:00
|
|
|
bits<16> offset;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x11;
|
|
|
|
let Inst{25-21} = 0x8;
|
2013-07-26 20:13:47 +00:00
|
|
|
let Inst{20-18} = fcc;
|
2012-12-13 01:32:36 +00:00
|
|
|
let Inst{17} = nd;
|
|
|
|
let Inst{16} = tf;
|
|
|
|
let Inst{15-0} = offset;
|
|
|
|
}
|
2012-12-13 01:34:09 +00:00
|
|
|
|
2013-12-20 15:44:08 +00:00
|
|
|
class CEQS_FM<bits<5> fmt> : StdArch {
|
2012-12-13 01:34:09 +00:00
|
|
|
bits<5> fs;
|
|
|
|
bits<5> ft;
|
|
|
|
bits<4> cond;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x11;
|
|
|
|
let Inst{25-21} = fmt;
|
|
|
|
let Inst{20-16} = ft;
|
|
|
|
let Inst{15-11} = fs;
|
|
|
|
let Inst{10-8} = 0; // cc
|
|
|
|
let Inst{7-4} = 0x3;
|
|
|
|
let Inst{3-0} = cond;
|
|
|
|
}
|
2012-12-13 01:41:15 +00:00
|
|
|
|
2013-07-16 10:07:14 +00:00
|
|
|
class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
|
|
|
|
let cond = c;
|
|
|
|
}
|
|
|
|
|
2013-12-25 10:09:27 +00:00
|
|
|
class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
|
2012-12-13 01:41:15 +00:00
|
|
|
bits<5> fd;
|
|
|
|
bits<5> fs;
|
|
|
|
bits<5> rt;
|
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x11;
|
|
|
|
let Inst{25-21} = fmt;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = fs;
|
|
|
|
let Inst{10-6} = fd;
|
|
|
|
let Inst{5-0} = funct;
|
|
|
|
}
|
|
|
|
|
2013-09-06 12:41:17 +00:00
|
|
|
class CMov_F_I_FM<bit tf> : StdArch {
|
2012-12-13 01:41:15 +00:00
|
|
|
bits<5> rd;
|
|
|
|
bits<5> rs;
|
2013-07-26 20:51:20 +00:00
|
|
|
bits<3> fcc;
|
2012-12-13 01:41:15 +00:00
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0;
|
|
|
|
let Inst{25-21} = rs;
|
2013-07-26 20:51:20 +00:00
|
|
|
let Inst{20-18} = fcc;
|
2012-12-13 01:41:15 +00:00
|
|
|
let Inst{17} = 0;
|
|
|
|
let Inst{16} = tf;
|
|
|
|
let Inst{15-11} = rd;
|
|
|
|
let Inst{10-6} = 0;
|
|
|
|
let Inst{5-0} = 1;
|
|
|
|
}
|
|
|
|
|
2013-12-25 10:09:27 +00:00
|
|
|
class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
|
2012-12-13 01:41:15 +00:00
|
|
|
bits<5> fd;
|
|
|
|
bits<5> fs;
|
2013-07-26 20:51:20 +00:00
|
|
|
bits<3> fcc;
|
2012-12-13 01:41:15 +00:00
|
|
|
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x11;
|
|
|
|
let Inst{25-21} = fmt;
|
2013-07-26 20:51:20 +00:00
|
|
|
let Inst{20-18} = fcc;
|
2012-12-13 01:41:15 +00:00
|
|
|
let Inst{17} = 0;
|
|
|
|
let Inst{16} = tf;
|
|
|
|
let Inst{15-11} = fs;
|
|
|
|
let Inst{10-6} = fd;
|
|
|
|
let Inst{5-0} = 0x11;
|
|
|
|
}
|
2014-04-03 13:21:51 +00:00
|
|
|
|
|
|
|
class BARRIER_FM<bits<5> op> : StdArch {
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0; // SPECIAL
|
|
|
|
let Inst{25-21} = 0;
|
|
|
|
let Inst{20-16} = 0; // rt = 0
|
|
|
|
let Inst{15-11} = 0; // rd = 0
|
|
|
|
let Inst{10-6} = op; // Operation
|
|
|
|
let Inst{5-0} = 0; // SLL
|
|
|
|
}
|
2014-05-08 11:51:18 +00:00
|
|
|
|
|
|
|
class COP0_TLB_FM<bits<6> op> : StdArch {
|
|
|
|
bits<32> Inst;
|
|
|
|
|
|
|
|
let Inst{31-26} = 0x10; // COP0
|
|
|
|
let Inst{25} = 1; // CO
|
|
|
|
let Inst{24-6} = 0;
|
|
|
|
let Inst{5-0} = op; // Operation
|
|
|
|
}
|