Bruno Cardoso Lopes
96716c7b92
Remove trailing whitespaces from file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:07:19 +00:00
Chris Lattner
599b531a96
Change LEA to have 5 operands for its memory operand, just
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like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 23:46:44 +00:00
Chris Lattner
ac0ed5dc08
add some long-overdue enums to refer to the parts of the 5-operand
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X86 memory operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107925 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:41:28 +00:00
Jakob Stoklund Olesen
61c8eccf24
Remember the VR64 register class
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107920 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:30:35 +00:00
Chris Lattner
834df19452
Rework segment prefix emission code to handle segments
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in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:28:12 +00:00
Chris Lattner
751e1123ce
introduce a new X86II::getMemoryOperandNo method, which
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returns the start of the memory operand for an instruction.
Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:27:06 +00:00
Jakob Stoklund Olesen
7db1e7a527
Teach the x86 floating point stackifier to handle COPY instructions.
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This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.
Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 19:46:30 +00:00
Jakob Stoklund Olesen
320bdcbfe2
Implement X86InstrInfo::copyPhysReg
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 19:46:25 +00:00
Jakob Stoklund Olesen
0bc25f4040
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
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EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:40:22 +00:00
Jakob Stoklund Olesen
5c00e07795
Remove references to INSERT_SUBREG after de-SSA.
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Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:40:15 +00:00
Eric Christopher
fb31ccb68c
A slight reworking of the custom patterns for x86-64 tpoff codegen and
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correct the testcase for valid assembly.
Needs more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 07:36:46 +00:00
Dan Gohman
f595141525
Revert 107840 107839 107813 107804 107800 107797 107791.
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Debug info intrinsics win for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 01:00:56 +00:00
Jakob Stoklund Olesen
5febd075df
fix copies to/from GR8_ABCD_H even more
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107832 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 23:04:56 +00:00
Chris Lattner
da3051a17f
finish up support for callw: PR7195
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:35:13 +00:00
Chris Lattner
9fc05227a2
Implement the major chunk of PR7195: support for 'callw'
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in the integrated assembler. Still some discussion to be
done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
cc69e13a36
Add more assembly opcodes for SSE compare instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:24:03 +00:00
Evan Cheng
bcc8017c73
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:15:37 +00:00
Devang Patel
03753fc734
Print undefined/unknown debug value as "undef".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 21:52:21 +00:00
Jakob Stoklund Olesen
f2e4afd96c
Allow copies between GR8_ABCD_L and GR8_ABCD_H.
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This fixes PR7540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 20:33:27 +00:00
Dan Gohman
4df83ed159
Implement bottom-up fast-isel. This has the advantage of not requiring
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a separate DCE pass over MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 19:20:32 +00:00
Dan Gohman
f423a69839
Add X86FastISel support for return statements. This entails refactoring
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a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:32:53 +00:00
Bruno Cardoso Lopes
ced9ec9bac
Add AVX AES instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:24:20 +00:00
Dan Gohman
eabaed26c3
Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
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around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 16:47:08 +00:00
Dan Gohman
a4160c3434
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
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instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 16:29:44 +00:00
Dan Gohman
c9403659a9
Split the SDValue out of OutputArg so that SelectionDAG-independent
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code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 15:54:55 +00:00
Bruno Cardoso Lopes
4f6bdf9042
Add AVX SSE4.2 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
332fce49e3
Use only one multiclass to pinsrq instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes
5e9fa98523
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes
09df2ae0d0
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
3c14822312
Add AVX SSE4.1 extractps and pinsr instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:01:13 +00:00
Bruno Cardoso Lopes
4fd32db6a6
Add AVX SSE4.1 Extract Integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 00:07:24 +00:00
Dale Johannesen
e2b448c208
Accept RIP-relative symbols with 'i' constraint, and
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print the (%rip) only if the 'a' modifier is present.
PR 7528.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:27:00 +00:00
Bruno Cardoso Lopes
ee94e8297e
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
36869b69b0
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
0106680a2c
Fix comment from previous patch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes
07de40629f
Add AVX vblendvpd, vblendvps and vpblendvb instructions
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Update VEX encoding to support those new instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:36:24 +00:00
Dan Gohman
c9af33c685
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
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SelectBasicBlock doesn't needs its BasicBlock argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:19:37 +00:00
Devang Patel
0d881dabc1
Propagate debug loc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:08:15 +00:00
Dan Gohman
14152b480d
Reapply r107655 with fixes; insert the pseudo instruction into
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the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 20:24:04 +00:00
Devang Patel
be35be614c
Fix PR7545 crash.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 18:18:32 +00:00
Dan Gohman
258c58cc62
Revert r107655.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 15:49:48 +00:00
Dan Gohman
b81c771c0d
Fix a bunch of custom-inserter functions to handle the case where
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the pseudo instruction is not at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 15:18:19 +00:00
Eric Christopher
f7a0c7bf8b
Fix up -fstack-protector on linux to use the segment
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registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 05:18:56 +00:00
Eric Christopher
62f35a2c13
Have the X86 backend use Triple instead of a string and some enums.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107625 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 19:26:33 +00:00
Chris Lattner
32b4b5aea6
more tidying.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 05:53:14 +00:00
Chris Lattner
c06cbad141
some notes about suboptimal insertps's
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107613 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 05:48:41 +00:00
Chris Lattner
a5b412581c
rip out even more sporadic v2f32 support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107610 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 04:38:33 +00:00
Chris Lattner
39aa20a981
rip out the various v2f32 "mmx" handling logic, now that
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v2f32 is illegal on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107609 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05 04:36:27 +00:00
Chris Lattner
f172ecd964
Just rip v2f32 support completely out of the X86 backend. In
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the example in the testcase, we now generate:
_test1: ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret
instead of:
_test1: ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret
v2f32 support did not work reliably because most of the X86
backend didn't know it was legal. It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode. If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32. However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 23:07:25 +00:00
Chris Lattner
e35d9842f7
fix PR7518 - terrible codegen of <2 x float>, by only marking
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v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 22:57:10 +00:00
Chris Lattner
9d19989fe3
indentation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107599 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 22:56:10 +00:00
Bill Wendling
f43f6bc3ec
Revert r107583. I no longer think that this is the way to solve the problem.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 09:16:57 +00:00
Bill Wendling
4a991a6fa6
Mark sse_load_f32 and sse_load_f64 as having memory operands
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(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 08:59:55 +00:00
Bruno Cardoso Lopes
68b559e5f3
Add AVX SSE4.1 blend, mpsadbw and vdp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
4a544be3a8
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107558 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
c607570563
Add AVX SSE4.1 Horizontal Minimum and Position instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:49:21 +00:00
Evan Cheng
ed2ae136d2
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:40:23 +00:00
Bruno Cardoso Lopes
2c70d4ad35
Add AVX SSE4.1 round instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
03560600b4
Simple refactoring of SSE4.1 instructions, making room for the AVX forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107540 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 23:27:59 +00:00
Bruno Cardoso Lopes
f5cd8c51e3
- Add support for the rest of AVX SSE3 instructions
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- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 22:06:54 +00:00
Evan Cheng
98ec91ea80
- Two-address pass should not assume unfolding is always successful.
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- X86 unfolding should check if the instructions being unfolded has memoperands.
If there is no memoperands, then it must assume conservative alignment. If this
would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
etc. should not unfold the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 20:36:18 +00:00
Bruno Cardoso Lopes
f12ad66741
Shrink down SSE3 code by more multiclass refactoring
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 23:10:49 +00:00
Bruno Cardoso Lopes
944facac2e
Shrink down SSE3 code by some multiclass refactoring - 1st part
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 22:33:18 +00:00
Bruno Cardoso Lopes
c6fcdeb8f9
Move SSE3 Move patterns to a more appropriate section
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Add AVX SSE3 packed horizontal and & sub instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
7144821c61
Add AVX SSE3 packed addsub instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 17:08:18 +00:00
Dan Gohman
20d4be151b
Enable on-demand fast-isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:58:57 +00:00
Dan Gohman
abd1d859b3
Fix X86FastISel's add folding to actually work, and not fall back
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to SelectionDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:58:21 +00:00
Bruno Cardoso Lopes
79b634c244
Add AVX SSE3 replicate and convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:33:39 +00:00
Dan Gohman
5c87bf64d6
Teach X86FastISel to fold constant offsets and scaled indices in
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the same address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:27:15 +00:00
Bruno Cardoso Lopes
6596a62076
- Add AVX SSE2 Move doubleword and quadword instructions.
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- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
7ac7ed868a
Move MOVD/MODQ code around, creating sections for each of them
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes
e26f14d150
Add AVX SSE2 mask creation and conditional store instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
130acd15fc
Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes
1e4b723b20
Add AVX SSE2 packed integer extract/insert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 17:03:03 +00:00
Gabor Greif
e1c2b9cc3d
use ArgOperand API
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 13:03:37 +00:00
Bruno Cardoso Lopes
876085dcfa
Add AVX SSE2 integer unpack instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
d252fec7ae
Add AVX SSE2 packed integer shuffle instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
555bea62dd
Small refactoring of SSE2 packed integer shuffle instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes
6d5d2b5de2
Add AVX SSE2 pack with saturation integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c0ea94a37c
Add AVX SSE2 integer packed compare instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
5a3a476750
- Add AVX form of all SSE2 logical instructions
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- Add VEX encoding bits to x86 MRM0r-MRM7r
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
6c9fa43716
Add *several* AVX integer packed binop instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes
2c818072cc
Move SSE2 Packed Integer instructions around, and create specific sections for each of them
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107211 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes
8d3cebca8e
Add AVX Move Aligned/Unaligned packed integers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 21:25:12 +00:00
Bruno Cardoso Lopes
147b7cad2f
Add AVX ld/st XCSR register.
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Add VEX encoding bits for MRMXm x86 form
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
721ef73d88
Add AVX non-temporal stores
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107178 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
de173ca1fb
Move non-temporal movs to their own section
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:42:37 +00:00
Bruno Cardoso Lopes
ea86423cbd
Add sqrt, rsqrt and rcp AVX instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107166 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:26:30 +00:00
Duncan Sands
78337b4d4d
Remove pointless and unused variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 12:48:49 +00:00
Bruno Cardoso Lopes
b22dc70a5c
Refactoring of arithmetic instruction classes with unary operator
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 01:33:09 +00:00
Bruno Cardoso Lopes
4548260ab5
Described the missing AVX forms of SSE2 convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 00:36:02 +00:00
Bill Wendling
c25ccf85e5
Reduce indentation via early exit. NFC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 21:08:32 +00:00
Gabor Greif
1cfe44a460
use ArgOperand API
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 11:51:52 +00:00
Jakob Stoklund Olesen
4f5d84e4ad
When creating X86 MUL8 and DIV8 instructions, make sure we don't produce
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CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.
Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).
This fixes PR7312.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 00:39:23 +00:00
Bruno Cardoso Lopes
bdffc16d65
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes
161476ec34
Reapply r106896:
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Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
95325b08a3
revert this now, it's using avx instead of sse :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes
544a95d716
Add several AVX MOV flavors
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Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:27:51 +00:00
Dale Johannesen
1784d160e4
The hasMemory argument is irrelevant to how the argument
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for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:55:36 +00:00
Dan Gohman
ca5b8553ea
pcmpeqd and friends are Commutable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:05:35 +00:00
Bill Wendling
730c07e50d
- Reapply r106066 now that the bzip2 build regression has been fixed.
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- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 20:48:10 +00:00
Bruno Cardoso Lopes
39afa908de
Move the last piece of SSE2 convert instructions to the Convert Instructions section
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106877 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 20:29:27 +00:00
Bruno Cardoso Lopes
6560ed35b4
More SSE refactoring, this time with different types of MOVs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 20:22:12 +00:00
Bruno Cardoso Lopes
0491e132fc
Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 18:06:22 +00:00
Bruno Cardoso Lopes
a0ae87fd5d
Add some AVX convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
8b94297727
Refactoring of SSE convert intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 23:37:07 +00:00
Bruno Cardoso Lopes
f241b26792
Refactoring of SSE conversion instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 22:22:21 +00:00
Bruno Cardoso Lopes
e0c437333e
Refactor SSE cmp intrinsics and declare the same for AVX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 22:04:40 +00:00
Bruno Cardoso Lopes
788184365a
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
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- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 20:48:23 +00:00
Dale Johannesen
e5ff9ef195
Disallow matching "i" constraint to symbol addresses when
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address requires a register or secondary load to compute
(most PIC modes). This improves "g" constraint handling. 8015842.
The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously. Fixed to use Linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106779 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 20:14:51 +00:00
Dan Gohman
4e39e9da0f
Reapply r106634, now that the bug it exposed is fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 14:30:44 +00:00
Chris Lattner
645b209c4a
Teach the x86 mc assembler that %dr6 = %db6, this implements
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rdar://8013734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106725 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 07:29:18 +00:00
Chris Lattner
adabe1a92c
more cleanups
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106724 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 07:18:14 +00:00
Chris Lattner
02758a44e4
reduce indentation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 07:16:25 +00:00
Dan Gohman
6b13cbca61
Fix a bug in the code which determines when it's safe to use the
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bt instruction, which was exposed by r106263.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 02:07:59 +00:00
Eric Christopher
37106afe02
Add a couple more quick comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 02:07:57 +00:00
Bruno Cardoso Lopes
6539dc6e6c
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
34a491bd8e
Move SSE and AVX shuffle, unpack and compare code to more appropriate places
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:15:50 +00:00
Bruno Cardoso Lopes
e93e300ad0
Add AVX MOVMSK{PS,PD}rr instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
428256b818
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 21:10:57 +00:00
Eric Christopher
749bb7e2d9
Update according to feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:49:35 +00:00
Bruno Cardoso Lopes
7dbfd07e32
Add AVX SHUF{PS,PD}{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106672 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:07:15 +00:00
Nico Weber
50b9efc2a8
Add support for the x86 instructions "pusha" and "popa".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:00:58 +00:00
Daniel Dunbar
cbe762b5d1
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 17:09:26 +00:00
Jim Grosbach
f1ab49e83a
The generic DAG combiner can now fold atomic fences when needed, so switch
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to using that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 16:25:07 +00:00
Eric Christopher
18ebf74781
Update uses, defs, and comments for darwin tls patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 08:01:49 +00:00
Daniel Dunbar
d24c9d5f91
Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.
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Conflicts:
lib/CodeGen/MachineSink.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106614 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 00:48:25 +00:00
Bruno Cardoso Lopes
62a76c6401
Add AVX compare packed instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
0caca3967b
Reapply support for AVX unpack and interleave instructions, with
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testcases this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
c3d57b179c
Add AVX MOV{SS,SD}{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:38:56 +00:00
Bill Wendling
19d8597bca
Fix the formatting of the switch statement and add a missing break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:16:17 +00:00
Jim Grosbach
dd11ee2273
fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106574 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 20:52:02 +00:00
Bruno Cardoso Lopes
d3a067bbc2
Reorganize logical and arithmetic SSE 1 & 2 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 18:17:40 +00:00
Bruno Cardoso Lopes
f23919b3e9
Reorganize SSE instructions, making easier to see oportunities for refactoring
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106556 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 18:09:32 +00:00
Dan Gohman
fe60104ac9
Use pre-increment instead of post-increment when the result is not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 15:08:57 +00:00
Bruno Cardoso Lopes
c27d1e4d17
revert r106482
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106499 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 22:59:03 +00:00
Bruno Cardoso Lopes
b7cc3f6ae6
change parameter name to avoid confusion with global definition
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106486 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:28:07 +00:00
Bruno Cardoso Lopes
b44e8b2d11
Add unpack and interleave AVX instructions, encoding tests cooming soon
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:21:48 +00:00
Bruno Cardoso Lopes
c79e43aee3
Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:36:04 +00:00
Bruno Cardoso Lopes
59bb6fae9a
Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106436 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:22:54 +00:00
Eric Christopher
18fb00b4b9
Add some codegen patterns for x86_64-linux-gnu tls codegen matching.
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Based on a patch by Patrick Marlier!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:21:27 +00:00
Rafael Espindola
c2b3e00cdf
Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch.
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I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 13:31:32 +00:00
Rafael Espindola
f0efafa61e
wip
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106408 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 02:17:34 +00:00
Nick Lewycky
2a3ee5e8e9
Fix warning in no-asserts build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-20 20:27:42 +00:00
Bruno Cardoso Lopes
f6ff003043
Refactoring of regular logical packed instructions to prepare for AVX ones.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 04:09:22 +00:00
Bruno Cardoso Lopes
f4f4bad696
Refactor aliased packed logical instructions, also add
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AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 02:44:01 +00:00
Bruno Cardoso Lopes
1e8d06282f
Move new sse 1 & 2 generic classes to a more appropriate place
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:32:46 +00:00
Bruno Cardoso Lopes
efc9b69deb
Remove unnecessary arguments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:22:34 +00:00
Bruno Cardoso Lopes
17227db062
Add AVX packed intrinsics for MIN, MAX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:17:05 +00:00
Eric Christopher
a938cfb13a
Finish ripping isTwoAddress out of X86. Some mindless formatting
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and operand renaming to help.
The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:37:40 +00:00