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3726 Commits

Author SHA1 Message Date
Evan Cheng
416941d50f Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 05:19:35 +00:00
Jim Grosbach
70933266ae Add ARM fixup info for load/store label references. Probably will need a bit of 
tweaking when we start using it for object file emission or JIT, but it's a
start.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118221 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 01:12:30 +00:00
Bill Wendling
2f46f1f59c Add encoding for VSTR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 00:59:42 +00:00
Jim Grosbach
806e80ef42 Teach ARM Target to use the tblgen support for generating an MC'ized 
CodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118209 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 23:52:49 +00:00
Owen Anderson
60f4870c22 Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. 
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 23:15:26 +00:00
Owen Anderson
d966817f3c Add support for code generation of the one register with immediate form of vorr. 
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 22:44:51 +00:00
Jim Grosbach
35b2de012d trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 22:03:20 +00:00
Eric Christopher
e5b13cfdd0 Optimize generated code for integer materialization a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118192 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 20:21:17 +00:00
Owen Anderson
7a25825033 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, 
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 18:16:27 +00:00
Bob Wilson
d168cef664 Add codegen patterns for VST1-lane instructions. Radar 8599955. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 16:24:53 +00:00
Bob Wilson
3468c2ee20 Check for extractelement with a variable operand for the element number. 
For NEON we had been assuming this was always an immediate constant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 16:24:50 +00:00
Duncan Sands
cdfad36b40 Simplify uses of MVT and EVT. An MVT can be compared directly 
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 12:17:33 +00:00
Duncan Sands
1440e8b918 Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 11:35:31 +00:00
Evan Cheng
dfed19fe2c Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 06:34:55 +00:00
Evan Cheng
bc7deb0f75 Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 05:14:24 +00:00
Bill Wendling
cdbbec43a8 Put the PC encoding in the correct bit position. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118151 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 04:57:44 +00:00
Eric Christopher
000cf708ef Invert these branches by default, it makes assembly comparisons a little 
easier to read.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118148 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 04:29:11 +00:00
Bill Wendling
92b5a2eb16 The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:49:29 +00:00
Jim Grosbach
2915eb4430 Remove unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118141 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:35:15 +00:00
Jim Grosbach
0a2287b909 Remove the no longer used 'Modifier' optional operand to the ARM 
printOperand() asm printer helper functions. rdar://8425198

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118140 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:11:15 +00:00
Jim Grosbach
496e2b2908 Remove unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118139 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:07:48 +00:00
Jim Grosbach
e6913600c7 Break ARM addrmode4 (load/store multiple base address) into its constituent 
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:01:43 +00:00
Evan Cheng
8239daf7c8 Two sets of changes. Sorry they are intermingled. 
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 00:45:17 +00:00
Evan Cheng
41957f6eb2 Modify scheduling itineraries to correct instruction latencies (not operand 
latencies) of loads.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118134 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 00:40:22 +00:00
Eric Christopher
4c914125c4 Make sure we're only storing a single bit here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118126 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 23:59:09 +00:00
Owen Anderson
f431edae5c Revert r118097 to fix buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 23:47:29 +00:00
Chris Lattner
a1ca91af4e Completely reject instructions that have an operand in their 
ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 23:40:41 +00:00
Bill Wendling
0800ce7189 Obsessive formatting changes. No functionality impact. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118103 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:53:11 +00:00
Bill Wendling
d3a124db4d Omit unused parameter name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118099 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:46:04 +00:00
Bill Wendling
7292e0a656 Simplify the EncodeInstruction method now that a lot of the special case stuff 
is handled with the MC encoder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118098 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:44:12 +00:00
Owen Anderson
1ba6064437 Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118097 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:41:42 +00:00
Bill Wendling
5df0e0a61d Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:31:46 +00:00
Owen Anderson
a2b50b300e Rename encoder methods to match naming convention. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118093 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:28:01 +00:00
Owen Anderson
b20594fce6 Provide correct encodings for the remaining vst variants that we currently generate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118087 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 22:18:18 +00:00
Owen Anderson
e95c946aeb Tentative encodings for the "single element from one lane" variant of vst1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118084 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 21:54:45 +00:00
Owen Anderson
a1a45fd254 Add correct encodings for basic variants for vst3 and vst4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 21:47:03 +00:00
Bob Wilson
d0c6bc2204 Add NEON VST1-lane instructions. Partial fix for Radar 8599955. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118069 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 21:18:25 +00:00
Owen Anderson
d2f3794e4d Add correct encodings for the basic variants for vst2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118068 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 21:16:58 +00:00
Owen Anderson
cfebe3a8b1 Add correct encodings for the basic form of vst1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 21:06:06 +00:00
Owen Anderson
d138d7034e Factor out a common encoding class for loads and stores with a lane parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118055 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 20:47:39 +00:00
Owen Anderson
f0ea0f2b15 Add correct encodings for the rest of the vld instructions that we generate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118053 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 20:40:59 +00:00
Jim Grosbach
28b108250d Sort bit assignments. Cosmetic change only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118029 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 17:59:04 +00:00
Jim Grosbach
ab3d00e535 Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke 
assumptions about stack layout. Specifically, LR must be saved next to FP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 17:35:25 +00:00
Owen Anderson
cf667be17b Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 01:24:55 +00:00
Eric Christopher
4053e63a4b Remove an assert - it's possible to be hit, and we just want to avoid 
handling those cases for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117996 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 01:24:49 +00:00
Eric Christopher
61d69da051 Whitespeace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117995 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 01:22:45 +00:00
Eric Christopher
aaa8df4cad No really, no thumb1 for arm fast isel. Also add an informative comment as 
to what someone would need to do to support thumb1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117994 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 01:21:28 +00:00
Owen Anderson
e85bd773e6 Attempt to provide correct encodings for a number of other vld1 variants, which we can't test 
since we can neither generate nor parse them at the moment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117988 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 00:24:52 +00:00
Owen Anderson
b552174a8c Add aesthetic break. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117986 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 00:14:00 +00:00
Owen Anderson
d9aa7d30aa Add correct NEON encodings for the "multiple single elements" form of vld. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-02 00:05:05 +00:00
Jim Grosbach
9af3d1c0dc Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME 
for handling the fixup necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117978 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 23:45:50 +00:00
Jim Grosbach
a502423d1e Remove unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117977 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 23:40:56 +00:00
Bob Wilson
665814b6be Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 23:40:51 +00:00
Bill Wendling
cd944a424c Missed reverting this bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117971 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 23:17:54 +00:00
Bill Wendling
160accad6b Minor cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117969 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 23:11:22 +00:00
Bob Wilson
b796bbb6de Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 22:04:05 +00:00
Bill Wendling
c2bf50245f Move the machine operand MC encoding patterns to the parent classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117956 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 21:17:06 +00:00
Bill Wendling
40a5eb18b0 When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 20:41:43 +00:00
Bob Wilson
24645a1a6d NEON does not support truncating vector stores. Radar 8598391. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 18:31:39 +00:00
Jim Grosbach
469ebbe148 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 18:11:14 +00:00
Jim Grosbach
6797f89815 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117931 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 17:08:58 +00:00
Jim Grosbach
833c93c795 Mark ARM subtarget features that are available for the assembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 16:59:54 +00:00
Jim Grosbach
d4462a5a4f trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117927 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 16:44:21 +00:00
Jim Grosbach
9729d2e998 The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the 
patterns as such

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117923 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 15:59:52 +00:00
Bill Wendling
69661191ce Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117906 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 06:00:39 +00:00
Chris Lattner
4d1189f385 reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117884 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 00:46:16 +00:00
Chris Lattner
150d20e8fc fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 19:22:57 +00:00
Chris Lattner
a4a3a5e3c2 two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 19:15:18 +00:00
Chris Lattner
39ee036f40 reapply r117858 with apparent editor malfunction fixed (somehow I 
got a dulicated line).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 19:10:56 +00:00
Chris Lattner
8b2f0822f3 revert r117858 while I check out a failure I missed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 19:05:32 +00:00
Chris Lattner
efa53760fe the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 18:48:12 +00:00
Eric Christopher
76d61478df Make sure we have a legal type (and simple) before continuing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117848 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 21:25:26 +00:00
Jim Grosbach
7644971232 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 14:54:23 +00:00
Jim Grosbach
4aaf59d8ed Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 12:59:16 +00:00
Chris Lattner
dba34d874d simplify this code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117771 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 04:35:59 +00:00
Chris Lattner
e5658fa15e split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 04:09:10 +00:00
Jim Grosbach
4b5236c966 Avoid re-evaluating MI.getNumOperands() every iteration of the loop. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117766 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 01:40:16 +00:00
Bob Wilson
f74a429816 Overhaul memory barriers in the ARM backend. Radar 8601999. 
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 00:54:37 +00:00
Jim Grosbach
6b5252db2d Encode the register list operands for ARM mode LDM/STM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-30 00:37:59 +00:00
Bill Wendling
52925b60f1 Some instructions end with an "ls" prefix, but it doesn't indicate that they are 
conditional. Check for those instructions explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 23:50:21 +00:00
Jim Grosbach
f38bfd1918 Remove hard tab characters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117742 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 23:23:15 +00:00
Jim Grosbach
c4bc2111a7 80 column fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 23:21:57 +00:00
Jim Grosbach
d8a11c25fa trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 23:21:03 +00:00
Jim Grosbach
0d2d2e9246 s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand 
encoder functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 23:19:55 +00:00
Evan Cheng
e09206d4d7 Fix fpscr <-> GPR latency info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117737 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 23:16:55 +00:00
Jim Grosbach
3df518e67e add FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117718 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 21:56:51 +00:00
Jim Grosbach
8e0a3eb957 Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in 
the ARMExpandPseudos pass rather than during the asm lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117714 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 21:35:25 +00:00
Eric Christopher
0e6233bfd7 Handle comparison values we already have - this fixes the consumer-typeset 
failure for llvm-gcc on arm fast isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 21:08:19 +00:00
Jim Grosbach
a3c1629ff5 ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to 
handle it in the asm lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 20:37:06 +00:00
Jim Grosbach
e317b13a2d Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117703 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 20:21:49 +00:00
Jim Grosbach
f32ecc69e5 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 20:21:36 +00:00
Jim Grosbach
86875a2463 ARM mode LDREX*/STREX* binary encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117695 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 19:58:57 +00:00
Jim Grosbach
27e900888e Encoding information for ARM conditional move instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117687 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 19:28:17 +00:00
Evan Cheng
089751535d Avoiding overly aggressive latency scheduling. If the two nodes share an 
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.

BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB

=>

BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB

This fixed the recent 256.bzip2 regression.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 18:09:28 +00:00
Evan Cheng
d7e473c629 - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency. 
- Compute CopyToReg use operand latency correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117674 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 18:07:31 +00:00
Jim Grosbach
80eb233a3c Handle ARM addrmode5 instructions with an offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117672 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 17:41:25 +00:00
John Thompson
44ab89eb37 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 17:29:13 +00:00
Jim Grosbach
d8d716fad3 Revert 117660. Apparently it's not as trivial as that... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117663 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 16:50:53 +00:00
Jim Grosbach
da54c6dd4f ARM addrmode5 instructions have neither writeback nor post-indexed modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 16:38:59 +00:00
Jim Grosbach
16c7425cff Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117651 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 14:46:02 +00:00
Benjamin Kramer
61a4d56a03 ARMAsmParser: Plug a memory leak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 09:43:39 +00:00
Eric Christopher
c223e2b10b Add an unreachable to silence warning - the switch is actually 
fully enumerated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117647 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 09:26:59 +00:00
Chris Lattner
14b93851cc add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 00:27:31 +00:00
Chris Lattner
e73d4f8ec7 give better error diagnostics, for example: 
t.s:1:14: error: invalid operand for instruction
vldr.64	d17, [r0]   
       	     ^

instead of:

t.s:1:1: error: unrecognized instruction
vldr.64	d17, [r0]   
^



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117611 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 21:41:58 +00:00
Chris Lattner
6274ec48b3 hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes 
the opcode string in the inst dump, e.g.:
	vmov	r2, r3, d17             @ encoding: [0x31,0x2b,0x53,0xec]
                                        @ <MCInst #989 VMOVRRD
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Reg:19>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

The "VMOVRRD" is new.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117609 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 21:37:33 +00:00
Chris Lattner
fa42fad8bf move a method out of line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117605 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 21:28:01 +00:00
Chris Lattner
550276ee5b remove the rest of hte owningptr's, no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 20:52:15 +00:00
Jim Grosbach
ab682a2090 PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 18:34:10 +00:00
Chris Lattner
c0ddfaa134 rearrange ParseRegisterList. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 17:23:41 +00:00
Chris Lattner
3a69756e39 refactor some code to simplify it, eliminating some owningptr's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117559 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 17:20:03 +00:00
Evan Cheng
7e2fe9150f Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 06:47:08 +00:00
Evan Cheng
9e08ee5d16 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 02:00:25 +00:00
Evan Cheng
0104d9de04 - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 01:49:06 +00:00
Owen Anderson
cfd0e1f3ae Add correct NEON encodings for vtbl and vtbx. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 00:18:46 +00:00
Owen Anderson
3eff4af42d Add correct NEON encodings for vext, vtrn, vuzp, and vzip. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:56:39 +00:00
Bob Wilson
1fa9d301a8 Fix compiler warnings about signed/unsigned comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:49:00 +00:00
Evan Cheng
f40deed62f Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:41:30 +00:00
Jim Grosbach
7e3383c007 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:12:14 +00:00
Owen Anderson
498ec20703 Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 22:49:00 +00:00
Jim Grosbach
6b15639e26 Trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 21:39:08 +00:00
Owen Anderson
d2fbdb7f5c Provide correct encodings for the get_lane and set_lane variants of vmov. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 21:28:09 +00:00
Jim Grosbach
ccf72caa92 JIT imm12 encoding for constant pool entry references. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 20:39:40 +00:00
Bob Wilson
f20700ca77 SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 20:38:28 +00:00
Jim Grosbach
f31430f6ec ARM JIT fix for LDRi12 and company. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 19:55:59 +00:00
Owen Anderson
f587a9352a Provide correct NEON encodings for vdup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 19:25:54 +00:00
Jim Grosbach
093177d5cd The new LDR* instruction patterns should handle the necessary encoding of 
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 17:52:51 +00:00
Owen Anderson
0745c389d9 Add correct NEON encodings for vsli and vsri. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 17:40:08 +00:00
Owen Anderson
dd31ed67e6 Add correct NEON encodings for vsra and vrsra. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 17:29:29 +00:00
Jim Grosbach
063efbf569 The immediate operands of an LDRi12 instruction doesn't need the addrmode2 
encoding tricks. Handle the 'imm doesn't fit in the insn' case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 16:50:31 +00:00
Jim Grosbach
77aee8e22c LDRi12 machine instructions handle negative offset operands normally (simple 
integer values), not with the addrmode2 encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 01:19:41 +00:00
Jim Grosbach
f85dd04bfa One more spot where the new arm mode LDR instruction representation 
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 00:38:16 +00:00
Jim Grosbach
c1d30212e9 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 00:19:44 +00:00
Jim Grosbach
28e3fe961f Since I parameterized this bit, I should probably actually use said parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117418 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 23:58:04 +00:00
Owen Anderson
86ed2324a6 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 22:50:46 +00:00
Jim Grosbach
3e55612472 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 22:37:02 +00:00
Owen Anderson
632c235a31 Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 21:58:41 +00:00
Owen Anderson
ac92262b61 Simplify classes for shift instructions, which are never commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117398 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 21:13:59 +00:00
Owen Anderson
3557d00a38 Provide correct NEON encodings for vshl, register and immediate forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 20:56:57 +00:00
Jim Grosbach
0eb7d06ab1 Grammar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117388 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 19:34:41 +00:00
Jim Grosbach
c3baf62800 Nuke extraneous comment. It's applicable elsewhere, but not in this func. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117387 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 19:22:23 +00:00
Owen Anderson
bc4118bd36 Add correct NEON encoding for vpadal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117380 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 18:18:03 +00:00
Owen Anderson
a88ea03bf2 Add NEON encodings for vmov and vmvn of immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 17:40:54 +00:00
Evan Cheng
c8141dfc7f Use instruction itinerary to determine what instructions are 'cheap'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 02:08:50 +00:00
Evan Cheng
0e9996ca94 NEON vmov's are in Neon domain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 02:03:05 +00:00
Bob Wilson
b3a6817d06 Tidy up redundant check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117331 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 00:02:19 +00:00
Rafael Espindola
3336384239 Produce the headers directly in the Finish method. This allows us to use 
the existing streamer methods that are endian safe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 22:26:55 +00:00
Owen Anderson
5258b61966 Add correct encodings for NEON vabal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117315 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 21:29:04 +00:00
Owen Anderson
410aebc670 Add correct NEON encodings for vaba. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 20:52:57 +00:00
Owen Anderson
31e6ed890a Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117294 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 20:17:22 +00:00
Owen Anderson
4110b4325d Provide correct NEON encodings for vbsl. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117293 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 20:13:13 +00:00
Jim Grosbach
458f2dc5d1 imm12 operands aren't Thumb2 only, so rename the printer helper function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 20:00:01 +00:00
Owen Anderson
162875a9f3 Add correct instruction encodings for vbic, vorn, and vmvn. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 18:43:52 +00:00
Rafael Espindola
4921e2356e Add a virtual destructor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 18:38:32 +00:00
Owen Anderson
8c71eff594 Provide correct NEON encodings for vand, veor, and vorr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 18:28:30 +00:00
Owen Anderson
d0c5b6170f Add NEON encoding tests for vcgt and vacgt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 18:03:59 +00:00
Rafael Espindola
cecbc3d282 Add support for emitting ARM file attributes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117275 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 17:50:35 +00:00
Owen Anderson
10c15e5d58 Add tests for NEON encodings of vcge and vacge. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 17:49:32 +00:00
Owen Anderson
4fe20bbd66 Add a warning about our inability to test the encoding of vceq with immediate zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117273 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 17:33:02 +00:00
Eric Christopher
a4633f5d74 Move rejection of NEON parameters earlier in fast isel call processing, 
note that we can actually handle some f64 arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117209 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 09:37:17 +00:00
Chandler Carruth
19e57025d4 Move the remaining attribute macros to systematic names based on the attribute 
name and prefixed with 'LLVM_'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117203 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 08:40:19 +00:00
Chandler Carruth
100c267249 Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names 
until other LLVM projects using these are cleaned up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117200 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 08:10:43 +00:00
Evan Cheng
5c2d428f43 Enable ARM fastcc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 02:19:37 +00:00
Evan Cheng
dd9dd6f857 Latency between CPSR def and branch is zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 02:04:38 +00:00
Jim Grosbach
a9a968d1ef Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117188 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 23:48:29 +00:00
Gabor Greif
41f31ef28e fix memory-layout assumption which only holds on little-endian systems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 23:16:11 +00:00
Jim Grosbach
f8da5f5dfa ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 22:12:16 +00:00
Evan Cheng
b179b46cc5 Transfer implicit ops when forming load multiple and return instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 21:29:58 +00:00
Owen Anderson
9b26497273 Add correct NEON encodings for vqdmlal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117134 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 19:35:48 +00:00
Jim Grosbach
385e136dce Add the encoding information for the rest of the ARM mode multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 19:15:30 +00:00
Owen Anderson
92205842ca Provide correct encodings for NEON vmlal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117131 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 19:05:25 +00:00
Evan Cheng
1f8b40d51c Silence compiler warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117128 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 18:57:05 +00:00
Owen Anderson
18341e9e31 Provide correct NEON encodings for vmla. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117126 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 18:54:37 +00:00
Jim Grosbach
3870b750e6 More ARM multiply instuction binary encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 18:35:16 +00:00
Evan Cheng
76f920d316 Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 18:23:05 +00:00
Jim Grosbach
929a7056d8 Parameterize a bit of ARM encoding information, simplifying some instruction 
definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 17:42:06 +00:00
Jim Grosbach
9463d0e400 More ARM multiply instruction encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 17:16:17 +00:00
Wesley Peck
eecb858ca8 Making the e_machine configurable by the target backend in ELFObjectWriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117099 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 15:52:49 +00:00
Eric Christopher
4f512efee9 Add some basic ret instruction support to arm fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117085 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 01:28:00 +00:00
Jim Grosbach
f50af8b5b8 ARM binary encoding for some of the multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117080 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 22:52:30 +00:00
Jim Grosbach
3686046a2c ARM binary encodings for MVN variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 22:19:32 +00:00
Jim Grosbach
3fea19105d ARM Binary encoding information for BFC/BFI instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 22:03:21 +00:00
Eric Christopher
1778772d1b These don't need to be virtual. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117068 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 21:47:51 +00:00
Owen Anderson
90d4cf9314 Move the encoding logic for Q registers into getMachineOpValue(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117060 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 20:49:13 +00:00
Owen Anderson
d451f888b8 ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower 
half of the Q register), rather than with just regno.  This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117056 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 20:21:49 +00:00
Eric Christopher
5b924809e4 Handle storing args to the stack for calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117055 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 20:09:54 +00:00
Eric Christopher
212ae937bb More load/store refactoring, call reg+offset simplification from within 
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117051 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 19:40:30 +00:00
Jim Grosbach
3ab5658a12 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117050 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 19:38:40 +00:00
Owen Anderson
1e93466c3a Add correct NEON encodings for vhadd and vrhadd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 18:55:04 +00:00
Owen Anderson
9d50559bae Add correct encodings for NEON vaddw.s* and vaddw.u*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117040 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 18:20:25 +00:00
Owen Anderson
e0e6dc3f4e Provide correct NEON encodings for vaddl.u* and vaddl.s*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 18:09:17 +00:00
Duncan Sands
dbbd99faf1 The return value of this call is not used, so no point 
in assigning it to a variable (gcc-4.6 warning).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 16:06:28 +00:00
Andrew Trick
5b7a825ec5 putback r116983 and fix simple-fp-encoding.ll tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 03:40:16 +00:00
Owen Anderson
d9707e3d85 Revert r116983, which is breaking all the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 03:11:16 +00:00
Evan Cheng
d6865de2d2 Add missing scheduling itineraries for transfers between core registers and VFP registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 01:12:00 +00:00
Owen Anderson
d7795540d0 Implement correct encodings for NEON vadd, both integer and floating point. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116981 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 00:48:00 +00:00
Eric Christopher
2d8f6fe610 Custom lower f64 args passed in integer registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116977 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 00:01:47 +00:00
Bill Wendling
01aabdac44 Add encoding for moving a value between two ARM core registers and a doublework 
extension register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116970 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 23:37:40 +00:00
Bill Wendling
7d31a169af Add encodings for movement between ARM core registers and single-precision 
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 22:44:54 +00:00
Dale Johannesen
e4d31593c5 Fix crash introduced in 116852. 8573915. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 22:03:37 +00:00
Chandler Carruth
1cd9708f5c Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three 
#includes in the process.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116919 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 08:27:02 +00:00