Commit Graph

1359 Commits

Author SHA1 Message Date
Chris Lattner
42b6418cc0 Remove some overridden functions in XCoreTargetAsmInfo that are
implemented exactly the same way as its ELFTargetAsmInfo subclass 
has them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76653 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21 21:26:32 +00:00
Eli Friedman
b3e7171926 Remove shift amount flavor. It isn't actually complete enough to
be useful, and it's currently unused.  (Some issues: it isn't actually 
rich enough to capture the semantics on many architectures, and
semantics can vary depending on the type being shifted.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76633 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21 20:12:16 +00:00
Chris Lattner
90f8b7073d Rename LessPrivateGlobalPrefix -> LinkerPrivateGlobalPrefix to match the
LLVM IR concept.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76590 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21 17:30:51 +00:00
David Greene
76081c4ef7 Re-apply 75490, 75806 and 76177 with fixes and tests. Efficiency comes
next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76486 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 22:02:59 +00:00
Eli Friedman
2f70f1a1d8 Remove FIXME that was already fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76457 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 19:45:16 +00:00
Daniel Dunbar
a3af370dc1 Add MCAsmParser interface.
- This provides the AsmParser interface to the target specific assembly
   parsers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76453 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 18:55:04 +00:00
Chris Lattner
1902fd9605 remove TargetAsmInfo::ExpandInlineAsm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76445 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 17:59:32 +00:00
Chris Lattner
b810565152 Copy ExpandInlineAsm to TargetLowering from TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76441 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 17:51:36 +00:00
Chris Lattner
ff3d3adddb add some fixme's and cleanups. TargetAsmInfo shouldn't depend on VMCore eventually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76439 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 17:47:48 +00:00
Chris Lattner
8f4e22ff9a remove dead forward decl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76433 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 17:23:00 +00:00
Chris Lattner
83757c7fb5 rename TargetAsmInfo::getASDirective -> getDataASDirective
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76431 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 17:12:46 +00:00
Bruno Cardoso Lopes
0a38dc5fda For PC relative relocations where symbols are defined in the same section they
are referenced, ignore the relocation entry and patch the relocatable field with
the computed symbol offset directly


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76414 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20 08:52:02 +00:00
Bruno Cardoso Lopes
e2b0ecd8be Use R_X86_64_32S to handle Jump Table Index relocation entries. Hide TAI usage inside getSection* functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76347 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-18 23:24:01 +00:00
Daniel Dunbar
edcb540496 Add some missing includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-18 23:22:46 +00:00
Bruno Cardoso Lopes
617dd7baa6 Use a better name for the label relocations while emitting them for Jump Tables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76334 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-18 20:52:11 +00:00
Bruno Cardoso Lopes
171375f73a Add support to properly reference private symbols on relocation entries.
Use proper relocation type to build relocations for JumpTables (rodata
sections).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76326 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-18 19:30:09 +00:00
Evan Cheng
5248468473 Enable cross register class coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76281 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-18 02:10:10 +00:00
Evan Cheng
3837b64f41 Revert 76177 for now. It's messing up ARM asm printing. Also this significant debate about its efficiency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76279 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-18 01:43:53 +00:00
Daniel Dunbar
cbdf0e2455 Add llvm::InitializeAllTargetInfos and llvm::InitializeAllAsmParsers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76253 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17 22:35:35 +00:00
Chris Lattner
e2cf37b88c Untangle a snarl that I discovered when updating the mangler,
starting in getCurrentFunctionEHName.  Among other problems,
we would try to privative a "foo.eh" label, but end up emitting
the label as _Lfoo.eh instead of L_foo.eh on darwin.  This is really
bad, and the linker has always tolerated these labels existing.
For now, just emit them as _foo.eh.

This patch also fixes problems with ".eh" labels on unnamed
functions and eliminates two strangely defined TargetAsmInfo
hooks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76231 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17 20:46:40 +00:00
Daniel Dunbar
092a9dda2d Sketch support for target specific assembly parser.
- Not fully enabled yet, need a configure regeneration.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76230 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17 20:42:00 +00:00
David Greene
ab9238e876 Add logic to align instruction operands to columns for pretty-printing.
No target uses this currently.  This patch only adds the mechanism so
that local installations can choose to enable this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76177 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17 14:24:46 +00:00
Evan Cheng
378445303b Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 09:20:10 +00:00
Daniel Dunbar
ff9834ab9d Kill off last uses of TargetMachineRegistry class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75892 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 02:41:19 +00:00
Daniel Dunbar
c981da0192 Fix gcc 4.0 build failure, can't rely on access inside nested friended class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75891 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 02:38:28 +00:00
Daniel Dunbar
603bea3274 Add registered target list to --version output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75889 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 02:06:09 +00:00
Daniel Dunbar
4ce78ee3be Add explicit comment that clients can call target initialization functions
multiple times.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75880 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 01:13:00 +00:00
Daniel Dunbar
5d77cad60b Lift addAssemblyEmitter into LLVMTargetMachine.
- No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75859 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 23:34:19 +00:00
Daniel Dunbar
cfe9a605ee Lift DumpAsm / -print-emitted-asm functionality into LLVMTargetMachine.
- No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75848 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 22:33:19 +00:00
Daniel Dunbar
51b198af83 Reapply TargetRegistry refactoring commits.
--- Reverse-merging r75799 into '.':
 U   test/Analysis/PointerTracking
U    include/llvm/Target/TargetMachineRegistry.h
U    include/llvm/Target/TargetMachine.h
U    include/llvm/Target/TargetRegistry.h
U    include/llvm/Target/TargetSelect.h
U    tools/lto/LTOCodeGenerator.cpp
U    tools/lto/LTOModule.cpp
U    tools/llc/llc.cpp
U    lib/Target/PowerPC/PPCTargetMachine.h
U    lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U    lib/Target/PowerPC/PPCTargetMachine.cpp
U    lib/Target/PowerPC/PPC.h
U    lib/Target/ARM/ARMTargetMachine.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/ARMTargetMachine.h
U    lib/Target/ARM/ARM.h
U    lib/Target/XCore/XCoreTargetMachine.cpp
U    lib/Target/XCore/XCoreTargetMachine.h
U    lib/Target/PIC16/PIC16TargetMachine.cpp
U    lib/Target/PIC16/PIC16TargetMachine.h
U    lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U    lib/Target/Alpha/AlphaTargetMachine.cpp
U    lib/Target/Alpha/AlphaTargetMachine.h
U    lib/Target/X86/X86TargetMachine.h
U    lib/Target/X86/X86.h
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U    lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U    lib/Target/X86/X86TargetMachine.cpp
U    lib/Target/MSP430/MSP430TargetMachine.cpp
U    lib/Target/MSP430/MSP430TargetMachine.h
U    lib/Target/CppBackend/CPPTargetMachine.h
U    lib/Target/CppBackend/CPPBackend.cpp
U    lib/Target/CBackend/CTargetMachine.h
U    lib/Target/CBackend/CBackend.cpp
U    lib/Target/TargetMachine.cpp
U    lib/Target/IA64/IA64TargetMachine.cpp
U    lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U    lib/Target/IA64/IA64TargetMachine.h
U    lib/Target/IA64/IA64.h
U    lib/Target/MSIL/MSILWriter.cpp
U    lib/Target/CellSPU/SPUTargetMachine.h
U    lib/Target/CellSPU/SPU.h
U    lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U    lib/Target/CellSPU/SPUTargetMachine.cpp
U    lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U    lib/Target/Mips/MipsTargetMachine.cpp
U    lib/Target/Mips/MipsTargetMachine.h
U    lib/Target/Mips/Mips.h
U    lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U    lib/Target/Sparc/SparcTargetMachine.cpp
U    lib/Target/Sparc/SparcTargetMachine.h
U    lib/ExecutionEngine/JIT/TargetSelect.cpp
U    lib/Support/TargetRegistry.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75820 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 20:24:03 +00:00
Stuart Hastings
2286f8dc4c Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to repair broken LLVM-GCC build.
Will revert 75770 in the llvm-gcc trunk.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75799 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 17:27:11 +00:00
Duncan Sands
8cb6626df1 Remove StringConstantPrefix now that the only user
(llvm-gcc) has gone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75781 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 12:39:48 +00:00
Daniel Dunbar
6c05796294 Kill off old (TargetMachine level, not Target level) match quality functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75780 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 12:26:05 +00:00
Daniel Dunbar
03f4bc5d6c Provide TargetMachine implementations with reference to Target they were created
from.
 - This commit is almost entirely propogating the reference through the
   TargetMachine subclasses' constructor calls.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75778 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 12:11:05 +00:00
Daniel Dunbar
6501145ec6 Kill off unused TargetMachineRegistry methods and ivars.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75774 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 11:48:36 +00:00
Daniel Dunbar
54785e6df0 Migrate llc and the JIT to using the TargetRegistry for lookups.
- They still use the TargetMachineRegistry to populate the contents of the
   -march option (via the listener interface). We can't just populate it in the
   option parser because we can't expect the TargetRegistry to be populated yet
   (we no longer rely on static constructors).

 - There are a couple ways to finish killing off TargetMachineRegistry, but I
   haven't figured out the cleanest one yet...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75773 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 11:36:15 +00:00
Daniel Dunbar
4d1be777f8 Include the Target& in the TargetMachineRegisterEntry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75772 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 11:23:49 +00:00
Daniel Dunbar
3fb7eee9c2 Allow multiple registrations of the same target.
- This doesn't necessarily seem like a good idea, but the JIT unittest
   currently relies on it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75769 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 10:32:44 +00:00
Daniel Dunbar
aca81c49d9 Initialize the target info via the InitializeNativeTarget() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75768 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 10:29:55 +00:00
Daniel Dunbar
e0bda7df1a Reimplement TargetMachineRegistry in terms of TargetRegistry.
- This is a temporary hack to aid in incremental refactoring, for now we
   allocate a new TargetMachineRegistryEntry on every getClosest... call.

 - No intended functionality change, other than the leaked memory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75766 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 09:53:37 +00:00
Daniel Dunbar
4883630360 Mark Target's creation routines as const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75763 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 09:38:10 +00:00
Daniel Dunbar
4246790aa8 Register Target's TargetMachine and AsmPrinter in the new registry.
- This abuses TargetMachineRegistry's constructor for now, this will get
   cleaned up in time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75762 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 09:22:31 +00:00
Daniel Dunbar
7a46d7898e Fix thinko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75760 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 08:56:49 +00:00
Daniel Dunbar
6461716b50 Include Target specific Info initialization routine when initializing all
targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 07:48:39 +00:00
Daniel Dunbar
73b3ec4134 Address some review comments on TargetRegistry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75753 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 07:09:29 +00:00
Daniel Dunbar
bb06129140 Add new TargetRegistry.
Targets implement a single global Target structure which will live in a new
<Target>/TargetInfo library; this will be present in any image which the target
is usable in.
 - Optional target specific classes can then be registered and attached to the
   Target description.

 - Registration for normal Targets will be done via the initialization functions
   instead of using static constructors.

 - This allows clients to use a single interface to obtain target data, without
   requiring the code generator be linked in. It also provides a natural
   extension point for adding new optional target data (assembler parser,
   disassembler, etc.).

 - This also provides a new entry point for obtaining a target for a particular
   triple (without a module).

 - Not yet used, however this should eventually replace the TargetMachineRegistry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75739 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15 04:24:58 +00:00
David Greene
71847813bc Have asm printers use formatted_raw_ostream directly to avoid a
dynamic_cast<>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75670 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-14 20:18:05 +00:00
Torok Edwin
c23197a26f llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-14 16:55:14 +00:00
Dan Gohman
2e4da5e4ab Delete a spurious const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75493 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-13 20:46:11 +00:00
David Greene
014700c1a8 Add infrastructure to allow post instruction printing action triggers.
We'll eventually use this to print comments in asm files and do other
fun things.

This adds interfaces to the AsmPrinter and changes TableGen to invoke
the postInstructionAction when appropriate.  It also add parameters to
TargetAsmInfo to control comment layout.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75490 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-13 20:25:48 +00:00
Jakob Stoklund Olesen
ee787ff01a Add CCIfSRet calling convention predicate.
The blackfin calling convention uses a different register for sret arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75417 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-12 13:15:50 +00:00
Torok Edwin
c25e7581b9 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-11 20:10:48 +00:00
Evan Cheng
261ce1d5f8 Remove TargetInstrInfo::CommuteChangesDestination and added findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75264 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 19:15:51 +00:00
Evan Cheng
bfa5cf144a 80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75226 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 05:20:19 +00:00
Evan Cheng
910139f9ca Targets sometimes assign fixed stack object to spill certain callee-saved
registers based on dynamic conditions. For example, X86 EBP/RBP, when used as
frame register has to be spilled in the first fixed object. It should inform
PEI this so it doesn't get allocated another stack object. Also, it should not
be spilled as other callee-saved registers but rather its spilling and restoring
are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75116 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09 06:53:48 +00:00
Bruno Cardoso Lopes
ac57e6e498 Add the Object Code Emitter class. Original patch by Aaron Gray, I did some
cleanup, removed some #includes and moved Object Code Emitter out-of-line.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74813 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-06 05:09:34 +00:00
Duncan Sands
98749f851d In this unreachable code, return an initialized value.
This stops gcc warning about possible uses of an uninitialized
value when compiling with assertions turned off.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74775 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 16:00:23 +00:00
Tilmann Scheller
ffd0200abf Implement the SVR4 ABI for PowerPC.
Implement LowerFORMAL_ARGUMENTS_SVR4().
Implement LowerCALL_SVR4().
Add support for split arguments.
Implement by value parameter passing for aggregates.
Add support for variable argument lists.
Create the spill area for argument registers of variable argument functions no longer at a fixed offset.
Make sure callee saved registers are spilled to the correct stack offsets.
Change allocation order of non-volatile floating-point registers.
Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls.
Add support for variable argument calls with Vector arguments.
Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers.
Stop creating illegal i8 values in LowerVASTART().
Add memory access width hints.
Make sure to reserve space on the stack for the frame pointer.
When using the SVR4 ABI, reserve r13 for the Small Data Area pointer.
Assure that the frame pointer is spilled to the correct location on the stack.
Some FP registers were not marked as volatile.
Make sure the i64 words from a long double are passed either both in registers or both on the stack.
Only put integer arguments in registers which are not marked with the inreg flag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 06:45:56 +00:00
Tilmann Scheller
6b61cd185e Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put 
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.

The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74764 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 06:44:53 +00:00
Bruno Cardoso Lopes
3d62a412fb Remove getFunctionAlignment from TargetELFInfo and use new MachineFunction alignment method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74686 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 02:13:13 +00:00
Bill Wendling
b4202b84d7 Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 18:50:55 +00:00
Bill Wendling
20c568f366 Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.

This allows for future work that would allow for precise no-op placement and the
like.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 22:38:32 +00:00
David Greene
02a6218774 Increase limit for OpActions array
The OpActions array had a limit of 32 value types, so change it to use
MVT::MAX_ALLOWED_VALUETYPE in its declaration and change the accesses to
this array to work with a VT.getSimpleVT() that is larger than 32.

Also, add a comment to the place where MVT::MAX_ALLOWED_VALUETYPE is
defined indicating that it must be a multiple of 32.

This is part of the work allow MVT::LAST_VALUETYPE be greater than 32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74130 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 22:22:02 +00:00
David Greene
f2e19d5dcf This increases the maximum for MVT::LAST_VALUETYPE
This change doubles the allowable value for MVT::LAST_VALUETYPE. It does
this by doing several things.

1. Introduces MVT::MAX_ALLOWED_LAST_VALUETYPE which in this change has a
value of 64.  This value contains the current maximum for the
MVT::LAST_VALUETYPE.

2. Instead of checking "MVT::LAST_VALUETYPE <= 32", all of those uses
now become "MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_LAST_VALUETYPE"

3. Changes the dimension of the ValueTypeActions from 2 elements to four
elements and adds comments ahead of the declaration indicating the it is
"(MVT::MAX_ALLOWED_LAST_VALUETYPE/32) * 2".  This at least lets us find
what is affected if and when MVT::MAX_ALLOWED_LAST_VALUETYPE gets
changed.

4. Adds initializers for the new elements of ValueTypeActions.

This does NOT add any types in MVT. That would be done separately.

This doubles the size of ValueTypeActions from 64 bits to 128 bits and
gives us the freedom to add more types for AVX.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74110 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-24 19:41:55 +00:00
Bob Wilson
a96751fc8f Provide InitializeAllTargets and InitializeNativeTarget functions in the
C bindings.  Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74026 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 23:59:40 +00:00
Douglas Gregor
bcba7f95c2 Work around build problem with OpenJDK, which defines X86 as a
macro. Fixes PR 4427. Patch by Xerxes Rånby!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 17:21:35 +00:00
Bruno Cardoso Lopes
0d3193ef3c Add more methods to gather target specific elf stuff
Support for .text relocations, implementing TargetELFWriter overloaded methods for x86/x86_64.
Use a map to track global values to their symbol table indexes
Code cleanup and small fixes



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22 19:16:16 +00:00
Chris Lattner
c12430644a implement support for lowering subregs when preparing to print
LEA64_32r, eliminating a bunch of modifier logic stuff on addr modes.

Implement support for printing mbb labels as operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73817 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20 07:03:18 +00:00
Devang Patel
1e86a66b00 mv CodeGen/DebugLoc.h Support/DebugLoc.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73786 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 22:08:58 +00:00
Chris Lattner
4e0f25b603 merge the common darwin settings from the X86/PPC/ARM targets
into DarwinTargetAsmInfo.cpp.  The remaining differences should
be evaluated.  It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 00:08:39 +00:00
Chris Lattner
a93ca92379 move mangler quote handling from asm printers to TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73738 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:41:35 +00:00
Chris Lattner
b839c3f577 simplify macro debug info directive handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73736 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 23:31:37 +00:00
Evan Cheng
f9f1da17f8 - Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18 02:04:01 +00:00
Chris Lattner
5f1a5c7f57 Add a utility header that makes it easy to link in the right set
of targets for various purposes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 16:42:01 +00:00
Anton Korobeynikov
0d492bdf4d Address more comments :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73430 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 22:08:48 +00:00
Anton Korobeynikov
52edfc7a6d Document ABIType enum. Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73427 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 21:46:02 +00:00
Evan Cheng
358dec5180 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
Evan Cheng
90f95f88c6 Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 20:22:55 +00:00
Bruno Cardoso Lopes
ae9163f0e2 Introduce new BinaryObject (blob) class, ELF Writer modified to use it. BinaryObject.h by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73333 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 07:53:21 +00:00
Bruno Cardoso Lopes
d00d4159d4 Use forward declarations and move TargetELFWriterInfo impl to a new file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73209 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-11 22:13:00 +00:00
Bruno Cardoso Lopes
c997d45ae5 Support for ELF Visibility
Emission for globals, using the correct data sections
Function alignment can be computed for each target using TargetELFWriterInfo
Some small fixes



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73201 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-11 19:16:03 +00:00
David Greene
f5aefbdb79 Change IndexedModeAction representation.
This changes the IndexedModeAction representation to remove the
limitation on the number of value types in MVT.  This limitation
prevents us from specifying AVX types.

Prior to this change IndexedModActions was represented as follows...

uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];

the first dimension was used to represent loads, then stores.  This
imposed a limitation of 32 on the number of value types that could be
handled with this method.  The value type was used to shift the two bits
into and out of the approprate bits in the uint64_t.

With this change the array is now represented as ...

uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];

Takes more space but removes the limitation on MVT::LAST_VALUETYPE.  The
first dimension is now the value_type for the reference.  The second
dimension is the load [0] vs. store[1].  The third dimension represents
the various modes for load store.  Accesses are now direct, no shifting
or masking.

There are other limitations that need to be removed, so that
MVT::LAST_VALUETYPE can be greater than 32.  This is merely the first
step towards that goal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73104 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-09 00:19:10 +00:00
David Greene
63ec51d86b Oops, didn't mean to commit 73102 yet. Revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73103 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 23:54:42 +00:00
David Greene
9df4eb8cfe Change IndexedModeAction representation.
This changes the IndexedModeAction representation to remove the
limitation on the number of value types in MVT.  This limitation
prevents us from specifying AVX types.

Prior to this change IndexedModActions was represented as follows...

uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];

the first dimension was used to represent loads, then stores.  This
imposed a limitation of 32 on the number of value types that could be
handled with this method.  The value type was used to shift the two bits
into and out of the approprate bits in the uint64_t.

With this change the array is now represented as ...

uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];

Takes more space but removes the limitation on MVT::LAST_VALUETYPE.  The
first dimension is now the value_type for the reference.  The second
dimension is the load [0] vs. store[1].  The third dimension represents
the various modes for load store.  Accesses are now direct, no shifting
or masking.

There are other limitations that need to be removed, so that
MVT::LAST_VALUETYPE can be greater than 32.  This is merely the first
step towards that goal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73102 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 23:53:19 +00:00
Anton Korobeynikov
0eebf653a7 The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 22:53:56 +00:00
David Greene
e1b469170b Make IntInits and ListInits typed. This helps deduce types of !if and
other operators.  For the rare cases where a list type cannot be
deduced, provide a []<type> syntax, where <type> is the list element
type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73078 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 20:23:18 +00:00
Bruno Cardoso Lopes
f5b0c5a1c7 Remove elf specific info from ELFWriter.h to Elf.h. Code cleanup and more comments added
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72982 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 03:56:29 +00:00
Devang Patel
578efa920a Add new function attribute - noimplicitfloat
Update code generator to use this attribute and remove NoImplicitFloat target option.
Update llc to set this attribute when -no-implicit-float command line option is used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72959 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 21:57:13 +00:00
Nate Begeman
abc0199680 Adapt the x86 build_vector dagcombine to the current state of the legalizer.
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 21:37:30 +00:00
Devang Patel
d18e31ae17 Add new function attribute - noredzone.
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:05:33 +00:00
Dale Johannesen
874ae251c3 Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 03:12:52 +00:00
Dale Johannesen
4150d83abe Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 23:27:20 +00:00
Bruno Cardoso Lopes
a3f99f9033 First patch in the direction of splitting MachineCodeEmitter in two subclasses:
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30 20:51:52 +00:00
Bill Wendling
4d4eab219a Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72603 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30 00:58:37 +00:00
Evan Cheng
abdbc57abb Default isNarrowingProfitable to false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72561 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-29 05:31:40 +00:00
Evan Cheng
8b944d39b3 Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
e.g.
orl     $65536, 8(%rax)
=>
orb     $1, 10(%rax)

Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 00:35:15 +00:00
Anton Korobeynikov
41a024385f Propagate CPU string out of SubtargetFeatures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:50:50 +00:00
Evan Cheng
6ebf7bc740 Run code placement optimization for targets that want it (arm and x86 for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:42:09 +00:00
Dan Gohman
f46ef0450f Clarify a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71561 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-12 17:08:34 +00:00
Jay Foad
8d730fbde5 Don't #include DerivedTypes.h from TargetData.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11 19:38:09 +00:00
Dan Gohman
20b7ca1eb9 Add a comment about the special meaning of VoidTy in this context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71466 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11 19:11:53 +00:00
Jay Foad
7524b59062 Change TargetData::getIntPtrType() to return an IntegerType instead of
just a Type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71426 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11 11:13:47 +00:00
Duncan Sands
777d2306b3 Rename PaddedSize to AllocSize, in the hope that this
will make it more obvious what it represents, and stop
it being confused with the StoreSize.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71349 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-09 07:06:46 +00:00
Duncan Sands
2a6e0a2140 Add some examples to show the difference between
the various notions of type size used in LLVM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71230 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-08 17:49:48 +00:00
Evan Cheng
d923fc621f Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70950 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-05 00:30:09 +00:00
Evan Cheng
c781a243a3 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70787 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-03 18:32:42 +00:00
Jakob Stoklund Olesen
ba67d87fe4 getCommonSubClass() - Calculate the largest common sub-class of two register
classes.

This is implemented as a function rather than a method on TargetRegisterClass
because it is symmetric in its arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70512 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30 21:23:32 +00:00
Bill Wendling
581b93415e Remove unused flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70459 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30 00:57:51 +00:00
Bill Wendling
b8cb0bb08c Remove LTO optimization level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70445 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 23:40:42 +00:00
Bill Wendling
98a366d547 Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 23:29:43 +00:00
Sanjiv Gupta
b27fa0afe2 Add directive to declare external globals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 08:23:18 +00:00
Nate Begeman
5a5ca1519e Implement review feedback for vector shuffle work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 05:20:52 +00:00
Bill Wendling
be8cc2a3de Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 00:15:41 +00:00
Bill Wendling
a24d1b1558 Correct comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70340 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-29 00:09:22 +00:00
Evan Cheng
8a8a0dfc3b Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70309 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 18:29:27 +00:00
Jakob Stoklund Olesen
fa4677b483 Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a TargetRegisterClass method.
Also make the method non-asserting. It will return NULL when given an invalid subreg index.

The method is needed by an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70296 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 16:34:09 +00:00
Bill Wendling
c69d56f115 r70270 isn't ready yet. Back this out. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 01:04:53 +00:00
Bill Wendling
2e9d5f912a Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28 00:21:31 +00:00
Nate Begeman
9008ca6b6b 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
PR2957

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27 18:41:29 +00:00
Rafael Espindola
15684b2955 Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 12:40:33 +00:00
Nate Begeman
b706d29f9c PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 03:42:54 +00:00
Dan Gohman
276944ef30 Delete an unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69375 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 20:03:31 +00:00
Bob Wilson
1f595bb429 Use CallConvLower.h and TableGen descriptions of the calling conventions
for ARM.  Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 19:07:39 +00:00
Dan Gohman
7beace5d06 Fix doxygen comment syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69128 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 01:44:07 +00:00
Dan Gohman
88c7af096b Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 21:06:25 +00:00
Devang Patel
0f7fef3872 Reapply 68847.
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68964 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 17:02:03 +00:00
Dan Gohman
f8c7394781 Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:38:05 +00:00
Dan Gohman
73099b1058 Add comments to INSERT_SUBREG, EXTRACT_SURBEG, SUBREG_TO_REG,
and IMPLICIT_DEF.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68949 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:12:29 +00:00
Owen Anderson
ddeed50d76 Use a hashtable for TargetRegisterClass::contains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68922 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12 22:31:17 +00:00
Chris Lattner
0461c0a8f5 Add new TargetInstrDesc::hasImplicitUseOfPhysReg and
hasImplicitDefOfPhysReg methods.  Use them to remove a 
look in X86 fast isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68886 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12 07:26:51 +00:00
Dan Gohman
c6fa3ff0bd Revert r68847. It breaks the build on non-Darwin targets, with this message
from the assembler:

Error: unknown pseudo-op: `.debug_inlined'


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68863 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-11 15:57:04 +00:00
Devang Patel
2057532679 Keep track of inlined functions and their locations. This information is collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.)
Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-11 00:16:47 +00:00
Owen Anderson
3ca15c989c Give register alias checking the hash table treatment too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68730 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 22:19:30 +00:00
Bob Wilson
d9df501704 Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 17:16:43 +00:00
Owen Anderson
7d770be047 Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68669 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09 03:50:16 +00:00
Dan Gohman
97121ba2af Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.

This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.

Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.

Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.

Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.

Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 00:15:30 +00:00
Jim Grosbach
30eae3c022 PR2985 / <rdar://problem/6584986>
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07 20:34:09 +00:00
Chris Lattner
41c90738e9 "This adds a getName() method to TargetRegisterClass, just like in TargetRegisterInfo.
This makes debugging register classes a bit easier."

Patch by Jakob Stoklund Olesen!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68400 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-03 20:25:41 +00:00
Dan Gohman
8f9643f0f7 Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.
Note that these are distinct from TargetInstrInfo::INSERT_SUBREG
and TargetInstrInfo::EXTRACT_SUBREG, which are used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68355 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-03 00:25:26 +00:00
Anton Korobeynikov
fca82deecb Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68032 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30 15:27:43 +00:00
Anton Korobeynikov
71a7c6cde0 Add data.rel stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68031 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30 15:27:03 +00:00
Anton Korobeynikov
db2323148b Honour relocation behaviour stuff for ro objects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68005 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-29 17:13:49 +00:00
Arnold Schwaighofer
e75fd69f15 Enable tail call optimization for functions that return a struct (bug 3664) and for functions that return types that need extending (e.g i1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67934 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28 08:33:27 +00:00
Evan Cheng
0b0cd9113a Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
x * 40
=>
shlq    $3, %rdi
leaq    (%rdi,%rdi,4), %rax

This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq    (%rdi,%rdi,2), %rax
leaq    (%rsi,%rax,8), %rax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67917 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28 05:57:29 +00:00
Evan Cheng
42bf74be14 CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-25 01:47:28 +00:00
Mon P Wang
bc65ca8de5 Added option to enable generating less precise mad (multiply addition)
for those architectures that support the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20 05:06:58 +00:00
Bill Wendling
f9abd7e33e Add a -no-implicit-float flag. This acts like -soft-float, but may generate
floating point instructions that are explicitly specified by the user.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66719 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11 22:30:01 +00:00
Dan Gohman
0f8b53f19d Fix a bunch of Doxygen syntax issues. Escape special characters,
and put @file directives on their own comment line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-03 02:55:14 +00:00
Rafael Espindola
9a58023c6c Refactor TLS code and add some tests. The tests and expected results are:
pic |  declaration | linkage  | visibility |

!pic |  declaration | external | default    | tls1.ll     tls2.ll     | local exec
 pic |  declaration | external | default    | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default    | tls3.ll     tls4.ll     | initial exec
 pic | !declaration | external | default    | tls3-pic.ll tls4-pic.ll | general dynamic

!pic |  declaration | external | hidden     | tls7.ll     tls8.ll     | local exec
 pic |  declaration | external | hidden     | X                       | local dynamic
!pic | !declaration | external | hidden     | tls9.ll     tls10.ll    | local exec
 pic | !declaration | external | hidden     | X                       | local dynamic

!pic |  declaration | internal | default    | tls5.ll     tls6.ll     | local exec
 pic |  declaration | internal | default    | X                       | local dynamic

The ones marked with an X have not been implemented since local dynamic is not implemented.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65632 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-27 13:37:18 +00:00
Mon P Wang
0d52ff1f7b Added support to have TableGen provide information if an intrinsic (core
or target) can be overloaded or not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-24 23:17:49 +00:00
Dale Johannesen
c1c9d7e6a9 Describe tail merging's use of InsertBranch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65062 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-19 19:40:21 +00:00
Nate Begeman
d6b7a242d3 Add support to the JIT for true non-lazy operation. When a call to a function
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT.  The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd.  A new interface for allocating and
updating empty stubs is provided.

Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.

Add support under a new ExecutionEngine flag for emitting the infomration 
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue.  This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64906 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 08:31:02 +00:00
Dan Gohman
865f006bb4 Eliminate several more unnecessary intptr_t casts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64888 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 05:09:16 +00:00
Evan Cheng
dc54d317e7 Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09 07:14:22 +00:00
Dan Gohman
1fdbc1dd4e Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-07 16:15:20 +00:00
Evan Cheng
37059d52b7 We don't really need the abort here. This unbreak x86_64 linux build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63940 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:51:34 +00:00
Evan Cheng
770bcc7b15 Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:43:24 +00:00
Evan Cheng
4350eb86a7 Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63936 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:17:30 +00:00
Evan Cheng
b3a021cdb3 Change -1 => negative number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63935 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:12:56 +00:00
Evan Cheng
6f8d762e6b Document the meaning of -1 for getCopyCost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63933 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:01:33 +00:00
Evan Cheng
758d20f653 Clarify comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63851 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05 08:41:53 +00:00
Dale Johannesen
49de98214b Reapply 63765. Patches for clang and llvm-gcc to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05 01:49:45 +00:00
Dale Johannesen
4d452de150 Reverting 63765. This broke the build of both clang
and llvm-gcc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63786 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04 22:47:25 +00:00
Nate Begeman
d24479730a New feature: add support for target intrinsics being defined in the
target directories themselves.  This also means that VMCore no longer
needs to know about every target's list of intrinsics.  Future work
will include converting the PowerPC target to this interface as an
example implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04 19:47:21 +00:00
Chris Lattner
e20e790074 add a friend needed by a stringmap change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63706 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04 01:51:53 +00:00
Dale Johannesen
0f502f6f44 Add some DL propagation to places that didn't
have it yet.  More coming.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63673 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-03 22:26:09 +00:00
Dale Johannesen
ff97d4fe81 Propagation in TargetLowering. Includes passing a DL
into SimplifySetCC which gets called elsewhere.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63583 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-03 00:47:48 +00:00
Sanjiv Gupta
3b020feb57 Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-02 16:53:06 +00:00
Dale Johannesen
f8a0a763d5 Fix build on case-sensitive filesystems (i.e. everybody else)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63448 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-30 23:20:42 +00:00
Dale Johannesen
7d2ad624fa Make LowerCallTo and LowerArguments take a DebugLoc
argument.  Adjust all callers and overloaded versions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-30 23:10:59 +00:00
Sanjiv Gupta
c8d7bc850d Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63377 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-30 04:25:10 +00:00
Dan Gohman
e5af2d3a22 Make x86's BT instruction matching more thorough, and add some
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63266 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-29 01:59:02 +00:00
Dan Gohman
f560ffae1f Make isOperationLegal do what its name suggests, and introduce a
new isOperationLegalOrCustom, which does what isOperationLegal
previously did.

Update a bunch of callers to use isOperationLegalOrCustom
instead of isOperationLegal. In some case it wasn't obvious
which behavior is desired; when in doubt I changed then to
isOperationLegalOrCustom as that preserves their previous
behavior.

This is for the second half of PR3376.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63212 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-28 17:46:25 +00:00
Scott Michel
210de72cd7 Make the Dwarf macro information section optional; CellSPU's assembler
doesn't support it. The default is set to 'true', so this should not
impact any other target backends.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63058 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-26 22:32:51 +00:00
Dan Gohman
92f4f16a19 Implement Red Zone utilization on x86-64. This is currently
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63056 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-26 22:22:31 +00:00
Evan Cheng
8c08d8c77c Cross register class coalescing. Not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62832 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-23 02:15:19 +00:00
Evan Cheng
536ab130ec Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-22 09:10:11 +00:00
Duncan Sands
9fbc7e2e7a Cleanup whitespace and comments, and tweak some
prototypes, in operand type legalization.  No
functionality change.


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2009-01-21 09:00:29 +00:00
Sanjiv Gupta
bb326bbe88 Allow targets to legalize operations (with illegal operands) that produces multiple values. For example, a load with an illegal operand (a load produces two values, a value and chain).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62663 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-21 04:48:39 +00:00
Evan Cheng
04ee5a1d92 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-20 19:12:24 +00:00
Mikhail Glushenkov
2388a588bd Registry.h should not depend on CommandLine.h.
Split Support/Registry.h into two files so that we have less to
recompile every time CommandLine.h is changed.

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2009-01-16 07:02:28 +00:00
Mikhail Glushenkov
5c1799b293 Delete trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62307 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-16 06:53:46 +00:00
Dan Gohman
c13cf130c4 Make getWidenVectorType const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62265 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15 17:34:08 +00:00
Dan Gohman
73e0914848 Const-qualify getPreIndexedAddressParts and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62259 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15 16:29:45 +00:00
Devang Patel
83489bb770 Use DebugInfo interface to lower dbg_* intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62127 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-13 00:35:13 +00:00
Duncan Sands
ceb4d1aecb Rename getABITypeSize to getTypePaddedSize, as
suggested by Chris.


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2009-01-12 20:38:59 +00:00
Chris Lattner
6688d75114 fit in 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61977 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-09 04:58:01 +00:00
Bill Wendling
d60de51878 Revert r61415 and r61484. Duncan was correct that these weren't needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 22:53:45 +00:00
Duncan Sands
676b9dfe2f Add a note about passing MVT::Other to getSetCCResultType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 21:33:06 +00:00
Dan Gohman
50b84f44e4 Add <climits>, to get the definition of CHAR_BIT. This should fix
build errors.


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2009-01-05 19:47:30 +00:00
Dan Gohman
11df7e5157 TargetLowering.h #includes SelectionDAGNodes.h, so it doesn't need its
own OpActionsCapacity magic number; it can just use ISD::BUILTIN_OP_END,
as long as it takes care to round up when needed.


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2009-01-05 19:40:39 +00:00
Dan Gohman
d68a07650c Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05 17:59:02 +00:00
Duncan Sands
5480c0469e Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType.  In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).


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2009-01-01 15:52:00 +00:00
Bill Wendling
998dee96d3 Linux wants the FDE initial location and address range to be forced to 32-bit.
Darwin doesn't. Make this optional for platforms.


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2008-12-29 22:12:11 +00:00
Bill Wendling
722f5f1cfb Darwin likes for the EH frame to be non-local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61420 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-24 08:05:17 +00:00
Bill Wendling
d4121bef3c GCC doesn't emit DW_EH_PE_sdata4 for the FDE encoding on Darwin. I'm not sure
about other platforms.


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2008-12-24 05:25:49 +00:00
Dan Gohman
0b1d4a798d Clean up the atomic opcodes in SelectionDAG.
This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.

This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.


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2008-12-23 21:37:04 +00:00
Dan Gohman
b5544940c1 Clarify a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61338 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-22 19:44:39 +00:00
Rafael Espindola
2f6fea90a5 Fix bug 3202.
The EH_frame and .eh symbols are now private, except for darwin9 and earlier.
The patch also fixes the definition of PrivateGlobalPrefix on pcc linux.



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2008-12-19 10:55:56 +00:00
Mon P Wang
87c8a8f304 Added support for vector widening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61209 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-18 20:03:17 +00:00