Dan Gohman
14152b480d
Reapply r107655 with fixes; insert the pseudo instruction into
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the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 20:24:04 +00:00
Rafael Espindola
a5e82a5748
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
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if profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 16:24:34 +00:00
Dan Gohman
258c58cc62
Revert r107655.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 15:49:48 +00:00
Dan Gohman
b81c771c0d
Fix a bunch of custom-inserter functions to handle the case where
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the pseudo instruction is not at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 15:18:19 +00:00
Evan Cheng
ed2ae136d2
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:40:23 +00:00
Evan Cheng
dca653951c
Remove early IT block formation. It's not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 21:07:09 +00:00
Bob Wilson
e45f72c833
Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so
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that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 17:23:44 +00:00
Bob Wilson
b5b5057a70
ARM function alignments were off by a power of two. svn 83242 changed
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getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer. The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 22:26:26 +00:00
Bob Wilson
21773e716f
Add support for encoding VDUP (ARM core register) instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 20:13:29 +00:00
Bob Wilson
d5a563de07
Add support for encoding NEON VMOV (from core register to scalar) instructions.
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The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:34:07 +00:00
Jim Grosbach
077f1bfa91
skip dbg_value instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 16:55:24 +00:00
Bob Wilson
1ab38469df
The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add
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a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 16:25:11 +00:00
Rafael Espindola
d31f972bd3
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
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of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 14:02:34 +00:00
Duncan Sands
31a3a3ebaf
Remove pointless variable LastDef.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 13:23:22 +00:00
Duncan Sands
58c86910b3
Remove unused variable Loc and pointless variables unified_syntax
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and thumb_mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107133 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 13:04:35 +00:00
Duncan Sands
978189e090
Remove an unused and a pointless variable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107131 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 13:00:29 +00:00
Duncan Sands
90c64f4aac
Remove initialized but otherwise unused variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107127 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 11:22:26 +00:00
Evan Cheng
c36b5b9730
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 05:38:36 +00:00
Evan Cheng
c170f66742
Change if-cvt options to something that actually as useable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 05:37:59 +00:00
Jakob Stoklund Olesen
628a79771b
When no memoperands are present, assume unaligned, volatile.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 01:13:07 +00:00
Bob Wilson
5cdede43e9
Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
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the same as ARM except that the condition code field is always set to ARMCC::AL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107107 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 00:26:13 +00:00
Bob Wilson
62d24a4b92
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
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of the Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107086 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 22:23:17 +00:00
Jim Grosbach
e89c5e57cc
tidy up style. no functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 21:29:17 +00:00
Bob Wilson
08baddbc07
Refactor encoding function for NEON 1-register with modified immediate format.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107070 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 21:16:30 +00:00
Bob Wilson
d896a97dc7
Support Thumb mode encoding of NEON instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 21:12:19 +00:00
Jim Grosbach
e9e3f20ffb
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106988 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28 04:27:01 +00:00
Eli Friedman
a2c6f457a4
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 04:36:50 +00:00
Bob Wilson
52e4a0a074
Add support for encoding NEON VMOV (from scalar to core register) instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 04:07:15 +00:00
Evan Cheng
f6799394d5
It's now possible to run code placement pass for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 01:52:05 +00:00
Bob Wilson
80d9bc0336
Renumber NEON instruction formats to be consecutive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 00:05:09 +00:00
Bob Wilson
184723d9be
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
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"N..." instead of "NEON..." for consistency with the other NEON format names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:56:05 +00:00
Bob Wilson
2653263165
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
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Renumber MiscFrm to 25.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:45:37 +00:00
Daniel Dunbar
e39e06af38
Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
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introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106908 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:14:54 +00:00
Evan Cheng
13151432ed
Change if-conversion block size limit checks to add some flexibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:42:03 +00:00
Bob Wilson
5e7b607f72
Add support for encoding 3-register NEON instructions, and fix
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emitNEON2RegInstruction's handling of 2-address operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:40:46 +00:00
Dale Johannesen
1784d160e4
The hasMemory argument is irrelevant to how the argument
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for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:55:36 +00:00
Bob Wilson
583a2a0615
Add support for encoding 2-register NEON instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:17:19 +00:00
Bob Wilson
8c605c601d
Fix indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 20:54:44 +00:00
Jim Grosbach
57bb394803
IT instructions are considered to be scheduling hazards, but are scheduled
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with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.
Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106871 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 18:43:14 +00:00
Bob Wilson
ade57fa619
Add missing ARM and Thumb data layout info for vector types.
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Radar 8128745.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 04:41:08 +00:00
Bob Wilson
86fe66db3a
Reduce indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 04:12:31 +00:00
Evan Cheng
8acf67672b
Oops. IT block formation pass needs to be run at any optimization level.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106775 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 19:10:14 +00:00
Eli Friedman
761fa7af9e
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 18:20:04 +00:00
Bob Wilson
789fef987f
PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
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form so they can be narrowed to 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 16:50:20 +00:00
Bill Wendling
4b722108e2
We are missing opportunites to use ldm. Take code like this:
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void t(int *cp0, int *cp1, int *dp, int fmd) {
int c0, c1, d0, d1, d2, d3;
c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
/* ... */
}
It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 23:00:16 +00:00
Dale Johannesen
e39fdbe118
Do not do tail calls to external symbols. If the
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branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this. 8120438.
If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 18:52:34 +00:00
Jim Grosbach
5def57aaf4
When using libcall expansions for the atomic intrinsics, the explicit
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MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106631 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 16:08:49 +00:00
Bob Wilson
a3a204664d
Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
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Radar 8031193.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:04:24 +00:00
Dan Gohman
fe60104ac9
Use pre-increment instead of post-increment when the result is not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 15:08:57 +00:00
Evan Cheng
4d54e5b2dd
Tail merging pass shall not break up IT blocks. rdar://8115404
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 01:18:16 +00:00
Bob Wilson
56a1a69a35
sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.
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Radar 8104310.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:27:34 +00:00
Jim Grosbach
a967d1121a
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
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being moved around away from the jump table it references. rdar://8104340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:27:27 +00:00
Evan Cheng
d95ea2da28
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 21:21:14 +00:00
Dale Johannesen
b0ccb757b3
Fix PR 7433. Silly typo in non-Darwin ARM tail call
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handling, plus correct R9 handling in that mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:21:49 +00:00
Jim Grosbach
9cfcfeb24b
early exit for dbg_value instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106430 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 17:49:23 +00:00
Evan Cheng
859df5e9f9
Fix a crash caused by dereference of MBB.end(). rdar://8110842
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-20 00:54:38 +00:00
Bob Wilson
31ef8e6663
Remove a fixme comment that is no longer relevant.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106382 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 05:32:41 +00:00
Bob Wilson
dc076da4d2
Fix error message to match function name.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 05:32:09 +00:00
Evan Cheng
02ba9e19c7
Ignore dbg_value's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 02:36:21 +00:00
Evan Cheng
0110ac66eb
Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:01:32 +00:00
Evan Cheng
6523d2ff7f
Indentation and remove dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:11:54 +00:00
Dan Gohman
9559e3b99a
Silence compiler warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:02:06 +00:00
Evan Cheng
96c3da6436
Move ARM if-conversion before post-ra scheduling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:32:07 +00:00
Evan Cheng
3ee608c5aa
Update cmake list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:12:10 +00:00
Evan Cheng
886459456c
Thumb2 hazard recognizer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:11:35 +00:00
Evan Cheng
86050dc8cc
Allow ARM if-converter to be run after post allocation scheduling.
...
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:09:54 +00:00
Jim Grosbach
ef6eb9c7ab
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:03:10 +00:00
Jim Grosbach
68741be5e6
Enable Expand handling of atomics for subtargets that can't do them inline.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 22:35:32 +00:00
Bob Wilson
ebe99b2c19
Rewrite chained if's as switches and replace assertions with llvm_unreachable
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(as suggested in radar 8104405).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106318 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 21:32:42 +00:00
Dale Johannesen
51bd47edbc
Fix ARM/Thumb reversal in previous attempt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106314 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 21:07:47 +00:00
Jakob Stoklund Olesen
52c61ec164
When using ADDri to get the address of a stack object, 255 is a conservative
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limit on the offset that can be materialized without using the register
scavenger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 20:59:25 +00:00
Dale Johannesen
10416803c1
An attempt to fix the problem Anton reported with
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ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 20:44:28 +00:00
Dale Johannesen
c66cdf74a9
Enable tail calls on ARM by default, with some
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basic tests.
This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
B.W <label in other function>
which it has not seen before, at least from llvm-based
compilers. I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 19:00:18 +00:00
Dan Gohman
a606d955de
Start TargetRegisterClass indices at 0 instead of 1, so that
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MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 18:13:55 +00:00
Dale Johannesen
df50d7e238
Last round of changes for ARM tail calls.
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Not turning them on yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 18:13:11 +00:00
Jakob Stoklund Olesen
0d8ba3303b
Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
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does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 16:49:33 +00:00
Dan Gohman
e368b460a2
Eliminate unnecessary uses of getZExtValue().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 14:22:04 +00:00
Stuart Hastings
3bf9125933
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
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addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 22:43:56 +00:00
Jim Grosbach
7072cf62a5
Thumb1 and any pre-v6 ARM target should use the libcall expansion of
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ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 02:02:03 +00:00
Jim Grosbach
c73993b678
simplify code a bit and add a more explanatory assert for cases that
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previously would result in 'cannot yet select' errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 01:37:00 +00:00
Jim Grosbach
7616b646f1
format and 80-column cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 23:45:49 +00:00
Jakob Stoklund Olesen
a2846b4bee
Don't attempt preserving conservative kill flags. We were doing it wrong.
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This is before LiveVariables anyway, where these kill flags are recalculated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106157 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 22:11:08 +00:00
Bob Wilson
07f6e805b1
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
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now, so there's no need to disable them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 21:34:01 +00:00
Evan Cheng
46df4eb46e
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 07:35:02 +00:00
Dale Johannesen
38d5f0441c
Add file missing from previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 22:24:08 +00:00
Dale Johannesen
6470a116f1
Next round of tail call changes. Register used in a tail
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call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 22:08:33 +00:00
Bob Wilson
827b2106fe
Add basic support for NEON modified immediates besides VMOV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 19:05:35 +00:00
Daniel Dunbar
f4a7bf4ec3
Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 14:50:42 +00:00
Bob Wilson
14f1d4e74b
VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 05:51:27 +00:00
Jim Grosbach
400c95fe38
Make sure to skip dbg_value instructions when finding an insertion point for
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the combined load/store instruction. rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 00:41:09 +00:00
Bob Wilson
d3c4284849
Rename functions referring to VMOV immediates to refer to NEON "modified
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immediate" operands. These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 22:19:57 +00:00
Bob Wilson
1114f568bc
Add a missing bitcast. This code used to only handle conversions between
...
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type. Radar 8084742.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 22:45:25 +00:00
Bob Wilson
1a913ed178
Add instruction encoding for the Neon VMOV immediate instruction. This changes
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the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 21:34:50 +00:00
Evan Cheng
aa4b5429ef
Delete code that's not safe.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-10 02:08:20 +00:00
Jim Grosbach
db03adb346
be slightly more subtle about skipping dbg_value instructions; otherwise, if a
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dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 22:21:24 +00:00
Evan Cheng
68fc2daf8f
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 19:26:01 +00:00
Evan Cheng
34aa423814
Typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 03:49:12 +00:00
Evan Cheng
d847124211
Thumb2 IT blocks are fairly expensive. When there are multiple selects using
...
the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.
Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105669 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 01:46:50 +00:00
Jim Grosbach
6335ac67b6
fix copy/paste/modify think-o
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:53:32 +00:00
Bruno Cardoso Lopes
99405df044
Reapply r105521, this time appending "LLU" to 64 bit
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immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:51:23 +00:00
Jim Grosbach
b84adb3b80
fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 20:06:55 +00:00
Bob Wilson
dd726e5bce
Fix up a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105591 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 00:42:08 +00:00
Bob Wilson
53dd2454d5
Further changes for Neon vector shuffles:
...
- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07 23:53:38 +00:00
Jim Grosbach
8077e76f93
Handle dbg_value instructions (i.e., skip them) when generating IT blocks.
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rdar://7797940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07 21:48:47 +00:00
Chris Lattner
1087f54ddb
revert r105521, which is breaking the buildbots with stuff like this:
...
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
3eca98bb3a
Initial AVX support for some instructions. No patterns matched
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yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 03:53:24 +00:00
Dale Johannesen
cf296fa162
Improvements to tail call code. No functional effect
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unless using -arm-tail-calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 00:51:39 +00:00
Dale Johannesen
8fa8e7fe95
More thoroughly disable tails calls by default.
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8060143, although this doesn't fix the real problem with tail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105472 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 18:04:24 +00:00
Jim Grosbach
8af44b687b
Another fix to prevent debug info from affecting codegen. rdar://7797940
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105470 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 17:57:34 +00:00
Jim Grosbach
958e4e1967
more dbg_value adjustments so debug info doesn't affect codegen
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 01:23:30 +00:00
Jim Grosbach
d089a7ac70
fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105441 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 00:15:00 +00:00
Bob Wilson
40cbe7d5d4
For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
...
VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized. That is pretty awful, but I guess it
makes sense for other targets. Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105439 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 00:04:02 +00:00
Jim Grosbach
3de755bb40
Teach the ARM load-store optimizer to deal with dbg_value instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 22:41:15 +00:00
Dale Johannesen
51e28e6348
Early implementation of tail call for ARM.
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A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 21:09:53 +00:00
Jakob Stoklund Olesen
9edf7deb37
Slightly change the meaning of the reMaterialize target hook when the original
...
instruction defines subregisters.
Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.
Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:
%reg1234:foo = FLAP %reg1234<imp-def>
will reMaterialize(%reg3333, bar) like this:
%reg3333:bar-foo = FLAP %reg333:bar<imp-def>
Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 22:47:25 +00:00
Jim Grosbach
18f30e6f5e
Clean up 80 column violations. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 21:53:11 +00:00
Rafael Espindola
42d075c4fb
Remove the TargetRegisterClass member from CalleeSavedInfo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 20:02:30 +00:00
Bob Wilson
91a74da036
Rename canCombinedSubRegIndex method to something more grammatically correct
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and tidy up the comment describing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 18:54:47 +00:00
Rafael Espindola
20fae65181
Replace ARM's getCalleeSavedRegClasses with a simpler solution
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 17:54:50 +00:00
Anton Korobeynikov
4ed81ecbcd
Some A9 load/store cleanups
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 19:25:39 +00:00
Anton Korobeynikov
8207fce96f
Some rough approximations for load/stores on A9
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 19:25:34 +00:00
Anton Korobeynikov
1098ef5fa4
NEON/VFP stuff can be issued only via Pipe1 on A9
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105107 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 19:25:29 +00:00
Anton Korobeynikov
1845a387e1
Add some integer instruction itineraries for A9
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105106 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 19:25:17 +00:00
Evan Cheng
c10f5434b4
Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 23:25:23 +00:00
Jim Grosbach
bc213209bf
correct retattr
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 18:03:48 +00:00
Jim Grosbach
c9792a3c1f
Cosmetic cleanup. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 17:51:20 +00:00
Jim Grosbach
5caeff5c01
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 17:37:40 +00:00
Bob Wilson
13ef840807
Add the cc_out operand for t2RSBrs instructions. I missed this when I changed
...
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 00:27:15 +00:00
Jim Grosbach
0798eddd07
Update the saved stack pointer in the sjlj function context following either
...
an alloca() or an llvm.stackrestore(). rdar://8031573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:49:24 +00:00
Evan Cheng
12616727c7
Use report_fatal_error, not llvm_unreachable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:45:31 +00:00
Jim Grosbach
a65850230a
back out 104862/104869. Can reuse stacksave after all. Very cool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:11:57 +00:00
Evan Cheng
84f60b7359
llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 22:08:38 +00:00
Bob Wilson
d984eb6073
Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases
...
should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 20:23:42 +00:00
Jim Grosbach
ad9aaf038e
add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH
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to update the jmpbuf in the presence of VLAs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 18:23:48 +00:00
Jakob Stoklund Olesen
c8b9f6ce23
Give SubRegIndex names to all ARM subregisters. This will be required by
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TableGen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 22:15:03 +00:00
Jim Grosbach
23ff7cff52
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
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ISD::. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:22:18 +00:00
Jakob Stoklund Olesen
ca561ffcf3
Replace the SubRegSet tablegen class with a less error-prone mechanism.
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A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:27:12 +00:00
Shih-wei Liao
9f3b6a381a
Coding style change (Adding 1 missing space.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104670 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 04:46:50 +00:00
Shih-wei Liao
45469f38b6
Adding the missing implementation for ARM::SBFX and ARM::UBFX.
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Fixing http://llvm.org/bugs/show_bug.cgi?id=7225 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 03:21:39 +00:00
Jim Grosbach
54e13eceff
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:22:21 +00:00
Jakob Stoklund Olesen
b555609e73
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
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This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
6a45d681e5
Replace the SubRegSet tablegen class with a less error-prone mechanism.
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A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:28:19 +00:00
Shih-wei Liao
6d37a29588
Adding the missing implementation of Bitfield's "clear" and "insert".
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Fixing http://llvm.org/bugs/show_bug.cgi?id=7222 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:25:05 +00:00
Shih-wei Liao
5170b71143
To handle s* registers in emitVFPLoadStoreMultipleInstruction().
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Fixing http://llvm.org/bugs/show_bug.cgi?id=7221 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:02:28 +00:00
Jakob Stoklund Olesen
4fda9670f0
Remove NumberHack entirely.
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SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:33 +00:00
Zonr Chang
f3c770a2cb
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 10:23:52 +00:00
Zonr Chang
f86399be0c
Add support to MOVimm32 using movt/movw for ARM JIT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 08:42:45 +00:00
Bob Wilson
a85df80ed7
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
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I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 04:51:47 +00:00
Bob Wilson
4876bdb69e
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
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Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 04:43:08 +00:00
Bob Wilson
ab3912e3ce
Clean up indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 03:36:52 +00:00
Jakob Stoklund Olesen
e00fa64c16
Use enums instead of literals in the ARM backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 00:15:15 +00:00
Jakob Stoklund Olesen
33276d95ef
Switch SubRegSet to using symbolic SubRegIndices
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 23:03:18 +00:00
Bob Wilson
c21763fd99
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
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version of t2MVN already allowed that, but not the register versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 22:41:19 +00:00
Jakob Stoklund Olesen
f27462eb29
Lose the dummies
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:47:01 +00:00
Jakob Stoklund Olesen
09bc029865
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
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structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:46:58 +00:00
Bob Wilson
d303846e16
Clean up some extra whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:08:34 +00:00
Bob Wilson
bb7ecb2bf5
Thumb2 RSBS instructions were being printed without the 'S' suffix.
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Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:44:06 +00:00
Evan Cheng
c7cf10c97e
LR is in GPR, not tGPR even in Thumb1 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:00:18 +00:00
Jakob Stoklund Olesen
7bb31e3187
Fix a few places that depended on the numeric value of subreg indices.
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Add assertions in places that depend on consecutive indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen
558661d271
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
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from ARMRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 16:54:32 +00:00
Bob Wilson
069e434868
VDUP doesn't support vectors with 64-bit elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 05:42:31 +00:00
Evan Cheng
2457f2c661
Implement @llvm.returnaddress. rdar://8015977.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:47:14 +00:00
Jim Grosbach
5eb1951539
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:06:18 +00:00
Bob Wilson
be751cfe9c
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
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copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:23:12 +00:00
Evan Cheng
f7d87ee158
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:43:17 +00:00
Evan Cheng
1cc3984148
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 23:26:43 +00:00
Bob Wilson
63b8845e78
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
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This fixes the remaining issue with pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 18:39:53 +00:00
Evan Cheng
211ffa1351
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:19:50 +00:00
Evan Cheng
9085f98b32
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 07:28:01 +00:00
Evan Cheng
27fa722311
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 07:26:50 +00:00
Evan Cheng
5fd1c9be2d
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 06:07:03 +00:00
Evan Cheng
3c3195cbf1
Target instruction selection should copy memoperands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 06:06:09 +00:00
Evan Cheng
ea420b20d4
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:52:25 +00:00
Evan Cheng
28dad2a5ca
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:31:17 +00:00
Jakob Stoklund Olesen
535af4a320
ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
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too large limit.
The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.
A test case is very difficult to produce because it will only fail when the
scavenger is used.
rdar://problem/7894847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:29:23 +00:00
Evan Cheng
47006be498
vmov of immediates are trivially re-materializable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:54:50 +00:00
Bob Wilson
7f43fd84db
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
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Obvious in retrospect but not fun to debug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:31:13 +00:00
Evan Cheng
6206124250
Turn on -neon-reg-sequence by default.
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Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 19:51:20 +00:00
Evan Cheng
9c207ac0dc
No reason not to run the NEON domain croassing fix up pass in thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 01:11:46 +00:00
Anton Korobeynikov
bd91ea53f8
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 09:15:36 +00:00
Anton Korobeynikov
4878b8415f
Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 08:54:20 +00:00
Evan Cheng
8f6de385d6
Model vst lane instructions with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 03:27:48 +00:00
Anton Korobeynikov
a9790d739a
Some cheap DAG combine goodness for multiplication with a particular constant.
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This can be extended later on to handle more "complex" constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 18:16:59 +00:00
Anton Korobeynikov
418d1d954d
"trap" pseudo-op turned out to be apple-local.
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Temporary emit it as raw bytes until it will be added to binutils as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 17:19:20 +00:00
Evan Cheng
7189fd03fa
Model 128-bit vld lane with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103868 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 07:53:37 +00:00
Evan Cheng
4782b1e2ca
v4i64 and v8i64 are only synthesizable when NEON is available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:20:21 +00:00
Evan Cheng
06b666c705
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
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allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:18:07 +00:00
Evan Cheng
7092c2bfcb
Model 64-bit lane vld with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 01:36:29 +00:00
Evan Cheng
b990a2f249
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
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instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
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%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 23:21:14 +00:00
Evan Cheng
12c24690c7
Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103833 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 22:54:52 +00:00
Bill Wendling
b92187a410
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
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the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:14:32 +00:00
Evan Cheng
5c6aba2e3a
Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 18:54:59 +00:00
Evan Cheng
22c687b642
Added a QQQQ register file to model 4-consecutive Q registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 02:13:41 +00:00
Evan Cheng
7f68719517
Fix comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 00:21:45 +00:00
Evan Cheng
c4ca40eb5e
Add comment about the pseudo registers QQ, each of which is a pair of Q registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 20:02:08 +00:00
Bob Wilson
1190c14b54
Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.
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Do not use those for Thumb1 functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 19:58:24 +00:00
Daniel Dunbar
1860e7dcfd
Fix -Asserts warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 03:19:36 +00:00
Evan Cheng
69b9f9883e
Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 01:12:06 +00:00
Evan Cheng
d929f77738
Expand VMOVQQ into a pair of VMOVQ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103684 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 00:17:02 +00:00
Evan Cheng
020cc1b4d0
Mark some pattern-less instructions as neverHasSideEffects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 00:16:46 +00:00
Evan Cheng
431300797b
Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 23:13:12 +00:00
Evan Cheng
a4d73d01c4
Remove a dead fixme.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 20:20:22 +00:00
Rafael Espindola
18c1021ec1
Add support for movi32 of global values to the new (MC) asm printer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 05:16:34 +00:00
Evan Cheng
5bdc2aa264
vst instructions are modeled as this:
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v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
= VSTxx <addr>, v1025, v1026
The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
= VSTxx <addr>, v1024:5, v1024:6
The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.
As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.
Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103540 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 01:42:50 +00:00
Evan Cheng
9647f3d981
Avoid breaking vstd when reg_sequence is not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 21:07:36 +00:00
Duncan Sands
16d8f8bd91
I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it
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to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 20:16:09 +00:00
Dan Gohman
ff7a562751
Implement a bunch more TargetSelectionDAGInfo infrastructure.
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Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 17:31:57 +00:00
Dan Gohman
419e4f9263
Remove the TargetLowering::getSubtarget() virtual function, which
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was unused. TargetMachine::getSubtarget() is used instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 16:21:03 +00:00
Evan Cheng
fb3611daad
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 07:26:32 +00:00
Evan Cheng
0ce537a9db
Model some vst3 and vst4 with reg_sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 01:19:40 +00:00
Evan Cheng
e9e2ba05de
Model some vld3 instructions with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 21:26:24 +00:00
Evan Cheng
603afbfe2a
Model vld2 / vst2 with reg_sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 17:34:18 +00:00
Jim Grosbach
4b77f6a85a
Clean up the conditional for handling of sign_extend_inreg based on
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whether the extract instructions are available.
rdar://7956878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 18:34:55 +00:00
Evan Cheng
435d499177
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 02:04:02 +00:00
Evan Cheng
07a6d9391c
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 01:54:08 +00:00
Evan Cheng
c10b5afbe8
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 00:24:52 +00:00
Dan Gohman
34dcc6fadc
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
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doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 19:06:44 +00:00
Bob Wilson
429009b0f1
Add a missing break statement to fix unintentional fall-through
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(replacing the previous patch for the same issue).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 16:05:26 +00:00
Jim Grosbach
d31f00b7f7
Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 15:32:49 +00:00
Shantonu Sen
eae216c6d3
Fix "warning: extra ';' inside a struct or union" when building llvm with clang
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 14:57:47 +00:00
Evan Cheng
b63387afc6
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 06:36:08 +00:00
Dan Gohman
1ef7c82128
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 05:08:57 +00:00
Eric Christopher
f865cb5c1f
Revert r103156 since it was breaking the build bots.
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Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 02:29:06 +00:00
Evan Cheng
9c35ee2099
Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:54:03 +00:00
Evan Cheng
4ffc22ae00
Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:52:03 +00:00
Evan Cheng
d31c5496d7
Cosmetic changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:34:11 +00:00
Evan Cheng
7f2f436267
storeRegToStackSlot has forgotten about QPR_8 register class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:32:54 +00:00
Jim Grosbach
29402132f3
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
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instructions to subtarget features and update tests to reflect.
PR5717.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 23:44:43 +00:00
Evan Cheng
676b2dfd27
Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 22:15:40 +00:00
Jim Grosbach
b1dc393bd5
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
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Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 20:44:35 +00:00
Evan Cheng
de8aa4ed9c
Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 18:28:36 +00:00
Evan Cheng
94cc6d3a2b
With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 20:39:49 +00:00
Evan Cheng
826bdfa603
Do not pre-allocate for registers which form a REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 20:38:12 +00:00
Jim Grosbach
6e62b4ef14
rdar://7937137 - dbg values not being handled in thumb1 version of
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eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 00:11:37 +00:00
Dan Gohman
af1d8ca44a
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
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changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:01:06 +00:00
Evan Cheng
8601a3d4de
Frame index can be negative.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29 01:13:30 +00:00
Jim Grosbach
d100755bab
Add sizes non-floating point versions for the eh sjlj intrinsic expansions.
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rdar://7895451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 20:33:09 +00:00
Bob Wilson
5dfa87ecc6
Handle register-to-register copies within the tGPR class.
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Radar 7896289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 23:20:08 +00:00
Dale Johannesen
3f282aa94b
Handle target-specific form of DBG_VALUE in AsmPrinter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 20:07:31 +00:00
Evan Cheng
62b50656ce
Add ARM specific emitFrameIndexDebugValue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 07:39:25 +00:00
Jim Grosbach
3a1287b470
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
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extraction. This fixes PR5998.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 23:24:18 +00:00
Johnny Chen
c048f1d12c
Modified some assert() msg strings; no other functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 18:37:48 +00:00
Evan Cheng
e566763b19
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
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optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 03:18:23 +00:00
Johnny Chen
52d2b0ed00
Thumb instructions which have reglist operands at the end and predicate operands
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before reglist were not properly handled with respect to IT Block. Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:01:19 +00:00
Johnny Chen
d6b5d72c0f
Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),
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instead of just asserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 21:29:28 +00:00
Johnny Chen
ef37e3abb7
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
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transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 17:28:50 +00:00
Johnny Chen
3974ade503
Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where
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d==15 is considered illegal. Return false instead of assert().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 01:01:57 +00:00
Johnny Chen
6bcf52f00a
More IT instruction error-handling improvements from fuzzing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101839 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 00:15:41 +00:00
Johnny Chen
d0f3c46d16
Better error handling of invalid IT mask '0000', instead of just asserting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 23:02:58 +00:00