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15216 Commits

Author SHA1 Message Date
Eli Friedman
761fa7af9e Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 18:20:04 +00:00
Bob Wilson
789fef987f PR7458: Try commuting Thumb2 instruction operands to put them into 2-address 
form so they can be narrowed to 16-bit instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 16:50:20 +00:00
Dan Gohman
4e39e9da0f Reapply r106634, now that the bug it exposed is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 14:30:44 +00:00
Chris Lattner
645b209c4a Teach the x86 mc assembler that %dr6 = %db6, this implements 
rdar://8013734


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106725 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 07:29:18 +00:00
Chris Lattner
adabe1a92c more cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106724 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 07:18:14 +00:00
Chris Lattner
02758a44e4 reduce indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106723 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 07:16:25 +00:00
Chris Lattner
f8cbde46fb fix breakage from r98938 by correctly marking msp430 calls as variadic. 
Patch by Ben Ransford!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106722 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 06:46:50 +00:00
Dan Gohman
6b13cbca61 Fix a bug in the code which determines when it's safe to use the 
bt instruction, which was exposed by r106263.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106718 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 02:07:59 +00:00
Eric Christopher
37106afe02 Add a couple more quick comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106717 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 02:07:57 +00:00
Devang Patel
e9916a302f Use ValueMap instead of DenseMap. 
The ValueMapper used by various cloning utility maps MDNodes also.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106706 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 00:33:28 +00:00
Bruno Cardoso Lopes
6539dc6e6c Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
34a491bd8e Move SSE and AVX shuffle, unpack and compare code to more appropriate places 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 00:15:50 +00:00
Bill Wendling
4b722108e2 We are missing opportunites to use ldm. Take code like this: 
void t(int *cp0, int *cp1, int *dp, int fmd) {
  int c0, c1, d0, d1, d2, d3;
  c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  /* ... */
}

It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 23:00:16 +00:00
Bruno Cardoso Lopes
e93e300ad0 Add AVX MOVMSK{PS,PD}rr instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
428256b818 Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106678 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 21:10:57 +00:00
Eric Christopher
749bb7e2d9 Update according to feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 20:49:35 +00:00
Bruno Cardoso Lopes
7dbfd07e32 Add AVX SHUF{PS,PD}{rr,rm} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106672 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 20:07:15 +00:00
Nico Weber
50b9efc2a8 Add support for the x86 instructions "pusha" and "popa". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 20:00:58 +00:00
Dale Johannesen
e39fdbe118 Do not do tail calls to external symbols. If the 
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this.  8120438.

If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106662 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 18:52:34 +00:00
Daniel Dunbar
cbe762b5d1 Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 17:09:26 +00:00
Jim Grosbach
f1ab49e83a The generic DAG combiner can now fold atomic fences when needed, so switch 
to using that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106633 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 16:25:07 +00:00
Jim Grosbach
5def57aaf4 When using libcall expansions for the atomic intrinsics, the explicit 
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106631 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 16:08:49 +00:00
Eric Christopher
18ebf74781 Update uses, defs, and comments for darwin tls patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106621 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 08:01:49 +00:00
Daniel Dunbar
d24c9d5f91 Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang. 
Conflicts:

	lib/CodeGen/MachineSink.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106614 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 00:48:25 +00:00
Bruno Cardoso Lopes
62a76c6401 Add AVX compare packed instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
0caca3967b Reapply support for AVX unpack and interleave instructions, with 
testcases this time.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106593 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
c3d57b179c Add AVX MOV{SS,SD}{rr,rm} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 22:38:56 +00:00
Bill Wendling
19d8597bca Fix the formatting of the switch statement and add a missing break. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106586 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 22:16:17 +00:00
Bob Wilson
a3a204664d Thumb1 functions using @llvm.returnaddress were not saving the incoming LR. 
Radar 8031193.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 22:04:24 +00:00
Jim Grosbach
dd11ee2273 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106574 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 20:52:02 +00:00
Bruno Cardoso Lopes
d3a067bbc2 Reorganize logical and arithmetic SSE 1 & 2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106557 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 18:17:40 +00:00
Bruno Cardoso Lopes
f23919b3e9 Reorganize SSE instructions, making easier to see oportunities for refactoring 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106556 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 18:09:32 +00:00
Dan Gohman
fe60104ac9 Use pre-increment instead of post-increment when the result is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 15:08:57 +00:00
Evan Cheng
4d54e5b2dd Tail merging pass shall not break up IT blocks. rdar://8115404 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 01:18:16 +00:00
Chris Lattner
ceea301c1d make sure to initialize indent_level 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 00:40:26 +00:00
Chris Lattner
3284877064 add some support for blockaddress. This isn't really enough to be useful, 
but it will cover uses of blockaddress that are actually in a function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106502 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 23:19:36 +00:00
Chris Lattner
1018c24c13 eliminate a mutable global variable, use raw_ostream::indent instead of 
rolling our own.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106501 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 23:14:47 +00:00
Chris Lattner
7e6d7451ae un-indent a huge amount of code out of an anonymous namespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106500 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 23:12:56 +00:00
Bruno Cardoso Lopes
c27d1e4d17 revert r106482 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106499 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 22:59:03 +00:00
Bruno Cardoso Lopes
b7cc3f6ae6 change parameter name to avoid confusion with global definition 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106486 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:28:07 +00:00
Bob Wilson
56a1a69a35 sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM. 
Radar 8104310.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106484 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:27:34 +00:00
Jim Grosbach
a967d1121a LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it 
being moved around away from the jump table it references. rdar://8104340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:27:27 +00:00
Bruno Cardoso Lopes
b44e8b2d11 Add unpack and interleave AVX instructions, encoding tests cooming soon 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106482 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:21:48 +00:00
Evan Cheng
d95ea2da28 Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:21:14 +00:00
Eric Christopher
be4e066ff9 Remove isTwoAddress from SystemZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106467 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:25:57 +00:00
Eric Christopher
c63a404d56 Remove isTwoAddress from Sparc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:22:35 +00:00
Eric Christopher
c452d79c43 Remove isTwoAddress from Mips. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106465 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:19:21 +00:00
Eric Christopher
b82a7ea1b2 Remove isTwoAddress from Blackfin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106457 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:13:37 +00:00
Eric Christopher
f704408bf7 Remove isTwoAddress from MSP430. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:07:30 +00:00
Eric Christopher
658ebcc7ec Make 80-column. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106448 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:56:55 +00:00
Eric Christopher
90301312d5 Remove isTwoAddress from PIC16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106447 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:55:01 +00:00
Eric Christopher
4a232f0836 Remove isTwoAddress from XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106446 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:51:38 +00:00
Eric Christopher
23265d0054 Remove isTwoAddress from Alpha. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106445 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:48:55 +00:00
Bruno Cardoso Lopes
c79e43aee3 Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:36:04 +00:00
Bruno Cardoso Lopes
59bb6fae9a Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106436 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:22:54 +00:00
Dale Johannesen
b0ccb757b3 Fix PR 7433. Silly typo in non-Darwin ARM tail call 
handling, plus correct R9 handling in that mode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:21:49 +00:00
Eric Christopher
18fb00b4b9 Add some codegen patterns for x86_64-linux-gnu tls codegen matching. 
Based on a patch by Patrick Marlier!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106433 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 18:21:27 +00:00
Jim Grosbach
9cfcfeb24b early exit for dbg_value instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106430 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 17:49:23 +00:00
Chris Lattner
9e13715fd5 remove some dead variables reported by clang++ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 17:20:18 +00:00
Kalle Raiskila
951b229ccf Mark the SPU 'lr' instruction to never have side effects. 
This allows the fast regiser allocator to remove redundant 
register moves.
Update a set of tests that depend on the register allocator
to be linear scan. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 15:08:16 +00:00
Kalle Raiskila
91fdee125c Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 14:42:19 +00:00
Rafael Espindola
c2b3e00cdf Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch. 
I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106413 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 13:31:32 +00:00
Kalle Raiskila
4794807134 Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm 
used to choke llc with the attached test.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 10:17:36 +00:00
Rafael Espindola
f0efafa61e wip 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106408 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 02:17:34 +00:00
Nick Lewycky
2a3ee5e8e9 Fix warning in no-asserts build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106405 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-20 20:27:42 +00:00
Evan Cheng
859df5e9f9 Fix a crash caused by dereference of MBB.end(). rdar://8110842 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-20 00:54:38 +00:00
Bob Wilson
31ef8e6663 Remove a fixme comment that is no longer relevant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106382 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 05:32:41 +00:00
Bob Wilson
dc076da4d2 Fix error message to match function name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106381 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 05:32:09 +00:00
Bruno Cardoso Lopes
f6ff003043 Refactoring of regular logical packed instructions to prepare for AVX ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 04:09:22 +00:00
Bruno Cardoso Lopes
f4f4bad696 Refactor aliased packed logical instructions, also add 
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 02:44:01 +00:00
Evan Cheng
02ba9e19c7 Ignore dbg_value's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 02:36:21 +00:00
Bruno Cardoso Lopes
1e8d06282f Move new sse 1 & 2 generic classes to a more appropriate place 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106372 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:32:46 +00:00
Bruno Cardoso Lopes
efc9b69deb Remove unnecessary arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106371 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:22:34 +00:00
Bruno Cardoso Lopes
17227db062 Add AVX packed intrinsics for MIN, MAX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106370 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:17:05 +00:00
Evan Cheng
0110ac66eb Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 01:01:32 +00:00
Eric Christopher
a938cfb13a Finish ripping isTwoAddress out of X86. Some mindless formatting 
and operand renaming to help.

The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:37:40 +00:00
Bruno Cardoso Lopes
be4d595afd Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106366 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:37:31 +00:00
Chris Lattner
617e595022 rip out dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:34:14 +00:00
Chris Lattner
1cf44fc051 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:34:00 +00:00
Evan Cheng
6523d2ff7f Indentation and remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106362 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:11:54 +00:00
Bruno Cardoso Lopes
fda1acb389 Clean up: remove now unnecessary Constraints 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106361 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:09:27 +00:00
Dan Gohman
9559e3b99a Silence compiler warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:02:06 +00:00
Bruno Cardoso Lopes
c82f199892 more refactoring! yay! big win over the intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-19 00:00:22 +00:00
Eric Christopher
96ab7f494d Remove isTwoAddress from here too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106358 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:56:07 +00:00
Bruno Cardoso Lopes
ccf30bd984 Fix typo, SSE1 should be used by XS, not SSE2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106357 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:53:27 +00:00
Eric Christopher
f6bc0b9d4b Remove isTwoAddress from 64-bit files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106356 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:51:21 +00:00
Evan Cheng
96c3da6436 Move ARM if-conversion before post-ra scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:32:07 +00:00
Dan Gohman
db4971259c Teach regular and fast isel to set dead flags on unused implicit defs 
on calls and similar instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:28:01 +00:00
Bruno Cardoso Lopes
8af5ed9e15 Apply some refactor to packed instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106349 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:13:35 +00:00
Evan Cheng
3ee608c5aa Update cmake list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:12:10 +00:00
Evan Cheng
886459456c Thumb2 hazard recognizer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:11:35 +00:00
Evan Cheng
86050dc8cc Allow ARM if-converter to be run after post allocation scheduling. 
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:09:54 +00:00
Jim Grosbach
ef6eb9c7ab back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 23:03:10 +00:00
Jim Grosbach
68741be5e6 Enable Expand handling of atomics for subtargets that can't do them inline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106336 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 22:35:32 +00:00
Bruno Cardoso Lopes
4b8921d1c7 Use the new 'defm' class inheritance in SSE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106327 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 22:10:11 +00:00
Bob Wilson
ebe99b2c19 Rewrite chained if's as switches and replace assertions with llvm_unreachable 
(as suggested in radar 8104405).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 21:32:42 +00:00
Dale Johannesen
51bd47edbc Fix ARM/Thumb reversal in previous attempt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 21:07:47 +00:00
Jakob Stoklund Olesen
52c61ec164 When using ADDri to get the address of a stack object, 255 is a conservative 
limit on the offset that can be materialized without using the register
scavenger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:59:25 +00:00
Dan Gohman
1415a602ad Make this comment less specific. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:45:41 +00:00
Dan Gohman
ea9f151cbc Fix X86FastISel's address-mode folding to stay within the 
original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:44:47 +00:00
Dale Johannesen
10416803c1 An attempt to fix the problem Anton reported with 
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:44:28 +00:00
Dale Johannesen
c66cdf74a9 Enable tail calls on ARM by default, with some 
basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 19:00:18 +00:00
Dan Gohman
a606d955de Start TargetRegisterClass indices at 0 instead of 1, so that 
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 18:13:55 +00:00
Dale Johannesen
df50d7e238 Last round of changes for ARM tail calls. 
Not turning them on yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 18:13:11 +00:00
Jakob Stoklund Olesen
0d8ba3303b Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 16:49:33 +00:00
Dan Gohman
027657db7c Change UpdateNodeOperands' operand and return value from SDValue to 
SDNode *, since it doesn't care about the ResNo value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106282 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 15:30:29 +00:00
Dan Gohman
5ff12fc41a Delete unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:32:32 +00:00
Dan Gohman
e368b460a2 Eliminate unnecessary uses of getZExtValue(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:22:04 +00:00
Dan Gohman
7720cb3823 isValueValidForType can be a static member function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 14:01:07 +00:00
Eric Christopher
f627dc37bf Some assorted isTwoAddress -> Constraints cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106273 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 02:41:19 +00:00
Dan Gohman
e54081088e Don't maintain a set of deleted nodes; instead, use a HandleSDNode 
to track a node over CSE events. This fixes PR7368.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:24:29 +00:00
Bruno Cardoso Lopes
d7f9cc4de7 Add {mix,max}{ss,sd}{rr,rm} AVX forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:12:56 +00:00
Dan Gohman
8a7f7426ee Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass, 
which is faster, simpler, and less surprising.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 01:05:21 +00:00
Bruno Cardoso Lopes
597ec8ed51 Use new tablegen resources in SSE tablegen code. This will 
be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 23:05:30 +00:00
Stuart Hastings
3bf9125933 Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This 
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 22:43:56 +00:00
Jim Grosbach
7072cf62a5 Thumb1 and any pre-v6 ARM target should use the libcall expansion of 
ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 02:02:03 +00:00
Jim Grosbach
c73993b678 simplify code a bit and add a more explanatory assert for cases that 
previously would result in 'cannot yet select' errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 01:37:00 +00:00
Eric Christopher
e98ad83543 Hack to let the move lowering handle dynamic-no-pic absolute moves of 
TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 00:51:48 +00:00
Jim Grosbach
7616b646f1 format and 80-column cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106173 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 23:45:49 +00:00
Jakob Stoklund Olesen
a2846b4bee Don't attempt preserving conservative kill flags. We were doing it wrong. 
This is before LiveVariables anyway, where these kill flags are recalculated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 22:11:08 +00:00
Bob Wilson
07f6e805b1 Remove the hidden "neon-reg-sequence" option. The reg sequences are working 
now, so there's no need to disable them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 21:34:01 +00:00
Benjamin Kramer
0f471e018f TODO-- 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 15:47:00 +00:00
Evan Cheng
46df4eb46e Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 07:35:02 +00:00
Bill Wendling
d361a77f14 Create a more targeted fix for not sinking instructions into a range where it 
will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 23:46:31 +00:00
Eric Christopher
6102549737 For 32-bit non-pic tlv mach-o addressing we don't need a pic base or 
a relative address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 23:08:42 +00:00
Dale Johannesen
38d5f0441c Add file missing from previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 22:24:08 +00:00
Dale Johannesen
6470a116f1 Next round of tail call changes. Register used in a tail 
call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 22:08:33 +00:00
Dale Johannesen
bf37850e42 Reapply 105986 with fix for bug pointed out by Jakob: 
flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info.  I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 21:36:43 +00:00
Chris Lattner
868ee9460c fix fastisel to handle GS and FS relative pointers. Patch by 
Nelson Elhage!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 19:08:40 +00:00
Bob Wilson
827b2106fe Add basic support for NEON modified immediates besides VMOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106030 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 19:05:35 +00:00
Daniel Dunbar
f4a7bf4ec3 Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105994 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 14:50:42 +00:00
Bob Wilson
14f1d4e74b VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105990 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 05:51:27 +00:00
Dale Johannesen
69ba5c6aa8 Revert 105986; looks like I'd better try bootstrapping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105988 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 04:55:06 +00:00
Dale Johannesen
4b559f070a The form of BuildMI used for TAILJMPr was changing the register 
containing the target address, an input, into an output.  I don't
think this actually broke anything on x86 (it does on ARM), but
it's wrong.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105986 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 03:13:49 +00:00
Jim Grosbach
400c95fe38 Make sure to skip dbg_value instructions when finding an insertion point for 
the combined load/store instruction. rdar://7797940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105982 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 00:41:09 +00:00
Bob Wilson
d3c4284849 Rename functions referring to VMOV immediates to refer to NEON "modified 
immediate" operands.  These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands.  No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105969 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 22:19:57 +00:00
Chris Lattner
6b601536ff fix a nasty bug where we were not treating available_externally 
symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105954 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 20:11:56 +00:00
Chris Lattner
ef66df4da8 fix a -Wbool-conversions warning from clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105943 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 18:28:57 +00:00
Eli Friedman
e103194851 Add back some possible optimizations for va_arg, with wording that makes it 
more clear what exactly is missing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 07:03:30 +00:00
Rafael Espindola
21d238fdba Merge getStoreRegOpcode and getLoadRegOpcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 20:13:29 +00:00
Eli Friedman
8c47d3b73f Add README entry; based on testcase from Bill Hart. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 05:54:27 +00:00
Bruno Cardoso Lopes
2dcf6d6019 make the avx intrinsics 3 address 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 03:12:14 +00:00
Bruno Cardoso Lopes
11ae95c175 Add some basic fp intrinsics for AVX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105873 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 02:38:32 +00:00
Bruno Cardoso Lopes
cf125d02a0 More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105870 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 01:53:48 +00:00
Bruno Cardoso Lopes
7be0d2c8e9 More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr 
Handle OpSize TSFlag for AVX



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105869 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 01:23:26 +00:00
Bruno Cardoso Lopes
e4f6907a7a Add some comments about REX fields 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 00:03:52 +00:00
Bruno Cardoso Lopes
c902a59f4c More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm) 
Introduce the VEX_X field


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-11 23:50:47 +00:00
Bob Wilson
1114f568bc Add a missing bitcast. This code used to only handle conversions between 
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type.  Radar 8084742.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-11 22:45:25 +00:00
Bob Wilson
1a913ed178 Add instruction encoding for the Neon VMOV immediate instruction. This changes 
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction.  This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed.  Testcase for the encoding will follow later when MC has
more support for ARM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-11 21:34:50 +00:00
Evan Cheng
aa4b5429ef Delete code that's not safe. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105774 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-10 02:08:20 +00:00
Jim Grosbach
db03adb346 be slightly more subtle about skipping dbg_value instructions; otherwise, if a 
dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105758 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 22:21:24 +00:00
Evan Cheng
68fc2daf8f Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 19:26:01 +00:00
Kalle Raiskila
43d225dc8b Fix SPU to cope with vector insertelement to an undef position. 
We default to inserting to lane 0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105722 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 09:58:17 +00:00
Kalle Raiskila
c6166c6bca Handle loading from/storing to undef pointers on SPU by inserting a 
random load/store, rather than crashing llc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 08:29:41 +00:00
Evan Cheng
34aa423814 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 03:49:12 +00:00
Eli Friedman
092f9c116a A few new x86-64 specific README entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105674 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 02:43:17 +00:00
Evan Cheng
d847124211 Thumb2 IT blocks are fairly expensive. When there are multiple selects using 
the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.

Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105669 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 01:46:50 +00:00
Kevin Enderby
09712b57ce Incremental improvement to the handling of the x86 "Jump if rCX Zero" 
instruction.  Added the 64-bit version "jrcxz" so it is recognized and also
added the checks for incorrect uses of "jcxz" in 64-bit mode and "jrcxz" in
32-bit mode.  Still to do is to correctly handle the encoding of the
instruction adding the Address-size override prefix byte, 0x67, when the width
of the count register is not the same as the mode the machine is running in.
Which for example means the encoding of "jecxz" depends if you are assembling
as a 32-bit target or a 64-bit target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 23:48:44 +00:00
Eric Christopher
497f1eb2b8 Split out these asserts so it's more apparent why we're not assembling 
that rip-relative address when executing in 32-bit mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105656 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 22:57:33 +00:00
Jim Grosbach
6335ac67b6 fix copy/paste/modify think-o 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 22:53:32 +00:00
Bruno Cardoso Lopes
99405df044 Reapply r105521, this time appending "LLU" to 64 bit 
immediates to avoid breaking the build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 22:51:23 +00:00
Eric Christopher
544153653b Ensure that mov and not lea are used to stick the address into 
the register.  While we're at it, make sure it's in the right one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105645 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 22:04:25 +00:00
Jim Grosbach
b84adb3b80 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 20:06:55 +00:00
Kalle Raiskila
e77ff11a34 Flag SPU's function call sequence together. 
Discussed here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032107.html


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 07:55:16 +00:00
Bob Wilson
dd726e5bce Fix up a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105591 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 00:42:08 +00:00
Bob Wilson
53dd2454d5 Further changes for Neon vector shuffles: 
- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
  elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
  not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105586 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-07 23:53:38 +00:00
Jim Grosbach
8077e76f93 Handle dbg_value instructions (i.e., skip them) when generating IT blocks. 
rdar://7797940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105557 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-07 21:48:47 +00:00
Bill Wendling
22a5b29820 Create new accessors to get arguments for call/invoke instructions. It breaks 
encapsulation to force the users of these classes to know about the internal
data structure of the Operands structure. It also can lead to errors, like in
the MSIL writer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105539 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-07 19:05:06 +00:00
Duncan Sands
431c3e7404 This bug is also present in MSVC10. Requested by Elrood on IRC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105527 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-05 12:40:43 +00:00
Chris Lattner
1087f54ddb revert r105521, which is breaking the buildbots with stuff like this: 
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
3eca98bb3a Initial AVX support for some instructions. No patterns matched 
yet, only assembly encoding support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-05 03:53:24 +00:00
Dale Johannesen
cf296fa162 Improvements to tail call code. No functional effect 
unless using -arm-tail-calls.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105515 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-05 00:51:39 +00:00
Dale Johannesen
88004c25c7 Fix some liveout handling related to tail calls, see comments. 
I don't think this ever resulted in problems on x86, but it
would on ARM.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-05 00:30:45 +00:00
Dale Johannesen
8fa8e7fe95 More thoroughly disable tails calls by default. 
8060143, although this doesn't fix the real problem with tail call.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105472 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 18:04:24 +00:00
Jim Grosbach
8af44b687b Another fix to prevent debug info from affecting codegen. rdar://7797940 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105470 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 17:57:34 +00:00
Jim Grosbach
958e4e1967 more dbg_value adjustments so debug info doesn't affect codegen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 01:23:30 +00:00
Jim Grosbach
d089a7ac70 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105441 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 00:15:00 +00:00
Bob Wilson
40cbe7d5d4 For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and 
VECTOR_SHUFFLEs to REG_SEQUENCE instructions.  The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized.  That is pretty awful, but I guess it
makes sense for other targets.  Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105439 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 00:04:02 +00:00
Jim Grosbach
3de755bb40 Teach the ARM load-store optimizer to deal with dbg_value instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 22:41:15 +00:00
Dale Johannesen
51e28e6348 Early implementation of tail call for ARM. 
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 21:09:53 +00:00
Eric Christopher
30ef0e5658 Add first pass at darwin tls compiler support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 04:07:48 +00:00
Eli Friedman
db1bf34178 Remove some already-fixed README entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 01:47:31 +00:00
Eli Friedman
a04a2c0a50 Remove README entry which no longer compiles to something sane. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 01:16:51 +00:00
Eli Friedman
2ad7e433c9 Remove a fixed item, update a couple partially-fixed items. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 01:01:48 +00:00
Jakob Stoklund Olesen
9edf7deb37 Slightly change the meaning of the reMaterialize target hook when the original 
instruction defines subregisters.

Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.

Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:

  %reg1234:foo = FLAP %reg1234<imp-def>

will reMaterialize(%reg3333, bar) like this:

  %reg3333:bar-foo = FLAP %reg333:bar<imp-def>

Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 22:47:25 +00:00
Jim Grosbach
18f30e6f5e Clean up 80 column violations. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 21:53:11 +00:00
Rafael Espindola
42d075c4fb Remove the TargetRegisterClass member from CalleeSavedInfo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 20:02:30 +00:00
Eli Friedman
962f549d20 Fix comment so it doesn't include comments which are irrelevant to the x86 
backend.  Add a FIXME noting what can be fixed here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 19:35:46 +00:00
Dan Gohman
71c62a2977 Use comments to document non-obvious code rather than 
mailing list archives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105341 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 19:13:40 +00:00
Bob Wilson
91a74da036 Rename canCombinedSubRegIndex method to something more grammatically correct 
and tidy up the comment describing it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 18:54:47 +00:00
Rafael Espindola
20fae65181 Replace ARM's getCalleeSavedRegClasses with a simpler solution 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 17:54:50 +00:00
Rafael Espindola
691820a1a0 Remove unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105325 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 15:44:20 +00:00
Rafael Espindola
6f07bd6ae8 cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 13:53:17 +00:00
Rafael Espindola
ce48c1de82 Remove uses of getCalleeSavedRegClasses from outside the 
backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 12:39:06 +00:00
Eli Friedman
a993f0a45f Don't try to custom-lower 64-bit add-with-overflow and friends on x86-32; the 
x86 backend currently doesn't know how to handle them.

This doesn't really fix anything because LegalizeTypes doesn't know how to
handle them either.  We do get a better error message, though.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105305 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 00:27:18 +00:00
Eli Friedman
b242563741 Remove outdated README entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105303 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 00:10:36 +00:00
Dan Gohman
d8acddda58 Fix the allocation of shadow space for the Win64 calling convention 
in X86FastISel. Patch by Jan Sjodin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105290 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-01 21:09:47 +00:00
Bruno Cardoso Lopes
7f5b0d8099 Refactor some SSE 2 unpack instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-01 17:02:50 +00:00
Kalle Raiskila
11fe24624a Fix handling of 'load' nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105269 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-01 13:34:47 +00:00
Anton Korobeynikov
4ed81ecbcd Some A9 load/store cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105109 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-29 19:25:39 +00:00
Anton Korobeynikov
8207fce96f Some rough approximations for load/stores on A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105108 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-29 19:25:34 +00:00
Anton Korobeynikov
1098ef5fa4 NEON/VFP stuff can be issued only via Pipe1 on A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105107 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-29 19:25:29 +00:00
Anton Korobeynikov
1845a387e1 Add some integer instruction itineraries for A9 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105106 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-29 19:25:17 +00:00
Evan Cheng
9c044674e6 Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105092 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-29 01:35:22 +00:00
Jakob Stoklund Olesen
05ce489871 Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndices 
were overspecified when inheriting sub-subregisters, for instance:

R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.

This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105063 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 23:48:29 +00:00
Evan Cheng
c10f5434b4 Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 23:25:23 +00:00
Dale Johannesen
2f05cc06a2 Fix comment typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105059 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 23:24:28 +00:00
Bruno Cardoso Lopes
f39e0ce4ec More SSE 1 & 2 merge, this time with logical instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105014 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 22:47:03 +00:00
Kevin Enderby
31cc9655b6 MC/X86: Add alias for movzx. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105005 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 21:20:21 +00:00
Kevin Enderby
5e394429ab MC/X86: Add alias for fwait. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105001 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 20:59:10 +00:00
Kevin Enderby
31b6c5b2f3 Fix the use of x86 control and debug registers so that the assertion failure in 
getX86RegNum() does not happen.  Patch by Shantonu Sen!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104994 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 19:01:27 +00:00
Jim Grosbach
bc213209bf correct retattr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 18:03:48 +00:00
Jim Grosbach
c9792a3c1f Cosmetic cleanup. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 17:51:20 +00:00
Jim Grosbach
5caeff5c01 make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 17:37:40 +00:00
Bob Wilson
13ef840807 Add the cc_out operand for t2RSBrs instructions. I missed this when I changed 
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 00:27:15 +00:00
Jim Grosbach
0798eddd07 Update the saved stack pointer in the sjlj function context following either 
an alloca() or an llvm.stackrestore(). rdar://8031573



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:49:24 +00:00
Evan Cheng
12616727c7 Use report_fatal_error, not llvm_unreachable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104899 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:45:31 +00:00
Jim Grosbach
a65850230a back out 104862/104869. Can reuse stacksave after all. Very cool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:11:57 +00:00
Evan Cheng
84f60b7359 llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 22:08:38 +00:00
Kevin Enderby
bd658918df MC/X86: Add aliases for Jcc variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104890 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 21:33:19 +00:00
Bob Wilson
d984eb6073 Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases 
should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 20:23:42 +00:00
Dale Johannesen
54feef2950 Mark some math lib intrinsic nodes Legal on SSE4.1. 
No functional effect as these nodes are not generated yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 20:12:41 +00:00
Dan Gohman
4d3d6e1a0c FastISel doesn't yet handle callee-pop functions. 
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104866 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 18:43:40 +00:00
Jim Grosbach
ad9aaf038e add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH 
to update the jmpbuf in the presence of VLAs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 18:23:48 +00:00
Bruno Cardoso Lopes
aa02ff1a2b Merge basic binops SSE 1 & 2 instruction classes. This is a step towards refactoring 
common code between SSE versions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 18:17:40 +00:00
Daniel Dunbar
dcbab9cf5a AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected 
to be matched.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104757 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 22:21:28 +00:00
Jakob Stoklund Olesen
c8b9f6ce23 Give SubRegIndex names to all ARM subregisters. This will be required by 
TableGen shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 22:15:03 +00:00
Daniel Dunbar
cb8326dc09 MC: Add TargetMachine support for setting the value of MCRelaxAll with 
-filetype=obj.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 21:48:55 +00:00
Jakob Stoklund Olesen
160a3bf74d Add StringRef::compare_numeric and use it to sort TableGen register records. 
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 21:47:28 +00:00
Jim Grosbach
23ff7cff52 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 20:22:18 +00:00
Kevin Enderby
b106543592 Fix the x86 move to/from segment register instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 20:10:45 +00:00
Daniel Dunbar
95506d40c5 MC: Change RelaxInstruction to only take the input and output instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104713 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 18:15:06 +00:00
Dan Gohman
d9c2af5409 Fix a typo in a comment that Gabor noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104711 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 18:03:53 +00:00
Daniel Dunbar
8488252855 MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it 
before encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 17:45:29 +00:00
Jakob Stoklund Olesen
ca561ffcf3 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 17:27:12 +00:00
Daniel Dunbar
c90e30aa6f MC: Eliminate MCAsmFixup, replace with MCFixup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104699 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 15:18:56 +00:00
Daniel Dunbar
482ad802f1 MC: Use accessors for access to MCAsmFixup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104697 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 15:18:31 +00:00
Daniel Dunbar
c9adb8c61e MC: Change MCInst::dump_pretty to not include a trailing newline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104696 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 15:18:13 +00:00
Zhongxing Xu
c2798a18a7 SRetReturnReg was set in LowerFormalArguments(). So only assert it here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104691 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 08:10:02 +00:00
Shih-wei Liao
9f3b6a381a Coding style change (Adding 1 missing space.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104670 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 04:46:50 +00:00
Shih-wei Liao
45469f38b6 Adding the missing implementation for ARM::SBFX and ARM::UBFX. 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 03:21:39 +00:00
Jim Grosbach
54e13eceff fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 01:22:21 +00:00
Jakob Stoklund Olesen
b555609e73 Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
6a45d681e5 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:28:19 +00:00
Shih-wei Liao
6d37a29588 Adding the missing implementation of Bitfield's "clear" and "insert". 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:25:05 +00:00
Shih-wei Liao
5170b71143 To handle s* registers in emitVFPLoadStoreMultipleInstruction(). 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:02:28 +00:00
Jakob Stoklund Olesen
76f0ad7bf5 Drop the SuperregHashTable. It is essentially the same as SubregHashTable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 23:43:18 +00:00
Kevin Enderby
cf50a5390c Changed the encoding of X86 floating point stack operations where both operands 
are st(0).  These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0.  To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used.  To do this the same logical trick is use from the darwin assembler
in converting things like this:

fmul %st(0), %st

into this:

fmul %st(0)

by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand.  This also has the add
benefit to allow things like:

fmul %st(1), %st

that llvm-mc did not assemble.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 20:52:34 +00:00
Jakob Stoklund Olesen
b53985239c Separate unrelated cases that once shared a numeric value 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104629 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:40 +00:00
Jakob Stoklund Olesen
1fc8e759a7 Print symbolic SubRegIndex names on machine operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:38 +00:00