Chris Lattner
0ea70b219a
Add some 64-bit logical ops.
...
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 22:34:10 +00:00
Chris Lattner
dd58343857
64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28880 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 21:39:30 +00:00
Chris Lattner
4e85e64007
Remove some now-unneeded casts from instruction patterns. With the casts
...
removed, tblgen produces identical output to with them in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28867 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-20 00:39:56 +00:00
Chris Lattner
66d7ebb777
In 64-bit mode, addr mode operands use G8RC instead of GPRC.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28840 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-16 21:29:03 +00:00
Chris Lattner
059ca0f5b7
fix some assumptions that pointers can only be 32-bits. With this, we can
...
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28839 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-16 21:01:35 +00:00
Chris Lattner
956f43c310
Split 64-bit instructions out into a separate .td file
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28838 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-16 20:22:01 +00:00
Chris Lattner
4a45abf66e
Fix a problem exposed by the local allocator. CALL instructions are not marked
...
as using incoming argument registers, so the local allocator would clobber them
between their set and use. To fix this, we give the call instructions a variable
number of uses in the CALL MachineInstr itself, so live variables understands
the live ranges of these register arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28744 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-10 01:14:28 +00:00
Chris Lattner
001db453f5
Add PowerPC intrinsics to support dcbz[l]
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28696 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-06 21:29:23 +00:00
Chris Lattner
c703a8fbf8
Make PPC call lowering more aggressive, making the isel matching code simple
...
enough to be autogenerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28354 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 19:00:46 +00:00
Chris Lattner
9a2a497284
Switch PPC over to a call-selection model where the lowering code creates
...
the copyto/fromregs instead of making the PPCISD::CALL selection code create
them. This vastly simplifies the selection code, and moves the ABI handling
parts into one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28346 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 06:01:33 +00:00
Nate Begeman
37efe67645
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-22 18:53:45 +00:00
Chris Lattner
80f362a48f
These are correctly encoded by the JIT. I checked :)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27810 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 19:03:38 +00:00
Chris Lattner
90564f26d1
Implement an important entry from README_ALTIVEC:
...
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27804 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18 17:59:36 +00:00
Chris Lattner
710ff32983
Add VRRC select support
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27543 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 22:45:08 +00:00
Chris Lattner
a17b1557ad
Lower vector compares to VCMP nodes, just like we lower vector comparison
...
predicates to VCMPo nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27285 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 05:13:27 +00:00
Chris Lattner
7f20b13518
Use normal lvx for scalar_to_vector instead of lve*x. They do the exact
...
same thing and we have a dag node for the former.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27205 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 01:43:22 +00:00
Chris Lattner
6d92caddc4
Codegen vector predicate compares.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27151 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 10:06:40 +00:00
Chris Lattner
b22a04d881
Move all Altivec stuff out into a new PPCInstrAltivec.td file.
...
Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27117 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:51:43 +00:00
Chris Lattner
8d052bc711
Add some basic patterns for other datatypes
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27116 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:39:07 +00:00
Chris Lattner
5a2025465b
Add support for __builtin_altivec_vnmsubfp /vmaddfp
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27112 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:05:55 +00:00
Chris Lattner
9c61dcf1aa
Codegen things like:
...
<int -1, int -1, int -1, int -1>
and
<int 65537, int 65537, int 65537, int 65537>
Using things like:
vspltisb v0, -1
and:
vspltish v0, 1
instead of using constant pool loads.
This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27106 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 06:12:06 +00:00
Chris Lattner
8edd11f33d
Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27069 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 18:24:43 +00:00
Chris Lattner
64b3a08bc6
add support for using vxor to build zero vectors. This implements
...
Regression/CodeGen/PowerPC/vec_zero.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27059 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 07:48:08 +00:00
Chris Lattner
9d5da1d96c
Gabor points out that we can't spell. :)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 07:12:19 +00:00
Chris Lattner
dc6af72781
Add PPC vector bit-convert support
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26995 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 19:54:27 +00:00
Chris Lattner
ecfe55e65b
When possible, custom lower 32-bit SINT_TO_FP to this:
...
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
Chris Lattner
eb8b09f69f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 01:44:36 +00:00
Chris Lattner
8593f9891d
When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26913 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 00:51:38 +00:00
Chris Lattner
bd83afd3cd
Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
...
figuring these out! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26904 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 18:26:51 +00:00
Chris Lattner
32f57d9e26
Fix the pattern for VADDUWM, add i32 splat
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26901 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 17:51:58 +00:00
Evan Cheng
e63d746ef6
Use tblgen'd VECTOR_SHUFFLE selection code.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 08:14:16 +00:00
Chris Lattner
dd4d2d0e40
Add support for generating vspltw, instead of a vperm instruction with a
...
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26898 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 06:51:10 +00:00
Chris Lattner
3c0f9cc90c
Check in some intermediate code that adds a skeleton for matching vsplt*
...
instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 06:15:45 +00:00
Chris Lattner
08e25de4d3
fix typo
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26889 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 05:05:55 +00:00
Chris Lattner
556aae0df0
add vsplat instructions, fix sched description for vperm
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26888 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 04:47:33 +00:00
Chris Lattner
f1d0b2beda
Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
...
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26887 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 01:53:53 +00:00
Chris Lattner
abdff1ee6d
add the vperm instruction
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26883 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 01:00:56 +00:00
Chris Lattner
b2177b9405
Custom lower SCALAR_TO_VECTOR into lve*x.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26868 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-19 06:55:52 +00:00
Chris Lattner
528180ed7b
add support for vector undef
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26863 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-19 06:10:09 +00:00
Chris Lattner
a17409dfd6
minor fixes
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26857 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-19 05:43:01 +00:00
Chris Lattner
0a7bff01d0
we don't use lmw/stmw. When we want them they are easy enough to add
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26853 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-19 04:33:37 +00:00
Nate Begeman
79691bc1f3
Fix subfic to match subc by default instead of sub so that it is correctly
...
cost-modeled as producing a flag. This fixes the test I just added for neg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26835 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-17 22:41:37 +00:00
Nate Begeman
81e8097377
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-17 01:40:33 +00:00
Chris Lattner
be80fc8d09
Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26808 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-16 22:35:59 +00:00
Chris Lattner
335fd3c7c2
Add support for copying registers. still needed: spilling and reloading them
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-16 20:03:58 +00:00
Nate Begeman
133decdceb
Update scheduling info for vrsave instruction
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26776 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-15 05:25:05 +00:00
Chris Lattner
1877ec9b02
For functions that use vector registers, save VRSAVE, mark used
...
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
Chris Lattner
fd97734f36
Mark instructions that are cracked by the PPC970 decoder as such.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 05:15:10 +00:00
Chris Lattner
88d211f823
Several big changes:
...
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-12 09:13:49 +00:00
Chris Lattner
bbf1c72d51
implement TII::insertNoop
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05 23:49:55 +00:00
Chris Lattner
5126984b1d
Compile this:
...
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 05:50:56 +00:00
Nate Begeman
551bf3f800
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 05:43:56 +00:00
Nate Begeman
789fd42320
Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/
...
PowerPC/and-imm.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26136 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-12 09:09:52 +00:00
Chris Lattner
cedc6f4b30
PHI and INLINEASM are now built-in instructions provided by Target.td
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 01:46:15 +00:00
Chris Lattner
a613d267ea
ahem :)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25239 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-12 02:05:36 +00:00
Nate Begeman
35ef913ec2
Add bswap, rotl, and rotr nodes
...
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25222 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-11 21:21:00 +00:00
Nate Begeman
49dddb273d
Remove a comment that no longer applies.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25167 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-10 00:15:59 +00:00
Chris Lattner
e5cf122869
add ret void support back
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25164 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-09 23:20:37 +00:00
Evan Cheng
6da8d99f70
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
...
hasInFlag, hasOutFlag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25155 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-09 18:28:21 +00:00
Jim Laskey
abf6d1784b
Added initial support for DEBUG_LABEL allowing debug specific labels to be
...
inserted in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25104 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-05 01:25:28 +00:00
Jim Laskey
5bf6f25b4a
Add unique id to debug location for debug label use (work in progress.)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25096 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-04 15:04:11 +00:00
Nate Begeman
b73628b5ab
Add support for generating v4i32 altivec code
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25046 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-30 00:12:56 +00:00
Evan Cheng
2b4ea795a2
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-26 09:11:45 +00:00
Evan Cheng
171049d10f
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
...
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24997 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 22:14:32 +00:00
Evan Cheng
6a3bfd97f2
Flip the meaning of FPContractions to reflect Requires<[]> change.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24884 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 20:08:53 +00:00
Nate Begeman
9e4dd9dfc9
Pattern-match return. Includes gross hack!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24874 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 00:26:01 +00:00
Nate Begeman
7fd1edd32e
Convert load/store over to being pattern matched
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24871 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-19 23:25:09 +00:00
Jim Laskey
f5395cee6a
Added source file/line correspondence for dwarf (PowerPC only at this point.)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24748 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-16 22:45:29 +00:00
Nate Begeman
f492f9901a
Add a second vector type to the VRRC register class, and fix some patterns
...
so that tablegen can infer all types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24746 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-16 09:19:13 +00:00
Nate Begeman
a07da92624
Use the new predicate support that Evan Cheng added to remove some code
...
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 22:54:33 +00:00
Evan Cheng
8c75ef9228
Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24716 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 22:07:12 +00:00
Nate Begeman
3fb6877cb4
Add support for fmul node of type v4f32.
...
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24701 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 00:34:09 +00:00
Nate Begeman
993aeb2ed9
Prepare support for AltiVec multiply, divide, and sqrt.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24700 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 22:55:22 +00:00
Chris Lattner
d717b19933
Remove type casts that are no longer needed
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24661 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-11 07:45:47 +00:00
Nate Begeman
28a6b02626
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24657 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-10 02:36:00 +00:00
Nate Begeman
0976122abc
Add support patterns to many load and store instructions which will
...
hopefully use patterns in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24651 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-09 23:54:18 +00:00
Chris Lattner
4172b10ca1
Use new PPC-specific nodes to represent shifts which require the 6-bit
...
amount handling that PPC provides. These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits. This fixes a miscompilation of crafty with
the new front-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24615 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-06 02:10:38 +00:00
Chris Lattner
bd05982b48
Add some explicit type casts so that tblgen knows the type of the shift
...
amount, which is not necessarily the same as the type being shifted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24594 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 02:34:05 +00:00
Chris Lattner
937a79dbe3
Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen
...
improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24591 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 19:01:59 +00:00
Chris Lattner
60a4ab2d5c
Finish moving uncond br over to .td file, remove from .cpp file.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24590 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 18:48:01 +00:00
Chris Lattner
1e48478557
Define BR in the .td file now that Evan made tblgen smarter.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24589 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 18:42:54 +00:00
Nate Begeman
7ac8e6b6a8
Represent the encoding of the SPR instructions as they actually are, so
...
that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24521 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 22:42:50 +00:00
Nate Begeman
9b14f66320
Add the remainder of the AltiVec 4 x float instructions. Further
...
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24516 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 08:04:45 +00:00
Nate Begeman
01595c52b3
Small tweaks noticed while on the plane.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24492 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-26 22:39:34 +00:00
Nate Begeman
e4f17a5f9b
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
...
Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-23 05:29:52 +00:00
Chris Lattner
3e7f86a037
disentangle call operands from branch operands a bit
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24400 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-17 19:16:08 +00:00
Chris Lattner
490ad08097
Generate LA and ADDIS when possible.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24395 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-17 17:52:01 +00:00
Chris Lattner
860e8862c1
Add an initial hack at legalizing GlobalAddress into the appropriate nodes
...
on Darwin to remove smarts from the isel. This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file. However, we can currently emit stuff like
this: :)
li r2, lo16(L_x$non_lazy_ptr)
lis r3, ha16(L_x$non_lazy_ptr)
lwzx r2, r3, r2
The obvious improvements will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24390 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-17 07:30:41 +00:00
Chris Lattner
bae5b3c1c6
LI could theoretically be used for the lo-part of a global address, just like
...
lis can be used for the high part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24388 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-17 07:04:43 +00:00
Nate Begeman
422b0cee7a
Patch to clean up function call pseudos and support the BLA instruction,
...
which branches to an absolute address. This is required to support objc
direct dispatch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24370 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-16 00:48:01 +00:00
Chris Lattner
6df2507121
add support for branch on ordered/unordered.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24067 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-28 20:32:44 +00:00
Chris Lattner
6e61ca6fa7
autogen undef
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23991 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-25 21:03:41 +00:00
Chris Lattner
3075a4e94d
Allow pseudos to have patterns, no functionality change
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23988 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-25 20:58:43 +00:00
Chris Lattner
9c73f095bb
Autogen fsel
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23987 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-25 20:55:47 +00:00
Chris Lattner
e6115b370a
Autogen a few new ppc-specific nodes
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23985 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-25 20:41:46 +00:00
Chris Lattner
dabb8291e8
Instead of aborting if not a case we can handle specially, break out and
...
let the generic code handle it. This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.
also, reindent this code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23874 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-21 21:17:10 +00:00
Nate Begeman
ae1641c39f
Match rotate. This does actually match the rotates in an rc5 cipher, but I
...
haven't seen it fire on our testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23863 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-21 06:36:18 +00:00
Nate Begeman
12a923408c
Add some more patterns for i64 on ppc
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23842 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-20 07:51:08 +00:00
Jim Laskey
538421411a
Added InstrSchedClass to each of the PowerPC Instructions.
...
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-19 19:51:16 +00:00
Nate Begeman
2d5aff761d
Write patterns for the various shl and srl patterns that don't involve
...
doing something clever.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23824 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-19 18:42:01 +00:00