Charles Davis
3a5d7d0665
Add a test for Win64 EH unwind information emission.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 03:54:43 +00:00
Charles Davis
3ac7b034d6
Add a test for the chained directives that I forgot last time.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 05:17:43 +00:00
Charles Davis
ca93138e11
Test .seh_startchained and .seh_endchained parsing.
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Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.
The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 02:45:47 +00:00
Charles Davis
410ef2b263
Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues with
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them.
I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 21:43:45 +00:00
Charles Davis
575630ccb8
Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix the
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buggy methods that parse these directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:51:25 +00:00
Charles Davis
47268164f3
Add a test for .seh_pushframe parsing. Fix the bug exposed by it (and another
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one I found by inspection).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132037 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:08:15 +00:00
Charles Davis
309213279e
Add a test for the .seh_handler directive. Fix problems with the parsing
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method exposed by the test. While we're at it, simplify the .seh_proc
parsing method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 01:33:42 +00:00
Bruno Cardoso Lopes
56926a3961
Fix PR9762
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Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 00:35:03 +00:00
Charles Davis
40de0e013a
Test basic SEH directive-parsing functionality. Fix a latent bug exposed by
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this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 21:22:53 +00:00
Chris Lattner
d521d8bf92
add test from PR9164
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 22:35:34 +00:00
Chris Lattner
b8a21ad915
testcase for PR9378
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 22:32:53 +00:00
Johnny Chen
75f4296c7c
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
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Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 17:51:04 +00:00
Rafael Espindola
b8adb8af0f
adds some attributes to attribute section when cpu is "xscale"
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(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 20:10:34 +00:00
Rafael Espindola
298c8e12ea
fixes target address tBL and tBLX and sets relocation type
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of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 20:01:01 +00:00
Jason W Kim
861b9c6a39
This fixes one divergence between LLVM and binutils for ARM in the
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text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:55:25 +00:00
Rafael Espindola
a3bff99f0a
ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
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Fixes PR9934.
We really need to start tblgening the relocation info :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:32:34 +00:00
Johnny Chen
a96581f4f7
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 20:32:41 +00:00
Rafael Espindola
6469540adf
sets bit 0 of the function address of thumb function in .symtab
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("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 16:17:21 +00:00
Owen Anderson
18901d63bf
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 17:00:48 +00:00
Rafael Espindola
e3a0e987f3
On MachO, unlike ELF, there should be no relocation to produce the CIE pointer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131149 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 20:59:42 +00:00
Rafael Espindola
0d450dc659
In a debug_frame the cfi offset is to the start of the debug_frame section!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131129 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 15:20:23 +00:00
Rafael Espindola
40a7dbbeff
Add support for producing .deubg_frame sections.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 03:54:12 +00:00
Jakob Stoklund Olesen
f695b3ad62
Explicitly request -join-physregs for some tests that depend on it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130855 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 19:01:59 +00:00
Eric Christopher
b65122c873
Remove some random comments that snuck in from somewhere.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 00:48:02 +00:00
Eric Christopher
2fc496fcf5
xmm0 is an implicit parameter in this and so shouldn't be in the
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string template.
Fixes rdar://8493866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 01:28:32 +00:00
Daniel Dunbar
c8497b6a25
MCAsmLayout: Add support for computing the symbol offset of variables. Not
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currently used, because variables don't get reported as being "defined".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130524 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 18:20:20 +00:00
Daniel Dunbar
90604ab725
MC: Change variable symbols to be recognized as defined, by assigning their sections based on FindAssociatedSection().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 18:20:17 +00:00
Johnny Chen
5a2336e794
Add tests for A8.6.110 NOP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-27 23:29:21 +00:00
Chandler Carruth
a4a2a03c31
Remove some hard coded CR-LFs. Some of these were the entire files, one of
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these was just one line of a file. Explicitly set the eol-style property on the
files to try and ensure this fix stays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-25 07:11:23 +00:00
Johnny Chen
597fa65373
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
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print out ldr, not ldr.n.
rdar://problem/9267772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 19:12:43 +00:00
Rafael Espindola
1ac7fe0f4d
Fix relative relocations. This is sufficient for running the rust testsuite with
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MC :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21 18:36:50 +00:00
Rafael Espindola
3660a847f1
Behave like gnu as when a relocation crosses sections.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20 14:01:45 +00:00
Johnny Chen
3a96122c4a
Thumb2 BFC was insufficiently encoded.
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rdar://problem/9292717
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 22:52:15 +00:00
Johnny Chen
a704bc9354
A8.6.315 VLD3 (single 3-element structure to all lanes)
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The a bit must be encoded as 0.
rdar://problem/9292625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129618 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 22:49:08 +00:00
Joerg Sonnenberger
c25e8d8cea
Add encoding tests for flds/filds
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 19:25:31 +00:00
Chris Lattner
7a2bdde0a0
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 05:18:47 +00:00
Johnny Chen
de29a52940
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
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(single element or n-element structure to all lanes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 00:10:45 +00:00
Johnny Chen
cd695fdac1
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 19:13:28 +00:00
Bill Wendling
d336de318e
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
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(movzx/movsx) because they give more information. Revert that part of the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:46:37 +00:00
Bill Wendling
c6df9883da
Have the X86 back-end emit the alias instead of what's being aliased. In most
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cases, it's much nicer and more informative reading the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:11:51 +00:00
Johnny Chen
e8d087ad35
Thumb disassembler did not handle tBRIND (indirect branch) properly.
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rdar://problem/9280370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 21:59:01 +00:00
Johnny Chen
6c7e4147dc
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
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rdar://problem/9280470
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 21:35:49 +00:00
Johnny Chen
471d73d5d3
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
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rdar://problem/9279440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 21:04:32 +00:00
Johnny Chen
9bb386a933
Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
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rdar://problem/9276651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 19:46:05 +00:00
Johnny Chen
119af20c7b
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
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rdar://problem/9276427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13 17:51:02 +00:00
Johnny Chen
55e6419b12
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
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rdar://problem/9273947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 23:31:00 +00:00
Johnny Chen
ec51a6225c
The Thumb2 RFE instructions need to have their second halfword fully specified.
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In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 21:41:51 +00:00
Johnny Chen
32cefad4b3
Add bad register checks for Thumb2 Ld/St instructions.
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rdar://problem/9269047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 21:17:51 +00:00
Johnny Chen
f9ce2cba42
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
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be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 18:48:00 +00:00
Johnny Chen
49fdfe3ce5
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 17:09:04 +00:00
Rafael Espindola
25f492e778
Fix the case of a .cfi_rel_offset before any .cfi_def_cfa_offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129362 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 16:12:03 +00:00
Rafael Espindola
c57543964d
Implement .cfi_same_value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129361 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 15:31:05 +00:00
Johnny Chen
163b6eaf25
Add one test case (svc).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129327 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 00:21:48 +00:00
Eric Christopher
05f9e4e8bd
Match case for invalid constant error messages and add a new
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test for invalid hexadecimals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129326 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 00:18:03 +00:00
Johnny Chen
e77f72d7d2
A8.6.16 B
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Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;
rdar://problem/9268681
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 00:14:49 +00:00
Eric Christopher
164254d77c
Test for invalid constant expr addition - bad octal constant.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 00:03:38 +00:00
Johnny Chen
de16508955
Thumb disassembler was erroneously rejecting "blx sp" instruction.
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rdar://problem/9267838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 23:33:30 +00:00
Rafael Espindola
a61842bf6e
Implement cfi_rel_offset
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129306 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 21:49:50 +00:00
Rafael Espindola
787d41aaa0
Add test for previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 21:41:34 +00:00
Johnny Chen
35563fee7b
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
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rdar://problem/9266265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 21:14:35 +00:00
Johnny Chen
e679d3331b
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
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invalid instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 18:34:12 +00:00
Chris Lattner
15f8951799
fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,
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InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09 19:41:05 +00:00
Benjamin Kramer
c18214a6e0
Don't store Twine temporaries, it's not safe.
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And don't append the name over and over again in the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129210 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09 11:26:27 +00:00
Johnny Chen
c636074afc
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
...
PR9650
rdar://problem/9257565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 19:41:22 +00:00
Johnny Chen
40de2b3f15
Sanity check the option operand for DMB/DSB.
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PR9648
rdar://problem/9257634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 19:18:07 +00:00
Johnny Chen
084b5df5ae
MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.
...
Add tests for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 17:29:58 +00:00
Johnny Chen
97fdff1d3f
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
...
Add more test cases to exercise the logical branches related to the above change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 00:29:09 +00:00
Rafael Espindola
9974b8b3cb
Update tests
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 23:51:25 +00:00
Johnny Chen
3cf3059b11
Add a VEXT test.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 22:04:01 +00:00
Rafael Espindola
ce8463f1fb
Add support for .skip.
...
Patch by Roman Divacky.
Fixes PR9361.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 20:26:23 +00:00
Johnny Chen
22dc4d9f59
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
...
Add some test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:28:58 +00:00
Johnny Chen
8dbda0b51b
Add sanity checking for invalid register encodings for saturating instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:02:08 +00:00
Johnny Chen
4d4e25740b
Add some more comments about checkings of invalid register numbers.
...
And two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 18:33:19 +00:00
Johnny Chen
f16f4e09ec
Sanity check MSRi for invalid mask values and reject it as invalid.
...
rdar://problem/9246844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 01:37:34 +00:00
Johnny Chen
8424a60fc9
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
...
for USAD8 and USADA8.
rdar://problem/9247060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 01:05:52 +00:00
Johnny Chen
2455268cdd
Should also check SMLAD for invalid register values.
...
rdar://problem/9246650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 00:50:25 +00:00
Johnny Chen
d8b4c4d74f
A8.6.393
...
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.
So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
vst2.32 {d0, d2}, [r3, :256], r3
we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 22:14:48 +00:00
Johnny Chen
4d81c9a6ba
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
...
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 20:49:02 +00:00
Johnny Chen
a9611549fe
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
...
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 18:27:46 +00:00
Johnny Chen
6a1220eeca
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
...
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 01:18:32 +00:00
Johnny Chen
2c868d1eef
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
...
encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 23:28:00 +00:00
Johnny Chen
c3281c10c9
A7.3 register encoding
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Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:57:07 +00:00
Johnny Chen
5438d76416
ARM disassembler was erroneously accepting an invalid RSC instruction.
...
Added checks for regs which should not be 15.
rdar://problem/9237734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:18:07 +00:00
Johnny Chen
c584e317e9
ARM disassembler was erroneously accepting an invalid LSL instruction.
...
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 21:49:44 +00:00
Johnny Chen
2c2130bc64
The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
...
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.
rdar://problem/9236873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 20:32:23 +00:00
Johnny Chen
bbc65bbb90
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 19:42:11 +00:00
Johnny Chen
5dc0c50372
LDRD now prints out two dst registers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 18:53:14 +00:00
Johnny Chen
12bb2958c4
Constants with multiple encodings (ARM):
...
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
<byte> is the numeric value of abcdefgh, in the range 0-255
<rot> is twice the numeric value of rotation, an even number in the range 0-30.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 18:02:46 +00:00
Johnny Chen
b26d8d7c49
Check for invalid register encodings for UMAAL and friends where:
...
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if dHi == dLo then UNPREDICTABLE;
rdar://problem/9230202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 17:43:10 +00:00
Johnny Chen
157536b1fb
Fix SRS/SRSW encoding bits.
...
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS
Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 00:16:18 +00:00
Johnny Chen
2d66cec9dd
Fix incorrect alignment for NEON VST2b32_UPD.
...
rdar://problem/9225433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 20:35:31 +00:00
Bruno Cardoso Lopes
ac79e4c82f
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
...
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:18:19 +00:00
Joerg Sonnenberger
4a8ac8de1d
Add support for the VIA PadLock instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 16:58:13 +00:00
Johnny Chen
04187ecd57
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
...
instead of the second operand in addrmode_imm12.
rdar://problem/9225289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 02:24:54 +00:00
Johnny Chen
103bf951a4
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
...
rdar://problem/9224276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 23:30:25 +00:00
Johnny Chen
6da3fe68c6
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
...
rdar://problem/9224120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 23:15:50 +00:00
Johnny Chen
857b1939da
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
...
all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 22:32:51 +00:00
Johnny Chen
ec30f6f5e5
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
...
as invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 20:21:38 +00:00
Johnny Chen
5307da994a
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
...
rdar://problem/9219356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 18:26:38 +00:00
Bruno Cardoso Lopes
ae0855401b
Apply again changes to support ARM memory asm parsing. I removed
...
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 23:26:08 +00:00
Johnny Chen
0c630b5f38
Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which
...
amounts to an UNDEFINED instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 20:54:30 +00:00
Johnny Chen
a52d7da1d8
Fix single word and unsigned byte data transfer instruction encodings so that
...
Inst{4} = 0.
rdar://problem/9213022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 19:28:35 +00:00
Johnny Chen
8901e6ff3d
Add BLXi to the instruction table for disassembly purpose.
...
A8.6.23 BLX (immediate)
rdar://problem/9212921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 17:53:50 +00:00
Daniel Dunbar
48a36158ec
Remove stray empty test file.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128640 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 17:01:56 +00:00
Bruno Cardoso Lopes
b41aaab5a1
Revert r128632 again, until I figure out what break the tests
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 15:54:36 +00:00
Bruno Cardoso Lopes
bcd3a9cd84
Reapply r128585 without generating a lib depedency cycle. An updated log:
...
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay
e4345c9977
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
...
This revision introduced a dependency cycle, as nlewycky mentioned by email.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 00:39:16 +00:00
Bruno Cardoso Lopes
40829ed6f5
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
...
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:32:32 +00:00
Johnny Chen
caee968481
Add a test case for thumb stc2 instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 01:02:06 +00:00
Kevin Enderby
b715ce35d7
Adding a test for "-inf" as well.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 21:54:10 +00:00
Johnny Chen
e077157e54
Add a test case for MSRi.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 21:52:02 +00:00
Kevin Enderby
360d8d7a02
Added support symbolic floating point constants in the MC assembler for Infinity
...
and Nans with the same strings as GAS supports. rdar://8673024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 21:11:52 +00:00
Johnny Chen
5726005e4f
Add a thumb test file for printf (iOS 4.3).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 21:09:30 +00:00
Johnny Chen
9eda569a74
A8.6.188 STC, STC2
...
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.
rdar://problem/9200661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 19:49:38 +00:00
Johnny Chen
4381dd1f21
Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 19:10:06 +00:00
Johnny Chen
288a4284bb
Add and modify some tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 19:08:52 +00:00
Owen Anderson
848b0c39b1
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 16:45:53 +00:00
Daniel Dunbar
c6cf43d258
MC: Add support for disabling "temporary label" behavior. Useful for debugging
...
on Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128430 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28 22:49:15 +00:00
Johnny Chen
d560a80925
Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases.
...
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128417 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28 18:41:58 +00:00
Johnny Chen
eca915fb52
Fixed the t2PLD and friends disassembly and add two test cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26 01:32:48 +00:00
Johnny Chen
cf0fe4650f
Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128306 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 23:02:58 +00:00
Johnny Chen
65c0a59869
Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128305 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 22:43:28 +00:00
Johnny Chen
a2755b9829
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
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Also add some test cases.
rdar://problem/9189829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 22:19:07 +00:00
Johnny Chen
abeea57639
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
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rdar://problem/9182892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 19:35:37 +00:00
Johnny Chen
b66a097612
A8.6.226 TBB, TBH:
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Add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 18:40:21 +00:00
Johnny Chen
ceceabd4b1
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
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t2LDREX/t2STREX instructions. Add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 18:29:49 +00:00
Daniel Dunbar
8b2b43c41d
MC: Improve some diagnostics on uses of '.' pseudo-symbol.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128289 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:47:17 +00:00
Johnny Chen
6c3891067b
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
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rdar://problem/9184053
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:31:16 +00:00
Johnny Chen
f14d5cf33a
Also need to handle invalid imod values for CPS2p.
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rdar://problem/9186136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:03:12 +00:00
Johnny Chen
a7078c4f27
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
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modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 01:09:48 +00:00
Johnny Chen
ef74e9ab40
delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 00:17:42 +00:00
Johnny Chen
8c13335c9a
The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since
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the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add
test cases for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 23:42:31 +00:00
Johnny Chen
1090d7711b
The ARM disassembler was confused with the 16-bit tSTMIA instruction.
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According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 23:21:14 +00:00
Johnny Chen
c39b6271be
Handle the added VBICiv*i* NEON instructions, too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 22:04:39 +00:00
Johnny Chen
9091bf25d9
T2 Load/Store Multiple:
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These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:36:56 +00:00
Benjamin Kramer
83ccbff84f
Plug a leak in the arm disassembler and put the tests back.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
505f3cd296
Add asm parsing support w/ testcases for strex/ldrex family of instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:04:58 +00:00
Johnny Chen
02af767dca
Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'.
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These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 20:56:23 +00:00
Johnny Chen
e6d69e7dbe
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
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Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 20:42:48 +00:00
Johnny Chen
b4ac342ea0
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
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VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:40:38 +00:00
Johnny Chen
ce1868b21c
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
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a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 17:04:22 +00:00
Johnny Chen
3d793962be
Load/Store Multiple:
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These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 01:40:42 +00:00
Johnny Chen
571f290376
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
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We now tag them as IndexModePost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 01:07:26 +00:00
Johnny Chen
2abc9d2444
The r128103 fix to cope with the removal of addressing modes from the MC instructions
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were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 00:28:38 +00:00
Johnny Chen
8d668a8605
Add disassembly test cases for:
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A8.6.292 VCMPE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128120 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 23:08:56 +00:00
Johnny Chen
27c6baeca2
LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
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We now tag them as IndexModePost.
This fixed http://llvm.org/bugs/show_bug.cgi?id=9530 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 22:28:49 +00:00
Johnny Chen
83cf2ffdcd
Add one more test case for VFP Load/Store Multiple (vpop).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 20:21:08 +00:00
Johnny Chen
758df29741
A8.6.399 VSTM:
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VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.
Also add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 20:00:10 +00:00
Rafael Espindola
7c18fa87a4
Write the section table and the section data in the same order that
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gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127972 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-20 18:44:20 +00:00
Johnny Chen
94dad03a96
Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
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The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 01:16:20 +00:00