42 Commits

Author	SHA1	Message	Date
Florian Reitz	93cd52b99c	Fix in VQ44 pinning	2019-06-02 19:35:28 +02:00
Florian Reitz	ffa94345b5	Asserts for simulation	2019-03-17 15:59:43 +01:00
Florian Reitz	3ccd8ec999	VHDL for VQFP and PLCC packages	2019-03-17 15:29:29 +01:00
Florian Reitz	781d283c3c	Flasher project added	2019-03-03 10:22:06 +01:00
Florian Reitz	02d9e608e1	Program enable added and verified	2019-03-03 10:21:02 +01:00
Florian Reitz	91d54ddd9c	AddressDecoder verified in simulation	2019-03-03 10:20:50 +01:00
Florian Reitz	70c0c118fc	Expected results added to AddressDecoder simulation	2019-03-03 10:20:46 +01:00
Florian Reitz	7a0480f05e	LED removed from AddressDecoder	2019-03-03 10:20:40 +01:00
Florian Reitz	b50b1037fd	NWE signal added, not tested	2019-03-03 10:20:33 +01:00
freitz85	505fe10434	SDHC flag added to CPLD	2017-11-25 19:42:33 +01:00
freitz85	9aa65960c4	SPI Mode 3	2017-11-01 16:50:56 +01:00
freitz85	cf98c54e77	Linear addressing from Cn00	2017-10-23 22:42:27 +02:00
freitz85	c5945ff0ec	New address decoding	2017-10-16 22:53:41 +02:00
freitz85	b37df65a45	Test for old AddressDecoder	2017-10-16 22:01:41 +02:00
freitz85	70def47cf2	More VDHL tests added	2017-10-15 20:58:33 +02:00
freitz85	723406657e	Fixes according to IIgs Tech Note #68	2017-10-13 23:04:38 +02:00
freitz85	eeb0b14725	AddressDecoder testbench	2017-10-12 20:37:37 +02:00
freitz85	819904bea2	Spi simulation working	2017-10-10 23:37:21 +02:00
freitz85	cc9d9d21db	Rename files	2017-10-10 22:57:47 +02:00
freitz85	7e2414c1bf	AddressDecoder in VHDL	2017-10-10 22:36:48 +02:00
freitz85	74c6b83b4e	Synthesis guards for debug signals	2017-10-10 21:58:22 +02:00
freitz85	2e4ebd9ac0	Test bench worst and best case timings	2017-10-10 21:22:18 +02:00
freitz85	8a6e7e647e	Test bench	2017-10-10 02:53:21 +02:00
freitz85	797993500e	Test bench added	2017-10-10 01:35:18 +02:00
freitz85	c03bc37834	Test bench	2017-10-10 00:41:31 +02:00
freitz85	caa40196d7	Removed BUFG constraint warnings	2017-10-09 23:35:52 +02:00
freitz85	b888590d11	Top level in VHDL	2017-10-09 22:35:47 +02:00
freitz85	84cfbdde92	test with clocked input buffers	2017-10-08 21:48:07 +02:00
Florian Reitz	d0a9254893	several fixes tried	2017-10-05 22:57:38 +02:00
freitz85	9c3b1c33ff	Reset inited on card remove	2017-09-10 14:07:23 +02:00
freitz85	04e26f32da	Update to ISE 14.7	2017-09-10 13:41:13 +02:00
Florian Reitz	2a06e1ba5d	Support for second partition, card detect and write protect added	2017-09-09 20:34:24 +02:00
freitz85	7425ad32fc	formatting	2017-09-03 14:51:09 +02:00
freitz85	63313fd7fa	inited flag is removed when card is ejected	2017-08-31 01:07:34 +02:00
freitz85	19632c05dc	inited signal added to cpld	2017-08-27 12:21:26 +02:00
freitz85	596e7c3f1f	Pin changes	2017-07-09 13:28:18 +02:00
freitz85	21acf3ac24	signal rename and pinning	2017-07-05 23:28:27 +02:00
freitz85	162ce22536	Address decoding corrected	2017-07-05 22:13:41 +02:00
freitz85	c4d43389c4	File rename	2017-07-05 19:41:29 +02:00
freitz85	cb9891374f	removed unnecessary Xilinx files	2017-07-05 19:32:25 +02:00
freitz85	ef10d991fe	Merge branch 'master' of https://github.com/freitz85/AppleIISd ... # Conflicts: # _ngo/netlist.lst # spi6502b.bld # spi6502b.ngc # spi6502b.ngd # spi6502b.ngr # spi6502b.prj # spi6502b.syr # spi6502b_pad.csv	2017-07-05 19:23:46 +02:00
freitz85	30a026b18a	folder structure added	2017-07-05 19:08:54 +02:00