mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-06-12 18:42:14 +00:00
verilog: test updates, source locations, labels, Silice
This commit is contained in:
parent
e703c16dfe
commit
b9a0de6cac
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@ -99,16 +99,21 @@ TODO:
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- verilog debugging/reloading makes it slow
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- why loadState() on verilog kill perf?
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- quantify verilog "graph iterations"
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- toolbar overlaps scope
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- CPU debugging
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- use $readmem for inline asm programs?
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- can't add control instructions b/c of split
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- bad error msg if >2 moduels and top module doesn't match filename
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- separate Scope View
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- Audio doesn't work if clock != default
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- change the input values for a module?
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- Silice rototexture.ice example bitmap corrupted?
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- scope: zoom in on cursor
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- Verilog WASM not yet supported:
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- wide numbers > 64 bits (and in scope view)
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- multiple modules instances
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- structs
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- other $funcs
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- multidim arrays
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- optimize trace log w/ wasm buffer
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- yosys compatibility
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- single-stepping vector games makes screen fade
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- break on stack overflow, illegal op, bad access, BRK, etc
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- show in scope instead?
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74
package-lock.json
generated
74
package-lock.json
generated
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@ -27,6 +27,7 @@
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"btoa": "^1.2.x",
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"chromedriver": "^90.0.1",
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"clipboard": "^2.0.6",
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"command-exists": "^1.2.9",
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"electron": "^9.4.0",
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"electron-packager": "^15.2.0",
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"file-saver": "^2.0.5",
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@ -37,6 +38,7 @@
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"localforage": "^1.9.0",
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"lzg": "^1.0.x",
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"mocha": "^7.2.0",
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"mocha-simple-html-reporter": "^2.0.0",
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"mousetrap": "^1.6.5",
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"nightwatch": "^1.6.4",
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"octokat": "^0.10.0",
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@ -1246,6 +1248,12 @@
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"node": ">= 0.8"
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}
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},
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"node_modules/command-exists": {
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"version": "1.2.9",
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"resolved": "https://registry.npmjs.org/command-exists/-/command-exists-1.2.9.tgz",
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"integrity": "sha512-LTQ/SGc+s0Xc0Fu5WaKnR0YiygZkm9eKFvyS+fRsU7/ZWFF8ykFM6Pc9aCVf1+xasOOZpO3BAVgVrKvsqKHV7w==",
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"dev": true
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},
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"node_modules/commander": {
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"version": "5.1.0",
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"resolved": "https://registry.npmjs.org/commander/-/commander-5.1.0.tgz",
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@ -4566,6 +4574,18 @@
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"url": "https://opencollective.com/mochajs"
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}
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},
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"node_modules/mocha-simple-html-reporter": {
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"version": "2.0.0",
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"resolved": "https://registry.npmjs.org/mocha-simple-html-reporter/-/mocha-simple-html-reporter-2.0.0.tgz",
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"integrity": "sha512-adaJlWWDoAT1OMjsjo6uOOOaMwmGf8ZQEXVoUdlD34Xjgz4M50FW7fe9ksl6UFLoisSB9Ai49LzRh6LuId1+cA==",
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"dev": true,
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"dependencies": {
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"pretty-ms": "7.0.1"
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},
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"engines": {
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"node": ">= 10.12.0"
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}
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},
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"node_modules/mocha/node_modules/ansi-regex": {
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"version": "4.1.0",
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"resolved": "https://registry.npmjs.org/ansi-regex/-/ansi-regex-4.1.0.tgz",
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@ -5705,6 +5725,15 @@
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"node": ">=0.10.0"
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}
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},
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"node_modules/parse-ms": {
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"version": "2.1.0",
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"resolved": "https://registry.npmjs.org/parse-ms/-/parse-ms-2.1.0.tgz",
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"integrity": "sha512-kHt7kzLoS9VBZfUsiKjv43mr91ea+U05EyKkEtqp7vNbHxmaVuEqN7XxeEVnGrMtYOAxGrDElSi96K7EgO1zCA==",
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"dev": true,
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"engines": {
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"node": ">=6"
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}
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},
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"node_modules/parse5": {
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"version": "5.1.0",
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"resolved": "https://registry.npmjs.org/parse5/-/parse5-5.1.0.tgz",
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@ -5886,6 +5915,21 @@
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"node": ">=4"
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}
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},
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"node_modules/pretty-ms": {
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"version": "7.0.1",
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"resolved": "https://registry.npmjs.org/pretty-ms/-/pretty-ms-7.0.1.tgz",
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"integrity": "sha512-973driJZvxiGOQ5ONsFhOF/DtzPMOMtgC11kCpUrPGMTgqp2q/1gwzCquocrN33is0VZ5GFHXZYMM9l6h67v2Q==",
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"dev": true,
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"dependencies": {
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"parse-ms": "^2.1.0"
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},
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"engines": {
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"node": ">=10"
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},
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"funding": {
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"url": "https://github.com/sponsors/sindresorhus"
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}
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},
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"node_modules/process-nextick-args": {
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"version": "2.0.1",
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"resolved": "https://registry.npmjs.org/process-nextick-args/-/process-nextick-args-2.0.1.tgz",
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@ -8644,6 +8688,12 @@
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"delayed-stream": "~1.0.0"
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}
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},
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"command-exists": {
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"version": "1.2.9",
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"resolved": "https://registry.npmjs.org/command-exists/-/command-exists-1.2.9.tgz",
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"integrity": "sha512-LTQ/SGc+s0Xc0Fu5WaKnR0YiygZkm9eKFvyS+fRsU7/ZWFF8ykFM6Pc9aCVf1+xasOOZpO3BAVgVrKvsqKHV7w==",
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"dev": true
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},
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"commander": {
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"version": "5.1.0",
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"resolved": "https://registry.npmjs.org/commander/-/commander-5.1.0.tgz",
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@ -11409,6 +11459,15 @@
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}
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}
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},
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"mocha-simple-html-reporter": {
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"version": "2.0.0",
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"resolved": "https://registry.npmjs.org/mocha-simple-html-reporter/-/mocha-simple-html-reporter-2.0.0.tgz",
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"integrity": "sha512-adaJlWWDoAT1OMjsjo6uOOOaMwmGf8ZQEXVoUdlD34Xjgz4M50FW7fe9ksl6UFLoisSB9Ai49LzRh6LuId1+cA==",
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"dev": true,
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"requires": {
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"pretty-ms": "7.0.1"
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}
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},
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"mousetrap": {
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"version": "1.6.5",
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"resolved": "https://registry.npmjs.org/mousetrap/-/mousetrap-1.6.5.tgz",
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@ -12193,6 +12252,12 @@
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"error-ex": "^1.2.0"
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}
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},
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"parse-ms": {
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"version": "2.1.0",
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"resolved": "https://registry.npmjs.org/parse-ms/-/parse-ms-2.1.0.tgz",
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"integrity": "sha512-kHt7kzLoS9VBZfUsiKjv43mr91ea+U05EyKkEtqp7vNbHxmaVuEqN7XxeEVnGrMtYOAxGrDElSi96K7EgO1zCA==",
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"dev": true
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},
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"parse5": {
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"version": "5.1.0",
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"resolved": "https://registry.npmjs.org/parse5/-/parse5-5.1.0.tgz",
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@ -12320,6 +12385,15 @@
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"integrity": "sha1-6SQ0v6XqjBn0HN/UAddBo8gZ2Jc=",
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"dev": true
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},
|
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"pretty-ms": {
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"version": "7.0.1",
|
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"resolved": "https://registry.npmjs.org/pretty-ms/-/pretty-ms-7.0.1.tgz",
|
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"integrity": "sha512-973driJZvxiGOQ5ONsFhOF/DtzPMOMtgC11kCpUrPGMTgqp2q/1gwzCquocrN33is0VZ5GFHXZYMM9l6h67v2Q==",
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"dev": true,
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"requires": {
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"parse-ms": "^2.1.0"
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}
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},
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"process-nextick-args": {
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"version": "2.0.1",
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"resolved": "https://registry.npmjs.org/process-nextick-args/-/process-nextick-args-2.0.1.tgz",
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|
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@ -28,6 +28,7 @@
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"btoa": "^1.2.x",
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"chromedriver": "^90.0.1",
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"clipboard": "^2.0.6",
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"command-exists": "^1.2.9",
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"electron": "^9.4.0",
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"electron-packager": "^15.2.0",
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"file-saver": "^2.0.5",
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|
@ -38,6 +39,7 @@
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"localforage": "^1.9.0",
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"lzg": "^1.0.x",
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"mocha": "^7.2.0",
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"mocha-simple-html-reporter": "^2.0.0",
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"mousetrap": "^1.6.5",
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"nightwatch": "^1.6.4",
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"octokat": "^0.10.0",
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@ -58,9 +60,10 @@
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"test": "npm run test-node",
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"test-one": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000",
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"test-node": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000 test/cli",
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"test-worker": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000 test/cli/testworker.js",
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"test-platforms": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000 test/cli/testplatforms.js",
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"test-profile": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000 --prof test/cli",
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"test-worker": "NODE_PATH=$(pwd) mocha --timeout 60000 test/cli/testworker.js",
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"test-platforms": "NODE_PATH=$(pwd) mocha --timeout 60000 test/cli/testplatforms.js",
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"test-verilog": "NODE_PATH=$(pwd) mocha --timeout 60000 --reporter mocha-simple-html-reporter --reporter-options output=test/output/verilog.html test/cli/testverilog.js",
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"test-web": "nightwatch -e chrome test/web",
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"start": "electron .",
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"fuzzbasic": "jsfuzz gen/common/basic/fuzz.js ~/basic/corpus/ --versifier false",
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@ -355,7 +355,7 @@ always @*
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*/
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always @(posedge clk)
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if( RDY )
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PC <= PC_temp + 16'(PC_inc);
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PC <= PC_temp + {15'b0, PC_inc};
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/*
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* Address Generator
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@ -1315,8 +1315,8 @@ wire temp_HC = temp_l[4] | HC9;
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// perform the addition as 2 separate nibble, so we get
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// access to the half carry flag
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always @* begin
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temp_l = temp_logic[3:0] + temp_BI[3:0] + 5'(adder_CI);
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temp_h = temp_logic[8:4] + temp_BI[7:4] + 5'(temp_HC);
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temp_l = temp_logic[3:0] + temp_BI[3:0] + {4'b0,adder_CI};
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temp_h = temp_logic[8:4] + temp_BI[7:4] + {4'b0,temp_HC};
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end
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// calculate the flags
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@ -1339,7 +1339,7 @@ endmodule
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module cpu6502_test_top(clk, reset, AB, DI, DO, WE);
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input clk,reset;
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output reg [15:0] AB; // address bus
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output var [7:0] DI; // data in, read bus
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output reg [7:0] DI; // data in, read bus
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output wire [7:0] DO; // data out, write bus
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output wire WE; // write enable
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wire IRQ=0; // interrupt request
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@ -1359,13 +1359,12 @@ wire RDY=1; // Ready signal. Pauses CPU when RDY=0
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// BNE .loop
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// BRK
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initial begin
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rom = '{
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8'ha0,8'h13,
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8'h88,
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8'hd0,8'hfd,
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0,0,0, 0,0,
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0,0, 0,0, 0,0
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};
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rom[0] = 8'ha0;
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rom[1] = 8'h13;
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rom[2] = 8'h88;
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rom[3] = 8'hd0;
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rom[4] = 8'hfd;
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rom[5] = 8'h00;
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end
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endmodule
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@ -9,12 +9,9 @@ module font_cp437_8x8(addr, data);
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input [10:0] addr;
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output [7:0] data;
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reg [7:0] bitarray[0:2047];
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assign data = bitarray[addr];
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initial begin/*{w:8,h:8,bpp:1,count:256}*/
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bitarray = '{
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localparam [7:0] bitarray[0:2047] = '{
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8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00, //0
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8'h7e,8'h81,8'ha5,8'h81,8'hbd,8'h99,8'h81,8'h7e, //1
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8'h7e,8'hff,8'hdb,8'hff,8'hc3,8'he7,8'hff,8'h7e, //2
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@ -272,7 +269,7 @@ module font_cp437_8x8(addr, data);
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8'h00,8'h00,8'h3c,8'h3c,8'h3c,8'h3c,8'h00,8'h00, //254
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8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00 //255
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};
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end
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endmodule
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`endif
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@ -1,4 +1,5 @@
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import { EmuHalt } from "../emu";
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import { byteArrayToString, safe_extend } from "../util";
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import { HDLBinop, HDLBlock, HDLConstant, HDLDataType, HDLExpr, HDLExtendop, HDLFuncCall, HDLModuleDef, HDLModuleRunner, HDLSourceLocation, HDLTriop, HDLUnop, HDLValue, HDLVariableDef, HDLVarRef, isArrayItem, isArrayType, isBigConstExpr, isBinop, isBlock, isConstExpr, isFuncCall, isLogicType, isTriop, isUnop, isVarDecl, isVarRef, isWhileop } from "./hdltypes";
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@ -10,14 +11,12 @@ interface VerilatorUnit {
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_change_request(state) : boolean;
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}
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export class HDLError extends Error {
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export class HDLError extends EmuHalt {
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obj: any;
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$loc: HDLSourceLocation;
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constructor(obj: any, msg: string) {
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super(msg);
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super(msg, obj ? obj.$loc : null);
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Object.setPrototypeOf(this, HDLError.prototype);
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this.obj = obj;
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if (obj && obj.$loc) this.$loc = obj.$loc;
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if (obj) console.log(obj);
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}
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}
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@ -1,3 +1,4 @@
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import { SourceLocation } from "../workertypes";
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export interface HDLModuleRunner {
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state: any; // live state or proxy object
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@ -54,12 +55,9 @@ export class HDLFile {
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isModule: boolean;
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}
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export interface HDLSourceLocation {
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file: HDLFile;
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line: number;
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col?: number;
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export interface HDLSourceLocation extends SourceLocation {
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hdlfile: HDLFile;
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end_line?: number;
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end_col?: number;
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}
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export interface HDLSourceObject {
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@ -1,6 +1,6 @@
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import binaryen = require('binaryen');
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import { hasDataType, HDLBinop, HDLBlock, HDLConstant, HDLDataType, HDLDataTypeObject, HDLExpr, HDLExtendop, HDLFuncCall, HDLModuleDef, HDLModuleRunner, HDLSourceLocation, HDLTriop, HDLUnop, HDLValue, HDLVariableDef, HDLVarRef, HDLWhileOp, isArrayItem, isArrayType, isBigConstExpr, isBinop, isBlock, isConstExpr, isFuncCall, isLogicType, isTriop, isUnop, isVarDecl, isVarRef, isWhileop } from "./hdltypes";
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import { hasDataType, HDLBinop, HDLBlock, HDLConstant, HDLDataType, HDLDataTypeObject, HDLExpr, HDLExtendop, HDLFuncCall, HDLModuleDef, HDLModuleRunner, HDLSourceLocation, HDLSourceObject, HDLTriop, HDLUnop, HDLValue, HDLVariableDef, HDLVarRef, HDLWhileOp, isArrayItem, isArrayType, isBigConstExpr, isBinop, isBlock, isConstExpr, isFuncCall, isLogicType, isTriop, isUnop, isVarDecl, isVarRef, isWhileop } from "./hdltypes";
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import { HDLError } from "./hdlruntime";
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const VERILATOR_UNIT_FUNCTIONS = [
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@ -14,6 +14,7 @@ const VERILATOR_UNIT_FUNCTIONS = [
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interface Options {
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store?: boolean;
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funcblock?: HDLBlock;
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funcarg?: boolean;
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resulttype?: number;
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}
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@ -64,7 +65,7 @@ function getArrayElementSizeFromExpr(e: HDLExpr) : number {
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if (hasDataType(e) && isArrayType(e.dtype)) {
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return getDataTypeSize(e.dtype.subtype);
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} else if (hasDataType(e) && isLogicType(e.dtype) && e.dtype.left > 63) {
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return 4; // TODO? for wordsel
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throw new HDLError(e, `elements > 64 bits not supported`);
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}
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throw new HDLError(e, `cannot figure out array element size`);
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}
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@ -78,7 +79,7 @@ function getArrayValueSize(e: HDLExpr) : number {
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} else if (isBinop(e) && e.op == 'arraysel') {
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return getArrayValueSize(e.left);
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} else if (isBinop(e) && e.op == 'wordsel') {
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return 4; // TODO? for wordsel
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return getArrayValueSize(e.left);
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}
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throw new HDLError(e, `cannot figure out array value size`);
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}
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@ -91,7 +92,9 @@ function getAlignmentForSize(size) {
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}
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function getBinaryenType(size: number) {
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return size <= 4 || size > 8 ? binaryen.i32 : binaryen.i64
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if (size <= 4) return binaryen.i32;
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else if (size <= 8) return binaryen.i64;
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else return binaryen.none;
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}
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interface StructRec {
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@ -480,7 +483,7 @@ export class HDLModuleWASM implements HDLModuleRunner {
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if (isArrayItem(e) && isConstExpr(e.expr)) {
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arr[e.index] = e.expr.cvalue;
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} else {
|
||||
throw new HDLError(e, `non-const expr in initarray`);
|
||||
throw new HDLError(e, `non-const expr in initarray (multidimensional arrays not supported)`);
|
||||
}
|
||||
}
|
||||
//console.log(rec.name, rec.type, arr);
|
||||
|
@ -509,8 +512,8 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
var n = 0;
|
||||
return {
|
||||
builtins: {
|
||||
$finish: (o) => { console.log('... Finished @', o); this.finished = true; },
|
||||
$stop: (o) => { console.log('... Stopped @', o); this.stopped = true; },
|
||||
$finish: (o) => { if (!this.finished) console.log('... Finished @', o); this.finished = true; },
|
||||
$stop: (o) => { if (!this.stopped) console.log('... Stopped @', o); this.stopped = true; },
|
||||
$time: (o) => BigInt(new Date().getTime()), // TODO: timescale
|
||||
$rand: (o) => (Math.random() * (65536 * 65536)) | 0,
|
||||
$readmem: (o,a,b) => this.$readmem(a, b)
|
||||
|
@ -536,6 +539,12 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
return 0;
|
||||
}
|
||||
|
||||
// create a new unique label
|
||||
labelseq = 0;
|
||||
private label(s?: string) : string {
|
||||
return `@${s||"label"}_${++this.labelseq}`;
|
||||
}
|
||||
|
||||
private addCopyTraceRecFunction() {
|
||||
const m = this.bmod;
|
||||
const o_TRACERECLEN = this.globals.lookup(TRACERECLEN).offset;
|
||||
|
@ -544,11 +553,13 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
const o_TRACEBUF = this.globals.lookup(TRACEBUF).offset;
|
||||
var i32 = binaryen.i32;
|
||||
var none = binaryen.none;
|
||||
var l_block = this.label("@block");
|
||||
var l_loop = this.label("@loop");
|
||||
m.addFunction("copyTraceRec",
|
||||
binaryen.createType([]),
|
||||
none,
|
||||
[i32, i32, i32], // src, len, dest
|
||||
m.block("@block", [
|
||||
m.block(l_block, [
|
||||
// $0 = 0 (start of globals)
|
||||
m.local.set(0, m.i32.const(GLOBALOFS)),
|
||||
// don't use $0 as data seg offset, assume trace buffer offsets start @ 0
|
||||
|
@ -557,12 +568,12 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
// $2 = TRACEOFS
|
||||
m.local.set(2, m.i32.load(0, 4, m.i32.const(o_TRACEOFS))),
|
||||
// while ($1--) [$0]++ = [$2]++
|
||||
m.loop("@loop", m.block(null, [
|
||||
m.loop(l_loop, m.block(null, [
|
||||
m.i64.store(0, 8, m.local.get(2, i32), m.i64.load(0, 8, m.local.get(0, i32))),
|
||||
m.local.set(0, m.i32.add(m.local.get(0, i32), m.i32.const(8))),
|
||||
m.local.set(2, m.i32.add(m.local.get(2, i32), m.i32.const(8))),
|
||||
m.local.set(1, m.i32.sub(m.local.get(1, i32), m.i32.const(8))),
|
||||
this.bmod.br_if("@loop", m.local.get(1, i32))
|
||||
this.bmod.br_if(l_loop, m.local.get(1, i32))
|
||||
])),
|
||||
// TRACEOFS += TRACERECLEN
|
||||
m.i32.store(0, 4, m.i32.const(o_TRACEOFS),
|
||||
|
@ -572,7 +583,7 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
)
|
||||
),
|
||||
// break if TRACEOFS < TRACEEND
|
||||
m.br_if("@block", m.i32.lt_u(
|
||||
m.br_if(l_block, m.i32.lt_u(
|
||||
m.i32.load(0, 4, m.i32.const(o_TRACEOFS)),
|
||||
m.i32.load(0, 4, m.i32.const(o_TRACEEND))
|
||||
)),
|
||||
|
@ -584,6 +595,7 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
|
||||
private addTick2Function() {
|
||||
const m = this.bmod;
|
||||
var l_loop = this.label("@loop");
|
||||
if (this.globals.lookup('clk')) {
|
||||
var l_dseg = m.local.get(0, binaryen.i32);
|
||||
var l_count = m.local.get(1, binaryen.i32);
|
||||
|
@ -591,7 +603,7 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
binaryen.createType([binaryen.i32, binaryen.i32]),
|
||||
binaryen.none,
|
||||
[],
|
||||
m.loop("@loop", m.block(null, [
|
||||
m.loop(l_loop, m.block(null, [
|
||||
this.makeSetVariableFunction("clk", 0),
|
||||
m.drop(m.call("eval", [l_dseg], binaryen.i32)),
|
||||
this.makeSetVariableFunction("clk", 1),
|
||||
|
@ -601,7 +613,7 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
// dec $1
|
||||
m.local.set(1, m.i32.sub(l_count, m.i32.const(1))),
|
||||
// goto @loop if $1
|
||||
m.br_if("@loop", l_count)
|
||||
m.br_if(l_loop, l_count)
|
||||
]))
|
||||
);
|
||||
m.addFunctionExport("tick2", "tick2");
|
||||
|
@ -669,7 +681,7 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
var type = getBinaryenType(size);
|
||||
if (type == binaryen.i32) return this.bmod.i32;
|
||||
else if (type == binaryen.i64) return this.bmod.i64;
|
||||
else throw new HDLError(null, `unknown type for i3264 ${type}`);
|
||||
else throw new HDLError(dt, `data types > 64 bits not supported`);
|
||||
}
|
||||
|
||||
private i3264rel(e: HDLBinop) {
|
||||
|
@ -726,7 +738,7 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
funccall2wasm(e: HDLFuncCall, opts?:Options) : number {
|
||||
var args = [this.dataptr()];
|
||||
for (var arg of e.args) {
|
||||
args.push(this.e2w(arg));
|
||||
args.push(this.e2w(arg, {funcarg:true}));
|
||||
}
|
||||
var internal = e.funcname;
|
||||
if (e.funcname.startsWith('$')) {
|
||||
|
@ -764,10 +776,10 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
if (local != null) {
|
||||
return this.bmod.local.get(local.index, local.itype);
|
||||
} else if (global != null) {
|
||||
if (global.size <= 8)
|
||||
return this.loadmem(this.dataptr(), global.offset, global.size);
|
||||
if (global.size > 8 && opts && opts.funcarg)
|
||||
return this.address2wasm(e); // TODO: only applies to wordsel
|
||||
else
|
||||
return this.address2wasm(e);
|
||||
return this.loadmem(e, this.dataptr(), global.offset, global.size);
|
||||
}
|
||||
throw new HDLError(e, `cannot lookup variable ${e.refname}`)
|
||||
}
|
||||
|
@ -786,18 +798,17 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
if (local != null) {
|
||||
return this.bmod.local.set(local.index, value);
|
||||
} else if (global != null) {
|
||||
return this.storemem(this.dataptr(), global.offset, global.size, value);
|
||||
return this.storemem(dest, this.dataptr(), global.offset, global.size, value);
|
||||
}
|
||||
} else if (isBinop(dest)) {
|
||||
// TODO: array bounds
|
||||
var addr = this.address2wasm(dest);
|
||||
var elsize = getArrayElementSizeFromExpr(dest.left);
|
||||
return this.storemem(addr, 0, elsize, value);
|
||||
var elsize = dest.op == 'wordsel' ? getDataTypeSize(dest.dtype) : getArrayElementSizeFromExpr(dest.left);
|
||||
return this.storemem(dest, addr, 0, elsize, value);
|
||||
}
|
||||
throw new HDLError([dest, src], `cannot complete assignment`);
|
||||
throw new HDLError(dest, `cannot complete assignment`);
|
||||
}
|
||||
|
||||
loadmem(ptr, offset:number, size:number) : number {
|
||||
loadmem(e: HDLSourceObject, ptr, offset:number, size:number) : number {
|
||||
if (size == 1) {
|
||||
return this.bmod.i32.load8_u(offset, 1, ptr);
|
||||
} else if (size == 2) {
|
||||
|
@ -807,11 +818,11 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
} else if (size == 8) {
|
||||
return this.bmod.i64.load(offset, 8, ptr);
|
||||
} else {
|
||||
throw new HDLError(null, `bad size ${size}`)
|
||||
throw new HDLError(e, `cannot load ${size} bytes (> 64 bits not supported)`)
|
||||
}
|
||||
}
|
||||
|
||||
storemem(ptr, offset:number, size:number, value) : number {
|
||||
storemem(e: HDLSourceObject, ptr, offset:number, size:number, value) : number {
|
||||
if (size == 1) {
|
||||
return this.bmod.i32.store8(offset, 1, ptr, value);
|
||||
} else if (size == 2) {
|
||||
|
@ -821,14 +832,14 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
} else if (size == 8) {
|
||||
return this.bmod.i64.store(offset, 8, ptr, value);
|
||||
} else {
|
||||
throw new HDLError(null, `bad size ${size}`)
|
||||
throw new HDLError(e, `cannot store ${size} bytes (> 64 bits not supported)`)
|
||||
}
|
||||
}
|
||||
|
||||
address2wasm(e: HDLExpr) : number {
|
||||
if (isBinop(e) && (e.op == 'arraysel' || e.op == 'wordsel')) {
|
||||
var elsize = e.op == 'wordsel' ? getDataTypeSize(e.dtype) : getArrayElementSizeFromExpr(e.left);
|
||||
var array = this.address2wasm(e.left);
|
||||
var elsize = getArrayElementSizeFromExpr(e.left);
|
||||
var index = this.e2w(e.right);
|
||||
return this.bmod.i32.add(
|
||||
array,
|
||||
|
@ -850,7 +861,7 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
_arraysel2wasm(e: HDLBinop, opts:Options) : number {
|
||||
var addr = this.address2wasm(e);
|
||||
var elsize = getArrayValueSize(e);
|
||||
return this.loadmem(addr, 0, elsize);
|
||||
return this.loadmem(e, addr, 0, elsize);
|
||||
}
|
||||
|
||||
_wordsel2wasm(e: HDLBinop, opts:Options) : number {
|
||||
|
@ -884,15 +895,18 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
}
|
||||
|
||||
_while2wasm(e: HDLWhileOp, opts:Options) {
|
||||
var l_block = this.label("@block");
|
||||
var l_loop = this.label("@loop");
|
||||
var block = [];
|
||||
if (e.precond) {
|
||||
block.push(this.e2w(e.precond));
|
||||
}
|
||||
if (e.loopcond) {
|
||||
// TODO: detect constant while loop condition
|
||||
block.push(this.bmod.if(
|
||||
this.e2w(e.loopcond, {resulttype:binaryen.i32}),
|
||||
this.bmod.nop(),
|
||||
this.bmod.br("@block") // exit loop
|
||||
this.bmod.br(l_block) // exit loop
|
||||
));
|
||||
}
|
||||
if (e.body) {
|
||||
|
@ -901,8 +915,8 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
if (e.inc) {
|
||||
block.push(this.e2w(e.inc));
|
||||
}
|
||||
block.push(this.bmod.br("@loop"));
|
||||
return this.bmod.loop("@loop", this.bmod.block("@block", block, binaryen.none));
|
||||
block.push(this.bmod.br(l_loop));
|
||||
return this.bmod.loop(l_loop, this.bmod.block(l_block, block, binaryen.none));
|
||||
}
|
||||
|
||||
_ccast2wasm(e: HDLUnop, opts:Options) {
|
||||
|
@ -953,13 +967,13 @@ export class HDLModuleWASM implements HDLModuleRunner {
|
|||
if (!req) throw new HDLError(e, `no changedet local`);
|
||||
var left = this.e2w(e.left);
|
||||
var right = this.e2w(e.right);
|
||||
let datainst = this.i3264(hasDataType(e.left) && e.left.dtype);
|
||||
return this.bmod.block(null, [
|
||||
// $$req |= (${this.expr2js(e.left)} ^ ${this.expr2js(e.right)})
|
||||
this.bmod.local.set(req.index,
|
||||
this.bmod.i32.or(
|
||||
this.bmod.local.get(req.index, req.itype),
|
||||
this.bmod.i32.xor(left, right) // TODO: i64?
|
||||
)
|
||||
// if (left != right) req = 1;
|
||||
this.bmod.if(
|
||||
datainst.ne(left, right),
|
||||
this.bmod.local.set(req.index, this.bmod.i32.const(1)),
|
||||
this.bmod.nop(),
|
||||
),
|
||||
// ${this.expr2js(e.right)} = ${this.expr2js(e.left)}`
|
||||
this.assign2wasm(e.right, e.left)
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
import { HDLError } from "./hdlruntime";
|
||||
import { HDLAlwaysBlock, HDLArrayItem, HDLBinop, HDLBlock, HDLConstant, HDLDataType, HDLDataTypeObject, HDLExpr, HDLExtendop, HDLFile, HDLFuncCall, HDLHierarchyDef, HDLInstanceDef, HDLLogicType, HDLModuleDef, HDLNativeType, HDLPort, HDLSensItem, HDLSourceLocation, HDLTriop, HDLUnit, HDLUnop, HDLUnpackArray, HDLValue, HDLVariableDef, HDLVarRef, HDLWhileOp, isArrayType, isBinop, isBlock, isConstExpr, isFuncCall, isLogicType, isTriop, isUnop, isVarDecl, isVarRef } from "./hdltypes";
|
||||
import { HDLAlwaysBlock, HDLArrayItem, HDLBinop, HDLBlock, HDLConstant, HDLDataType, HDLDataTypeObject, HDLExpr, HDLExtendop, HDLFile, HDLFuncCall, HDLHierarchyDef, HDLInstanceDef, HDLLogicType, HDLModuleDef, HDLNativeType, HDLPort, HDLSensItem, HDLSourceLocation, HDLSourceObject, HDLTriop, HDLUnit, HDLUnop, HDLUnpackArray, HDLValue, HDLVariableDef, HDLVarRef, HDLWhileOp, isArrayType, isBinop, isBlock, isConstExpr, isFuncCall, isLogicType, isTriop, isUnop, isVarDecl, isVarRef } from "./hdltypes";
|
||||
|
||||
/**
|
||||
* Whaa?
|
||||
|
@ -17,10 +17,11 @@ import { HDLAlwaysBlock, HDLArrayItem, HDLBinop, HDLBlock, HDLConstant, HDLDataT
|
|||
* https://developer.mozilla.org/en-US/docs/Web/JavaScript/Reference/Global_Objects/SharedArrayBuffer
|
||||
*/
|
||||
|
||||
export class CompileError extends Error {
|
||||
constructor(obj: HDLSourceLocation|XMLNode, msg: string) {
|
||||
export class CompileError extends Error implements HDLSourceObject {
|
||||
$loc: HDLSourceLocation;
|
||||
constructor($loc: HDLSourceLocation, msg: string) {
|
||||
super(msg);
|
||||
console.log(obj);
|
||||
this.$loc = $loc;
|
||||
Object.setPrototypeOf(this, CompileError.prototype);
|
||||
}
|
||||
}
|
||||
|
@ -56,7 +57,7 @@ function parseXMLPoorly(s: string, openfn?: XMLVisitFunction, closefn?: XMLVisit
|
|||
|
||||
function closetop() {
|
||||
top = stack.pop();
|
||||
if (top == null || top.type != ident) throw new CompileError(node, "mismatch close tag: " + ident);
|
||||
if (top == null || top.type != ident) throw new CompileError(null, "mismatch close tag: " + ident);
|
||||
if (closefn) {
|
||||
top.obj = closefn(top);
|
||||
}
|
||||
|
@ -108,6 +109,7 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
|
||||
cur_node : XMLNode;
|
||||
cur_module : HDLModuleDef;
|
||||
cur_loc : HDLSourceLocation;
|
||||
cur_deferred = [];
|
||||
|
||||
constructor() {
|
||||
|
@ -138,13 +140,13 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
}
|
||||
|
||||
name2js(s: string) {
|
||||
if (s == null) throw new CompileError(null, `no name`);
|
||||
if (s == null) throw new CompileError(this.cur_loc, `no name`);
|
||||
return s.replace(/[^a-z0-9_]/gi, '$');
|
||||
}
|
||||
|
||||
findChildren(node: XMLNode, type: string, required: boolean) : XMLNode[] {
|
||||
var arr = node.children.filter((n) => n.type == type);
|
||||
if (arr.length == 0 && required) throw new CompileError(node, `no child of type ${type}`);
|
||||
if (arr.length == 0 && required) throw new CompileError(this.cur_loc, `no child of type ${type}`);
|
||||
return arr;
|
||||
}
|
||||
|
||||
|
@ -152,13 +154,16 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
var loc = node.attrs['loc'];
|
||||
if (loc) {
|
||||
var [fileid, line, col, end_line, end_col] = loc.split(',');
|
||||
return {
|
||||
file: this.files[fileid],
|
||||
var $loc = {
|
||||
hdlfile: this.files[fileid],
|
||||
path: this.files[fileid].filename,
|
||||
line: parseInt(line),
|
||||
col: parseInt(col),
|
||||
end_line: parseInt(line),
|
||||
end_col: parseInt(col),
|
||||
start: parseInt(col)-1,
|
||||
end_line: parseInt(end_line),
|
||||
end: parseInt(end_col)-1,
|
||||
}
|
||||
this.cur_loc = $loc;
|
||||
return $loc;
|
||||
} else {
|
||||
return null;
|
||||
}
|
||||
|
@ -173,7 +178,7 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
instances: [],
|
||||
vardefs: {},
|
||||
}
|
||||
if (this.cur_module) throw new CompileError(node, `nested modules not supported`);
|
||||
if (this.cur_module) throw new CompileError(this.cur_loc, `nested modules not supported`);
|
||||
this.cur_module = module;
|
||||
return module;
|
||||
}
|
||||
|
@ -184,7 +189,7 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
this.defer(() => {
|
||||
def.dtype = this.dtypes[dtype_id];
|
||||
if (!def.dtype) {
|
||||
throw new CompileError(node, `Unknown data type ${dtype_id} for ${node.type}`);
|
||||
throw new CompileError(this.cur_loc, `Unknown data type ${dtype_id} for ${node.type}`);
|
||||
}
|
||||
})
|
||||
}
|
||||
|
@ -200,19 +205,19 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
else
|
||||
return BigInt('0x' + numstr);
|
||||
} else {
|
||||
throw new CompileError(null, `could not parse constant "${s}"`);
|
||||
throw new CompileError(this.cur_loc, `could not parse constant "${s}"`);
|
||||
}
|
||||
}
|
||||
|
||||
resolveVar(s: string, mod: HDLModuleDef) : HDLVariableDef {
|
||||
var def = mod.vardefs[s];
|
||||
if (def == null) throw new CompileError(null, `could not resolve variable "${s}"`);
|
||||
if (def == null) throw new CompileError(this.cur_loc, `could not resolve variable "${s}"`);
|
||||
return def;
|
||||
}
|
||||
|
||||
resolveModule(s: string) : HDLModuleDef {
|
||||
var mod = this.modules[s];
|
||||
if (mod == null) throw new CompileError(null, `could not resolve module "${s}"`);
|
||||
if (mod == null) throw new CompileError(this.cur_loc, `could not resolve module "${s}"`);
|
||||
return mod;
|
||||
}
|
||||
|
||||
|
@ -372,6 +377,14 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
return instance;
|
||||
}
|
||||
|
||||
visit_iface(node: XMLNode) {
|
||||
throw new CompileError(this.cur_loc, `interfaces not supported`);
|
||||
}
|
||||
|
||||
visit_intfref(node: XMLNode) {
|
||||
throw new CompileError(this.cur_loc, `interfaces not supported`);
|
||||
}
|
||||
|
||||
visit_port(node: XMLNode) : HDLPort {
|
||||
this.expectChildren(node, 1, 1);
|
||||
var varref: HDLPort = {
|
||||
|
@ -435,6 +448,8 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
parent: null,
|
||||
children: node.children.map((n) => n.obj),
|
||||
}
|
||||
if (node.children.length > 0)
|
||||
throw new CompileError(this.cur_loc, `multiple non-flattened modules not yet supported`);
|
||||
node.children.forEach((n) => (n.obj as HDLHierarchyDef).parent = hier);
|
||||
this.defer(() => {
|
||||
hier.module = this.resolveModule(node.attrs['submodname']);
|
||||
|
@ -467,18 +482,31 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
default:
|
||||
dtype = this.dtypes[dtypename];
|
||||
if (dtype == null) {
|
||||
throw new CompileError(node, `unknown data type ${dtypename}`);
|
||||
throw new CompileError(this.cur_loc, `unknown data type ${dtypename}`);
|
||||
}
|
||||
}
|
||||
this.dtypes[id] = dtype;
|
||||
return dtype;
|
||||
}
|
||||
|
||||
visit_refdtype(node: XMLNode) {
|
||||
}
|
||||
|
||||
visit_enumdtype(node: XMLNode) {
|
||||
}
|
||||
|
||||
visit_enumitem(node: XMLNode) {
|
||||
}
|
||||
|
||||
visit_packarraydtype(node: XMLNode): HDLDataType {
|
||||
// TODO: packed?
|
||||
return this.visit_unpackarraydtype(node);
|
||||
}
|
||||
|
||||
visit_memberdtype(node: XMLNode) {
|
||||
throw new CompileError(null, `structs not supported`);
|
||||
}
|
||||
|
||||
visit_unpackarraydtype(node: XMLNode): HDLDataType {
|
||||
let id = node.attrs['id'];
|
||||
let sub_dtype_id = node.attrs['sub_dtype_id'];
|
||||
|
@ -493,18 +521,18 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
this.dtypes[id] = dtype;
|
||||
this.defer(() => {
|
||||
dtype.subtype = this.dtypes[sub_dtype_id];
|
||||
if (!dtype.subtype) throw new CompileError(node, `Unknown data type ${sub_dtype_id} for array`);
|
||||
if (!dtype.subtype) throw new CompileError(this.cur_loc, `Unknown data type ${sub_dtype_id} for array`);
|
||||
})
|
||||
return dtype;
|
||||
} else {
|
||||
throw new CompileError(node, `could not parse constant exprs in array`)
|
||||
throw new CompileError(this.cur_loc, `could not parse constant exprs in array`)
|
||||
}
|
||||
}
|
||||
|
||||
visit_senitem(node: XMLNode) : HDLSensItem {
|
||||
var edgeType = node.attrs['edgeType'];
|
||||
if (edgeType != "POS" && edgeType != "NEG")
|
||||
throw new CompileError(node, "POS/NEG required")
|
||||
throw new CompileError(this.cur_loc, "POS/NEG required")
|
||||
return {
|
||||
$loc: this.parseSourceLocation(node),
|
||||
edgeType: edgeType,
|
||||
|
@ -532,7 +560,7 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
|
||||
expectChildren(node: XMLNode, low: number, high: number) {
|
||||
if (node.children.length < low || node.children.length > high)
|
||||
throw new CompileError(node, `expected between ${low} and ${high} children`);
|
||||
throw new CompileError(this.cur_loc, `expected between ${low} and ${high} children`);
|
||||
}
|
||||
|
||||
__visit_unop(node: XMLNode) : HDLUnop {
|
||||
|
@ -551,7 +579,7 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
var unop = this.__visit_unop(node) as HDLExtendop;
|
||||
unop.width = parseInt(node.attrs['width']);
|
||||
unop.widthminv = parseInt(node.attrs['widthminv']);
|
||||
if (unop.width != 32) throw new CompileError(node, `extends width ${unop.width} != 32`)
|
||||
if (unop.width != 32) throw new CompileError(this.cur_loc, `extends width ${unop.width} != 32`)
|
||||
return unop;
|
||||
}
|
||||
|
||||
|
@ -692,6 +720,7 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
|
||||
visit_display(node: XMLNode) { return null; }
|
||||
visit_sformatf(node: XMLNode) { return null; }
|
||||
visit_scopename(node: XMLNode) { return null; }
|
||||
|
||||
visit_readmem(node: XMLNode) { return this.__visit_func(node); }
|
||||
|
||||
|
@ -711,7 +740,7 @@ export class VerilogXMLParser implements HDLUnit {
|
|||
if (method) {
|
||||
return method.bind(this)(node);
|
||||
} else {
|
||||
throw new CompileError(node, `no visitor for ${node.type}`)
|
||||
throw new CompileError(this.cur_loc, `no visitor for ${node.type}`)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -47,6 +47,10 @@ var VERILOG_PRESETS = [
|
|||
{id:'cpu_platform.v', name:'CPU Platform'},
|
||||
{id:'test2.asm', name:'16-bit ASM Game'},
|
||||
{id:'cpu6502.v', name:'6502 CPU'},
|
||||
{id:'test_pattern.ice', name:'Test Pattern (Silice)'},
|
||||
{id:'copperbars.ice', name:'Animated Bars (Silice)'},
|
||||
{id:'rototexture.ice', name:'Rotating Texture (Silice)'},
|
||||
//{id:'life.ice', name:'Conway\'s Life (Silice)'},
|
||||
];
|
||||
|
||||
var VERILOG_KEYCODE_MAP = makeKeycodeMap([
|
||||
|
@ -397,8 +401,8 @@ var VerilogPlatform = function(mainElement, options) {
|
|||
} else if (!framehsync && top.state.hsync) {
|
||||
framehsync = true;
|
||||
} else if ((framehsync && !top.state.hsync) || framex > videoWidth*2) {
|
||||
if (sync && framehsync) scanlineCycles = framex; // set cycles/scanline for fast update function
|
||||
framehsync = false;
|
||||
if (sync) scanlineCycles = framex;
|
||||
framex = 0;
|
||||
framey++;
|
||||
top.state.hpaddle = framey > video.paddle_x ? 1 : 0;
|
||||
|
@ -425,7 +429,7 @@ var VerilogPlatform = function(mainElement, options) {
|
|||
// use trace buffer to update video
|
||||
updateVideoFrameFast(tmod: HDLModuleTrace) {
|
||||
var maxLineCycles = 1009; // prime number so we eventually sync up
|
||||
var nextlineCycles = scanlineCycles;
|
||||
var nextlineCycles = scanlineCycles || maxLineCycles;
|
||||
// TODO: we can go faster if no paddle/sound
|
||||
frameidx = 0;
|
||||
var wasvsync = false;
|
||||
|
@ -460,19 +464,21 @@ var VerilogPlatform = function(mainElement, options) {
|
|||
if (tmod.trace.hsync) {
|
||||
if (!hsyncStart) hsyncStart = n;
|
||||
hsyncEnd = n;
|
||||
} else if (hsyncEnd)
|
||||
} else if (hsyncEnd) {
|
||||
break;
|
||||
}
|
||||
spkr();
|
||||
tmod.nextTrace();
|
||||
n++;
|
||||
}
|
||||
// see if our scanline cycle count is stable (can't read tmod.trace after end of line)
|
||||
if (hsyncStart < hsyncEnd && hsyncEnd == scanlineCycles-1) {
|
||||
if (hsyncStart < hsyncEnd && hsyncEnd == nextlineCycles-1) {
|
||||
// scanline cycle count locked in, reset buffer to improve cache locality
|
||||
nextlineCycles = scanlineCycles;
|
||||
tmod.resetTrace();
|
||||
nextlineCycles = scanlineCycles;
|
||||
} else {
|
||||
// not in sync, don't reset buffer (TODO: take some of the cycles back)
|
||||
// not in sync, don't reset buffer
|
||||
// TODO: determine scanlineCycles here instead of letting slow loop do it
|
||||
//console.log('scanline', framey, scanlineCycles, nextlineCycles, n, hsyncStart, hsyncEnd);
|
||||
nextlineCycles = Math.min(maxLineCycles, n + scanlineCycles);
|
||||
}
|
||||
|
@ -676,6 +682,7 @@ var VerilogPlatform = function(mainElement, options) {
|
|||
getFrameRate() { return frameRate; }
|
||||
|
||||
poweron() {
|
||||
if (!top) return;
|
||||
top.powercycle();
|
||||
this.reset();
|
||||
}
|
||||
|
@ -690,6 +697,7 @@ var VerilogPlatform = function(mainElement, options) {
|
|||
if (!this.hasvideo) this.resume(); // TODO?
|
||||
}
|
||||
tick() {
|
||||
if (!top) return;
|
||||
top.tick2(1);
|
||||
}
|
||||
getToolForFilename(fn) {
|
||||
|
@ -706,7 +714,7 @@ var VerilogPlatform = function(mainElement, options) {
|
|||
inspect_obj = inspect_sym = null;
|
||||
return;
|
||||
}
|
||||
var val = top.state[name];
|
||||
var val = top && top.state[name];
|
||||
/* TODO
|
||||
if (val === undefined && current_output.code) {
|
||||
var re = new RegExp("(\\w+__DOT__(?:_[dcw]_)" + name + ")\\b", "gm");
|
||||
|
@ -730,17 +738,17 @@ var VerilogPlatform = function(mainElement, options) {
|
|||
getDebugTree() {
|
||||
return {
|
||||
runtime: top,
|
||||
state: top.getGlobals()
|
||||
state: top && top.getGlobals()
|
||||
}
|
||||
}
|
||||
|
||||
// TODO: bind() a function to avoid depot?
|
||||
saveState() {
|
||||
return {o: top.saveState()};
|
||||
return {o: top && top.saveState()};
|
||||
}
|
||||
|
||||
loadState(state) {
|
||||
top.loadState(state.o);
|
||||
if (state.o) top.loadState(state.o);
|
||||
}
|
||||
|
||||
saveControlsState() {
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
"use strict";
|
||||
|
||||
import { WorkerResult, WorkerFileUpdate, WorkerBuildStep, WorkerMessage, WorkerError, Dependency, SourceLine, CodeListing, CodeListingMap, Segment, WorkerOutput } from "../common/workertypes";
|
||||
import { WorkerResult, WorkerFileUpdate, WorkerBuildStep, WorkerMessage, WorkerError, Dependency, SourceLine, CodeListing, CodeListingMap, Segment, WorkerOutput, SourceLocation } from "../common/workertypes";
|
||||
|
||||
declare var WebAssembly;
|
||||
declare function importScripts(path:string);
|
||||
|
@ -20,8 +20,8 @@ var wasmMemory;
|
|||
function getWASMMemory() {
|
||||
if (wasmMemory == null) {
|
||||
wasmMemory = new WebAssembly.Memory({
|
||||
'initial': 32768,
|
||||
'maximum': 32768,
|
||||
'initial': 1024, // 64MB
|
||||
'maximum': 16384, // 1024MB
|
||||
});
|
||||
}
|
||||
return wasmMemory;
|
||||
|
@ -1661,7 +1661,7 @@ function preprocessMCPP(step:BuildStep, filesys:string) {
|
|||
|
||||
function detectModuleName(code:string) {
|
||||
var m = /^\s*module\s+(\w+_top)\b/m.exec(code)
|
||||
|| /^\s*module\s+(top)\b/m.exec(code)
|
||||
|| /^\s*module\s+(top|t)\b/m.exec(code)
|
||||
|| /^\s*module\s+(\w+)\b/m.exec(code);
|
||||
return m ? m[1] : null;
|
||||
}
|
||||
|
@ -1772,8 +1772,8 @@ function compileVerilator(step:BuildStep) {
|
|||
loadRequire("hdltypes", "common/hdl/hdltypes");
|
||||
loadRequire("vxmlparser", "common/hdl/vxmlparser");
|
||||
var platform = step.platform || 'verilog';
|
||||
var errors = [];
|
||||
var asmlines = [];
|
||||
var errors : WorkerError[] = [];
|
||||
var asmlines : SourceLine[] = [];
|
||||
gatherFiles(step);
|
||||
// compile verilog if files are stale
|
||||
var xmlPath = "main.xml";
|
||||
|
@ -1803,7 +1803,7 @@ function compileVerilator(step:BuildStep) {
|
|||
try {
|
||||
var args = ["--cc", "-O3"/*abcdefstzsuka*/, "-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod,
|
||||
"-Wall", "-Wno-DECLFILENAME", "-Wno-UNUSED", '--report-unoptflat',
|
||||
"--x-assign", "fast", "--noassert", "--pins-bv", "33",
|
||||
"--x-assign", "fast", "--noassert", "--pins-sc-biguint",
|
||||
"--xml-output", xmlPath,
|
||||
"--top-module", topmod, step.path]
|
||||
verilator_mod.callMain(args);
|
||||
|
@ -1829,7 +1829,12 @@ function compileVerilator(step:BuildStep) {
|
|||
xmlParser.parse(xmlContent);
|
||||
} catch(e) {
|
||||
console.log(e, e.stack);
|
||||
if (e.$loc != null) {
|
||||
let $loc = e.$loc as SourceLocation;
|
||||
errors.push({msg:""+e, path:$loc.path, line:$loc.line});
|
||||
} else {
|
||||
errors.push({line:0,msg:""+e});
|
||||
}
|
||||
return {errors:errors, listings:listings};
|
||||
}
|
||||
//rtn.intermediate = {listing:h_file + cpp_file}; // TODO
|
||||
|
|
|
@ -6,6 +6,10 @@ var _cproc = require('child_process');
|
|||
var fs = require('fs');
|
||||
var wtu = require('./workertestutils.js');
|
||||
var heapdump = require("heapdump");
|
||||
var commandExists = require('command-exists');
|
||||
|
||||
var has_yosys = commandExists('yosys');
|
||||
var has_iverilog = commandExists('iverilog');
|
||||
|
||||
createTestDOM();
|
||||
|
||||
|
@ -71,7 +75,7 @@ function compileVerilator(filename, code, callback, nerrors, depends) {
|
|||
global.postMessage = async function(msg) {
|
||||
try {
|
||||
if (msg.errors && msg.errors.length) {
|
||||
console.log(msg.errors);
|
||||
if (msg.errors.length > 0 && nerrors == 0) throw new Error(JSON.stringify(msg.errors));
|
||||
assert.equal(nerrors||0, msg.errors.length, "errors");
|
||||
} else {
|
||||
assert.equal(nerrors||0, 0, "errors");
|
||||
|
@ -84,13 +88,9 @@ function compileVerilator(filename, code, callback, nerrors, depends) {
|
|||
}
|
||||
callback(null, msg);
|
||||
} catch (e) {
|
||||
if (e.msg && e.msg.indexOf('WebAssembly.Memory()') >= 0) {
|
||||
process.exit(1);
|
||||
} else {
|
||||
//fs.unlinkSync(filename);
|
||||
console.log('rm', filename); //fs.unlinkSync(filename);
|
||||
callback(e, null);
|
||||
}
|
||||
}
|
||||
};
|
||||
// send files to worker for build
|
||||
try {
|
||||
|
@ -101,23 +101,38 @@ function compileVerilator(filename, code, callback, nerrors, depends) {
|
|||
}
|
||||
});
|
||||
} catch (e) {
|
||||
if (e.msg && e.msg.indexOf('WebAssembly.Memory()') >= 0) {
|
||||
process.exit(1);
|
||||
} else {
|
||||
//fs.unlinkSync(filename);
|
||||
console.log('rm', filename); //fs.unlinkSync(filename);
|
||||
callback(e, null);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
function testIcarus(filename) {
|
||||
_cproc.execSync('iverilog -I./presets/verilog ./' + filename);
|
||||
if (has_iverilog) it('should icarus '+filename, function(done) {
|
||||
_cproc.exec('iverilog -g2012 -I./presets/verilog -I./tests/cli/verilog ./' + filename, function(err,stdout,stderr) {
|
||||
if (err) {
|
||||
console.log(stdout);
|
||||
console.log(stderr);
|
||||
}
|
||||
done(err);
|
||||
});
|
||||
});
|
||||
}
|
||||
|
||||
function testYosys(filename) {
|
||||
if (has_yosys) it('should yosys '+filename, function(done) {
|
||||
_cproc.exec(`yosys -q -p "read_verilog -sv ./${filename}"`, function(err,stdout,stderr) {
|
||||
if (err) {
|
||||
console.log(stdout);
|
||||
console.log(stderr);
|
||||
}
|
||||
done(err);
|
||||
});
|
||||
});
|
||||
}
|
||||
|
||||
function testVerilator(filename, disables, nerrors, depends) {
|
||||
it('should translate '+filename, function(done) {
|
||||
it('should verilate '+filename, function(done) {
|
||||
console.log(filename);
|
||||
//if (depends) testIcarus(filename);
|
||||
var csource = ab2str(fs.readFileSync(filename));
|
||||
var header = '';
|
||||
for (var i=0; i<(disables||[]).length; i++)
|
||||
|
@ -126,29 +141,43 @@ function testVerilator(filename, disables, nerrors, depends) {
|
|||
});
|
||||
}
|
||||
|
||||
function testModule(filename, disables, nerrors, depends) {
|
||||
testVerilator(filename, disables, nerrors, depends);
|
||||
//testIcarus(filename);
|
||||
//testYosys(filename);
|
||||
}
|
||||
|
||||
describe('Verilog Worker', function() {
|
||||
|
||||
var files = _fs.readdirSync('test/cli/verilog').filter(fn => fn.endsWith('.v'));
|
||||
//files = files.slice(0,75);
|
||||
for (var fn of files) {
|
||||
testVerilator('test/cli/verilog/' + fn,
|
||||
testModule('test/cli/verilog/' + fn,
|
||||
['UNDRIVEN','BLKSEQ','WIDTH','PINCONNECTEMPTY','SYNCASYNCNET','UNOPT','UNOPTFLAT','VARHIDDEN','EOFNEWLINE','ASSIGNDLY','CASEX','SYMRSVDWORD','STMTDLY','PROCASSWIRE']
|
||||
);
|
||||
global.onmessage({data:{reset:true}});
|
||||
}
|
||||
|
||||
testVerilator('presets/verilog/hvsync_generator.v');
|
||||
testVerilator('presets/verilog/digits10.v', null, null, ['digits10.v', 'hvsync_generator.v']);
|
||||
testVerilator('presets/verilog/scoreboard.v', null, null, ['scoreboard.v', 'digits10.v', 'hvsync_generator.v']);
|
||||
testVerilator('presets/verilog/ball_paddle.v', null, null, ['ball_paddle.v', 'scoreboard.v', 'digits10.v', 'hvsync_generator.v']);
|
||||
testVerilator('presets/verilog/sprite_rotation.v', null, null, ['sprite_rotation.v', 'hvsync_generator.v']);
|
||||
testVerilator('presets/verilog/lfsr.v');
|
||||
testVerilator('presets/verilog/starfield.v', null, null, ['starfield.v', 'lfsr.v', 'hvsync_generator.v']);
|
||||
testVerilator('presets/verilog/ram.v');
|
||||
testVerilator('presets/verilog/font_cp437_8x8.v');
|
||||
testVerilator('presets/verilog/sprite_scanline_renderer.v', null, null, ['sprite_scanline_renderer.v', 'ram.v', 'hvsync_generator.v']);
|
||||
testVerilator('presets/verilog/tile_renderer.v', null, null, ['tile_renderer.v', 'font_cp437_8x8.v', 'ram.v', 'hvsync_generator.v']);
|
||||
testVerilator('presets/verilog/cpu6502.v');
|
||||
testModule('presets/verilog/hvsync_generator.v');
|
||||
testModule('presets/verilog/test_hvsync.v', null, null, ['test_hvsync.v', 'hvsync_generator.v']);
|
||||
testModule('presets/verilog/digits10.v', null, null, ['digits10.v', 'hvsync_generator.v']);
|
||||
testModule('presets/verilog/scoreboard.v', null, null, ['scoreboard.v', 'digits10.v', 'hvsync_generator.v']);
|
||||
testModule('presets/verilog/ball_paddle.v', null, null, ['ball_paddle.v', 'scoreboard.v', 'digits10.v', 'hvsync_generator.v']);
|
||||
testModule('presets/verilog/sprite_rotation.v', null, null, ['sprite_rotation.v', 'hvsync_generator.v']);
|
||||
testModule('presets/verilog/lfsr.v');
|
||||
testModule('presets/verilog/starfield.v', null, null, ['starfield.v', 'lfsr.v', 'hvsync_generator.v']);
|
||||
testModule('presets/verilog/ram.v');
|
||||
testModule('presets/verilog/font_cp437_8x8.v');
|
||||
testModule('presets/verilog/sprite_scanline_renderer.v', null, null, ['sprite_scanline_renderer.v', 'ram.v', 'hvsync_generator.v']);
|
||||
testModule('presets/verilog/tile_renderer.v', null, null, ['tile_renderer.v', 'font_cp437_8x8.v', 'ram.v', 'hvsync_generator.v']);
|
||||
testModule('presets/verilog/cpu6502.v');
|
||||
|
||||
testYosys('presets/verilog/ball_paddle.v');
|
||||
testYosys('presets/verilog/starfield.v');
|
||||
testYosys('presets/verilog/racing_game.v');
|
||||
testYosys('presets/verilog/racing_game_cpu.v');
|
||||
// TODO: fix testYosys('presets/verilog/cpu_platform.v');
|
||||
testYosys('presets/verilog/cpu6502.v');
|
||||
|
||||
}).afterAll(() => {
|
||||
/*
|
||||
|
|
97
test/cli/verilog/t_EXAMPLE.v
Normal file
97
test/cli/verilog/t_EXAMPLE.v
Normal file
|
@ -0,0 +1,97 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// Use this file as a template for submitting bugs, etc.
|
||||
// This module takes a single clock input, and should either
|
||||
// $write("*-* All Finished *-*\n");
|
||||
// $finish;
|
||||
// on success, or $stop.
|
||||
//
|
||||
// The code as shown applies a random vector to the Test
|
||||
// module, then calculates a CRC on the Test module's outputs.
|
||||
//
|
||||
// **If you do not wish for your code to be released to the public
|
||||
// please note it here, otherwise:**
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2021 by ____YOUR_NAME_HERE____.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t(/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [31:0] in = crc[31:0];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [31:0] out; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test(/*AUTOINST*/
|
||||
// Outputs
|
||||
.out (out[31:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.in (in[31:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {32'h0, out};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc == 0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= '0;
|
||||
end
|
||||
else if (cyc < 10) begin
|
||||
sum <= '0;
|
||||
end
|
||||
else if (cyc < 90) begin
|
||||
end
|
||||
else if (cyc == 99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test(/*AUTOARG*/
|
||||
// Outputs
|
||||
out,
|
||||
// Inputs
|
||||
clk, in
|
||||
);
|
||||
|
||||
// Replace this module with the device under test.
|
||||
//
|
||||
// Change the code in the t module to apply values to the inputs and
|
||||
// merge the output values into the result vector.
|
||||
|
||||
input clk;
|
||||
input [31:0] in;
|
||||
output reg [31:0] out;
|
||||
|
||||
always @(posedge clk) begin
|
||||
out <= in;
|
||||
end
|
||||
endmodule
|
|
@ -1,54 +0,0 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2021 by Noam Gallmann.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define stop $stop
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
|
||||
|
||||
module t(/*AUTOARG*/);
|
||||
localparam int SIZES [3:0] = '{1,2,3,4};
|
||||
typedef int calc_sums_t [3:0];
|
||||
|
||||
localparam int SUMS_ARRAY [3:0] = calc_sums_array(SIZES, 4);
|
||||
function calc_sums_t calc_sums_array(int s[3:0], int n);
|
||||
int sum = 0;
|
||||
for (int ii = 0; ii < n; ++ii) begin
|
||||
sum = sum + s[ii];
|
||||
calc_sums_array[ii] = sum;
|
||||
end
|
||||
endfunction
|
||||
|
||||
`ifndef VERILATOR
|
||||
localparam int SUMS_DYN [3:0] = calc_sums_dyn(SIZES, 4);
|
||||
`endif
|
||||
function calc_sums_t calc_sums_dyn(int s[], int n);
|
||||
int sum = 0;
|
||||
for (int ii = 0; ii < n; ++ii) begin
|
||||
sum = sum + s[ii];
|
||||
calc_sums_dyn[ii] = sum;
|
||||
end
|
||||
endfunction
|
||||
|
||||
initial begin
|
||||
`checkh(SIZES[0], 4);
|
||||
`checkh(SIZES[1], 3);
|
||||
`checkh(SIZES[2], 2);
|
||||
`checkh(SIZES[3], 1);
|
||||
|
||||
`checkh(SUMS_ARRAY[0], 4);
|
||||
`checkh(SUMS_ARRAY[1], 7);
|
||||
`checkh(SUMS_ARRAY[2], 9);
|
||||
`checkh(SUMS_ARRAY[3], 10);
|
||||
|
||||
`ifndef VERILATOR
|
||||
`checkh(SUMS_DYN[0], 1);
|
||||
`checkh(SUMS_DYN[1], 3);
|
||||
`checkh(SUMS_DYN[2], 6);
|
||||
`checkh(SUMS_DYN[3], 10);
|
||||
`endif
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
122
test/cli/verilog/t_gate_elim.v
Normal file
122
test/cli/verilog/t_gate_elim.v
Normal file
|
@ -0,0 +1,122 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2005 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=1;
|
||||
|
||||
reg b;
|
||||
|
||||
wire vconst1 = 1'b0;
|
||||
wire vconst2 = !(vconst1);
|
||||
wire vconst3 = !vconst2;
|
||||
wire vconst = vconst3;
|
||||
|
||||
wire qa;
|
||||
wire qb;
|
||||
wire qc;
|
||||
wire qd;
|
||||
wire qe;
|
||||
ta ta (.b(b), .vconst(vconst), .q(qa));
|
||||
tb tb (.clk(clk), .vconst(vconst), .q(qb));
|
||||
tc tc (.b(b), .vconst(vconst), .q(qc));
|
||||
td td (.b(b), .vconst(vconst), .q(qd));
|
||||
te te (.clk(clk), .b(b), .vconst(vconst), .q(qe));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$display("%b",{qa,qb,qc,qd,qe});
|
||||
`endif
|
||||
if (cyc!=0) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==1) begin
|
||||
b <= 1'b1;
|
||||
end
|
||||
if (cyc==2) begin
|
||||
if (qa!=1'b1) $stop;
|
||||
if (qb!=1'b0) $stop;
|
||||
if (qd!=1'b0) $stop;
|
||||
b <= 1'b0;
|
||||
end
|
||||
if (cyc==3) begin
|
||||
if (qa!=1'b0) $stop;
|
||||
if (qb!=1'b0) $stop;
|
||||
if (qd!=1'b0) $stop;
|
||||
if (qe!=1'b0) $stop;
|
||||
b <= 1'b1;
|
||||
end
|
||||
if (cyc==4) begin
|
||||
if (qa!=1'b1) $stop;
|
||||
if (qb!=1'b0) $stop;
|
||||
if (qd!=1'b0) $stop;
|
||||
if (qe!=1'b1) $stop;
|
||||
b <= 1'b0;
|
||||
end
|
||||
if (cyc==5) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module ta (
|
||||
input vconst,
|
||||
input b,
|
||||
output reg q);
|
||||
|
||||
always @ (/*AS*/b or vconst) begin
|
||||
q = vconst | b;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module tb (
|
||||
input vconst,
|
||||
input clk,
|
||||
output reg q);
|
||||
|
||||
always @ (posedge clk) begin
|
||||
q <= vconst;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module tc (
|
||||
input vconst,
|
||||
input b,
|
||||
output reg q);
|
||||
always @ (posedge vconst) begin
|
||||
q <= b;
|
||||
$stop;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module td (
|
||||
input vconst,
|
||||
input b,
|
||||
output reg q);
|
||||
|
||||
always @ (/*AS*/vconst) begin
|
||||
q = vconst;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module te (
|
||||
input clk,
|
||||
input vconst,
|
||||
input b,
|
||||
output reg q);
|
||||
reg qmid;
|
||||
always @ (posedge vconst or posedge clk) begin
|
||||
qmid <= b;
|
||||
end
|
||||
always @ (posedge clk or posedge vconst) begin
|
||||
q <= qmid;
|
||||
end
|
||||
endmodule
|
66
test/cli/verilog/t_gate_lvalue_const.v
Normal file
66
test/cli/verilog/t_gate_lvalue_const.v
Normal file
|
@ -0,0 +1,66 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2019 by Driss Hafdi.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk, rst
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rst;
|
||||
|
||||
logic [2:0] ctrl_inc_single;
|
||||
logic [2:0] ctrl_inc_double;
|
||||
|
||||
logic [2:0] cnt_single;
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_single <= '0;
|
||||
end
|
||||
else if (ctrl_inc_single != '0 && cnt_single != '1) begin
|
||||
cnt_single <= cnt_single + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
logic [2:0] cnt_double;
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_double <= '0;
|
||||
end
|
||||
else if (ctrl_inc_double != '0 && cnt_double != '1) begin
|
||||
cnt_double <= cnt_double + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb ctrl_inc_single = '0;
|
||||
always_comb ctrl_inc_double = '0;
|
||||
|
||||
testMod test_i (.data_i(cnt_single));
|
||||
testMod test_j (.data_i(cnt_double));
|
||||
|
||||
initial begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module testMod
|
||||
(input wire [2:0] data_i);
|
||||
|
||||
typedef logic [63:0] time_t;
|
||||
time_t [2:0] last_transition;
|
||||
genvar b;
|
||||
|
||||
generate
|
||||
for (b = 0; b <= 2; b++) begin : gen_trans
|
||||
always_ff @(posedge data_i[b] or negedge data_i[b]) begin
|
||||
last_transition[b] <= $time;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
56
test/cli/verilog/t_gated_clk_1.v
Normal file
56
test/cli/verilog/t_gated_clk_1.v
Normal file
|
@ -0,0 +1,56 @@
|
|||
// DESCRIPTION: Verilator: Test of gated clock detection
|
||||
//
|
||||
// The code as shown generates a result by a delayed assignment from PC. The
|
||||
// creation of the result is from a clock gated from the clock that sets
|
||||
// PC. Howevever since they are essentially the same clock, the result should
|
||||
// be delayed by one cycle.
|
||||
//
|
||||
// Standard Verilator treats them as different clocks, so the result stays in
|
||||
// step with the PC. An event drive simulator always allows the clock to win.
|
||||
//
|
||||
// The problem is caused by the extra loop added by Verilator to the
|
||||
// evaluation of all internally generated clocks (effectively removed by
|
||||
// marking the clock enable).
|
||||
//
|
||||
// This test is added to facilitate experiments with solutions.
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2013 by Jeremy Bennett <jeremy.bennett@embecosm.com>.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
reg gated_clk_en = 1'b0 ;
|
||||
reg [1:0] pc = 2'b0;
|
||||
reg [1:0] res = 2'b0;
|
||||
|
||||
wire gated_clk = gated_clk_en & clk;
|
||||
|
||||
always @(posedge clk) begin
|
||||
pc <= pc + 1;
|
||||
gated_clk_en <= 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge gated_clk) begin
|
||||
res <= pc;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (pc == 2'b11) begin
|
||||
// Correct behaviour is that res should be lagging pc in the count
|
||||
// by one cycle
|
||||
if (res == 2'b10) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
else begin
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
139
test/cli/verilog/t_gen_cond_bitrange.v
Normal file
139
test/cli/verilog/t_gen_cond_bitrange.v
Normal file
|
@ -0,0 +1,139 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if"
|
||||
//
|
||||
// The given generate loops should only access valid bits of mask, since that
|
||||
// is defined by SIZE. However since the loop range is larger, this only works
|
||||
// if short-circuited evaluation of the generate loop is in place.
|
||||
|
||||
// This file ONLY is placed into the Public Domain, for any use, without
|
||||
// warranty, 2012 by Jeremy Bennett.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define MAX_SIZE 4
|
||||
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
// Set the parameters, so that we use a size less than MAX_SIZE
|
||||
test_gen
|
||||
#(.SIZE (2),
|
||||
.MASK (2'b11))
|
||||
i_test_gen (.clk (clk));
|
||||
|
||||
// This is only a compilation test, but for good measure we do one clock
|
||||
// cycle.
|
||||
integer count;
|
||||
|
||||
initial begin
|
||||
count = 0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (count == 1) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
else begin
|
||||
count = count + 1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // t
|
||||
|
||||
|
||||
module test_gen
|
||||
|
||||
#( parameter
|
||||
SIZE = `MAX_SIZE,
|
||||
MASK = `MAX_SIZE'b0)
|
||||
|
||||
(/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
// Generate blocks that rely on short-circuiting of the logic to avoid errors.
|
||||
generate
|
||||
genvar g;
|
||||
|
||||
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
|
||||
if ((g < SIZE) && MASK[g]) begin
|
||||
always @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
|
||||
`endif
|
||||
if (g >= SIZE) begin
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
|
||||
if (!((g >= SIZE) || ~MASK[g])) begin
|
||||
always @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]);
|
||||
`endif
|
||||
if (g >= SIZE) begin
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
|
||||
if (!((g < SIZE) -> ~MASK[g])) begin
|
||||
always @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]);
|
||||
`endif
|
||||
if (g >= SIZE) begin
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
|
||||
if ( g < SIZE ? MASK[g] : 1'b0) begin
|
||||
always @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]);
|
||||
`endif
|
||||
if (g >= SIZE) begin
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// The other way round
|
||||
generate
|
||||
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
|
||||
if ( g >= SIZE ? 1'b0 : MASK[g]) begin
|
||||
always @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]);
|
||||
`endif
|
||||
if (g >= SIZE) begin
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
72
test/cli/verilog/t_gen_cond_const.v
Normal file
72
test/cli/verilog/t_gen_cond_const.v
Normal file
|
@ -0,0 +1,72 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test for generate IF constants
|
||||
//
|
||||
// The given generate loop should have a constant expression as argument. This
|
||||
// test checks it really does evaluate as constant.
|
||||
|
||||
// This file ONLY is placed into the Public Domain, for any use, without
|
||||
// warranty, 2012 by Jeremy Bennett.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
|
||||
`define MAX_SIZE 4
|
||||
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
// Set the parameters, so that we use a size less than MAX_SIZE
|
||||
test_gen
|
||||
#(.SIZE (2),
|
||||
.MASK (4'b1111))
|
||||
i_test_gen (.clk (clk));
|
||||
|
||||
// This is only a compilation test, but for good measure we do one clock
|
||||
// cycle.
|
||||
integer count;
|
||||
|
||||
initial begin
|
||||
count = 0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (count == 1) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
else begin
|
||||
count = count + 1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // t
|
||||
|
||||
|
||||
module test_gen
|
||||
|
||||
#( parameter
|
||||
SIZE = `MAX_SIZE,
|
||||
MASK = `MAX_SIZE'b0)
|
||||
|
||||
(/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
// Generate blocks that rely on short-circuiting of the logic to avoid
|
||||
// errors.
|
||||
generate
|
||||
if ((SIZE < 8'h04) && MASK[0]) begin
|
||||
always @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write ("Generate IF MASK[0] = %d\n", MASK[0]);
|
||||
`endif
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
39
test/cli/verilog/t_gen_div0.v
Normal file
39
test/cli/verilog/t_gen_div0.v
Normal file
|
@ -0,0 +1,39 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2012 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOINST*/);
|
||||
|
||||
Test #(
|
||||
.BIT_WIDTH (72),
|
||||
.BYTE_WIDTH (9)
|
||||
)
|
||||
|
||||
u_test_inst();
|
||||
|
||||
initial begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test ();
|
||||
|
||||
parameter BIT_WIDTH = "";
|
||||
parameter BYTE_WIDTH = "";
|
||||
|
||||
localparam BYTES = BIT_WIDTH / BYTE_WIDTH;
|
||||
|
||||
wire [BYTES - 1:0] i;
|
||||
wire [BYTES - 1:0] o;
|
||||
|
||||
genvar g;
|
||||
generate
|
||||
for (g = 0; g < BYTES; g = g + 1) begin: gen
|
||||
assign o[g] = (i[g] !== 1'b0);
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
173
test/cli/verilog/t_gen_for.v
Normal file
173
test/cli/verilog/t_gen_for.v
Normal file
|
@ -0,0 +1,173 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2003 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
integer cyc=0;
|
||||
|
||||
reg [7:0] crc;
|
||||
genvar g;
|
||||
|
||||
wire [7:0] out_p1;
|
||||
wire [15:0] out_p2;
|
||||
wire [7:0] out_p3;
|
||||
wire [7:0] out_p4;
|
||||
|
||||
paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1));
|
||||
paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2));
|
||||
paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3));
|
||||
gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4));
|
||||
|
||||
wire [7:0] out_ef;
|
||||
enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
//$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 8'hed;
|
||||
end
|
||||
else if (cyc==1) begin
|
||||
end
|
||||
else if (cyc==3) begin
|
||||
if (out_p1 !== 8'h2d) $stop;
|
||||
if (out_p2 !== 16'h2d2d) $stop;
|
||||
if (out_p3 !== 8'h78) $stop;
|
||||
if (out_p4 !== 8'h44) $stop;
|
||||
if (out_ef !== 8'hda) $stop;
|
||||
end
|
||||
else if (cyc==9) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module gencase (/*AUTOARG*/
|
||||
// Outputs
|
||||
out,
|
||||
// Inputs
|
||||
in
|
||||
);
|
||||
parameter MODE = 0;
|
||||
input [7:0] in;
|
||||
output [7:0] out;
|
||||
generate // : genblk1
|
||||
begin
|
||||
case (MODE)
|
||||
2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]}));
|
||||
default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]}));
|
||||
endcase
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module paramed (/*AUTOARG*/
|
||||
// Outputs
|
||||
out,
|
||||
// Inputs
|
||||
in
|
||||
);
|
||||
parameter WIDTH = 1;
|
||||
parameter MODE = 0;
|
||||
input [WIDTH-1:0] in;
|
||||
output [WIDTH-1:0] out;
|
||||
|
||||
generate
|
||||
if (MODE==0) initial $write("Mode=0\n");
|
||||
// No else
|
||||
endgenerate
|
||||
|
||||
`ifndef NC // for(genvar) unsupported
|
||||
`ifndef ATSIM // for(genvar) unsupported
|
||||
generate
|
||||
// Empty loop body, local genvar
|
||||
for (genvar j=0; j<3; j=j+1) begin end
|
||||
// Ditto to make sure j has new scope
|
||||
for (genvar j=0; j<5; j=j+1) begin end
|
||||
endgenerate
|
||||
`endif
|
||||
`endif
|
||||
|
||||
generate
|
||||
endgenerate
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
if (MODE==0) begin
|
||||
// Flip bitorder, direct assign method
|
||||
for (i=0; i<WIDTH; i=i+1) begin
|
||||
assign out[i] = in[WIDTH-i-1];
|
||||
end
|
||||
end
|
||||
else if (MODE==1) begin
|
||||
// Flip using instantiation
|
||||
for (i=0; i<WIDTH; i=i+1) begin
|
||||
integer from = WIDTH-i-1;
|
||||
if (i==0) begin // Test if's within a for
|
||||
mbuf m0 (.q(out[i]), .a(in[from]));
|
||||
end
|
||||
else begin
|
||||
mbuf ma (.q(out[i]), .a(in[from]));
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
for (i=0; i<WIDTH; i=i+1) begin
|
||||
mbuf ma (.q(out[i]), .a(in[i^1]));
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module mbuf (
|
||||
input a,
|
||||
output q
|
||||
);
|
||||
assign q = a;
|
||||
endmodule
|
||||
|
||||
module enflop (clk, oe_e1, a,q);
|
||||
parameter WIDTH=1;
|
||||
|
||||
input clk;
|
||||
input oe_e1;
|
||||
input [WIDTH-1:0] a;
|
||||
output [WIDTH-1:0] q;
|
||||
|
||||
reg [WIDTH-1:0] oe_r;
|
||||
reg [WIDTH-1:0] q_r;
|
||||
genvar i;
|
||||
|
||||
generate
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin : datapath_bits
|
||||
enflop_one enflop_one
|
||||
(.clk (clk),
|
||||
.d (a[i]),
|
||||
.q_r (q_r[i]));
|
||||
|
||||
always @(posedge clk) oe_r[i] <= oe_e1;
|
||||
|
||||
assign q[i] = oe_r[i] ? q_r[i] : 1'bx;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module enflop_one (
|
||||
input clk,
|
||||
input d,
|
||||
output reg q_r
|
||||
);
|
||||
always @(posedge clk) q_r <= d;
|
||||
endmodule
|
48
test/cli/verilog/t_gen_for0.v
Normal file
48
test/cli/verilog/t_gen_for0.v
Normal file
|
@ -0,0 +1,48 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2007 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
|
||||
Testit testit (/*AUTOINST*/
|
||||
// Inputs
|
||||
.clk (clk));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==0) begin
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Testit (clk);
|
||||
input clk;
|
||||
|
||||
genvar igen;
|
||||
generate
|
||||
for (igen=0; igen<0; igen=igen+1) begin : test_gen
|
||||
always @ (posedge clk) begin
|
||||
$display("igen1 = %d", igen);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
84
test/cli/verilog/t_gen_for1.v
Normal file
84
test/cli/verilog/t_gen_for1.v
Normal file
|
@ -0,0 +1,84 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2007 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire b;
|
||||
reg reset;
|
||||
integer cyc=0;
|
||||
|
||||
Testit testit (/*AUTOINST*/
|
||||
// Outputs
|
||||
.b (b),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.reset (reset));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==0) begin
|
||||
reset <= 1'b0;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
reset <= 1'b1;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
reset <= 1'b0;
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Testit (clk, reset, b);
|
||||
input clk;
|
||||
input reset;
|
||||
output b;
|
||||
|
||||
wire [0:0] c;
|
||||
wire my_sig;
|
||||
wire [0:0] d;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for(i = 0; i >= 0; i = i-1) begin: fnxtclk1
|
||||
fnxtclk fnxtclk1
|
||||
(.u(c[i]),
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
.w(d[i]) );
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign b = d[0];
|
||||
assign c[0] = my_sig;
|
||||
assign my_sig = 1'b1;
|
||||
|
||||
endmodule
|
||||
|
||||
module fnxtclk (u, reset, clk, w );
|
||||
input u;
|
||||
input reset;
|
||||
input clk;
|
||||
output reg w;
|
||||
|
||||
always @ (posedge clk or posedge reset) begin
|
||||
if (reset == 1'b1) begin
|
||||
w <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
w <= u;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
32
test/cli/verilog/t_gen_for_interface.v
Normal file
32
test/cli/verilog/t_gen_for_interface.v
Normal file
|
@ -0,0 +1,32 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2015 by Johan Bjork.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
parameter N = 5;
|
||||
|
||||
interface intf;
|
||||
logic [N-1:0] data;
|
||||
endinterface
|
||||
|
||||
module t (
|
||||
input logic clk
|
||||
);
|
||||
intf localinterface [N-1:0]();
|
||||
|
||||
generate
|
||||
genvar i,j;
|
||||
for(i = 0; i < N; i++) begin
|
||||
logic [N-1:0] dummy;
|
||||
for(j = 0; j < N; j++) begin
|
||||
assign dummy[j] = localinterface[j].data[i];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
initial begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
50
test/cli/verilog/t_gen_for_overlap.v
Normal file
50
test/cli/verilog/t_gen_for_overlap.v
Normal file
|
@ -0,0 +1,50 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2014 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// bug749
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
genvar g;
|
||||
for (g=1; g<3; ++g) begin : gblk
|
||||
sub2 #(.IN(g)) u ();
|
||||
//sub #(.IN(g)) u2 ();
|
||||
end
|
||||
|
||||
sub1 #(.IN(0)) u ();
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (t.u.IN != 0) $stop;
|
||||
if (t.u.FLAVOR != 1) $stop;
|
||||
//if (t.u2.IN != 0) $stop; // This should be not found
|
||||
if (t.gblk[1].u.IN != 1) $stop;
|
||||
if (t.gblk[2].u.IN != 2) $stop;
|
||||
if (t.gblk[1].u.FLAVOR != 2) $stop;
|
||||
if (t.gblk[2].u.FLAVOR != 2) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub1 (/*AUTOARG*/);
|
||||
parameter [31:0] IN = 99;
|
||||
parameter FLAVOR = 1;
|
||||
`ifdef TEST_VERBOSE
|
||||
initial $display("%m");
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
module sub2 (/*AUTOARG*/);
|
||||
parameter [31:0] IN = 99;
|
||||
parameter FLAVOR = 2;
|
||||
`ifdef TEST_VERBOSE
|
||||
initial $display("%m");
|
||||
`endif
|
||||
endmodule
|
80
test/cli/verilog/t_gen_for_shuffle.v
Normal file
80
test/cli/verilog/t_gen_for_shuffle.v
Normal file
|
@ -0,0 +1,80 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2009 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [31:0] in = crc[31:0];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [31:0] out; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.out (out[31:0]),
|
||||
// Inputs
|
||||
.in (in[31:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {32'h0, out};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'h3e3a62edb61f8c7f
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
out,
|
||||
// Inputs
|
||||
in
|
||||
);
|
||||
|
||||
input [31:0] in;
|
||||
output [31:0] out;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i=0; i<16; i=i+1) begin : gblk
|
||||
assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)];
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
109
test/cli/verilog/t_gen_inc.v
Normal file
109
test/cli/verilog/t_gen_inc.v
Normal file
|
@ -0,0 +1,109 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2009 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
integer cyc=0;
|
||||
|
||||
genvar g;
|
||||
integer i;
|
||||
|
||||
reg [31:0] v;
|
||||
|
||||
reg [31:0] gen_pre_PLUSPLUS = 32'h0;
|
||||
reg [31:0] gen_pre_MINUSMINUS = 32'h0;
|
||||
reg [31:0] gen_post_PLUSPLUS = 32'h0;
|
||||
reg [31:0] gen_post_MINUSMINUS = 32'h0;
|
||||
reg [31:0] gen_PLUSEQ = 32'h0;
|
||||
reg [31:0] gen_MINUSEQ = 32'h0;
|
||||
reg [31:0] gen_TIMESEQ = 32'h0;
|
||||
reg [31:0] gen_DIVEQ = 32'h0;
|
||||
reg [31:0] gen_MODEQ = 32'h0;
|
||||
reg [31:0] gen_ANDEQ = 32'h0;
|
||||
reg [31:0] gen_OREQ = 32'h0;
|
||||
reg [31:0] gen_XOREQ = 32'h0;
|
||||
reg [31:0] gen_SLEFTEQ = 32'h0;
|
||||
reg [31:0] gen_SRIGHTEQ = 32'h0;
|
||||
reg [31:0] gen_SSRIGHTEQ = 32'h0;
|
||||
|
||||
generate
|
||||
for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1;
|
||||
for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1;
|
||||
for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1;
|
||||
for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1;
|
||||
for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1;
|
||||
for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1;
|
||||
for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1;
|
||||
for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1;
|
||||
for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1;
|
||||
for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1;
|
||||
for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1;
|
||||
for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1;
|
||||
for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1;
|
||||
for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1;
|
||||
for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1;
|
||||
endgenerate
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc == 3) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS);
|
||||
$write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS);
|
||||
$write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS);
|
||||
$write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS);
|
||||
$write("gen_PLUSEQ %b\n", gen_PLUSEQ);
|
||||
$write("gen_MINUSEQ %b\n", gen_MINUSEQ);
|
||||
$write("gen_TIMESEQ %b\n", gen_TIMESEQ);
|
||||
$write("gen_DIVEQ %b\n", gen_DIVEQ);
|
||||
$write("gen_MODEQ %b\n", gen_MODEQ);
|
||||
$write("gen_ANDEQ %b\n", gen_ANDEQ);
|
||||
$write("gen_OREQ %b\n", gen_OREQ);
|
||||
$write("gen_XOREQ %b\n", gen_XOREQ);
|
||||
$write("gen_SLEFTEQ %b\n", gen_SLEFTEQ);
|
||||
$write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ);
|
||||
$write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ);
|
||||
`endif
|
||||
if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop;
|
||||
if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop;
|
||||
if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop;
|
||||
if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop;
|
||||
if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop;
|
||||
if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop;
|
||||
if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop;
|
||||
if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop;
|
||||
if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop;
|
||||
if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop;
|
||||
if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop;
|
||||
if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop;
|
||||
if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop;
|
||||
if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
|
||||
if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
|
||||
|
||||
v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
|
||||
v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
|
||||
v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
|
||||
v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
|
||||
v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
|
||||
v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
|
||||
v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
|
||||
v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
|
||||
v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop;
|
||||
v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop;
|
||||
v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop;
|
||||
v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop;
|
||||
v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop;
|
||||
v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
|
||||
v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
72
test/cli/verilog/t_gen_index.v
Normal file
72
test/cli/verilog/t_gen_index.v
Normal file
|
@ -0,0 +1,72 @@
|
|||
// DESCRIPTION: Verilator: Test generate index usage.
|
||||
//
|
||||
// The code illustrates a problem in Verilator's handling of constant
|
||||
// expressions inside generate indexes.
|
||||
//
|
||||
// This is a regression test against issue 517.
|
||||
//
|
||||
// **If you do not wish for your code to be released to the public
|
||||
// please note it here, otherwise:**
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2012 by Jeremy Bennett.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define START 8
|
||||
`define SIZE 4
|
||||
`define END (`START + `SIZE)
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
reg [`END-1:0] y;
|
||||
wire [`END-1:0] x;
|
||||
|
||||
foo foo_i (.y (y),
|
||||
.x (x),
|
||||
.clk (clk));
|
||||
|
||||
always @(posedge clk) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule // t
|
||||
|
||||
|
||||
module foo(output wire [`END-1:0] y,
|
||||
input wire [`END-1:0] x,
|
||||
input wire clk);
|
||||
|
||||
function peek_bar;
|
||||
peek_bar = bar_inst[`START].i_bar.r; // this is ok
|
||||
peek_bar = bar_inst[`START + 1].i_bar.r; // this fails, should not.
|
||||
endfunction
|
||||
|
||||
genvar g;
|
||||
generate
|
||||
for (g = `START; g < `END; g = g + 1) begin: bar_inst
|
||||
bar i_bar(.x (x[g]),
|
||||
.y (y[g]),
|
||||
.clk (clk));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule : foo
|
||||
|
||||
|
||||
module bar(output wire y,
|
||||
input wire x,
|
||||
input wire clk);
|
||||
|
||||
reg r = 0;
|
||||
assign y = r;
|
||||
|
||||
always @(posedge clk) begin
|
||||
r = x ? ~x : y;
|
||||
end
|
||||
|
||||
endmodule : bar
|
161
test/cli/verilog/t_gen_intdot2.v
Normal file
161
test/cli/verilog/t_gen_intdot2.v
Normal file
|
@ -0,0 +1,161 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2003-2007 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define STRINGIFY(x) `"x`"
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
integer cyc=0;
|
||||
|
||||
reg check;
|
||||
initial check = 1'b0;
|
||||
Genit g (.clk(clk), .check(check));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
check <= 1'b0;
|
||||
end
|
||||
else if (cyc==1) begin
|
||||
check <= 1'b1;
|
||||
end
|
||||
else if (cyc==9) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
//`define WAVES
|
||||
`ifdef WAVES
|
||||
initial begin
|
||||
$dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
|
||||
$dumpvars(12, t);
|
||||
end
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
module One;
|
||||
wire one = 1'b1;
|
||||
endmodule
|
||||
|
||||
module Genit (
|
||||
input clk,
|
||||
input check);
|
||||
|
||||
// ARRAY
|
||||
One cellarray1[1:0] (); //cellarray[0..1][0..1]
|
||||
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
|
||||
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
|
||||
|
||||
// IF
|
||||
generate
|
||||
// genblk1 refers to the if's name, not the "generate" itself.
|
||||
if (1'b1) // IMPLIED begin: genblk1
|
||||
One ifcell1(); // genblk1.ifcell1
|
||||
else
|
||||
One ifcell1(); // genblk1.ifcell1
|
||||
endgenerate
|
||||
// DISAGREEMENT on this naming
|
||||
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
|
||||
|
||||
generate
|
||||
begin : namedif2
|
||||
if (1'b1)
|
||||
One ifcell2(); // namedif2.genblk1.ifcell2
|
||||
end
|
||||
endgenerate
|
||||
// DISAGREEMENT on this naming
|
||||
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
|
||||
|
||||
generate
|
||||
if (1'b1)
|
||||
begin : namedif3
|
||||
One ifcell3(); // namedif3.ifcell3
|
||||
end
|
||||
endgenerate
|
||||
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
|
||||
|
||||
// CASE
|
||||
generate
|
||||
begin : casecheck
|
||||
case (1'b1)
|
||||
1'b1 :
|
||||
One casecell10(); // genblk4.casecell10
|
||||
endcase
|
||||
end
|
||||
endgenerate
|
||||
// DISAGREEMENT on this naming
|
||||
always @ (posedge clk) if (casecheck.genblk1.casecell10.one !== 1'b1) $stop;
|
||||
|
||||
generate
|
||||
case (1'b1)
|
||||
1'b1 : begin : namedcase11
|
||||
One casecell11();
|
||||
end
|
||||
endcase
|
||||
endgenerate
|
||||
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
|
||||
|
||||
genvar i;
|
||||
genvar j;
|
||||
|
||||
generate
|
||||
begin : genfor
|
||||
for (i = 0; i < 2; i = i + 1)
|
||||
One cellfor20 (); // genfor.genblk1[0..1].cellfor20
|
||||
end
|
||||
endgenerate
|
||||
// DISAGREEMENT on this naming
|
||||
always @ (posedge clk) if (genfor.genblk1[0].cellfor20.one !== 1'b1) $stop;
|
||||
always @ (posedge clk) if (genfor.genblk1[1].cellfor20.one !== 1'b1) $stop;
|
||||
|
||||
// COMBO
|
||||
generate
|
||||
for (i = 0; i < 2; i = i + 1)
|
||||
begin : namedfor21
|
||||
One cellfor21 (); // namedfor21[0..1].cellfor21
|
||||
end
|
||||
endgenerate
|
||||
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
|
||||
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
|
||||
|
||||
generate
|
||||
for (i = 0; i < 2; i = i + 1)
|
||||
begin : namedfor30
|
||||
for (j = 0; j < 2; j = j + 1)
|
||||
begin : forb30
|
||||
if (j == 0)
|
||||
begin : forif30
|
||||
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
|
||||
end
|
||||
else
|
||||
`ifdef verilator
|
||||
begin : forif30b
|
||||
`else
|
||||
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
|
||||
`endif
|
||||
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
|
||||
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
|
||||
`ifdef verilator
|
||||
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
|
||||
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
|
||||
`else
|
||||
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
|
||||
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
|
||||
`endif
|
||||
|
||||
endmodule
|
36
test/cli/verilog/t_gen_local.v
Normal file
36
test/cli/verilog/t_gen_local.v
Normal file
|
@ -0,0 +1,36 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2007 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
integer cyc=0;
|
||||
|
||||
localparam N = 31;
|
||||
|
||||
wire [31:0] vec;
|
||||
|
||||
generate
|
||||
genvar g; // bug461
|
||||
begin : topgen
|
||||
for (g=0; g<N; ++g) begin : gfor
|
||||
assign vec[g] = (g<2);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc == 3) begin
|
||||
if (vec != 32'b0011) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
84
test/cli/verilog/t_inside_wild.v
Normal file
84
test/cli/verilog/t_inside_wild.v
Normal file
|
@ -0,0 +1,84 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2014 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
wire [4:0] in = crc[4:0];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
logic out; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.out (out),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.in (in[4:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {63'h0, out};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'h7a7bd4ee927e7cc3
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
out,
|
||||
// Inputs
|
||||
clk, in
|
||||
);
|
||||
|
||||
//bug718
|
||||
|
||||
input clk;
|
||||
|
||||
input logic [4:0] in;
|
||||
|
||||
output logic out;
|
||||
|
||||
always @(posedge clk) begin
|
||||
out <= in inside {5'b1_1?1?};
|
||||
end
|
||||
|
||||
endmodule
|
132
test/cli/verilog/t_inst_dff.v
Normal file
132
test/cli/verilog/t_inst_dff.v
Normal file
|
@ -0,0 +1,132 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2012 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [31:0] in = crc[31:0];
|
||||
|
||||
localparam WIDTH = 31;
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [WIDTH-1:0] b; // From test of Test.v
|
||||
wire [WIDTH-1:0] c; // From test of Test.v
|
||||
// End of automatics
|
||||
reg rst_l;
|
||||
|
||||
Test #(.WIDTH(WIDTH))
|
||||
test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.b (b[WIDTH-1:0]),
|
||||
.c (c[WIDTH-1:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.rst_l (rst_l),
|
||||
.in (in[WIDTH-1:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {1'h0, c, 1'b0, b};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= 64'h0;
|
||||
rst_l <= ~1'b1;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
rst_l <= ~1'b1;
|
||||
// Hold reset while summing
|
||||
end
|
||||
else if (cyc<20) begin
|
||||
rst_l <= ~1'b0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'hbcfcebdb75ec9d32
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
b, c,
|
||||
// Inputs
|
||||
clk, rst_l, in
|
||||
);
|
||||
|
||||
parameter WIDTH = 5;
|
||||
|
||||
input clk;
|
||||
input rst_l;
|
||||
|
||||
input [WIDTH-1:0] in;
|
||||
output wire [WIDTH-1:0] b;
|
||||
output wire [WIDTH-1:0] c;
|
||||
|
||||
dff # ( .WIDTH (WIDTH),
|
||||
.RESET ('0), // Although this is a single bit, the parameter must be the specified type
|
||||
.RESET_WIDTH (1) )
|
||||
sub1
|
||||
( .clk(clk), .rst_l(rst_l), .q(b), .d(in) );
|
||||
|
||||
dff # ( .WIDTH (WIDTH),
|
||||
.RESET ({ 1'b1, {(WIDTH-1){1'b0}} }),
|
||||
.RESET_WIDTH (WIDTH))
|
||||
sub2
|
||||
( .clk(clk), .rst_l(rst_l), .q(c), .d(in) );
|
||||
|
||||
endmodule
|
||||
|
||||
module dff (/*AUTOARG*/
|
||||
// Outputs
|
||||
q,
|
||||
// Inputs
|
||||
clk, rst_l, d
|
||||
);
|
||||
|
||||
parameter WIDTH = 1;
|
||||
parameter RESET = {WIDTH{1'b0}};
|
||||
parameter RESET_WIDTH = WIDTH;
|
||||
|
||||
input clk;
|
||||
input rst_l;
|
||||
input [WIDTH-1:0] d;
|
||||
output reg [WIDTH-1:0] q;
|
||||
|
||||
always_ff @(posedge clk or negedge rst_l) begin
|
||||
if ($bits(RESET) != RESET_WIDTH) $stop;
|
||||
// verilator lint_off WIDTH
|
||||
if (~rst_l) q <= RESET;
|
||||
// verilator lint_on WIDTH
|
||||
else q <= d;
|
||||
end
|
||||
endmodule
|
42
test/cli/verilog/t_inst_mism.v
Normal file
42
test/cli/verilog/t_inst_mism.v
Normal file
|
@ -0,0 +1,42 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2013 by Alex Solomatnikov.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
//bug595
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
logic [6-1:0] foo; initial foo = 20;
|
||||
|
||||
dut #(.W(6)) udut(.clk(clk),
|
||||
.foo(foo-16));
|
||||
endmodule
|
||||
|
||||
module dut
|
||||
#(parameter W = 1)
|
||||
(input logic clk,
|
||||
input logic [W-1:0] foo);
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < W; i++) begin
|
||||
suba ua(.clk(clk), .foo(foo[i]));
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module suba
|
||||
(input logic clk,
|
||||
input logic foo);
|
||||
|
||||
always @(posedge clk) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
18
test/cli/verilog/t_inst_missing.v
Normal file
18
test/cli/verilog/t_inst_missing.v
Normal file
|
@ -0,0 +1,18 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2012 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
wire ok = 1'b0;
|
||||
// verilator lint_off PINNOCONNECT
|
||||
// verilator lint_off PINCONNECTEMPTY
|
||||
sub sub (.ok(ok), , .nc());
|
||||
// verilator lint_on PINCONNECTEMPTY
|
||||
// verilator lint_on PINNOCONNECT
|
||||
endmodule
|
||||
|
||||
module sub (input ok, input none, input nc);
|
||||
initial if (ok && none && nc) begin end // No unused warning
|
||||
endmodule
|
72
test/cli/verilog/t_inst_mnpipe.v
Normal file
72
test/cli/verilog/t_inst_mnpipe.v
Normal file
|
@ -0,0 +1,72 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2005 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=0;
|
||||
|
||||
reg [7:0] crc;
|
||||
reg [2:0] sum;
|
||||
wire [2:0] in = crc[2:0];
|
||||
wire [2:0] out;
|
||||
|
||||
MxN_pipeline pipe (in, out, clk);
|
||||
|
||||
always @ (posedge clk) begin
|
||||
//$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum);
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 8'hed;
|
||||
sum <= 3'h0;
|
||||
end
|
||||
else if (cyc>10 && cyc<90) begin
|
||||
sum <= {sum[1:0],sum[2]} ^ out;
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
if (crc !== 8'b01110000) $stop;
|
||||
if (sum !== 3'h3) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module dffn (q,d,clk);
|
||||
parameter BITS = 1;
|
||||
|
||||
input [BITS-1:0] d;
|
||||
output reg [BITS-1:0] q;
|
||||
input clk;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
q <= d;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module MxN_pipeline (in, out, clk);
|
||||
parameter M=3, N=4;
|
||||
|
||||
input [M-1:0] in;
|
||||
output [M-1:0] out;
|
||||
input clk;
|
||||
|
||||
// Unsupported: Per-bit array instantiations with output connections to non-wires.
|
||||
//wire [M*(N-1):1] t;
|
||||
//dffn #(M) p[N:1] ({out,t},{t,in},clk);
|
||||
|
||||
wire [M*(N-1):1] w;
|
||||
wire [M*N:1] q;
|
||||
dffn #(M) p[N:1] (q,{w,in},clk);
|
||||
assign {out,w} = q;
|
||||
|
||||
endmodule
|
49
test/cli/verilog/t_inst_port_array.v
Normal file
49
test/cli/verilog/t_inst_port_array.v
Normal file
|
@ -0,0 +1,49 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2013 by Alex Solomatnikov.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
logic [6-1:0] foo[4-1:0];
|
||||
|
||||
//initial $display("%m: %p\n", foo);
|
||||
//initial $display("%m: %p\n", foo[3:0]); // VCS not supported %p with slice
|
||||
//logic [6-1:0] foo2[4-1:0][5:6];
|
||||
//initial $display("%m: %p\n", foo2[3:0][5:6]); // This is not legal
|
||||
|
||||
dut #(.W(6),
|
||||
.D(4)) udut(.clk(clk),
|
||||
.foo(foo[4-1:0]));
|
||||
endmodule
|
||||
|
||||
module dut
|
||||
#(parameter W = 1,
|
||||
parameter D = 1)
|
||||
(input logic clk,
|
||||
input logic [W-1:0] foo[D-1:0]);
|
||||
|
||||
genvar i, j;
|
||||
generate
|
||||
for (j = 0; j < D; j++) begin
|
||||
for (i = 0; i < W; i++) begin
|
||||
suba ua(.clk(clk), .foo(foo[j][i]));
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module suba
|
||||
(input logic clk,
|
||||
input logic foo);
|
||||
|
||||
always @(posedge clk) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
33
test/cli/verilog/t_inst_prepost.v
Normal file
33
test/cli/verilog/t_inst_prepost.v
Normal file
|
@ -0,0 +1,33 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2012 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t;
|
||||
sub #(10,11,12,13) sub ();
|
||||
|
||||
endmodule
|
||||
|
||||
module sub ();
|
||||
parameter A = 0;
|
||||
parameter B = 1;
|
||||
|
||||
ip ip();
|
||||
|
||||
parameter C = 2;
|
||||
parameter D = 3;
|
||||
|
||||
initial begin
|
||||
if (A!=10) $stop;
|
||||
if (B!=11) $stop;
|
||||
if (C!=12) $stop;
|
||||
if (D!=13) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module ip;
|
||||
endmodule
|
66
test/cli/verilog/t_inst_signed.v
Normal file
66
test/cli/verilog/t_inst_signed.v
Normal file
|
@ -0,0 +1,66 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2004 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
integer cyc; initial cyc=0;
|
||||
|
||||
wire signed [7:0] sgn_wide;
|
||||
wire [7:0] unsgn_wide;
|
||||
|
||||
// The instantiation will Z extend, not sign extend
|
||||
// verilator lint_off WIDTH
|
||||
sub sub (.clk,
|
||||
.sgn(sgn_wide), .unsgn(unsgn_wide),
|
||||
.iss(3'sh7), .isu(3'h7),
|
||||
.ius(3'sh7), .iuu(3'h7));
|
||||
// verilator lint_on WIDTH
|
||||
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide);
|
||||
`endif
|
||||
if (sgn_wide[2:0] != 3'sh7) $stop;
|
||||
if (unsgn_wide[2:0] != 3'h7) $stop;
|
||||
// Simulators differ here.
|
||||
if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC
|
||||
&& sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS
|
||||
if (unsgn_wide !== 8'sbzzzzz111
|
||||
&& unsgn_wide!== 8'sb00000111) $stop;
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==3) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub (
|
||||
input clk,
|
||||
output wire signed [2:0] sgn,
|
||||
output wire [2:0] unsgn,
|
||||
input signed [7:0] iss,
|
||||
input signed [7:0] isu,
|
||||
input [7:0] ius,
|
||||
input [7:0] iuu);
|
||||
assign sgn = 3'sh7;
|
||||
assign unsgn = 3'h7;
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("in: %x %x %x %x\n", iss, isu, ius, iuu);
|
||||
if (iss != 8'hff) $stop;
|
||||
if (isu != 8'h07) $stop;
|
||||
if (ius != 8'hff) $stop;
|
||||
if (iuu != 8'h07) $stop;
|
||||
`endif
|
||||
end
|
||||
|
||||
endmodule
|
52
test/cli/verilog/t_inst_signed1.v
Normal file
52
test/cli/verilog/t_inst_signed1.v
Normal file
|
@ -0,0 +1,52 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2018 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
reg signed i;
|
||||
wire signed o1;
|
||||
wire signed o2;
|
||||
|
||||
integer cyc; initial cyc=0;
|
||||
|
||||
sub1 sub1 (.i(i), .o(o1));
|
||||
sub2 sub2 (.i(o1), .o(o2));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==0) begin
|
||||
i <= 1'b0;
|
||||
end
|
||||
else if (cyc==1) begin
|
||||
if (o2 != 1'b0) $stop;
|
||||
i <= 1'b1;
|
||||
end
|
||||
else if (cyc==2) begin
|
||||
if (o2 != 1'b1) $stop;
|
||||
end
|
||||
if (cyc==3) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
//msg2540
|
||||
module sub1 (
|
||||
input signed i,
|
||||
output wire signed o);
|
||||
assign o = ~i;
|
||||
endmodule
|
||||
|
||||
module sub2 (i,o);
|
||||
input signed i;
|
||||
output signed o;
|
||||
wire signed o = ~i;
|
||||
endmodule
|
85
test/cli/verilog/t_inst_slice.v
Normal file
85
test/cli/verilog/t_inst_slice.v
Normal file
|
@ -0,0 +1,85 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2015 by Varun Koyyalagunta.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// bug1015
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [1:0] i = crc[1:0];
|
||||
logic [1:0] o [13:10] ;
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.o (o/*[1:0].[3:0]*/),
|
||||
// Inputs
|
||||
.i (i[1:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {32'h0, 6'h0,o[13], 6'h0,o[12], 6'h0,o[11], 6'h0,o[10]};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n",$time, cyc, crc, result, sum);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= '0;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= '0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'hb42b2f48a0a9375a
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test
|
||||
(
|
||||
output logic [1:0] o [3:0],
|
||||
//but this works
|
||||
//logic [N-1:0] o
|
||||
input [1:0] i);
|
||||
|
||||
parameter N = 4;
|
||||
|
||||
logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3};
|
||||
|
||||
sub sub [N-1:0] (.o (o), // many-to-many
|
||||
.a (a), // many-to-many
|
||||
.i (i)); // many-to-one
|
||||
endmodule
|
||||
|
||||
module sub
|
||||
(
|
||||
input logic [1:0] i,
|
||||
input logic [1:0] a,
|
||||
output logic [1:0] o
|
||||
);
|
||||
assign o = i + a;
|
||||
endmodule
|
93
test/cli/verilog/t_inst_slice_part_select.v
Normal file
93
test/cli/verilog/t_inst_slice_part_select.v
Normal file
|
@ -0,0 +1,93 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2020 by engr248.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t(/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
wire [31:0] in = 0;
|
||||
wire [31:0] out;
|
||||
|
||||
Test test(
|
||||
.out(out[31:0]),
|
||||
.clk(clk),
|
||||
.in (in[31:0])
|
||||
);
|
||||
|
||||
always @ (posedge clk) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
interface Intf ();
|
||||
endinterface
|
||||
|
||||
module Select
|
||||
#(
|
||||
parameter int NUM_MASTER = 1
|
||||
)
|
||||
(
|
||||
Intf Upstream,
|
||||
Intf Downstream[NUM_MASTER]
|
||||
);
|
||||
endmodule
|
||||
|
||||
module Crossbar
|
||||
#(
|
||||
parameter int NUM_MASTER = 1,
|
||||
parameter int NUM_SLAVE = 1
|
||||
)
|
||||
(
|
||||
Intf Masters[NUM_MASTER]
|
||||
);
|
||||
|
||||
Intf selectOut[(NUM_MASTER * (NUM_SLAVE))-1 : 0]();
|
||||
|
||||
|
||||
genvar i;
|
||||
|
||||
for (i = 0; i < NUM_MASTER; i = i + 1) begin
|
||||
Select #(
|
||||
.NUM_MASTER(NUM_SLAVE)
|
||||
)
|
||||
select_inst (
|
||||
.Upstream(Masters[i]),
|
||||
// Following line seems to trigger a bad calculation for dimension where port
|
||||
// is calculated as width 1 (correctly) and expression is calculated as NUM_MASTER*NUM_SLAVE rather than NUM_SLAVE
|
||||
.Downstream(selectOut[(i)*(NUM_SLAVE) +: (NUM_SLAVE)])
|
||||
// The following line works as intended and should be functionally identical to the above line
|
||||
// .Downstream(selectOut[(i+1)*(NUM_SLAVE)-1 : i*(NUM_SLAVE)])
|
||||
);
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test
|
||||
(
|
||||
input clk,
|
||||
input [31:0] in,
|
||||
output reg [31:0] out
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
out <= in;
|
||||
end
|
||||
|
||||
Intf MST[10]();
|
||||
|
||||
Crossbar #(
|
||||
.NUM_MASTER(10),
|
||||
.NUM_SLAVE(1)
|
||||
)
|
||||
xbar_inst (
|
||||
.Masters(MST)
|
||||
);
|
||||
|
||||
endmodule
|
87
test/cli/verilog/t_inst_tree.v
Normal file
87
test/cli/verilog/t_inst_tree.v
Normal file
|
@ -0,0 +1,87 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2003 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=1;
|
||||
|
||||
// verilator lint_off GENCLK
|
||||
reg printclk;
|
||||
// verilator lint_on GENCLK
|
||||
ps ps (printclk);
|
||||
|
||||
reg [7:0] a;
|
||||
wire [7:0] z;
|
||||
|
||||
l1 u (~a,z);
|
||||
|
||||
always @ (posedge clk) begin
|
||||
printclk <= 0;
|
||||
if (cyc!=0) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==1) begin
|
||||
printclk <= 1'b1;
|
||||
end
|
||||
if (cyc==2) begin
|
||||
a <= 8'b1;
|
||||
end
|
||||
if (cyc==3) begin
|
||||
if (z !== 8'hf8) $stop;
|
||||
//if (u.u1.u1.u1.u0.PARAM !== 1) $stop;
|
||||
//if (u.u1.u1.u1.u1.PARAM !== 2) $stop;
|
||||
//if (u.u0.u0.u0.u0.z !== 8'hfe) $stop;
|
||||
//if (u.u0.u0.u0.u1.z !== 8'hff) $stop;
|
||||
//if (u.u1.u1.u1.u0.z !== 8'h00) $stop;
|
||||
//if (u.u1.u1.u1.u1.z !== 8'h01) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module ps (input printclk);
|
||||
// Check that %m stays correct across inlines
|
||||
always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time);
|
||||
endmodule
|
||||
|
||||
module l1 (input [7:0] a, output [7:0] z);
|
||||
wire [7:0] z0; wire [7:0] z1;
|
||||
assign z = z0+z1;
|
||||
l2 u0 (a, z0); l2 u1 (a, z1);
|
||||
endmodule
|
||||
|
||||
module l2 (input [7:0] a, output [7:0] z);
|
||||
wire [7:0] z0; wire [7:0] z1;
|
||||
assign z = z0+z1;
|
||||
wire [7:0] a1 = a+8'd1;
|
||||
l3 u0 (a, z0); l3 u1 (a1, z1);
|
||||
endmodule
|
||||
|
||||
module l3 (input [7:0] a, output [7:0] z);
|
||||
wire [7:0] z0; wire [7:0] z1;
|
||||
assign z = z0+z1;
|
||||
wire [7:0] a1 = a+8'd1;
|
||||
l4 u0 (a, z0); l4 u1 (a1, z1);
|
||||
endmodule
|
||||
|
||||
module l4 (input [7:0] a, output [7:0] z);
|
||||
wire [7:0] z0; wire [7:0] z1;
|
||||
assign z = z0+z1;
|
||||
wire [7:0] a1 = a+8'd1;
|
||||
l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1);
|
||||
endmodule
|
||||
|
||||
module l5 (input [7:0] a, output [7:0] z);
|
||||
parameter PARAM = 5;
|
||||
wire [7:0] z0; wire [7:0] z1;
|
||||
assign z = a;
|
||||
endmodule
|
46
test/cli/verilog/t_interface1.v
Normal file
46
test/cli/verilog/t_interface1.v
Normal file
|
@ -0,0 +1,46 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2013 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// Very simple test for interface pathclearing
|
||||
|
||||
interface ifc;
|
||||
logic [3:0] value;
|
||||
endinterface
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc=1;
|
||||
|
||||
ifc itop();
|
||||
|
||||
sub c1 (.isub(itop),
|
||||
.i_value(4'h4));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==20) begin
|
||||
if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison
|
||||
if (itop.value != 4) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub
|
||||
(
|
||||
ifc isub,
|
||||
input logic [3:0] i_value
|
||||
);
|
||||
|
||||
always @* begin
|
||||
isub.value = i_value;
|
||||
end
|
||||
endmodule : sub
|
57
test/cli/verilog/t_interface1_modport.v
Normal file
57
test/cli/verilog/t_interface1_modport.v
Normal file
|
@ -0,0 +1,57 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2013 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// Very simple test for interface pathclearing
|
||||
|
||||
interface ifc;
|
||||
integer hidden_from_isub;
|
||||
integer value;
|
||||
modport out_modport (output value);
|
||||
endinterface
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc=1;
|
||||
|
||||
ifc itop();
|
||||
|
||||
sub c1 (.isub(itop),
|
||||
.i_value(4));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==20) begin
|
||||
if (itop.value != 4) $stop;
|
||||
itop.hidden_from_isub = 20;
|
||||
if (itop.hidden_from_isub != 20) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub
|
||||
`ifdef NANSI // bug868
|
||||
(
|
||||
isub, i_value
|
||||
);
|
||||
ifc.out_modport isub; // Note parenthesis are not legal here
|
||||
input integer i_value;
|
||||
`else
|
||||
(
|
||||
ifc.out_modport isub,
|
||||
input integer i_value
|
||||
);
|
||||
`endif
|
||||
|
||||
always @* begin
|
||||
isub.value = i_value;
|
||||
end
|
||||
endmodule
|
30
test/cli/verilog/t_interface_ar2a.v
Normal file
30
test/cli/verilog/t_interface_ar2a.v
Normal file
|
@ -0,0 +1,30 @@
|
|||
// DESCRIPTION: Verilator: SystemVerilog interface test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2020 by Thierry Tambe.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ();
|
||||
|
||||
ahb_slave_intf AHB_S[1]();
|
||||
|
||||
AHB_MEM uMEM(.S(AHB_S[0].source));
|
||||
// AHB_MEM V_MEM(.S(AHB_S[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
module AHB_MEM
|
||||
(
|
||||
ahb_slave_intf.source S
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
interface ahb_slave_intf
|
||||
();
|
||||
|
||||
logic [31:0] HADDR;
|
||||
|
||||
modport source (input HADDR);
|
||||
|
||||
endinterface
|
35
test/cli/verilog/t_interface_ar2b.v
Normal file
35
test/cli/verilog/t_interface_ar2b.v
Normal file
|
@ -0,0 +1,35 @@
|
|||
// DESCRIPTION: Verilator: SystemVerilog interface test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2020 by Thierry Tambe.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ();
|
||||
|
||||
sub sub [1] ();
|
||||
|
||||
ahb_slave_intf AHB_S[1]();
|
||||
|
||||
AHB_MEM uMEM(.S(AHB_S[0]));
|
||||
// AHB_MEM uMEM(.S(AHB_S[0].source));
|
||||
|
||||
endmodule
|
||||
|
||||
module sub;
|
||||
endmodule
|
||||
|
||||
module AHB_MEM
|
||||
(
|
||||
ahb_slave_intf.source S
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
interface ahb_slave_intf
|
||||
();
|
||||
|
||||
logic [31:0] HADDR;
|
||||
|
||||
modport source (input HADDR);
|
||||
|
||||
endinterface
|
88
test/cli/verilog/t_interface_gen.v
Normal file
88
test/cli/verilog/t_interface_gen.v
Normal file
|
@ -0,0 +1,88 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2013 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// Very simple test for interface pathclearing
|
||||
|
||||
`ifdef VCS
|
||||
`define UNSUPPORTED_MOD_IN_GENS
|
||||
`endif
|
||||
`ifdef VERILATOR
|
||||
`define UNSUPPORTED_MOD_IN_GENS
|
||||
`endif
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc=1;
|
||||
|
||||
ifc #(1) itopa();
|
||||
ifc #(2) itopb();
|
||||
|
||||
sub #(1) ca (.isub(itopa),
|
||||
.i_value(4));
|
||||
sub #(2) cb (.isub(itopb),
|
||||
.i_value(5));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==1) begin
|
||||
if (itopa.MODE != 1) $stop;
|
||||
if (itopb.MODE != 2) $stop;
|
||||
end
|
||||
if (cyc==20) begin
|
||||
if (itopa.get_value() != 4) $stop;
|
||||
if (itopb.get_value() != 5) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub
|
||||
#(parameter MODE = 0)
|
||||
(
|
||||
ifc.out_modport isub,
|
||||
input integer i_value
|
||||
);
|
||||
|
||||
`ifdef UNSUPPORTED_MOD_IN_GENS
|
||||
always @* isub.value = i_value;
|
||||
`else
|
||||
generate if (MODE == 1) begin
|
||||
always @* isub.valuea = i_value;
|
||||
end
|
||||
else if (MODE == 2) begin
|
||||
always @* isub.valueb = i_value;
|
||||
end
|
||||
endgenerate
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
interface ifc;
|
||||
parameter MODE = 0;
|
||||
// Modports under generates not supported by all commercial simulators
|
||||
`ifdef UNSUPPORTED_MOD_IN_GENS
|
||||
integer value;
|
||||
modport out_modport (output value);
|
||||
function integer get_value(); return value; endfunction
|
||||
`else
|
||||
generate if (MODE == 0) begin
|
||||
integer valuea;
|
||||
modport out_modport (output valuea);
|
||||
function integer get_valuea(); return valuea; endfunction
|
||||
end
|
||||
else begin
|
||||
integer valueb;
|
||||
modport out_modport (output valueb);
|
||||
function integer get_valueb(); return valueb; endfunction
|
||||
end
|
||||
endgenerate
|
||||
`endif
|
||||
endinterface
|
30
test/cli/verilog/t_interface_gen12.v
Normal file
30
test/cli/verilog/t_interface_gen12.v
Normal file
|
@ -0,0 +1,30 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// bug1005
|
||||
|
||||
module foo_module;
|
||||
generate
|
||||
for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block
|
||||
logic baz;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module bar_module;
|
||||
foo_module foo();
|
||||
endmodule
|
||||
|
||||
module t;
|
||||
bar_module bar();
|
||||
initial begin
|
||||
bar.foo.my_gen_block[0].baz = 1;
|
||||
if (bar.foo.my_gen_block[0].baz) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
59
test/cli/verilog/t_interface_gen4.v
Normal file
59
test/cli/verilog/t_interface_gen4.v
Normal file
|
@ -0,0 +1,59 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2013 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// bug789 generates
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc=1;
|
||||
|
||||
ifc #(1) itopa();
|
||||
ifc #(2) itopb();
|
||||
|
||||
sub #(1) ca (.isub(itopa),
|
||||
.i_value(4));
|
||||
sub #(2) cb (.isub(itopb),
|
||||
.i_value(5));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==1) begin
|
||||
if (itopa.MODE != 1) $stop;
|
||||
if (itopb.MODE != 2) $stop;
|
||||
end
|
||||
if (cyc==20) begin
|
||||
if (itopa.i != 4) $stop;
|
||||
if (itopb.i != 5) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub
|
||||
#(parameter MODE = 0)
|
||||
(
|
||||
ifc isub,
|
||||
input integer i_value
|
||||
);
|
||||
|
||||
// Commercial unsupported Xmrs into scopes within interfaces
|
||||
generate
|
||||
always_comb isub.i = i_value;
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
interface ifc;
|
||||
parameter MODE = 0;
|
||||
// Commercial unsupported Xmrs into scopes within interfaces
|
||||
generate
|
||||
integer i;
|
||||
endgenerate
|
||||
endinterface
|
61
test/cli/verilog/t_interface_gen5.v
Normal file
61
test/cli/verilog/t_interface_gen5.v
Normal file
|
@ -0,0 +1,61 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// bug998
|
||||
|
||||
interface intf
|
||||
#(parameter PARAM = 0)
|
||||
();
|
||||
logic val;
|
||||
function integer func (); return 5; endfunction
|
||||
endinterface
|
||||
|
||||
module t1(intf mod_intf);
|
||||
initial begin
|
||||
$display("%m %d", mod_intf.val);
|
||||
end
|
||||
endmodule
|
||||
|
||||
module t();
|
||||
generate
|
||||
begin : TestIf
|
||||
intf #(.PARAM(1)) my_intf ();
|
||||
assign my_intf.val = '0;
|
||||
t1 t (.mod_intf(my_intf));
|
||||
// initial $display("%0d", my_intf.func());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
begin
|
||||
intf #(.PARAM(1)) my_intf ();
|
||||
assign my_intf.val = '1;
|
||||
t1 t (.mod_intf(my_intf));
|
||||
// initial $display("%0d", my_intf.func());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
localparam LP = 1;
|
||||
logic val;
|
||||
|
||||
generate begin
|
||||
if (LP) begin
|
||||
intf #(.PARAM(2)) my_intf ();
|
||||
assign my_intf.val = '1;
|
||||
assign val = my_intf.val;
|
||||
end else begin
|
||||
intf #(.PARAM(3)) my_intf ();
|
||||
assign my_intf.val = '1;
|
||||
assign val = my_intf.val;
|
||||
end
|
||||
end endgenerate
|
||||
|
||||
initial begin
|
||||
$display("%0d", val);
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
57
test/cli/verilog/t_interface_gen6.v
Normal file
57
test/cli/verilog/t_interface_gen6.v
Normal file
|
@ -0,0 +1,57 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// bug1001
|
||||
|
||||
interface intf
|
||||
#(parameter PARAM = 0)
|
||||
();
|
||||
logic val;
|
||||
endinterface
|
||||
|
||||
module t();
|
||||
|
||||
generate
|
||||
if (1) begin
|
||||
intf #(.PARAM(2)) my_intf ();
|
||||
assign my_intf.val = '1;
|
||||
end else begin
|
||||
intf #(.PARAM(3)) my_intf ();
|
||||
assign my_intf.val = '0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
begin
|
||||
if (1) begin
|
||||
intf #(.PARAM(2)) my_intf ();
|
||||
assign my_intf.val = '1;
|
||||
end else begin
|
||||
intf #(.PARAM(3)) my_intf ();
|
||||
assign my_intf.val = '0;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
begin
|
||||
begin
|
||||
if (1) begin
|
||||
intf #(.PARAM(2)) my_intf ();
|
||||
assign my_intf.val = '1;
|
||||
end else begin
|
||||
intf #(.PARAM(3)) my_intf ();
|
||||
assign my_intf.val = '0;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
initial begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
59
test/cli/verilog/t_interface_modport_import.v
Normal file
59
test/cli/verilog/t_interface_modport_import.v
Normal file
|
@ -0,0 +1,59 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// A test of the import parameter used with modport
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2013 by Jeremy Bennett.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
interface test_if;
|
||||
|
||||
// Interface variable
|
||||
logic data;
|
||||
|
||||
// Modport
|
||||
modport mp(
|
||||
import myfunc,
|
||||
output data
|
||||
);
|
||||
|
||||
function automatic logic myfunc (input logic val);
|
||||
begin
|
||||
myfunc = (val == 1'b0);
|
||||
end
|
||||
endfunction
|
||||
|
||||
endinterface // test_if
|
||||
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
test_if i ();
|
||||
|
||||
testmod testmod_i (.clk (clk),
|
||||
.i (i.mp));
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module testmod
|
||||
(
|
||||
input clk,
|
||||
test_if.mp i
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
i.data = 1'b0;
|
||||
if (i.myfunc (1'b0)) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
else begin
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endmodule
|
24
test/cli/verilog/t_interface_modportlist.v
Normal file
24
test/cli/verilog/t_interface_modportlist.v
Normal file
|
@ -0,0 +1,24 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2016 by Adrian Wise.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
//bug1246
|
||||
|
||||
module t(input clk);
|
||||
my_interface iface();
|
||||
my_module m(.clk(clk), iface);
|
||||
endmodule
|
||||
|
||||
module my_module(input clk, my_interface.my_port iface);
|
||||
always @(posedge clk) begin
|
||||
iface.b <= iface.a;
|
||||
iface.c <= iface.a;
|
||||
end
|
||||
endmodule
|
||||
|
||||
interface my_interface;
|
||||
logic a, b, c;
|
||||
modport my_port(input a, output b, c);
|
||||
endinterface
|
52
test/cli/verilog/t_interface_param1.v
Normal file
52
test/cli/verilog/t_interface_param1.v
Normal file
|
@ -0,0 +1,52 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2014 by Jie Xu.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
//bug692
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input wire clk;
|
||||
|
||||
wire [31:0] result;
|
||||
test_if #(.id(3)) s();
|
||||
sub_test U_SUB_TEST(s.a.b, result); // the line causing error
|
||||
endmodule : t
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
module sub_test
|
||||
(
|
||||
input [31:0] b,
|
||||
output [31:0] c
|
||||
);
|
||||
assign c = b;
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
interface test_if
|
||||
#(parameter id = 0)
|
||||
();
|
||||
|
||||
typedef struct packed {
|
||||
logic a;
|
||||
logic [31:0] b;
|
||||
} aType;
|
||||
|
||||
aType a;
|
||||
|
||||
typedef struct packed {
|
||||
logic c;
|
||||
logic [31:0] d;
|
||||
} bType;
|
||||
|
||||
bType b;
|
||||
|
||||
modport master (input a, output b);
|
||||
|
||||
endinterface
|
141
test/cli/verilog/t_interface_parameter_access.v
Normal file
141
test/cli/verilog/t_interface_parameter_access.v
Normal file
|
@ -0,0 +1,141 @@
|
|||
// DESCRIPTION: Verilator: Interface parameter getter
|
||||
//
|
||||
// A test of the import parameter used with modport
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2015 by Todd Strader
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
interface test_if #(parameter integer FOO = 1);
|
||||
|
||||
// Interface variable
|
||||
logic data;
|
||||
|
||||
localparam integer BAR = FOO + 1;
|
||||
|
||||
// Modport
|
||||
modport mp(
|
||||
import getFoo,
|
||||
output data
|
||||
);
|
||||
|
||||
function integer getFoo ();
|
||||
return FOO;
|
||||
endfunction
|
||||
|
||||
endinterface // test_if
|
||||
|
||||
function integer identity (input integer x);
|
||||
return x;
|
||||
endfunction
|
||||
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
test_if #( .FOO (identity(5)) ) the_interface ();
|
||||
test_if #( .FOO (identity(7)) ) array_interface [1:0] ();
|
||||
|
||||
testmod testmod_i (.clk (clk),
|
||||
.intf (the_interface),
|
||||
.intf_no_mp (the_interface),
|
||||
.intf_array (array_interface)
|
||||
);
|
||||
|
||||
localparam THE_TOP_FOO = the_interface.FOO;
|
||||
localparam THE_TOP_FOO_BITS = $bits({the_interface.FOO, the_interface.FOO});
|
||||
localparam THE_ARRAY_FOO = array_interface[0].FOO;
|
||||
|
||||
initial begin
|
||||
if (THE_TOP_FOO != 5) begin
|
||||
$display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO);
|
||||
$stop;
|
||||
end
|
||||
if (THE_TOP_FOO_BITS != 64) begin
|
||||
$display("%%Error: THE_TOP_FOO_BITS = %0d", THE_TOP_FOO_BITS);
|
||||
$stop;
|
||||
end
|
||||
if (THE_ARRAY_FOO != 7) begin
|
||||
$display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module testmod
|
||||
(
|
||||
input clk,
|
||||
test_if.mp intf,
|
||||
test_if intf_no_mp,
|
||||
test_if.mp intf_array [1:0]
|
||||
);
|
||||
|
||||
localparam THE_FOO = intf.FOO;
|
||||
localparam THE_OTHER_FOO = intf_no_mp.FOO;
|
||||
localparam THE_ARRAY_FOO = intf_array[0].FOO;
|
||||
localparam THE_BAR = intf.BAR;
|
||||
localparam THE_OTHER_BAR = intf_no_mp.BAR;
|
||||
localparam THE_ARRAY_BAR = intf_array[0].BAR;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (THE_FOO != 5) begin
|
||||
$display("%%Error: THE_FOO = %0d", THE_FOO);
|
||||
$stop;
|
||||
end
|
||||
if (THE_OTHER_FOO != 5) begin
|
||||
$display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO);
|
||||
$stop;
|
||||
end
|
||||
if (THE_ARRAY_FOO != 7) begin
|
||||
$display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO);
|
||||
$stop;
|
||||
end
|
||||
if (intf.FOO != 5) begin
|
||||
$display("%%Error: intf.FOO = %0d", intf.FOO);
|
||||
$stop;
|
||||
end
|
||||
if (intf_no_mp.FOO != 5) begin
|
||||
$display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO);
|
||||
$stop;
|
||||
end
|
||||
if (intf_array[0].FOO != 7) begin
|
||||
$display("%%Error: intf_array[0].FOO = %0d", intf_array[0].FOO);
|
||||
$stop;
|
||||
end
|
||||
// if (i.getFoo() != 5) begin
|
||||
// $display("%%Error: i.getFoo() = %0d", i.getFoo());
|
||||
// $stop;
|
||||
// end
|
||||
if (THE_BAR != 6) begin
|
||||
$display("%%Error: THE_BAR = %0d", THE_BAR);
|
||||
$stop;
|
||||
end
|
||||
if (THE_OTHER_BAR != 6) begin
|
||||
$display("%%Error: THE_OTHER_BAR = %0d", THE_OTHER_BAR);
|
||||
$stop;
|
||||
end
|
||||
if (THE_ARRAY_BAR != 8) begin
|
||||
$display("%%Error: THE_ARRAY_BAR = %0d", THE_ARRAY_BAR);
|
||||
$stop;
|
||||
end
|
||||
if (intf.BAR != 6) begin
|
||||
$display("%%Error: intf.BAR = %0d", intf.BAR);
|
||||
$stop;
|
||||
end
|
||||
if (intf_no_mp.BAR != 6) begin
|
||||
$display("%%Error: intf_no_mp.BAR = %0d", intf_no_mp.BAR);
|
||||
$stop;
|
||||
end
|
||||
if (intf_array[0].BAR != 8) begin
|
||||
$display("%%Error: intf_array[0].BAR = %0d", intf_array[0].BAR);
|
||||
$stop;
|
||||
end
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
48
test/cli/verilog/t_interface_twod.v
Normal file
48
test/cli/verilog/t_interface_twod.v
Normal file
|
@ -0,0 +1,48 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2013 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
interface ifc;
|
||||
integer value;
|
||||
modport i (output value);
|
||||
modport o (input value);
|
||||
endinterface
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
integer cyc=1;
|
||||
|
||||
ifc itop1a(),
|
||||
itop1b();
|
||||
|
||||
wrapper c1 (.isuba(itop1a),
|
||||
.isubb(itop1b),
|
||||
.i_valuea(14),
|
||||
.i_valueb(15));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==20) begin
|
||||
if (itop1a.value != 14) $stop;
|
||||
if (itop1b.value != 15) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module wrapper
|
||||
(
|
||||
ifc.i isuba, isubb,
|
||||
input integer i_valuea, i_valueb
|
||||
);
|
||||
always @* begin
|
||||
isuba.value = i_valuea;
|
||||
isubb.value = i_valueb;
|
||||
end
|
||||
endmodule
|
51
test/cli/verilog/t_langext_1.v
Normal file
51
test/cli/verilog/t_langext_1.v
Normal file
|
@ -0,0 +1,51 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// A test of the +verilog1995ext+ and +verilog2001ext+ flags.
|
||||
//
|
||||
// This source code contains constructs that are valid in Verilog 2001 and
|
||||
// SystemVerilog 2005/2009, but not in Verilog 1995. So it should fail if we
|
||||
// set the language to be 1995, but not 2001.
|
||||
//
|
||||
// Compile only test, so no need for "All Finished" output.
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2012 by Jeremy Bennett.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [1:0] res;
|
||||
|
||||
// Instantiate the test
|
||||
test test_i (// Outputs
|
||||
.res (res[1:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.in (1'b1));
|
||||
|
||||
endmodule
|
||||
|
||||
module test (// Outputs
|
||||
res,
|
||||
// Inputs
|
||||
clk,
|
||||
in
|
||||
);
|
||||
output reg [1:0] res;
|
||||
input clk;
|
||||
input in;
|
||||
|
||||
// This is a Verilog 2001 test
|
||||
generate
|
||||
genvar i;
|
||||
for (i=0; i<2; i=i+1) begin
|
||||
always @(posedge clk) begin
|
||||
res[i:i] <= in;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
56
test/cli/verilog/t_langext_2.v
Normal file
56
test/cli/verilog/t_langext_2.v
Normal file
|
@ -0,0 +1,56 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// A test of the +1364-1995ext+ and +systemverilogext+ flags.
|
||||
//
|
||||
// This source code contains constructs that are valid in SystemVerilog 2009
|
||||
// but not in Verilog 1995. So it should fail if we set the language to be
|
||||
// Verilog 1995, but not SystemVerilog 2009.
|
||||
//
|
||||
// Compile only test, so no need for "All Finished" output.
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2012 by Jeremy Bennett.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
reg [1:0] res;
|
||||
|
||||
|
||||
// Instantiate the test
|
||||
test test_i (/*AUTOINST*/
|
||||
// Outputs
|
||||
.res (res),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.in (1'b1));
|
||||
|
||||
endmodule
|
||||
|
||||
module test (// Outputs
|
||||
res,
|
||||
// Inputs
|
||||
clk,
|
||||
in
|
||||
);
|
||||
output [1:0] res;
|
||||
input clk;
|
||||
input in;
|
||||
|
||||
// This is a SystemVerilog 2009 only test
|
||||
generate
|
||||
genvar i;
|
||||
for (i=0; i<2; i=i+1) begin
|
||||
always @(posedge clk) begin
|
||||
unique0 case (i)
|
||||
0: res[0:0] <= in;
|
||||
1: res[1:1] <= in;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
22
test/cli/verilog/t_langext_3.v
Normal file
22
test/cli/verilog/t_langext_3.v
Normal file
|
@ -0,0 +1,22 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// A test of the +verilog2001ext+ and +verilog2005ext+ flags.
|
||||
//
|
||||
// This source code uses the uwire declaration, which is only valid in Verilog
|
||||
// 2005.
|
||||
//
|
||||
// Compile only test, so no need for "All Finished" output.
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2012 by Jeremy Bennett.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
uwire w; // Only in Verilog 2005
|
||||
|
||||
endmodule
|
169
test/cli/verilog/t_math_cmp.v
Normal file
169
test/cli/verilog/t_math_cmp.v
Normal file
|
@ -0,0 +1,169 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2004 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
reg [2:0] index_a;
|
||||
reg [2:0] index_b;
|
||||
|
||||
prover #(4) p4 (/*AUTOINST*/
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.index_a (index_a),
|
||||
.index_b (index_b));
|
||||
prover #(32) p32 (/*AUTOINST*/
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.index_a (index_a),
|
||||
.index_b (index_b));
|
||||
prover #(63) p63 (/*AUTOINST*/
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.index_a (index_a),
|
||||
.index_b (index_b));
|
||||
prover #(64) p64 (/*AUTOINST*/
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.index_a (index_a),
|
||||
.index_b (index_b));
|
||||
prover #(72) p72 (/*AUTOINST*/
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.index_a (index_a),
|
||||
.index_b (index_b));
|
||||
prover #(126) p126 (/*AUTOINST*/
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.index_a (index_a),
|
||||
.index_b (index_b));
|
||||
prover #(128) p128 (/*AUTOINST*/
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.index_a (index_a),
|
||||
.index_b (index_b));
|
||||
|
||||
integer cyc; initial cyc=0;
|
||||
initial index_a = 3'b0;
|
||||
initial index_b = 3'b0;
|
||||
always @* begin
|
||||
index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4;
|
||||
index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module prover (
|
||||
input clk,
|
||||
input [2:0] index_a,
|
||||
input [2:0] index_b
|
||||
);
|
||||
|
||||
parameter WIDTH = 4;
|
||||
|
||||
|
||||
reg signed [WIDTH-1:0] as;
|
||||
reg signed [WIDTH-1:0] bs;
|
||||
wire [WIDTH-1:0] b = bs;
|
||||
|
||||
// verilator lint_off LATCH
|
||||
always @* begin
|
||||
casez (index_a)
|
||||
3'd0: as = {(WIDTH){1'd0}}; // 0
|
||||
3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
|
||||
3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
|
||||
3'd3: as = {(WIDTH){1'd1}}; // -1
|
||||
3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
|
||||
default: $stop;
|
||||
endcase
|
||||
casez (index_b)
|
||||
3'd0: bs = {(WIDTH){1'd0}}; // 0
|
||||
3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
|
||||
3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
|
||||
3'd3: bs = {(WIDTH){1'd1}}; // -1
|
||||
3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
|
||||
default: $stop;
|
||||
endcase
|
||||
end
|
||||
// verilator lint_on LATCH
|
||||
|
||||
reg [7:0] results[4:0][4:0];
|
||||
|
||||
wire gt = as>b;
|
||||
wire gts = as>bs;
|
||||
wire gte = as>=b;
|
||||
wire gtes = as>=bs;
|
||||
wire lt = as<b;
|
||||
wire lts = as<bs;
|
||||
wire lte = as<=b;
|
||||
wire ltes = as<=bs;
|
||||
|
||||
reg [7:0] exp;
|
||||
reg [7:0] got;
|
||||
|
||||
integer cyc=0;
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc>2) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
|
||||
index_a, index_b,
|
||||
gt, gts, gte, gtes, lt, lts, lte, ltes);
|
||||
`endif
|
||||
exp = results[index_a][index_b];
|
||||
got = {gt, gts, gte, gtes, lt, lts, lte, ltes};
|
||||
if (exp !== got) begin
|
||||
$display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Result table
|
||||
initial begin
|
||||
// Indexes: 0, 1, -1, 127, -128
|
||||
// Gt Gts Gte Gtes Lt Lts Lte Ltes
|
||||
results[0][0] = 8'b0_0_1_1_0_0_1_1;
|
||||
results[0][1] = 8'b0_0_0_0_1_1_1_1;
|
||||
results[0][2] = 8'b0_0_1_1_0_0_1_1;
|
||||
results[0][3] = 8'b0_1_0_1_1_0_1_0;
|
||||
results[0][4] = 8'b0_1_0_1_1_0_1_0;
|
||||
results[1][0] = 8'b1_1_1_1_0_0_0_0;
|
||||
results[1][1] = 8'b0_0_1_1_0_0_1_1;
|
||||
results[1][2] = 8'b1_1_1_1_0_0_0_0;
|
||||
results[1][3] = 8'b0_1_0_1_1_0_1_0;
|
||||
results[1][4] = 8'b0_1_0_1_1_0_1_0;
|
||||
results[2][0] = 8'b0_0_1_1_0_0_1_1;
|
||||
results[2][1] = 8'b0_0_0_0_1_1_1_1;
|
||||
results[2][2] = 8'b0_0_1_1_0_0_1_1;
|
||||
results[2][3] = 8'b0_1_0_1_1_0_1_0;
|
||||
results[2][4] = 8'b0_1_0_1_1_0_1_0;
|
||||
results[3][0] = 8'b1_0_1_0_0_1_0_1;
|
||||
results[3][1] = 8'b1_0_1_0_0_1_0_1;
|
||||
results[3][2] = 8'b1_0_1_0_0_1_0_1;
|
||||
results[3][3] = 8'b0_0_1_1_0_0_1_1;
|
||||
results[3][4] = 8'b1_1_1_1_0_0_0_0;
|
||||
results[4][0] = 8'b1_0_1_0_0_1_0_1;
|
||||
results[4][1] = 8'b1_0_1_0_0_1_0_1;
|
||||
results[4][2] = 8'b1_0_1_0_0_1_0_1;
|
||||
results[4][3] = 8'b0_0_0_0_1_1_1_1;
|
||||
results[4][4] = 8'b0_0_1_1_0_0_1_1;
|
||||
end
|
||||
|
||||
endmodule
|
75
test/cli/verilog/t_math_concat.v
Normal file
75
test/cli/verilog/t_math_concat.v
Normal file
|
@ -0,0 +1,75 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2004 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=1;
|
||||
|
||||
reg [255:0] i;
|
||||
wire [255:0] q;
|
||||
|
||||
assign q = {
|
||||
i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039],
|
||||
i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048],
|
||||
i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234],
|
||||
i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122],
|
||||
i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034],
|
||||
i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174],
|
||||
i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110],
|
||||
i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183],
|
||||
i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128],
|
||||
i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139],
|
||||
i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173],
|
||||
i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142],
|
||||
i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119],
|
||||
i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035],
|
||||
i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149],
|
||||
i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144],
|
||||
i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070],
|
||||
i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017],
|
||||
i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084],
|
||||
i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118],
|
||||
i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171],
|
||||
i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112],
|
||||
i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179],
|
||||
i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002],
|
||||
i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161],
|
||||
i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151],
|
||||
i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098],
|
||||
i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013],
|
||||
i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050],
|
||||
i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219],
|
||||
i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029],
|
||||
i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093]
|
||||
};
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (cyc!=0) begin
|
||||
cyc <= cyc + 1;
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("%x %x\n", q, i);
|
||||
`endif
|
||||
if (cyc==1) begin
|
||||
i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
|
||||
end
|
||||
if (cyc==2) begin
|
||||
i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
|
||||
if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop;
|
||||
end
|
||||
if (cyc==3) begin
|
||||
if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop;
|
||||
end
|
||||
if (cyc==4) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
88
test/cli/verilog/t_math_concat0.v
Normal file
88
test/cli/verilog/t_math_concat0.v
Normal file
|
@ -0,0 +1,88 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2009 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [15:0] in = crc[15:0];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [15:0] outa; // From test of Test.v
|
||||
wire [15:0] outb; // From test of Test.v
|
||||
wire [15:0] outc; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.outa (outa[15:0]),
|
||||
.outb (outb[15:0]),
|
||||
.outc (outc[15:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.in (in[15:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {16'h0, outa, outb, outc};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'h09be74b1b0f8c35d
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
outa, outb, outc,
|
||||
// Inputs
|
||||
clk, in
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [15:0] in;
|
||||
output reg [15:0] outa;
|
||||
output reg [15:0] outb;
|
||||
output reg [15:0] outc;
|
||||
|
||||
parameter WIDTH = 0;
|
||||
always @(posedge clk) begin
|
||||
outa <= {in};
|
||||
outb <= {{WIDTH{1'b0}}, in};
|
||||
outc <= {in, {WIDTH{1'b0}}};
|
||||
end
|
||||
endmodule
|
131
test/cli/verilog/t_math_concat64.v
Normal file
131
test/cli/verilog/t_math_concat64.v
Normal file
|
@ -0,0 +1,131 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2005 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=1;
|
||||
|
||||
reg [127:0] i;
|
||||
wire [127:0] q1;
|
||||
wire [127:0] q32;
|
||||
wire [127:0] q64;
|
||||
wire [63:0] q64_low;
|
||||
|
||||
assign q1 = {
|
||||
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
|
||||
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
|
||||
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
|
||||
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
|
||||
|
||||
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
|
||||
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
|
||||
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
|
||||
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1],
|
||||
|
||||
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
|
||||
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
|
||||
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
|
||||
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
|
||||
|
||||
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
|
||||
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
|
||||
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
|
||||
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
|
||||
|
||||
assign q64[127:64] = {
|
||||
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
|
||||
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
|
||||
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
|
||||
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
|
||||
|
||||
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
|
||||
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
|
||||
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
|
||||
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
|
||||
assign q64[63:0] = {
|
||||
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
|
||||
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
|
||||
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
|
||||
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
|
||||
|
||||
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
|
||||
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
|
||||
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
|
||||
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
|
||||
|
||||
assign q64_low = {
|
||||
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
|
||||
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
|
||||
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
|
||||
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
|
||||
|
||||
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
|
||||
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
|
||||
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
|
||||
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
|
||||
|
||||
assign q32[127:96] = {
|
||||
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
|
||||
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
|
||||
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
|
||||
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]};
|
||||
assign q32[95:64] = {
|
||||
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
|
||||
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
|
||||
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
|
||||
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
|
||||
assign q32[63:32] = {
|
||||
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
|
||||
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
|
||||
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
|
||||
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]};
|
||||
assign q32[31:0] = {
|
||||
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
|
||||
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
|
||||
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
|
||||
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (cyc!=0) begin
|
||||
cyc <= cyc + 1;
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("%x %x\n", q1, i);
|
||||
`endif
|
||||
if (cyc==1) begin
|
||||
i <= 128'hed388e646c843d35de489bab2413d770;
|
||||
end
|
||||
if (cyc==2) begin
|
||||
i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3;
|
||||
if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop;
|
||||
if (q1 != q32) $stop;
|
||||
if (q1 != q64) $stop;
|
||||
if (q1[63:0] != q64_low) $stop;
|
||||
end
|
||||
if (cyc==3) begin
|
||||
i <= 128'he236ddfddddbdad20a48e039c9f395b8;
|
||||
if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop;
|
||||
if (q1 != q32) $stop;
|
||||
if (q1 != q64) $stop;
|
||||
if (q1[63:0] != q64_low) $stop;
|
||||
end
|
||||
if (cyc==4) begin
|
||||
i <= 128'h45e0eb7642b148537491f3da147e7f26;
|
||||
if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop;
|
||||
if (q1 != q32) $stop;
|
||||
if (q1 != q64) $stop;
|
||||
if (q1[63:0] != q64_low) $stop;
|
||||
end
|
||||
if (cyc==9) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
95
test/cli/verilog/t_math_cond_clean.v
Normal file
95
test/cli/verilog/t_math_cond_clean.v
Normal file
|
@ -0,0 +1,95 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2019 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [3:0] cnt = crc[3:0];
|
||||
wire [6:0] decr = crc[14:8];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [3:0] next; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.next (next[3:0]),
|
||||
// Inputs
|
||||
.cnt (cnt[3:0]),
|
||||
.decr (decr[6:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {60'h0, next};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= '0;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= '0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'h7cd85c944415d2ef
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
next,
|
||||
// Inputs
|
||||
cnt, decr
|
||||
);
|
||||
|
||||
input [3:0] cnt;
|
||||
input signed [6:0] decr;
|
||||
output reg [3:0] next;
|
||||
|
||||
always_comb begin
|
||||
reg signed [6:0] tmp;
|
||||
tmp = 0;
|
||||
// verilator lint_off WIDTH
|
||||
tmp = ($signed({1'b0, cnt}) - decr);
|
||||
// verilator lint_on WIDTH
|
||||
if ((tmp > 15)) begin
|
||||
next = 15;
|
||||
end
|
||||
else if ((tmp < 0)) begin
|
||||
next = 0;
|
||||
end
|
||||
else begin
|
||||
next = tmp[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
93
test/cli/verilog/t_math_eq.v
Normal file
93
test/cli/verilog/t_math_eq.v
Normal file
|
@ -0,0 +1,93 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2007 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [31:0] in = crc[31:0];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [3:0] out; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.out (out[3:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.in (in[31:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {60'h0, out};
|
||||
|
||||
// What checksum will we end up with
|
||||
`define EXPECTED_SUM 64'h1a0d07009b6a30d2
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
out,
|
||||
// Inputs
|
||||
clk, in
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [31:0] in;
|
||||
output [3:0] out;
|
||||
|
||||
assign out[0] = in[3:0] ==? 4'b1001;
|
||||
assign out[1] = in[3:0] !=? 4'b1001;
|
||||
assign out[2] = in[3:0] ==? 4'bx01x;
|
||||
assign out[3] = in[3:0] !=? 4'bx01x;
|
||||
|
||||
wire signed [3:0] ins = in[3:0];
|
||||
|
||||
wire signed [3:0] outs;
|
||||
|
||||
assign outs[0] = ins ==? 4'sb1001;
|
||||
assign outs[1] = ins !=? 4'sb1001;
|
||||
assign outs[2] = ins ==? 4'sbx01x;
|
||||
assign outs[3] = ins !=? 4'sbx01x;
|
||||
|
||||
always_comb if (out != outs) $stop;
|
||||
|
||||
endmodule
|
74
test/cli/verilog/t_math_equal.v
Normal file
74
test/cli/verilog/t_math_equal.v
Normal file
|
@ -0,0 +1,74 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2003 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
integer _mode;
|
||||
|
||||
reg _guard1;
|
||||
reg [127:0] r_wide0;
|
||||
reg _guard2;
|
||||
wire [63:0] r_wide1;
|
||||
reg _guard3;
|
||||
reg _guard4;
|
||||
reg _guard5;
|
||||
reg _guard6;
|
||||
|
||||
assign r_wide1 = r_wide0[127:64];
|
||||
|
||||
// surefire lint_off STMINI
|
||||
initial _mode = 0;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (_mode==0) begin
|
||||
$write("[%0t] t_equal: Running\n", $time);
|
||||
_guard1 <= 0;
|
||||
_guard2 <= 0;
|
||||
_guard3 <= 0;
|
||||
_guard4 <= 0;
|
||||
_guard5 <= 0;
|
||||
_guard6 <= 0;
|
||||
|
||||
_mode<=1;
|
||||
r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444};
|
||||
end
|
||||
else if (_mode==1) begin
|
||||
_mode<=2;
|
||||
//
|
||||
if (5'd10 != 5'b1010) $stop;
|
||||
if (5'd10 != 5'd10) $stop;
|
||||
if (5'd10 != 5'd1_0) $stop;
|
||||
if (5'd10 != 5'ha) $stop;
|
||||
if (5'd10 != 5'o12) $stop;
|
||||
if (5'd10 != 5'o1_2) $stop;
|
||||
if (5'd10 != 5'B 1010) $stop;
|
||||
if (5'd10 != 5'B 10_10) $stop;
|
||||
if (5'd10 != 5'D10) $stop;
|
||||
if (5'd10 != 5'H a) $stop;
|
||||
if (5'd10 != 5 'O 12) $stop;
|
||||
if (24'h29cbb8 != 24'o12345670) $stop;
|
||||
if (24'h29__cbb8 != 24'o123456__70) $stop;
|
||||
if (6'b111xxx !== 6'o7x) $stop;
|
||||
if (6'b111??? !== 6'o7?) $stop;
|
||||
if (6'b111zzz !== 6'o7z) $stop;
|
||||
//
|
||||
if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop;
|
||||
if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop;
|
||||
if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
|
||||
$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
|
||||
$stop;
|
||||
end
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
114
test/cli/verilog/t_math_imm.v
Normal file
114
test/cli/verilog/t_math_imm.v
Normal file
|
@ -0,0 +1,114 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2005 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
//
|
||||
// Example module to create problem.
|
||||
//
|
||||
// generate a 64 bit value with bits
|
||||
// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1
|
||||
// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1
|
||||
// all other bits zero.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=0;
|
||||
reg [7:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [63:0] HighLogicImm; // From example of example.v
|
||||
wire [63:0] LogicImm; // From example of example.v
|
||||
wire [63:0] LowLogicImm; // From example of example.v
|
||||
// End of automatics
|
||||
|
||||
wire [5:0] LowMaskSel_Top = crc[5:0];
|
||||
wire [5:0] LowMaskSel_Bot = crc[5:0];
|
||||
wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]};
|
||||
wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]};
|
||||
|
||||
example example (/*AUTOINST*/
|
||||
// Outputs
|
||||
.LogicImm (LogicImm[63:0]),
|
||||
.LowLogicImm (LowLogicImm[63:0]),
|
||||
.HighLogicImm (HighLogicImm[63:0]),
|
||||
// Inputs
|
||||
.LowMaskSel_Top (LowMaskSel_Top[5:0]),
|
||||
.HighMaskSel_Top (HighMaskSel_Top[5:0]),
|
||||
.LowMaskSel_Bot (LowMaskSel_Bot[5:0]),
|
||||
.HighMaskSel_Bot (HighMaskSel_Bot[5:0]));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc,
|
||||
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
|
||||
LowLogicImm, HighLogicImm, LogicImm);
|
||||
`endif
|
||||
if (cyc==0) begin
|
||||
// Single case
|
||||
crc <= 8'h0;
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc==1) begin
|
||||
// Setup
|
||||
crc <= 8'hed;
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
sum <= {sum[62:0],sum[63]} ^ LogicImm;
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 8'b00111000) $stop;
|
||||
if (sum !== 64'h58743ffa61e41075) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module example (/*AUTOARG*/
|
||||
// Outputs
|
||||
LogicImm, LowLogicImm, HighLogicImm,
|
||||
// Inputs
|
||||
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot
|
||||
);
|
||||
|
||||
input [5:0] LowMaskSel_Top, HighMaskSel_Top;
|
||||
input [5:0] LowMaskSel_Bot, HighMaskSel_Bot;
|
||||
output [63:0] LogicImm;
|
||||
|
||||
output [63:0] LowLogicImm, HighLogicImm;
|
||||
|
||||
|
||||
wire [63:0] LowLogicImm, HighLogicImm;
|
||||
|
||||
/* verilator lint_off UNSIGNED */
|
||||
/* verilator lint_off CMPCONST */
|
||||
genvar i;
|
||||
generate
|
||||
for (i=0;i<64;i=i+1) begin : MaskVal
|
||||
if (i >= 32) begin
|
||||
assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]);
|
||||
assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]);
|
||||
end
|
||||
else begin
|
||||
assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]);
|
||||
assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
/* verilator lint_on UNSIGNED */
|
||||
/* verilator lint_on CMPCONST */
|
||||
|
||||
assign LogicImm = LowLogicImm & HighLogicImm;
|
||||
endmodule
|
43
test/cli/verilog/t_math_imm2.v
Normal file
43
test/cli/verilog/t_math_imm2.v
Normal file
|
@ -0,0 +1,43 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2005 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
//
|
||||
// Example module to create problem.
|
||||
//
|
||||
// generate a 64 bit value with bits
|
||||
// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1
|
||||
// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1
|
||||
// all other bits zero.
|
||||
|
||||
module t_math_imm2 (/*AUTOARG*/
|
||||
// Outputs
|
||||
LogicImm, LowLogicImm, HighLogicImm,
|
||||
// Inputs
|
||||
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot
|
||||
);
|
||||
input [4:0] LowMaskSel_Top, HighMaskSel_Top;
|
||||
input [4:0] LowMaskSel_Bot, HighMaskSel_Bot;
|
||||
output [63:0] LogicImm;
|
||||
|
||||
output [63:0] LowLogicImm, HighLogicImm;
|
||||
|
||||
/* verilator lint_off UNSIGNED */
|
||||
/* verilator lint_off CMPCONST */
|
||||
genvar i;
|
||||
generate
|
||||
for (i=0;i<64;i=i+1) begin : MaskVal
|
||||
if (i >= 32) begin
|
||||
assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]);
|
||||
assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]);
|
||||
end
|
||||
else begin
|
||||
assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]);
|
||||
assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign LogicImm = LowLogicImm & HighLogicImm;
|
||||
endmodule
|
75
test/cli/verilog/t_math_msvc_64.v
Normal file
75
test/cli/verilog/t_math_msvc_64.v
Normal file
|
@ -0,0 +1,75 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2010 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
|
||||
reg [89:0] in;
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [89:0] out; // From test of Test.v
|
||||
wire [44:0] line0;
|
||||
wire [44:0] line1;
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.out (out[89:0]),
|
||||
.line0 (line0[44:0]),
|
||||
.line1 (line1[44:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.in (in[89:0]));
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
|
||||
end
|
||||
else if (cyc==10) begin
|
||||
if (in==out) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
else begin
|
||||
$write("*-* Failed!! *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
line0, line1, out,
|
||||
// Inputs
|
||||
clk, in
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [89:0] in;
|
||||
|
||||
output reg [44:0] line0;
|
||||
output reg [44:0] line1;
|
||||
output reg [89:0] out;
|
||||
|
||||
assign {line0,line1} = in;
|
||||
always @(posedge clk) begin
|
||||
out <= {line0,line1};
|
||||
end
|
||||
endmodule
|
72
test/cli/verilog/t_math_mul.v
Normal file
72
test/cli/verilog/t_math_mul.v
Normal file
|
@ -0,0 +1,72 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2006 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
integer cyc; initial cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
wire [31:0] out1;
|
||||
wire [31:0] out2;
|
||||
sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2);
|
||||
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
|
||||
if (cyc==1) begin
|
||||
// Setup
|
||||
crc <= 64'h00000000_00000097;
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc==90) begin
|
||||
if (sum !== 64'he396068aba3898a2) $stop;
|
||||
end
|
||||
else if (cyc==91) begin
|
||||
end
|
||||
else if (cyc==92) begin
|
||||
end
|
||||
else if (cyc==93) begin
|
||||
end
|
||||
else if (cyc==94) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module sub (/*AUTOARG*/
|
||||
// Outputs
|
||||
out1, out2,
|
||||
// Inputs
|
||||
in1, in2
|
||||
);
|
||||
|
||||
input [15:0] in1;
|
||||
input [15:0] in2;
|
||||
output reg signed [31:0] out1;
|
||||
output reg unsigned [31:0] out2;
|
||||
|
||||
always @* begin
|
||||
// verilator lint_off WIDTH
|
||||
out1 = $signed(in1) * $signed(in2);
|
||||
out2 = $unsigned(in1) * $unsigned(in2);
|
||||
// verilator lint_on WIDTH
|
||||
end
|
||||
|
||||
endmodule
|
83
test/cli/verilog/t_math_pick.v
Normal file
83
test/cli/verilog/t_math_pick.v
Normal file
|
@ -0,0 +1,83 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2013.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire pick1 = crc[0];
|
||||
wire [13:0][1:0] data1 = crc[27+1:1];
|
||||
wire [3:0][2:0][1:0] data2 = crc[23+29:29];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
logic [15:0] [1:0] datao; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.datao (datao/*[15:0][1:0]*/),
|
||||
// Inputs
|
||||
.pick1 (pick1),
|
||||
.data1 (data1/*[13:0][1:0]*/),
|
||||
.data2 (data2/*[2:0][3:0][1:0]*/));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {32'h0, datao};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'h3ff4bf0e6407b281
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test
|
||||
(
|
||||
input logic pick1,
|
||||
input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits
|
||||
input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits
|
||||
output logic [15:0] [1:0] datao // 16 x 2 = 32 bits
|
||||
);
|
||||
// verilator lint_off WIDTH
|
||||
always_comb datao[13: 0] // 28 bits
|
||||
= (pick1)
|
||||
? {data1} // 28 bits
|
||||
: {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized
|
||||
// verilator lint_on WIDTH
|
||||
always_comb datao[15:14] = '0;
|
||||
endmodule
|
19
test/cli/verilog/t_math_real_public.v
Normal file
19
test/cli/verilog/t_math_real_public.v
Normal file
|
@ -0,0 +1,19 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2018 by Alex Solomatnikov
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t;
|
||||
sub #(.REAL(2.0)) sub;
|
||||
endmodule
|
||||
|
||||
module sub ();
|
||||
parameter REAL = 0.0;
|
||||
|
||||
initial begin
|
||||
$display("REAL %g", REAL);
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
65
test/cli/verilog/t_math_red.v
Normal file
65
test/cli/verilog/t_math_red.v
Normal file
|
@ -0,0 +1,65 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2004 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=0;
|
||||
|
||||
reg [67:0] r;
|
||||
|
||||
wire and_reduce = &r;
|
||||
wire or_reduce = |r;
|
||||
wire xor_reduce = ^r;
|
||||
wire xnor_reduce = ~^r;
|
||||
wire check_equal = r == 68'hffff_ffff_ffff_ffff_f;
|
||||
|
||||
always @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$display("cyc=%0d, r = %x, and_reduce = %x, or=%x xor=%x check_equal = %x",
|
||||
cyc, r, and_reduce, or_reduce, xor_reduce, check_equal);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
if (cyc == 1) begin
|
||||
r <= 68'd0;
|
||||
end
|
||||
else if (cyc == 10) begin
|
||||
`checkh(r, 68'h0000_0000_0000_0000_0);
|
||||
`checkh(and_reduce, '0);
|
||||
`checkh(or_reduce, '0);
|
||||
`checkh(xor_reduce, '0);
|
||||
`checkh(xnor_reduce, '1);
|
||||
r <= 68'hffff_ffff_ffff_ffff_e;
|
||||
end
|
||||
else if (cyc == 11) begin
|
||||
`checkh(r, 68'hffff_ffff_ffff_ffff_e);
|
||||
`checkh(and_reduce, '0);
|
||||
`checkh(or_reduce, '1);
|
||||
`checkh(xor_reduce, '1);
|
||||
`checkh(xnor_reduce, '0);
|
||||
r <= 68'hffff_ffff_ffff_ffff_f;
|
||||
end
|
||||
else if (cyc == 12) begin
|
||||
`checkh(r, 68'hffff_ffff_ffff_ffff_f);
|
||||
`checkh(and_reduce, '1);
|
||||
`checkh(or_reduce, '1);
|
||||
`checkh(xor_reduce, '0);
|
||||
`checkh(xnor_reduce, '1);
|
||||
end
|
||||
else if (cyc == 90) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
else begin
|
||||
r <= 68'd0;
|
||||
end
|
||||
end
|
||||
endmodule
|
110
test/cli/verilog/t_math_repl.v
Normal file
110
test/cli/verilog/t_math_repl.v
Normal file
|
@ -0,0 +1,110 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2004 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=1;
|
||||
|
||||
reg [63:0] rf;
|
||||
reg [63:0] rf2;
|
||||
reg [63:0] biu;
|
||||
reg b;
|
||||
|
||||
always @* begin
|
||||
rf[63:32] = biu[63:32] & {32{b}};
|
||||
rf[31:0] = {32{b}};
|
||||
rf2 = rf;
|
||||
rf2[31:0] = ~{32{b}};
|
||||
end
|
||||
|
||||
reg [31:0] src1, src0, sr, mask;
|
||||
wire [31:0] dualasr
|
||||
= ((| src1[31:4])
|
||||
? {{16{src0[31]}}, {16{src0[15]}}}
|
||||
: ( ( sr & {2{mask[31:16]}})
|
||||
| ( {{16{src0[31]}}, {16{src0[15]}}}
|
||||
& {2{~mask[31:16]}})));
|
||||
|
||||
wire [31:0] sl_mask
|
||||
= (32'hffffffff << src1[4:0]);
|
||||
|
||||
wire [31:0] sr_mask
|
||||
= {sl_mask[0], sl_mask[1],
|
||||
sl_mask[2], sl_mask[3], sl_mask[4],
|
||||
sl_mask[5], sl_mask[6], sl_mask[7],
|
||||
sl_mask[8], sl_mask[9],
|
||||
sl_mask[10], sl_mask[11],
|
||||
sl_mask[12], sl_mask[13], sl_mask[14],
|
||||
sl_mask[15], sl_mask[16],
|
||||
sl_mask[17], sl_mask[18], sl_mask[19],
|
||||
sl_mask[20], sl_mask[21],
|
||||
sl_mask[22], sl_mask[23], sl_mask[24],
|
||||
sl_mask[25], sl_mask[26],
|
||||
sl_mask[27], sl_mask[28], sl_mask[29],
|
||||
sl_mask[30], sl_mask[31]};
|
||||
|
||||
wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}};
|
||||
wire [1:0] w = {2{b}};
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (cyc!=0) begin
|
||||
cyc <= cyc + 1;
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep);
|
||||
`endif
|
||||
if (cyc==1) begin
|
||||
biu <= 64'h12451282_abadee00;
|
||||
b <= 1'b0;
|
||||
src1 <= 32'h00000001;
|
||||
src0 <= 32'h9a4f1235;
|
||||
sr <= 32'h0f19f567;
|
||||
mask <= 32'h7af07ab4;
|
||||
end
|
||||
if (cyc==2) begin
|
||||
biu <= 64'h12453382_abad8801;
|
||||
b <= 1'b1;
|
||||
if (rf != 64'h0) $stop;
|
||||
if (rf2 != 64'h00000000ffffffff) $stop;
|
||||
src1 <= 32'h0010000f;
|
||||
src0 <= 32'h028aa336;
|
||||
sr <= 32'h42ad0377;
|
||||
mask <= 32'h1ab3b906;
|
||||
if (dualasr != 32'h8f1f7060) $stop;
|
||||
if (sl_mask != 32'hfffffffe) $stop;
|
||||
if (sr_mask != 32'h7fffffff) $stop;
|
||||
if (widerep != '0) $stop;
|
||||
end
|
||||
if (cyc==3) begin
|
||||
biu <= 64'h12422382_77ad8802;
|
||||
b <= 1'b1;
|
||||
if (rf != 64'h12453382ffffffff) $stop;
|
||||
if (rf2 != 64'h1245338200000000) $stop;
|
||||
src1 <= 32'h0000000f;
|
||||
src0 <= 32'h5c158f71;
|
||||
sr <= 32'h7076c40a;
|
||||
mask <= 32'h33eb3d44;
|
||||
if (dualasr != 32'h0000ffff) $stop;
|
||||
if (sl_mask != 32'hffff8000) $stop;
|
||||
if (sr_mask != 32'h0001ffff) $stop;
|
||||
if (widerep != '1) $stop;
|
||||
end
|
||||
if (cyc==4) begin
|
||||
if (rf != 64'h12422382ffffffff) $stop;
|
||||
if (rf2 != 64'h1242238200000000) $stop;
|
||||
if (dualasr != 32'h3062cc1e) $stop;
|
||||
if (sl_mask != 32'hffff8000) $stop;
|
||||
if (sr_mask != 32'h0001ffff) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
if (widerep != '1) $stop;
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
83
test/cli/verilog/t_math_reverse.v
Normal file
83
test/cli/verilog/t_math_reverse.v
Normal file
|
@ -0,0 +1,83 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2005 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=1;
|
||||
|
||||
reg [7:0] crc;
|
||||
|
||||
// Build up assignments
|
||||
wire [7:0] bitrev;
|
||||
assign bitrev[7] = crc[0];
|
||||
assign bitrev[6] = crc[1];
|
||||
assign bitrev[5] = crc[2];
|
||||
assign bitrev[4] = crc[3];
|
||||
assign bitrev[0] = crc[7];
|
||||
assign bitrev[1] = crc[6];
|
||||
assign bitrev[2] = crc[5];
|
||||
assign bitrev[3] = crc[4];
|
||||
|
||||
// Build up always assignments
|
||||
reg [7:0] bitrevb;
|
||||
always @ (/*AS*/crc) begin
|
||||
bitrevb[7] = crc[0];
|
||||
bitrevb[6] = crc[1];
|
||||
bitrevb[5] = crc[2];
|
||||
bitrevb[4] = crc[3];
|
||||
bitrevb[0] = crc[7];
|
||||
bitrevb[1] = crc[6];
|
||||
bitrevb[2] = crc[5];
|
||||
bitrevb[3] = crc[4];
|
||||
end
|
||||
|
||||
// Build up always assignments
|
||||
reg [7:0] bitrevr;
|
||||
always @ (posedge clk) begin
|
||||
bitrevr[7] <= crc[0];
|
||||
bitrevr[6] <= crc[1];
|
||||
bitrevr[5] <= crc[2];
|
||||
bitrevr[4] <= crc[3];
|
||||
bitrevr[0] <= crc[7];
|
||||
bitrevr[1] <= crc[6];
|
||||
bitrevr[2] <= crc[5];
|
||||
bitrevr[3] <= crc[4];
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (cyc!=0) begin
|
||||
cyc<=cyc+1;
|
||||
//$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev);
|
||||
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
|
||||
if (cyc==1) begin
|
||||
crc <= 8'hed;
|
||||
end
|
||||
if (cyc==2 && bitrev!=8'hb7) $stop;
|
||||
if (cyc==3 && bitrev!=8'h5b) $stop;
|
||||
if (cyc==4 && bitrev!=8'h2d) $stop;
|
||||
if (cyc==5 && bitrev!=8'h16) $stop;
|
||||
if (cyc==6 && bitrev!=8'h8b) $stop;
|
||||
if (cyc==7 && bitrev!=8'hc5) $stop;
|
||||
if (cyc==8 && bitrev!=8'he2) $stop;
|
||||
if (cyc==9 && bitrev!=8'hf1) $stop;
|
||||
if (bitrevb != bitrev) $stop;
|
||||
if (cyc==3 && bitrevr!=8'hb7) $stop;
|
||||
if (cyc==4 && bitrevr!=8'h5b) $stop;
|
||||
if (cyc==5 && bitrevr!=8'h2d) $stop;
|
||||
if (cyc==6 && bitrevr!=8'h16) $stop;
|
||||
if (cyc==7 && bitrevr!=8'h8b) $stop;
|
||||
if (cyc==8 && bitrevr!=8'hc5) $stop;
|
||||
if (cyc==9) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
239
test/cli/verilog/t_math_shift.v
Normal file
239
test/cli/verilog/t_math_shift.v
Normal file
|
@ -0,0 +1,239 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2004 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Outputs
|
||||
ign, ign2, ign3, ign4, ign4s,
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
output [31:0] ign;
|
||||
output [3:0] ign2;
|
||||
output [11:0] ign3;
|
||||
|
||||
parameter [95:0] P6 = 6;
|
||||
localparam P64 = (1 << P6);
|
||||
|
||||
// verilator lint_off WIDTH
|
||||
localparam [4:0] PBIG23 = 1'b1 << ~73'b0;
|
||||
localparam [3:0] PBIG29 = 4'b1 << 33'h100000000;
|
||||
// verilator lint_on WIDTH
|
||||
|
||||
reg [31:0] iright;
|
||||
reg signed [31:0] irights;
|
||||
reg [31:0] ileft;
|
||||
reg [P64-1:0] qright;
|
||||
reg signed [P64-1:0] qrights;
|
||||
reg [P64-1:0] qleft;
|
||||
reg [95:0] wright;
|
||||
reg signed [95:0] wrights;
|
||||
reg [95:0] wleft;
|
||||
|
||||
reg [31:0] q_iright;
|
||||
reg signed [31:0] q_irights;
|
||||
reg [31:0] q_ileft;
|
||||
reg [P64-1:0] q_qright;
|
||||
reg signed [P64-1:0] q_qrights;
|
||||
reg [P64-1:0] q_qleft;
|
||||
reg [95:0] q_wright;
|
||||
reg signed [95:0] q_wrights;
|
||||
reg [95:0] q_wleft;
|
||||
|
||||
|
||||
reg [31:0] w_iright;
|
||||
reg signed [31:0] w_irights;
|
||||
reg [31:0] w_ileft;
|
||||
reg [P64-1:0] w_qright;
|
||||
reg signed [P64-1:0] w_qrights;
|
||||
reg [P64-1:0] w_qleft;
|
||||
reg [95:0] w_wright;
|
||||
reg signed [95:0] w_wrights;
|
||||
reg [95:0] w_wleft;
|
||||
|
||||
reg [31:0] iamt;
|
||||
reg [63:0] qamt;
|
||||
reg [95:0] wamt;
|
||||
|
||||
assign ign = {31'h0, clk} >>> 4'bx; // bug760
|
||||
assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174
|
||||
assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}},
|
||||
iamt[1:0] >> {11{iamt[5:2]}},
|
||||
$signed(iamt[1:0]) >>> {22{iamt[5:2]}},
|
||||
$signed(iamt[1:0]) >>> {11{iamt[5:2]}},
|
||||
iamt[1:0] << {22{iamt[5:2]}},
|
||||
iamt[1:0] << {11{iamt[5:2]}}};
|
||||
|
||||
wire [95:0] wamtt = {iamt,iamt,iamt};
|
||||
output wire [95:0] ign4;
|
||||
assign ign4 = wamtt >> {11{iamt[5:2]}};
|
||||
output wire signed [95:0] ign4s;
|
||||
assign ign4s = $signed(wamtt) >>> {11{iamt[5:2]}};
|
||||
|
||||
always @* begin
|
||||
iright = 32'h819b018a >> iamt;
|
||||
irights = 32'sh819b018a >>> signed'(iamt);
|
||||
ileft = 32'h819b018a << iamt;
|
||||
qright = 64'hf784bf8f_12734089 >> iamt;
|
||||
qrights = 64'shf784bf8f_12734089 >>> signed'(iamt);
|
||||
qleft = 64'hf784bf8f_12734089 << iamt;
|
||||
wright = 96'hf784bf8f_12734089_190abe48 >> iamt;
|
||||
wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(iamt);
|
||||
wleft = 96'hf784bf8f_12734089_190abe48 << iamt;
|
||||
|
||||
q_iright = 32'h819b018a >> qamt;
|
||||
q_irights = 32'sh819b018a >>> signed'(qamt);
|
||||
q_ileft = 32'h819b018a << qamt;
|
||||
q_qright = 64'hf784bf8f_12734089 >> qamt;
|
||||
q_qrights = 64'shf784bf8f_12734089 >>> signed'(qamt);
|
||||
q_qleft = 64'hf784bf8f_12734089 << qamt;
|
||||
q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt;
|
||||
q_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(qamt);
|
||||
q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt;
|
||||
|
||||
w_iright = 32'h819b018a >> wamt;
|
||||
w_irights = 32'sh819b018a >>> signed'(wamt);
|
||||
w_ileft = 32'h819b018a << wamt;
|
||||
w_qright = 64'hf784bf8f_12734089 >> wamt;
|
||||
w_qrights = 64'shf784bf8f_12734089 >>> signed'(wamt);
|
||||
w_qleft = 64'hf784bf8f_12734089 << wamt;
|
||||
w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt;
|
||||
w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt);
|
||||
w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt;
|
||||
end
|
||||
|
||||
integer cyc; initial cyc=1;
|
||||
always @ (posedge clk) begin
|
||||
if (cyc!=0) begin
|
||||
cyc <= cyc + 1;
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright);
|
||||
`endif
|
||||
if (cyc==1) begin
|
||||
iamt <= 0;
|
||||
qamt <= 0;
|
||||
wamt <= 0;
|
||||
if (P64 != 64) $stop;
|
||||
if (5'b10110>>2 != 5'b00101) $stop;
|
||||
if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness
|
||||
if (5'b10110<<2 != 5'b11000) $stop;
|
||||
if (5'b10110<<<2 != 5'b11000) $stop;
|
||||
if (5'sb10110>>2 != 5'sb00101) $stop;
|
||||
if (5'sb10110>>>2 != 5'sb11101) $stop;
|
||||
if (5'sb10110<<2 != 5'sb11000) $stop;
|
||||
if (5'sb10110<<<2 != 5'sb11000) $stop;
|
||||
// Allow >64 bit shifts if the shift amount is a constant
|
||||
if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop;
|
||||
end
|
||||
if (cyc==2) begin
|
||||
iamt <= 28;
|
||||
qamt <= 28;
|
||||
wamt <= 28;
|
||||
if (ileft != 32'h819b018a) $stop;
|
||||
if (iright != 32'h819b018a) $stop;
|
||||
if (irights != 32'h819b018a) $stop;
|
||||
if (qleft != 64'hf784bf8f_12734089) $stop;
|
||||
if (qright != 64'hf784bf8f_12734089) $stop;
|
||||
if (qrights != 64'hf784bf8f_12734089) $stop;
|
||||
if (wleft != 96'hf784bf8f12734089190abe48) $stop;
|
||||
if (wright != 96'hf784bf8f12734089190abe48) $stop;
|
||||
if (wrights != 96'hf784bf8f12734089190abe48) $stop;
|
||||
end
|
||||
if (cyc==3) begin
|
||||
iamt <= 31;
|
||||
qamt <= 31;
|
||||
wamt <= 31;
|
||||
if (ileft != 32'ha0000000) $stop;
|
||||
if (iright != 32'h8) $stop;
|
||||
if (irights != 32'hfffffff8) $stop;
|
||||
if (qleft != 64'hf127340890000000) $stop;
|
||||
if (qright != 64'h0000000f784bf8f1) $stop;
|
||||
if (qrights != 64'hffffffff784bf8f1) $stop;
|
||||
if (wleft != 96'hf12734089190abe480000000) $stop;
|
||||
if (wright != 96'h0000000f784bf8f127340891) $stop;
|
||||
if (wrights != 96'hffffffff784bf8f127340891) $stop;
|
||||
end
|
||||
if (cyc==4) begin
|
||||
iamt <= 32;
|
||||
qamt <= 32;
|
||||
wamt <= 32;
|
||||
if (ileft != 32'h0) $stop;
|
||||
if (iright != 32'h1) $stop;
|
||||
if (qleft != 64'h8939a04480000000) $stop;
|
||||
if (qright != 64'h00000001ef097f1e) $stop;
|
||||
end
|
||||
if (cyc==5) begin
|
||||
iamt <= 33;
|
||||
qamt <= 33;
|
||||
wamt <= 33;
|
||||
if (ileft != 32'h0) $stop;
|
||||
if (iright != 32'h0) $stop;
|
||||
if (qleft != 64'h1273408900000000) $stop;
|
||||
if (qright != 64'h00000000f784bf8f) $stop;
|
||||
end
|
||||
if (cyc==6) begin
|
||||
iamt <= 64;
|
||||
qamt <= 64;
|
||||
wamt <= 64;
|
||||
if (ileft != 32'h0) $stop;
|
||||
if (iright != 32'h0) $stop;
|
||||
if (qleft != 64'h24e6811200000000) $stop;
|
||||
if (qright != 64'h000000007bc25fc7) $stop;
|
||||
end
|
||||
if (cyc==7) begin
|
||||
iamt <= 128;
|
||||
qamt <= 128;
|
||||
wamt <= 128;
|
||||
if (ileft != 32'h0) $stop;
|
||||
if (iright != 32'h0) $stop;
|
||||
if (qleft != 64'h0) $stop;
|
||||
if (qright != 64'h0) $stop;
|
||||
end
|
||||
if (cyc==8) begin
|
||||
iamt <= 100;
|
||||
qamt <= {32'h10, 32'h0};
|
||||
wamt <= {32'h10, 64'h0};
|
||||
if (ileft != '0) $stop;
|
||||
if (iright != '0) $stop;
|
||||
if (irights != '1) $stop;
|
||||
if (qleft != '0) $stop;
|
||||
if (qright != '0) $stop;
|
||||
if (qrights != '1) $stop;
|
||||
if (wleft != '0) $stop;
|
||||
if (wright != '0) $stop;
|
||||
if (wrights != '1) $stop;
|
||||
end
|
||||
if (cyc==19) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
// General rule to test all q's
|
||||
if (cyc != 0) begin
|
||||
if (ileft != q_ileft) $stop;
|
||||
if (iright != q_iright) $stop;
|
||||
if (irights != q_irights) $stop;
|
||||
if (qleft != q_qleft) $stop;
|
||||
if (qright != q_qright) $stop;
|
||||
if (qrights != q_qrights) $stop;
|
||||
if (wleft != q_wleft) $stop;
|
||||
if (wright != q_wright) $stop;
|
||||
if (wrights != q_wrights) $stop;
|
||||
|
||||
if (ileft != w_ileft) $stop;
|
||||
if (iright != w_iright) $stop;
|
||||
if (irights != w_irights) $stop;
|
||||
if (qleft != w_qleft) $stop;
|
||||
if (qright != w_qright) $stop;
|
||||
if (qrights != w_qrights) $stop;
|
||||
if (wleft != w_wleft) $stop;
|
||||
if (wright != w_wright) $stop;
|
||||
if (wrights != w_wrights) $stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
64
test/cli/verilog/t_math_shift_extend.v
Normal file
64
test/cli/verilog/t_math_shift_extend.v
Normal file
|
@ -0,0 +1,64 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2020 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
logic in1 = 1;
|
||||
logic [1:0] in2 = 2'b11;
|
||||
logic [31:0] out;
|
||||
logic [7:0] ones = 8'b11111111;
|
||||
logic [9:0] ones10 = 10'b1111111111;
|
||||
|
||||
typedef logic [7:0] data_t;
|
||||
|
||||
typedef logic [9:0] ten_t;
|
||||
ten_t out10;
|
||||
|
||||
// verilator lint_off WIDTH
|
||||
initial begin
|
||||
in1 = 1;
|
||||
in2 = 0;
|
||||
out = data_t'(in1 << in2);
|
||||
if (out != 8'b1) $stop;
|
||||
|
||||
in2 = 1;
|
||||
out = data_t'(in1 << in2);
|
||||
if (out != 8'b10) $stop;
|
||||
|
||||
in2 = 2;
|
||||
out = data_t'(in1 << in2);
|
||||
if (out != 8'b100) $stop;
|
||||
|
||||
in2 = 3;
|
||||
out = data_t'(in1 << in2);
|
||||
if (out != 8'b1000) $stop;
|
||||
|
||||
// Check upper bits get cleared when cast
|
||||
in2 = 3;
|
||||
out = data_t'(ones << in2);
|
||||
if (out != 8'b11111000) $stop;
|
||||
|
||||
in2 = 3;
|
||||
out = data_t'(ones10 << in2);
|
||||
if (out != 8'b11111000) $stop;
|
||||
|
||||
// bug2597
|
||||
out = data_t'(10'h208 >> 2);
|
||||
if (out != 8'h82) $stop;
|
||||
|
||||
out = data_t'(10'h208 >> 2);
|
||||
if (out != 8'h82) $stop;
|
||||
|
||||
out = data_t'('h208 >> 2);
|
||||
if (out != 8'h82) $stop;
|
||||
|
||||
out10 = ten_t'('h404 >> 2);
|
||||
if (out10 != 10'h101) $stop;
|
||||
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish();
|
||||
end
|
||||
endmodule
|
78
test/cli/verilog/t_math_shift_rep.v
Normal file
78
test/cli/verilog/t_math_shift_rep.v
Normal file
|
@ -0,0 +1,78 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2014 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
//bug765; disappears if add this wire
|
||||
//wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values
|
||||
wire [7:0] a = crc[7:0];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [15:0] y; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.y (y[15:0]),
|
||||
// Inputs
|
||||
.a (a[7:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {48'h0, y};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'h0
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
y,
|
||||
// Inputs
|
||||
a
|
||||
);
|
||||
input signed [7:0] a;
|
||||
output [15:0] y;
|
||||
// verilator lint_off WIDTH
|
||||
assign y = ~66'd0 <<< {4{a}};
|
||||
// verilator lint_on WIDTH
|
||||
endmodule
|
88
test/cli/verilog/t_math_shift_sel.v
Normal file
88
test/cli/verilog/t_math_shift_sel.v
Normal file
|
@ -0,0 +1,88 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2017 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [106:0] in = {~crc[42:0], crc[63:0]};
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [7:0] out1; // From test of Test.v
|
||||
wire [7:0] out2; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.out1 (out1[7:0]),
|
||||
.out2 (out2[7:0]),
|
||||
// Inputs
|
||||
.in (in[106:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {48'h0, out1, out1};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= '0;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= '0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
// What checksum will we end up with (above print should match)
|
||||
`define EXPECTED_SUM 64'hc746017202a24ecc
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
out1, out2,
|
||||
// Inputs
|
||||
in
|
||||
);
|
||||
|
||||
// Replace this module with the device under test.
|
||||
//
|
||||
// Change the code in the t module to apply values to the inputs and
|
||||
// merge the output values into the result vector.
|
||||
|
||||
input [106:0] in;
|
||||
output [7:0] out1, out2;
|
||||
|
||||
// verilator lint_off WIDTH
|
||||
// Better written as onibble[99 +: 8]. Verilator will convert it.
|
||||
wire [7:0] out1 = (in >>> 99) & 255;
|
||||
// verilator lint_on WIDTH
|
||||
wire [7:0] out2 = in[106:99];
|
||||
|
||||
endmodule
|
57
test/cli/verilog/t_math_shiftrs.v
Normal file
57
test/cli/verilog/t_math_shiftrs.v
Normal file
|
@ -0,0 +1,57 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2004 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=1;
|
||||
|
||||
reg signed [64+15:0] data;
|
||||
integer i;
|
||||
integer b;
|
||||
reg signed [64+15:0] srs;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (cyc!=0) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==2) begin
|
||||
data <= 80'h0;
|
||||
data[75] <= 1'b1;
|
||||
data[10] <= 1'b1;
|
||||
end
|
||||
if (cyc==3) begin
|
||||
for (i=0; i<85; i=i+1) begin
|
||||
srs = data>>>i;
|
||||
//$write (" %x >>> %d == %x\n",data,i,srs);
|
||||
for (b=0; b<80; b=b+1) begin
|
||||
if (srs[b] != (b==(75-i) || b==(10-i))) $stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
if (cyc==10) begin
|
||||
data <= 80'h0;
|
||||
data[79] <= 1'b1;
|
||||
data[10] <= 1'b1;
|
||||
end
|
||||
if (cyc==12) begin
|
||||
for (i=0; i<85; i=i+1) begin
|
||||
srs = data>>>i;
|
||||
//$write (" %x >>> %d == %x\n",data,i,srs);
|
||||
for (b=0; b<80; b=b+1) begin
|
||||
if (srs[b] != (b>=(79-i) || b==(10-i))) $stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
if (cyc==20) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
132
test/cli/verilog/t_math_sign_extend.v
Normal file
132
test/cli/verilog/t_math_sign_extend.v
Normal file
|
@ -0,0 +1,132 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This test demonstrates an issue with sign extension.
|
||||
// Assigning to localparms larger than 32 bits broke in 3.862
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2015 by Mike Thyer.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
|
||||
localparam [ 0:0] one1_lp = 1;
|
||||
localparam [ 1:0] one2_lp = 1;
|
||||
localparam [ 2:0] one3_lp = 1;
|
||||
localparam [ 3:0] one4_lp = 1;
|
||||
localparam [ 4:0] one5_lp = 1;
|
||||
localparam [ 5:0] one6_lp = 1;
|
||||
localparam [ 6:0] one7_lp = 1;
|
||||
localparam [ 7:0] one8_lp = 1;
|
||||
localparam [ 8:0] one9_lp = 1;
|
||||
localparam [ 9:0] one10_lp = 1;
|
||||
localparam [19:0] one20_lp = 1;
|
||||
localparam [29:0] one30_lp = 1;
|
||||
localparam [30:0] one31_lp = 1;
|
||||
localparam [31:0] one32_lp = 1;
|
||||
localparam [32:0] one33_lp = 1;
|
||||
localparam [33:0] one34_lp = 1;
|
||||
localparam [34:0] one35_lp = 1;
|
||||
localparam [35:0] one36_lp = 1;
|
||||
localparam [36:0] one37_lp = 1;
|
||||
localparam [37:0] one38_lp = 1;
|
||||
localparam [38:0] one39_lp = 1;
|
||||
localparam [39:0] one40_lp = 1;
|
||||
localparam [49:0] one50_lp = 1;
|
||||
localparam [59:0] one60_lp = 1;
|
||||
localparam [60:0] one61_lp = 1;
|
||||
localparam [61:0] one62_lp = 1;
|
||||
localparam [62:0] one63_lp = 1;
|
||||
localparam [63:0] one64_lp = 1;
|
||||
localparam [64:0] one65_lp = 1;
|
||||
localparam [65:0] one66_lp = 1;
|
||||
localparam [66:0] one67_lp = 1;
|
||||
localparam [67:0] one68_lp = 1;
|
||||
localparam [68:0] one69_lp = 1;
|
||||
localparam [69:0] one70_lp = 1;
|
||||
|
||||
bit all_ok = 1;
|
||||
|
||||
initial begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$display("one1_lp : %x %d", one1_lp, one1_lp==1);
|
||||
$display("one2_lp : %x %d", one2_lp, one2_lp==1);
|
||||
$display("one3_lp : %x %d", one3_lp, one3_lp==1);
|
||||
$display("one4_lp : %x %d", one4_lp, one4_lp==1);
|
||||
$display("one5_lp : %x %d", one5_lp, one5_lp==1);
|
||||
$display("one6_lp : %x %d", one6_lp, one6_lp==1);
|
||||
$display("one7_lp : %x %d", one7_lp, one7_lp==1);
|
||||
$display("one8_lp : %x %d", one8_lp, one8_lp==1);
|
||||
$display("one9_lp : %x %d", one9_lp, one9_lp==1);
|
||||
$display("one10_lp: %x %d", one10_lp, one10_lp==1);
|
||||
$display("one20_lp: %x %d", one20_lp, one20_lp==1);
|
||||
$display("one30_lp: %x %d", one30_lp, one30_lp==1);
|
||||
$display("one31_lp: %x %d", one31_lp, one31_lp==1);
|
||||
$display("one32_lp: %x %d", one32_lp, one32_lp==1);
|
||||
$display("one33_lp: %x %d", one33_lp, one33_lp==1);
|
||||
$display("one34_lp: %x %d", one34_lp, one34_lp==1);
|
||||
$display("one35_lp: %x %d", one35_lp, one35_lp==1);
|
||||
$display("one36_lp: %x %d", one36_lp, one36_lp==1);
|
||||
$display("one37_lp: %x %d", one37_lp, one37_lp==1);
|
||||
$display("one38_lp: %x %d", one38_lp, one38_lp==1);
|
||||
$display("one39_lp: %x %d", one39_lp, one39_lp==1);
|
||||
$display("one40_lp: %x %d", one40_lp, one40_lp==1);
|
||||
$display("one50_lp: %x %d", one50_lp, one50_lp==1);
|
||||
$display("one60_lp: %x %d", one60_lp, one60_lp==1);
|
||||
$display("one61_lp: %x %d", one61_lp, one61_lp==1);
|
||||
$display("one62_lp: %x %d", one62_lp, one62_lp==1);
|
||||
$display("one63_lp: %x %d", one63_lp, one63_lp==1);
|
||||
$display("one64_lp: %x %d", one64_lp, one64_lp==1);
|
||||
$display("one65_lp: %x %d", one65_lp, one65_lp==1);
|
||||
$display("one66_lp: %x %d", one66_lp, one66_lp==1);
|
||||
$display("one67_lp: %x %d", one67_lp, one67_lp==1);
|
||||
$display("one68_lp: %x %d", one68_lp, one68_lp==1);
|
||||
$display("one69_lp: %x %d", one69_lp, one69_lp==1);
|
||||
$display("one70_lp: %x %d", one70_lp, one70_lp==1);
|
||||
`endif
|
||||
|
||||
all_ok &= one1_lp == 1;
|
||||
all_ok &= one2_lp == 1;
|
||||
all_ok &= one3_lp == 1;
|
||||
all_ok &= one4_lp == 1;
|
||||
all_ok &= one5_lp == 1;
|
||||
all_ok &= one6_lp == 1;
|
||||
all_ok &= one7_lp == 1;
|
||||
all_ok &= one8_lp == 1;
|
||||
all_ok &= one9_lp == 1;
|
||||
all_ok &= one10_lp == 1;
|
||||
all_ok &= one20_lp == 1;
|
||||
all_ok &= one30_lp == 1;
|
||||
all_ok &= one31_lp == 1;
|
||||
all_ok &= one32_lp == 1;
|
||||
all_ok &= one33_lp == 1;
|
||||
all_ok &= one34_lp == 1;
|
||||
all_ok &= one35_lp == 1;
|
||||
all_ok &= one36_lp == 1;
|
||||
all_ok &= one37_lp == 1;
|
||||
all_ok &= one38_lp == 1;
|
||||
all_ok &= one39_lp == 1;
|
||||
all_ok &= one40_lp == 1;
|
||||
all_ok &= one50_lp == 1;
|
||||
all_ok &= one60_lp == 1;
|
||||
all_ok &= one61_lp == 1;
|
||||
all_ok &= one62_lp == 1;
|
||||
all_ok &= one63_lp == 1;
|
||||
all_ok &= one64_lp == 1;
|
||||
all_ok &= one65_lp == 1;
|
||||
all_ok &= one66_lp == 1;
|
||||
all_ok &= one67_lp == 1;
|
||||
all_ok &= one68_lp == 1;
|
||||
all_ok &= one69_lp == 1;
|
||||
all_ok &= one70_lp == 1;
|
||||
|
||||
if (!all_ok) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
|
||||
end
|
||||
endmodule
|
67
test/cli/verilog/t_math_signed2.v
Normal file
67
test/cli/verilog/t_math_signed2.v
Normal file
|
@ -0,0 +1,67 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2007 by Peter Debacker.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
reg [10:0] in;
|
||||
reg signed[7:0] min;
|
||||
reg signed[7:0] max;
|
||||
wire signed[7:0] filtered_data;
|
||||
reg signed[7:0] delay_minmax[31:0];
|
||||
integer k;
|
||||
|
||||
initial begin
|
||||
in = 11'b10000001000;
|
||||
for(k=0;k<32;k=k+1)
|
||||
delay_minmax[k] = 0;
|
||||
end
|
||||
|
||||
assign filtered_data = $signed(in[10:3]);
|
||||
|
||||
always @(posedge clk) begin
|
||||
in = in + 8;
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("filtered_data: %d\n", filtered_data);
|
||||
`endif
|
||||
// delay line shift
|
||||
for (k=31;k>0;k=k-1) begin
|
||||
delay_minmax[k] = delay_minmax[k-1];
|
||||
end
|
||||
delay_minmax[0] = filtered_data;
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("delay_minmax[0] = %d\n", delay_minmax[0]);
|
||||
$write("delay_minmax[31] = %d\n", delay_minmax[31]);
|
||||
`endif
|
||||
// find min and max
|
||||
min = 127;
|
||||
max = -128;
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("max init: %d\n", max);
|
||||
$write("min init: %d\n", min);
|
||||
`endif
|
||||
for(k=0;k<32;k=k+1) begin
|
||||
if ((delay_minmax[k]) > $signed(max))
|
||||
max = delay_minmax[k];
|
||||
if ((delay_minmax[k]) < $signed(min))
|
||||
min = delay_minmax[k];
|
||||
end
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("max: %d\n", max);
|
||||
$write("min: %d\n", min);
|
||||
`endif
|
||||
if (min == 127) begin
|
||||
$stop;
|
||||
end
|
||||
else if (filtered_data >= -61) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
101
test/cli/verilog/t_math_signed3.v
Normal file
101
test/cli/verilog/t_math_signed3.v
Normal file
|
@ -0,0 +1,101 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2014 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
// verilator lint_off WIDTH
|
||||
wire [1:0] bug729_au = ~0;
|
||||
wire signed [1:0] bug729_as = ~0;
|
||||
wire [2:0] bug729_b = ~0;
|
||||
// the $signed output is unsigned because the input is unsigned; the signedness does not change.
|
||||
wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0
|
||||
wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0
|
||||
wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1
|
||||
wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1
|
||||
wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0
|
||||
wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0
|
||||
wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1
|
||||
wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1
|
||||
|
||||
wire [3:0] bug733_a = 4'b0010;
|
||||
wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned
|
||||
wire signed [3:0] bug733_ys = $signed(|bug733_a); // 4'b1111
|
||||
|
||||
wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111
|
||||
wire signed [3:0] bug733_zs = $signed(2'sb11); // 4'b1111
|
||||
|
||||
// When RHS of assignment is fewer bits than lhs, RHS sign or zero extends based on RHS's sign
|
||||
|
||||
wire [3:0] bug733_qu = 2'sb11; // 4'b1111
|
||||
wire signed [3:0] bug733_qs = 2'sb11; // 4'b1111
|
||||
reg signed [32:0] bug349_s;
|
||||
reg signed [32:0] bug349_u;
|
||||
|
||||
wire signed [1:0] sb11 = 2'sb11;
|
||||
|
||||
wire [3:0] subout_u;
|
||||
sub sub (.a(2'sb11), .z(subout_u));
|
||||
initial `checkh(subout_u, 4'b1111);
|
||||
|
||||
wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111;
|
||||
initial `checkh(cond_a, 6'b111111);
|
||||
wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111;
|
||||
initial `checkh(cond_b, 6'b111111);
|
||||
|
||||
initial begin
|
||||
// verilator lint_on WIDTH
|
||||
`checkh(bug729_yuu, 1'b0);
|
||||
`checkh(bug729_ysu, 1'b0);
|
||||
`checkh(bug729_yus, 1'b1);
|
||||
`checkh(bug729_yss, 1'b1);
|
||||
|
||||
`checkh(bug729_zuu, 1'b0);
|
||||
`checkh(bug729_zsu, 1'b0);
|
||||
`checkh(bug729_zus, 1'b1);
|
||||
`checkh(bug729_zss, 1'b1);
|
||||
|
||||
`checkh(bug733_yu, 4'b1111);
|
||||
`checkh(bug733_ys, 4'b1111);
|
||||
|
||||
`checkh(bug733_zu, 4'b1111);
|
||||
`checkh(bug733_zs, 4'b1111);
|
||||
|
||||
`checkh(bug733_qu, 4'b1111);
|
||||
`checkh(bug733_qs, 4'b1111);
|
||||
|
||||
// verilator lint_off WIDTH
|
||||
bug349_s = 4'sb1111;
|
||||
`checkh(bug349_s, 33'h1ffffffff);
|
||||
bug349_u = 4'sb1111;
|
||||
`checkh(bug349_u, 33'h1ffffffff);
|
||||
|
||||
bug349_s = 4'sb1111 - 1'b1;
|
||||
`checkh(bug349_s,33'he);
|
||||
|
||||
bug349_s = 4'sb1111 - 5'b00001;
|
||||
`checkh(bug349_s,33'he);
|
||||
|
||||
case (2'sb11)
|
||||
4'b1111: ;
|
||||
default: $stop;
|
||||
endcase
|
||||
|
||||
case (sb11)
|
||||
4'b1111: ;
|
||||
default: $stop;
|
||||
endcase
|
||||
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub (input [3:0] a,
|
||||
output [3:0] z);
|
||||
assign z = a;
|
||||
endmodule
|
141
test/cli/verilog/t_math_signed4.v
Normal file
141
test/cli/verilog/t_math_signed4.v
Normal file
|
@ -0,0 +1,141 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2014 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
|
||||
`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
bit fail;
|
||||
|
||||
localparam signed [3:0] bug737_p1 = 4'b1000;
|
||||
|
||||
wire [3:0] bug737_a = 4'b1010;
|
||||
reg [5:0] bug737_y;
|
||||
reg signed [3:0] w4_s;
|
||||
reg signed [4:0] w5_s;
|
||||
reg [3:0] w4_u;
|
||||
reg [4:0] w5_u;
|
||||
reg signed [8:0] w9_s;
|
||||
real r;
|
||||
initial begin
|
||||
// verilator lint_off WIDTH
|
||||
bug737_y = bug737_a + (bug737_p1 + 4'sb0);
|
||||
`checkh(bug737_y, 6'b010010); //bug737
|
||||
|
||||
// 6u +[6u] 4s +[6s] 6s
|
||||
bug737_y = 6'b001010 + (4'sb1000 + 6'sb0);
|
||||
`checkh(bug737_y, 6'b010010); //bug737, getx 000010
|
||||
|
||||
// 6u +[6u] 4s +[6s] 6s
|
||||
bug737_y = 6'b001010 + (4'b1000 + 6'sb0);
|
||||
`checkh(bug737_y, 6'b010010); //ok
|
||||
|
||||
bug737_y = 6'b001010 + (6'sb111000 + 6'sb0);
|
||||
`checkh(bug737_y, 6'b000010); //ok
|
||||
|
||||
// v--- sign extends to 6-bits
|
||||
bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0);
|
||||
`checkh(bug737_y, 6'b000010); //ok
|
||||
|
||||
// From t_math_signed_3
|
||||
w4_s = 4'sb1111 - 1'b1;
|
||||
`checkh(w4_s,33'he);
|
||||
|
||||
w4_s = 4'sb1111 - 5'b00001;
|
||||
`checkh(w4_s,33'he);
|
||||
|
||||
w4_s = 4'sb1111 - 1'sb1;
|
||||
`checkh(w4_s,4'h0);
|
||||
w5_s = 4'sb1111 - 1'sb1;
|
||||
`checkh(w5_s,4'h0);
|
||||
|
||||
w4_s = 4'sb1111 - 4'sb1111;
|
||||
`checkh(w4_s,4'h0);
|
||||
w5_s = 4'sb1111 - 4'sb1111;
|
||||
`checkh(w5_s,5'h0);
|
||||
|
||||
// The assign LHS being signed or unsigned does not matter per IEEE
|
||||
// The upper add being signed DOES matter propagating to lower
|
||||
w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add
|
||||
`checkh(w4_s,4'he);
|
||||
w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend
|
||||
`checkh(w4_s,4'h0);
|
||||
w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend
|
||||
`checkh(w4_s,4'he); // BUG, Verilator says 'h0
|
||||
|
||||
w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS
|
||||
`checkh(w5_u, 5'b10000);
|
||||
w4_u = 4'b1111 + 4'b0001; // Normal case
|
||||
`checkh(w4_u, 4'b0000);
|
||||
|
||||
// Another example of promotion, the add is 4 bits wide
|
||||
w4_u = 3'b111 + 3'b010;
|
||||
`checkh(w4_u, 4'b1001);
|
||||
//
|
||||
w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter
|
||||
`checkh(w4_u, 4'sb1111);
|
||||
w4_s = 3'sb111 * 3'sb001; // Signed output
|
||||
`checkh(w4_s, 4'sb1111);
|
||||
w4_s = 3'b111 * 3'sb001; // Unsigned output
|
||||
`checkh(w4_s, 4'b0111);
|
||||
|
||||
// Conditionals get width from parent; are assignment-like
|
||||
w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11);
|
||||
`checkh(w4_u, 4'b0100);
|
||||
w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000);
|
||||
`checkh(w4_u, 4'b0000);
|
||||
|
||||
// If RHS is larger, that larger size is used
|
||||
w4_u = 5'b10000 / 5'b00100;
|
||||
`checkh(w4_u, 4'b0100);
|
||||
|
||||
// bug754
|
||||
w5_u = 4'sb0010 << -2'sd1; // << 3
|
||||
`ifdef VCS
|
||||
`checkh(w5_u, 5'b00000); // VCS E-2014.03 bug
|
||||
`else
|
||||
`checkh(w5_u, 5'b10000); // VCS E-2014.03 bug
|
||||
`endif
|
||||
w5_u = 4'sb1000 << 0; // Sign extends
|
||||
`checkh(w5_u, 5'b11000);
|
||||
|
||||
// Reals do not propagate to children
|
||||
r = 1.0 + ( 1 + (1 / 2));
|
||||
`checkf(r, 2.0);
|
||||
|
||||
// Self determined sign extension
|
||||
r = $itor(3'sb111);
|
||||
`checkf(r, -1.0);
|
||||
|
||||
// If any part of case is real, all is real
|
||||
case (22)
|
||||
22.0: ;
|
||||
22.1: $stop;
|
||||
default: $stop;
|
||||
endcase
|
||||
|
||||
// bug759
|
||||
w5_u = { -4'sd7 };
|
||||
`checkh(w5_u, 5'b01001);
|
||||
w5_u = {2{ -2'sd1 }};
|
||||
`checkh(w5_u, 5'b01111);
|
||||
// Don't break concats....
|
||||
w5_u = {{0{1'b1}}, -4'sd7 };
|
||||
`checkh(w5_u, 5'b01001);
|
||||
w9_s = { -4'sd7, -4'sd7 };
|
||||
`checkh(w9_s, 9'b010011001);
|
||||
{w5_u, {w4_u}} = 9'b10101_1100;
|
||||
`checkh(w5_u, 5'b10101);
|
||||
`checkh(w4_u, 4'b1100);
|
||||
{w4_u} = 4'b1011;
|
||||
`checkh(w4_u, 4'b1011);
|
||||
|
||||
if (fail) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
37
test/cli/verilog/t_math_signed6.v
Normal file
37
test/cli/verilog/t_math_signed6.v
Normal file
|
@ -0,0 +1,37 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2015 by Iztok Jeras.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
// signed source
|
||||
logic signed [8-1:0] src;
|
||||
|
||||
// destination structure
|
||||
struct packed {
|
||||
logic signed [16-1:0] s;
|
||||
logic unsigned [16-1:0] u;
|
||||
} dst;
|
||||
|
||||
initial begin
|
||||
// bug882
|
||||
// verilator lint_off WIDTH
|
||||
src = 8'sh05;
|
||||
dst = '{s: src, u: src};
|
||||
`checkh (dst.s, 16'h0005);
|
||||
`checkh (dst.u, 16'h0005);
|
||||
|
||||
src = 8'shf5;
|
||||
dst = '{s: src, u: src};
|
||||
`checkh (dst.s, 16'hfff5);
|
||||
`checkh (dst.u, 16'hfff5);
|
||||
// verilator lint_on WIDTH
|
||||
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
45
test/cli/verilog/t_math_signed7.v
Normal file
45
test/cli/verilog/t_math_signed7.v
Normal file
|
@ -0,0 +1,45 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2015 by Iztok Jeras.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
reg alu_ltu, alu_lts;
|
||||
logic [3:0] in_op1;
|
||||
logic [3:0] in_op2;
|
||||
|
||||
|
||||
reg aaa_ltu, aaa_lts;
|
||||
always @(posedge clk) begin
|
||||
in_op1 = 4'sb1110;
|
||||
in_op2 = 4'b0010;
|
||||
aaa_ltu = in_op1 < in_op2;
|
||||
// bug999
|
||||
aaa_lts = $signed(in_op1) < $signed(in_op2);
|
||||
`checkh (aaa_ltu, 1'b0);
|
||||
`checkh (aaa_lts, 1'b1);
|
||||
end
|
||||
|
||||
generate if (1) begin
|
||||
always @(posedge clk) begin
|
||||
in_op1 = 4'sb1110;
|
||||
in_op2 = 4'b0010;
|
||||
alu_ltu = in_op1 < in_op2;
|
||||
// bug999
|
||||
alu_lts = $signed(in_op1) < $signed(in_op2);
|
||||
`checkh (alu_ltu, 1'b0);
|
||||
`checkh (alu_lts, 1'b1);
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
54
test/cli/verilog/t_math_signed_wire.v
Normal file
54
test/cli/verilog/t_math_signed_wire.v
Normal file
|
@ -0,0 +1,54 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2012 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// bug511
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [7:0] au;
|
||||
wire [7:0] as;
|
||||
|
||||
Test1 test1 (.au);
|
||||
Test2 test2 (.as);
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] result=%x %x\n",$time, au, as);
|
||||
`endif
|
||||
if (au != 'h12) $stop;
|
||||
if (as != 'h02) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test1 (output [7:0] au);
|
||||
wire [7:0] b;
|
||||
wire signed [3:0] c;
|
||||
|
||||
// verilator lint_off WIDTH
|
||||
assign c=-1; // 'hf
|
||||
assign b=3; // 'h3
|
||||
assign au=b+c; // 'h12
|
||||
// verilator lint_on WIDTH
|
||||
endmodule
|
||||
|
||||
|
||||
module Test2 (output [7:0] as);
|
||||
wire signed [7:0] b;
|
||||
wire signed [3:0] c;
|
||||
|
||||
// verilator lint_off WIDTH
|
||||
assign c=-1; // 'hf
|
||||
assign b=3; // 'h3
|
||||
assign as=b+c; // 'h12
|
||||
// verilator lint_on WIDTH
|
||||
endmodule
|
20
test/cli/verilog/t_math_strwidth.v
Normal file
20
test/cli/verilog/t_math_strwidth.v
Normal file
|
@ -0,0 +1,20 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2008-2008 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
reg [4*8:1] strg;
|
||||
|
||||
initial begin
|
||||
strg = "CHK";
|
||||
if (strg != "CHK") $stop;
|
||||
if (strg == "JOE") $stop;
|
||||
$write("String = %s = %x\n", strg, strg);
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
41
test/cli/verilog/t_math_svl2.v
Normal file
41
test/cli/verilog/t_math_svl2.v
Normal file
|
@ -0,0 +1,41 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2006 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
integer cyc; initial cyc=1;
|
||||
always @ (posedge clk) begin
|
||||
if (cyc!=0) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==1) begin
|
||||
// New number format
|
||||
if ('0 !== {66{1'b0}}) $stop;
|
||||
if ('1 !== {66{1'b1}}) $stop;
|
||||
if ('x !== {66{1'bx}}) $stop;
|
||||
if ('z !== {66{1'bz}}) $stop;
|
||||
`ifndef NC // NC-Verilog 5.50-s09 chokes on this test
|
||||
if ("\v" != 8'd11) $stop;
|
||||
if ("\f" != 8'd12) $stop;
|
||||
if ("\a" != 8'd7) $stop;
|
||||
if ("\x9a" != 8'h9a) $stop;
|
||||
if ("\xf1" != 8'hf1) $stop;
|
||||
`endif
|
||||
end
|
||||
if (cyc==8) begin
|
||||
end
|
||||
if (cyc==9) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
165
test/cli/verilog/t_math_swap.v
Normal file
165
test/cli/verilog/t_math_swap.v
Normal file
|
@ -0,0 +1,165 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2008 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [31:0] Operand1 = crc[31:0];
|
||||
wire [15:0] Operand2 = crc[47:32];
|
||||
wire Unsigned = crc[48];
|
||||
reg rst;
|
||||
|
||||
parameter wl = 16;
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [wl-1:0] Quotient; // From test of Test.v
|
||||
wire [wl-1:0] Remainder; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.Quotient (Quotient[wl-1:0]),
|
||||
.Remainder (Remainder[wl-1:0]),
|
||||
// Inputs
|
||||
.Operand1 (Operand1[wl*2-1:0]),
|
||||
.Operand2 (Operand2[wl-1:0]),
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.Unsigned (Unsigned));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {32'h0, Quotient, Remainder};
|
||||
|
||||
// What checksum will we end up with
|
||||
`define EXPECTED_SUM 64'h98d41f89a8be5693
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x it=%x\n",$time, cyc, crc, result, test.Iteration);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
if (cyc < 20 || test.Iteration==4'd15) begin
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
end
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
rst <= 1'b1;
|
||||
end
|
||||
else if (cyc<20) begin
|
||||
sum <= 64'h0;
|
||||
rst <= 1'b0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'h8dd70a44972ad809) $stop;
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder);
|
||||
|
||||
parameter wl = 16;
|
||||
|
||||
input [wl*2-1:0] Operand1;
|
||||
input [wl-1:0] Operand2;
|
||||
input clk, rst, Unsigned;
|
||||
output [wl-1:0] Quotient, Remainder;
|
||||
|
||||
reg Cy, Overflow, Sign1, Sign2, Zero, Negative;
|
||||
reg [wl-1:0] ah,al,Quotient, Remainder;
|
||||
reg [3:0] Iteration;
|
||||
reg [wl-1:0] sub_quot,op;
|
||||
reg ah_ext;
|
||||
|
||||
reg [1:0] a,b,c,d,e;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!rst) begin
|
||||
{a,b,c,d,e} = Operand1[9:0];
|
||||
{a,b,c,d,e} = {e,d,c,b,a};
|
||||
if (a != Operand1[1:0]) $stop;
|
||||
if (b != Operand1[3:2]) $stop;
|
||||
if (c != Operand1[5:4]) $stop;
|
||||
if (d != Operand1[7:6]) $stop;
|
||||
if (e != Operand1[9:8]) $stop;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
Iteration <= 0;
|
||||
Quotient <= 0;
|
||||
Remainder <= 0;
|
||||
end
|
||||
else begin
|
||||
if (Iteration == 0) begin
|
||||
{ah,al} = Operand1;
|
||||
op = Operand2;
|
||||
Cy = 0;
|
||||
Overflow = 0;
|
||||
Sign1 = (~Unsigned)&ah[wl-1];
|
||||
Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]);
|
||||
if (Sign1) {ah,al} = -{ah,al};
|
||||
end
|
||||
`define BUG1
|
||||
`ifdef BUG1
|
||||
{ah_ext,ah,al} = {ah,al,Cy};
|
||||
`else
|
||||
ah_ext = ah[15];
|
||||
ah[15:1] = ah[14:0];
|
||||
ah[0] = al[15];
|
||||
al[15:1] = al[14:0];
|
||||
al[0] = Cy;
|
||||
`endif
|
||||
`ifdef TEST_VERBOSE
|
||||
$display("%x %x %x %x %x %x %x %x %x",
|
||||
Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy);
|
||||
`endif
|
||||
{Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op};
|
||||
if (Cy)
|
||||
begin
|
||||
{ah_ext,ah} = {1'b0,sub_quot};
|
||||
end
|
||||
if (Iteration != 15 )
|
||||
begin
|
||||
if (ah_ext) Overflow = 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (al[14] && ~Unsigned) Overflow = 1;
|
||||
Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy};
|
||||
Remainder <= Sign1 ? -ah : ah;
|
||||
if (Overflow)
|
||||
begin
|
||||
Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}};
|
||||
Remainder <= Unsigned ? 16'hffff : 16'h8000;
|
||||
Zero = 1;
|
||||
Negative = 1;
|
||||
end
|
||||
end
|
||||
Iteration <= Iteration + 1; // Count number of times this instruction is repeated
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
22
test/cli/verilog/t_math_tri.v
Normal file
22
test/cli/verilog/t_math_tri.v
Normal file
|
@ -0,0 +1,22 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2003 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
reg [3:0] a;
|
||||
reg [99:0] x;
|
||||
|
||||
initial begin
|
||||
a = 4'b010x;
|
||||
if (a[3:2] !== 2'b01) $stop;
|
||||
if (|a !== 1'b1) $stop;
|
||||
if (&a !== 1'b0) $stop;
|
||||
x = 100'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
104
test/cli/verilog/t_math_vliw.v
Normal file
104
test/cli/verilog/t_math_vliw.v
Normal file
|
@ -0,0 +1,104 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2005 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
integer cyc; initial cyc=0;
|
||||
reg [7:0] crc;
|
||||
reg [223:0] sum;
|
||||
|
||||
wire [255:0] mglehy = {32{~crc}};
|
||||
wire [215:0] drricx = {27{crc}};
|
||||
wire [15:0] apqrli = {2{~crc}};
|
||||
wire [2:0] szlfpf = crc[2:0];
|
||||
wire [15:0] dzosui = {2{crc}};
|
||||
wire [31:0] zndrba = {16{crc[1:0]}};
|
||||
wire [223:0] bxiouf;
|
||||
|
||||
vliw vliw (
|
||||
// Outputs
|
||||
.bxiouf (bxiouf),
|
||||
// Inputs
|
||||
.mglehy (mglehy[255:0]),
|
||||
.drricx (drricx[215:0]),
|
||||
.apqrli (apqrli[15:0]),
|
||||
.szlfpf (szlfpf[2:0]),
|
||||
.dzosui (dzosui[15:0]),
|
||||
.zndrba (zndrba[31:0]));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 8'hed;
|
||||
sum <= 224'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
//$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf);
|
||||
sum <= {sum[222:0],sum[223]} ^ bxiouf;
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 8'b01110000) $stop;
|
||||
if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module vliw (
|
||||
input[255:0] mglehy,
|
||||
input[215:0] drricx,
|
||||
input[15:0] apqrli,
|
||||
input[2:0] szlfpf,
|
||||
input[15:0] dzosui,
|
||||
input[31:0] zndrba,
|
||||
output wire [223:0] bxiouf
|
||||
);
|
||||
|
||||
wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]})
|
||||
| ({29{apqrli}} & {mglehy[247:0], drricx});
|
||||
wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128])
|
||||
| ({21{dzosui}} & zhknfc[335:0]);
|
||||
wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
|
||||
wire [223:0] rzyeut = viuvoc[335:112];
|
||||
assign bxiouf = {rzyeut[7:0],
|
||||
rzyeut[15:8],
|
||||
rzyeut[23:16],
|
||||
rzyeut[31:24],
|
||||
rzyeut[39:32],
|
||||
rzyeut[47:40],
|
||||
rzyeut[55:48],
|
||||
rzyeut[63:56],
|
||||
rzyeut[71:64],
|
||||
rzyeut[79:72],
|
||||
rzyeut[87:80],
|
||||
rzyeut[95:88],
|
||||
rzyeut[103:96],
|
||||
rzyeut[111:104],
|
||||
rzyeut[119:112],
|
||||
rzyeut[127:120],
|
||||
rzyeut[135:128],
|
||||
rzyeut[143:136],
|
||||
rzyeut[151:144],
|
||||
rzyeut[159:152],
|
||||
rzyeut[167:160],
|
||||
rzyeut[175:168],
|
||||
rzyeut[183:176],
|
||||
rzyeut[191:184],
|
||||
rzyeut[199:192],
|
||||
rzyeut[207:200],
|
||||
rzyeut[215:208],
|
||||
rzyeut[223:216]};
|
||||
|
||||
endmodule
|
59
test/cli/verilog/t_math_width.v
Normal file
59
test/cli/verilog/t_math_width.v
Normal file
|
@ -0,0 +1,59 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2014 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ();
|
||||
|
||||
// See also t_lint_width
|
||||
|
||||
parameter A_ONE = '1;
|
||||
// verilator lint_off WIDTH
|
||||
parameter [3:0] A_W4 = A_ONE;
|
||||
// verilator lint_on WIDTH
|
||||
initial begin
|
||||
if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop;
|
||||
if ($bits(A_W4) != 4) $stop;
|
||||
if (A_W4 != 4'b0001) $stop;
|
||||
end
|
||||
|
||||
b #(.B_WIDTH(48)) b ();
|
||||
|
||||
reg [4:0] c;
|
||||
integer c_i;
|
||||
initial begin
|
||||
c_i = 3;
|
||||
c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax
|
||||
if (c != 5'b1000) $stop;
|
||||
end
|
||||
|
||||
localparam D_TT = 32'd23;
|
||||
localparam D_SIX = 6;
|
||||
// verilator lint_off WIDTH
|
||||
localparam [5:0] D_SUB = D_TT - D_SIX;
|
||||
// verilator lint_on WIDTH
|
||||
initial begin
|
||||
if (D_SUB != 17) $stop;
|
||||
end
|
||||
|
||||
initial begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module b;
|
||||
parameter B_WIDTH = 1;
|
||||
localparam B_VALUE0 = {B_WIDTH{1'b0}};
|
||||
localparam B_VALUE1 = {B_WIDTH{1'b1}};
|
||||
reg [47:0] b_val;
|
||||
initial begin
|
||||
b_val = B_VALUE0;
|
||||
if (b_val != 48'b0) $stop;
|
||||
b_val = B_VALUE1;
|
||||
if (b_val != ~48'b0) $stop;
|
||||
end
|
||||
endmodule
|
84
test/cli/verilog/t_math_yosys.v
Normal file
84
test/cli/verilog/t_math_yosys.v
Normal file
|
@ -0,0 +1,84 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2020 Claire Wolf.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t(/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [7:0] y1; // From d1 of demo_001.v
|
||||
wire [7:0] y2; // From d1 of demo_001.v
|
||||
wire [7:0] y3; // From d1 of demo_001.v
|
||||
wire [7:0] y4; // From d1 of demo_001.v
|
||||
wire [31:0] z0; // From d2 of demo_002.v
|
||||
wire [31:0] z1; // From d2 of demo_002.v
|
||||
wire [31:0] z2; // From d2 of demo_002.v
|
||||
wire [31:0] z3; // From d2 of demo_002.v
|
||||
// End of automatics
|
||||
|
||||
demo_001 d1(/*AUTOINST*/
|
||||
// Outputs
|
||||
.y1 (y1[7:0]),
|
||||
.y2 (y2[7:0]),
|
||||
.y3 (y3[7:0]),
|
||||
.y4 (y4[7:0]));
|
||||
demo_002 d2(/*AUTOINST*/
|
||||
// Outputs
|
||||
.z0 (z0[31:0]),
|
||||
.z1 (z1[31:0]),
|
||||
.z2 (z2[31:0]),
|
||||
.z3 (z3[31:0]));
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (y1 !== 8'h7b) $stop;
|
||||
if (y2 !== 8'h7c) $stop;
|
||||
if (y3 !== 8'h7b) $stop;
|
||||
if (y4 !== 8'h7c) $stop;
|
||||
if (z0 !== 32'h00000000) $stop;
|
||||
if (z1 !== 32'hffffffff) $stop;
|
||||
if (z2 !== 32'hffffffff) $stop;
|
||||
if (z3 !== 32'hffffffff) $stop;
|
||||
if (cyc == 99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module demo_001(y1, y2, y3, y4);
|
||||
output [7:0] y1, y2, y3, y4;
|
||||
|
||||
// verilator lint_off REALCVT
|
||||
localparam [7:0] p1 = 123.45;
|
||||
localparam real p2 = 123.45;
|
||||
localparam real p3 = 123;
|
||||
localparam p4 = 123.45;
|
||||
|
||||
// verilator lint_off WIDTH
|
||||
assign y1 = p1 + 0.2;
|
||||
assign y2 = p2 + 0.2;
|
||||
assign y3 = p3 + 0.2;
|
||||
assign y4 = p4 + 0.2;
|
||||
// verilator lint_on WIDTH
|
||||
endmodule
|
||||
|
||||
module demo_002(z0, z1, z2, z3);
|
||||
output [31:0] z0, z1, z2, z3;
|
||||
|
||||
// verilator lint_off WIDTH
|
||||
assign z0 = 1'bx >= (-1 * -1.17);
|
||||
// verilator lint_on WIDTH
|
||||
assign z1 = 1 ? 1 ? -1 : 'd0 : 0.0;
|
||||
assign z2 = 1 ? -1 : 1 ? 'd0 : 0.0;
|
||||
assign z3 = 1 ? -1 : 'd0;
|
||||
endmodule
|
73
test/cli/verilog/t_mem_banks.v
Normal file
73
test/cli/verilog/t_mem_banks.v
Normal file
|
@ -0,0 +1,73 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2017 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/);
|
||||
|
||||
reg [5:0] addr;
|
||||
|
||||
parameter BANKS = 6;
|
||||
parameter ROWS = 8;
|
||||
|
||||
wire [2:0] bank;
|
||||
wire [2:0] row;
|
||||
|
||||
integer a;
|
||||
integer used[BANKS][ROWS];
|
||||
|
||||
// Test loop
|
||||
initial begin
|
||||
for (a = 0; a < BANKS*ROWS; ++a) begin
|
||||
addr[5:0] = a[5:0];
|
||||
hash (addr, bank, row);
|
||||
used [bank][row] ++;
|
||||
if (used [bank][row] > 1) begin
|
||||
$write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row);
|
||||
end
|
||||
end
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
task hash (input [5:0] addr,
|
||||
output [2:0] bank,
|
||||
output [2:0] row);
|
||||
|
||||
reg [1:0] third;
|
||||
reg [1:0] fourth;
|
||||
|
||||
third = {addr[5], addr[4]};
|
||||
fourth = {addr[3] ^ addr[1],
|
||||
addr[2] ^ addr[0]};
|
||||
|
||||
case (third)
|
||||
2'h0:
|
||||
case (fourth)
|
||||
2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end
|
||||
2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end
|
||||
2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end
|
||||
2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end
|
||||
endcase
|
||||
|
||||
2'h1:
|
||||
case (fourth)
|
||||
2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end
|
||||
2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end
|
||||
2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end
|
||||
2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end
|
||||
endcase
|
||||
|
||||
2'h2:
|
||||
case (fourth)
|
||||
2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end
|
||||
2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end
|
||||
2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end
|
||||
2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end
|
||||
endcase
|
||||
|
||||
2'h3: $stop;
|
||||
endcase
|
||||
endtask
|
||||
endmodule
|
31
test/cli/verilog/t_mem_cond.v
Normal file
31
test/cli/verilog/t_mem_cond.v
Normal file
|
@ -0,0 +1,31 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2006 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Outputs
|
||||
b,
|
||||
// Inputs
|
||||
clk, en, a
|
||||
);
|
||||
|
||||
// bug1017
|
||||
|
||||
input clk;
|
||||
|
||||
input en;
|
||||
input a[1];
|
||||
output logic b[1];
|
||||
|
||||
always_ff @ (posedge clk) begin
|
||||
b <= en ? a : b;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
111
test/cli/verilog/t_mem_fifo.v
Normal file
111
test/cli/verilog/t_mem_fifo.v
Normal file
|
@ -0,0 +1,111 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2006 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
integer cyc; initial cyc=0;
|
||||
reg [63:0] crc;
|
||||
|
||||
wire [65:0] outData; // From fifo of fifo.v
|
||||
wire [15:0] inData = crc[15:0];
|
||||
wire [1:0] inWordPtr = crc[17:16];
|
||||
wire wrEn = crc[20];
|
||||
wire [1:0] wrPtr = crc[33:32];
|
||||
wire [1:0] rdPtr = crc[34:33];
|
||||
|
||||
fifo fifo (
|
||||
// Outputs
|
||||
.outData (outData[65:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.inWordPtr (inWordPtr[1:0]),
|
||||
.inData (inData[15:0]),
|
||||
.rdPtr (rdPtr),
|
||||
.wrPtr (wrPtr),
|
||||
.wrEn (wrEn));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
end
|
||||
else if (cyc==90) begin
|
||||
if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop;
|
||||
end
|
||||
else if (cyc==91) begin
|
||||
if (outData[63:0] != 64'hef77cd9b13a866f0) $stop;
|
||||
end
|
||||
else if (cyc==92) begin
|
||||
if (outData[63:0] != 64'h2750cd9b13a866f0) $stop;
|
||||
end
|
||||
else if (cyc==93) begin
|
||||
if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop;
|
||||
end
|
||||
else if (cyc==94) begin
|
||||
if (outData[63:0] != 64'h9d41bc276f0984ea) $stop;
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module fifo (/*AUTOARG*/
|
||||
// Outputs
|
||||
outData,
|
||||
// Inputs
|
||||
clk, inWordPtr, inData, wrPtr, rdPtr, wrEn
|
||||
);
|
||||
|
||||
parameter fifoDepthLog2 = 1;
|
||||
parameter fifoDepth = 1<<fifoDepthLog2;
|
||||
|
||||
`define PTRBITS (fifoDepthLog2+1)
|
||||
`define PTRBITSM1 fifoDepthLog2
|
||||
`define PTRBITSM2 (fifoDepthLog2-1)
|
||||
|
||||
input clk;
|
||||
input [1:0] inWordPtr;
|
||||
input [15:0] inData;
|
||||
input [`PTRBITSM1:0] wrPtr;
|
||||
input [`PTRBITSM1:0] rdPtr;
|
||||
|
||||
output [65:0] outData;
|
||||
input wrEn;
|
||||
|
||||
reg [65:0] outData;
|
||||
|
||||
// verilator lint_off VARHIDDEN
|
||||
// verilator lint_off LITENDIAN
|
||||
reg [65:0] fifo[0:fifoDepth-1];
|
||||
// verilator lint_on LITENDIAN
|
||||
// verilator lint_on VARHIDDEN
|
||||
|
||||
//reg [65:0] temp;
|
||||
|
||||
always @(posedge clk) begin
|
||||
//$write ("we=%x PT=%x ID=%x D=%x\n", wrEn, wrPtr[`PTRBITSM2:0], {1'b0,~inWordPtr,4'b0}, inData[15:0]);
|
||||
if (wrEn) begin
|
||||
fifo[ wrPtr[`PTRBITSM2:0] ][{1'b0,~inWordPtr,4'b0}+:16] <= inData[15:0];
|
||||
// Equivelent to:
|
||||
//temp = fifo[ wrPtr[`PTRBITSM2:0] ];
|
||||
//temp [{1'b0,~inWordPtr,4'b0}+:16] = inData[15:0];
|
||||
//fifo[ wrPtr[`PTRBITSM2:0] ] <= temp;
|
||||
end
|
||||
outData <= fifo[rdPtr[`PTRBITSM2:0]];
|
||||
end
|
||||
|
||||
endmodule
|
124
test/cli/verilog/t_mem_func.v
Normal file
124
test/cli/verilog/t_mem_func.v
Normal file
|
@ -0,0 +1,124 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2008 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [2:0] q; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (
|
||||
// Outputs
|
||||
.q (q[2:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.reset_l (crc[0]),
|
||||
.enable (crc[2]),
|
||||
.q_var0 (crc[19:10]),
|
||||
.q_var2 (crc[29:20]),
|
||||
.q_var4 (crc[39:30]),
|
||||
.q_var6 (crc[49:40])
|
||||
/*AUTOINST*/);
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {61'h0,q};
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
`define EXPECTED_SUM 64'h58b162c58d6e35ba
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
module Test
|
||||
(
|
||||
input clk,
|
||||
input reset_l,
|
||||
input enable,
|
||||
|
||||
input [ 9:0] q_var0,
|
||||
input [ 9:0] q_var2,
|
||||
input [ 9:0] q_var4,
|
||||
input [ 9:0] q_var6,
|
||||
|
||||
output reg [2:0] q
|
||||
);
|
||||
|
||||
reg [7:0] p1_r [6:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!reset_l) begin
|
||||
p1_r[0] <= 'b0;
|
||||
p1_r[1] <= 'b0;
|
||||
p1_r[2] <= 'b0;
|
||||
p1_r[3] <= 'b0;
|
||||
p1_r[4] <= 'b0;
|
||||
p1_r[5] <= 'b0;
|
||||
p1_r[6] <= 'b0;
|
||||
end
|
||||
else if (enable) begin : pass1
|
||||
match(q_var0, q_var2, q_var4, q_var6);
|
||||
end
|
||||
end
|
||||
|
||||
// verilator lint_off WIDTH
|
||||
always @(posedge clk) begin : l
|
||||
reg [10:0] bd;
|
||||
reg [3:0] idx;
|
||||
|
||||
q = 0;
|
||||
bd = 0;
|
||||
for (idx=0; idx<7; idx=idx+1) begin
|
||||
q = idx+1;
|
||||
bd = bd + p1_r[idx];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
task match;
|
||||
input [9:0] p0, p1, p2, p3;
|
||||
reg [9:0] p[3:0];
|
||||
begin
|
||||
p[0] = p0;
|
||||
p[1] = p1;
|
||||
p[2] = p2;
|
||||
p[3] = p3;
|
||||
p1_r[0] <= p[0];
|
||||
p1_r[1] <= p[1];
|
||||
end
|
||||
endtask
|
||||
endmodule
|
103
test/cli/verilog/t_mem_iforder.v
Normal file
103
test/cli/verilog/t_mem_iforder.v
Normal file
|
@ -0,0 +1,103 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2006 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
integer cyc; initial cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [31:0] sum;
|
||||
|
||||
wire [15:0] out0;
|
||||
wire [15:0] out1;
|
||||
wire [15:0] inData = crc[15:0];
|
||||
wire wr0a = crc[16];
|
||||
wire wr0b = crc[17];
|
||||
wire wr1a = crc[18];
|
||||
wire wr1b = crc[19];
|
||||
|
||||
fifo fifo (
|
||||
// Outputs
|
||||
.out0 (out0[15:0]),
|
||||
.out1 (out1[15:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.wr0a (wr0a),
|
||||
.wr0b (wr0b),
|
||||
.wr1a (wr1a),
|
||||
.wr1b (wr1b),
|
||||
.inData (inData[15:0]));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
//$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
sum <= 32'h0;
|
||||
end
|
||||
else if (cyc>10 && cyc<90) begin
|
||||
sum <= {sum[30:0],sum[31]} ^ {out1, out0};
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
if (sum !== 32'he8bbd130) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module fifo (/*AUTOARG*/
|
||||
// Outputs
|
||||
out0, out1,
|
||||
// Inputs
|
||||
clk, wr0a, wr0b, wr1a, wr1b, inData
|
||||
);
|
||||
|
||||
input clk;
|
||||
input wr0a;
|
||||
input wr0b;
|
||||
input wr1a;
|
||||
input wr1b;
|
||||
input [15:0] inData;
|
||||
|
||||
output [15:0] out0;
|
||||
output [15:0] out1;
|
||||
|
||||
reg [15:0] mem [1:0];
|
||||
reg [15:0] memtemp2 [1:0];
|
||||
reg [15:0] memtemp3 [1:0];
|
||||
|
||||
assign out0 = {mem[0] ^ memtemp2[0]};
|
||||
assign out1 = {mem[1] ^ memtemp3[1]};
|
||||
|
||||
always @(posedge clk) begin
|
||||
// These mem assignments must be done in order after processing
|
||||
if (wr0a) begin
|
||||
memtemp2[0] <= inData;
|
||||
mem[0] <= inData;
|
||||
end
|
||||
if (wr0b) begin
|
||||
memtemp3[0] <= inData;
|
||||
mem[0] <= ~inData;
|
||||
end
|
||||
if (wr1a) begin
|
||||
memtemp3[1] <= inData;
|
||||
mem[1] <= inData;
|
||||
end
|
||||
if (wr1b) begin
|
||||
memtemp2[1] <= inData;
|
||||
mem[1] <= ~inData;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
63
test/cli/verilog/t_mem_multi_io.v
Normal file
63
test/cli/verilog/t_mem_multi_io.v
Normal file
|
@ -0,0 +1,63 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2009 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
logic [7:0] arr [7:0];
|
||||
logic [7:0] arri [7:0];
|
||||
|
||||
has_array am1 (.clk(clk), .arri(arr), .arro(arri));
|
||||
|
||||
integer cyc; initial cyc = 0;
|
||||
|
||||
initial begin
|
||||
for (int i = 0; i < 8; i++) begin
|
||||
arr[i] = 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc == 5 && arri[1] != 8) begin
|
||||
$stop;
|
||||
end
|
||||
for (int i = 0; i < 7; ++i) begin
|
||||
arr[i+1] <= arr[i];
|
||||
end
|
||||
arr[0] <= arr[0] + 1;
|
||||
end
|
||||
|
||||
endmodule : t
|
||||
|
||||
module has_array (
|
||||
input clk,
|
||||
input logic [7:0] arri [7:0],
|
||||
output logic [7:0] arro [7:0]
|
||||
);
|
||||
|
||||
integer cyc; initial cyc = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (arri[0] == 10 && cyc == 10) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
for (integer i = 0; i < 7; ++i) begin
|
||||
arro[i+1] <= arro[i];
|
||||
end
|
||||
arro[0] = arro[0] + 2;
|
||||
end
|
||||
|
||||
endmodule : has_array
|
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Reference in New Issue
Block a user