2009-05-29 23:41:08 +00:00
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//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Thumb2 instruction set.
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//
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//===----------------------------------------------------------------------===//
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2009-06-17 18:13:58 +00:00
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2009-07-10 01:54:42 +00:00
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// IT block predicate field
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def it_pred : Operand<i32> {
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2010-03-02 17:57:15 +00:00
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let PrintMethod = "printMandatoryPredicateOperand";
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2009-07-10 01:54:42 +00:00
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}
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// IT block condition mask
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def it_mask : Operand<i32> {
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let PrintMethod = "printThumbITMask";
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}
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2009-07-29 02:18:14 +00:00
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// Table branch address
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def tb_addrmode : Operand<i32> {
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let PrintMethod = "printTBAddrMode";
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}
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2009-06-17 18:13:58 +00:00
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// Shifted operands. No register controlled shifts for Thumb2.
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// Note: We do not support rrx shifted operands yet.
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def t2_so_reg : Operand<i32>, // reg imm
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2009-06-27 02:26:13 +00:00
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ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
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2009-06-17 18:13:58 +00:00
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[shl,srl,sra,rotr]> {
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2010-11-15 05:19:05 +00:00
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let EncoderMethod = "getT2SORegOpValue";
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2009-06-27 02:26:13 +00:00
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let PrintMethod = "printT2SOOperand";
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Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
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let MIOperandInfo = (ops rGPR, i32imm);
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2009-06-17 18:13:58 +00:00
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}
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2009-06-23 17:48:47 +00:00
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// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
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def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
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2009-08-11 20:47:22 +00:00
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return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
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2009-06-17 18:13:58 +00:00
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}]>;
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2009-06-23 17:48:47 +00:00
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// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
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def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
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2009-08-11 20:47:22 +00:00
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return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
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2009-06-23 17:48:47 +00:00
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}]>;
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// t2_so_imm - Match a 32-bit immediate operand, which is an
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// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
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// immediate splatted into multiple bytes of the word. t2_so_imm values are
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// represented in the imm field in the same 12-bit form that they are encoded
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2009-11-24 00:20:27 +00:00
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// into t2_so_imm instructions: the 8-bit immediate is the least significant
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// bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
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2010-11-12 21:12:40 +00:00
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def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]> {
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2010-11-15 05:19:05 +00:00
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let EncoderMethod = "getT2SOImmOpValue";
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2010-11-12 21:12:40 +00:00
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}
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2009-06-17 18:13:58 +00:00
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2010-02-16 21:07:46 +00:00
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// t2_so_imm_not - Match an immediate that is a complement
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2009-06-23 17:48:47 +00:00
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// of a t2_so_imm.
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def t2_so_imm_not : Operand<i32>,
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PatLeaf<(imm), [{
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2009-07-08 21:03:57 +00:00
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return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
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}], t2_so_imm_not_XFORM>;
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2009-06-23 17:48:47 +00:00
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// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
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def t2_so_imm_neg : Operand<i32>,
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PatLeaf<(imm), [{
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2010-11-12 22:42:47 +00:00
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return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
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2009-07-08 21:03:57 +00:00
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}], t2_so_imm_neg_XFORM>;
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2009-06-17 18:13:58 +00:00
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2009-10-21 20:44:34 +00:00
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// Break t2_so_imm's up into two pieces. This handles immediates with up to 16
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// bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
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// to get the first/second pieces.
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def t2_so_imm2part : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
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}]> {
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}
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def t2_so_imm2part_1 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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def t2_so_imm2part_2 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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2009-11-23 20:35:53 +00:00
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def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
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return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
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}]> {
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}
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def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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2009-06-23 19:39:13 +00:00
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/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
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def imm1_31 : PatLeaf<(i32 imm), [{
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return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
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}]>;
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2009-06-23 17:48:47 +00:00
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/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
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2009-08-07 00:34:42 +00:00
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def imm0_4095 : Operand<i32>,
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PatLeaf<(i32 imm), [{
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2009-06-23 17:48:47 +00:00
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return (uint32_t)N->getZExtValue() < 4096;
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}]>;
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2009-06-17 18:13:58 +00:00
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2010-02-16 21:07:46 +00:00
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def imm0_4095_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)(-N->getZExtValue()) < 4096;
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}], imm_neg_XFORM>;
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2009-06-17 18:13:58 +00:00
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2009-08-04 01:41:15 +00:00
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def imm0_255_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)(-N->getZExtValue()) < 255;
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2010-02-16 21:07:46 +00:00
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}], imm_neg_XFORM>;
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2009-08-04 01:41:15 +00:00
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2010-07-14 17:45:16 +00:00
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def imm0_255_not : PatLeaf<(i32 imm), [{
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return (uint32_t)(~N->getZExtValue()) < 255;
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}], imm_comp_XFORM>;
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2009-06-29 07:51:04 +00:00
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// Define Thumb2 specific addressing modes.
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// t2addrmode_imm12 := reg + imm12
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def t2addrmode_imm12 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
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2010-10-25 20:00:01 +00:00
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let PrintMethod = "printAddrModeImm12Operand";
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2009-06-29 07:51:04 +00:00
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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2010-03-04 17:40:44 +00:00
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// t2addrmode_imm8 := reg +/- imm8
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2009-06-29 07:51:04 +00:00
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def t2addrmode_imm8 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
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let PrintMethod = "printT2AddrModeImm8Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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2009-07-03 00:06:39 +00:00
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def t2am_imm8_offset : Operand<i32>,
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2010-09-21 20:31:19 +00:00
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ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
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[], [SDNPWantRoot]> {
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2009-07-02 07:28:31 +00:00
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let PrintMethod = "printT2AddrModeImm8OffsetOperand";
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}
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2009-07-09 22:21:59 +00:00
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// t2addrmode_imm8s4 := reg +/- (imm8 << 2)
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2010-09-05 22:51:11 +00:00
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def t2addrmode_imm8s4 : Operand<i32> {
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2009-07-09 22:21:59 +00:00
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let PrintMethod = "printT2AddrModeImm8s4Operand";
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2009-06-30 22:50:01 +00:00
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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2010-03-11 01:13:36 +00:00
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def t2am_imm8s4_offset : Operand<i32> {
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let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
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}
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2009-07-09 20:40:44 +00:00
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// t2addrmode_so_reg := reg + (reg << imm2)
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2009-06-29 07:51:04 +00:00
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def t2addrmode_so_reg : Operand<i32>,
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ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
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let PrintMethod = "printT2AddrModeSoRegOperand";
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Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
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let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
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2009-06-29 07:51:04 +00:00
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}
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2009-06-17 18:13:58 +00:00
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//===----------------------------------------------------------------------===//
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2009-06-27 02:26:13 +00:00
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// Multiclass helpers...
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2009-06-17 18:13:58 +00:00
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//
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2010-11-15 18:45:17 +00:00
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class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
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2010-11-14 05:37:38 +00:00
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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bits<4> Rd;
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2010-11-15 18:45:17 +00:00
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bits<12> imm;
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let Inst{11-8} = Rd{3-0};
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let Inst{26} = imm{11};
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let Inst{14-12} = imm{10-8};
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let Inst{7-0} = imm{7-0};
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}
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2010-11-15 19:58:36 +00:00
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2010-11-15 18:45:17 +00:00
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class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2sI<oops, iops, itin, opc, asm, pattern> {
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bits<4> Rd;
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2010-11-14 05:37:38 +00:00
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bits<4> Rn;
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bits<12> imm;
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let Inst{11-8} = Rd{3-0};
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let Inst{26} = imm{11};
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let Inst{14-12} = imm{10-8};
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let Inst{7-0} = imm{7-0};
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}
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2010-11-15 19:58:36 +00:00
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class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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bits<4> Rn;
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bits<12> imm;
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let Inst{19-16} = Rn{3-0};
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let Inst{26} = imm{11};
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let Inst{14-12} = imm{10-8};
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let Inst{7-0} = imm{7-0};
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}
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2010-11-15 18:45:17 +00:00
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class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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bits<4> Rd;
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bits<12> ShiftedRm;
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let Inst{11-8} = Rd{3-0};
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let Inst{3-0} = ShiftedRm{3-0};
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let Inst{5-4} = ShiftedRm{6-5};
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let Inst{14-12} = ShiftedRm{11-9};
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let Inst{7-6} = ShiftedRm{8-7};
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}
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class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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bits<4> Rd;
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bits<12> ShiftedRm;
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let Inst{11-8} = Rd{3-0};
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let Inst{3-0} = ShiftedRm{3-0};
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let Inst{5-4} = ShiftedRm{6-5};
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let Inst{14-12} = ShiftedRm{11-9};
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let Inst{7-6} = ShiftedRm{8-7};
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}
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2010-11-15 19:58:36 +00:00
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class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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bits<4> Rn;
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bits<12> ShiftedRm;
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let Inst{19-16} = Rn{3-0};
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let Inst{3-0} = ShiftedRm{3-0};
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let Inst{5-4} = ShiftedRm{6-5};
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let Inst{14-12} = ShiftedRm{11-9};
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let Inst{7-6} = ShiftedRm{8-7};
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}
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2010-11-15 18:45:17 +00:00
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class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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bits<4> Rd;
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bits<4> Rm;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{3-0} = Rm{3-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string opc, string asm, list<dag> pattern>
|
|
|
|
: T2sI<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
bits<4> Rd;
|
|
|
|
bits<4> Rm;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{3-0} = Rm{3-0};
|
|
|
|
}
|
|
|
|
|
2010-11-15 19:58:36 +00:00
|
|
|
class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string opc, string asm, list<dag> pattern>
|
|
|
|
: T2I<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
bits<4> Rn;
|
|
|
|
bits<4> Rm;
|
|
|
|
|
|
|
|
let Inst{19-16} = Rn{3-0};
|
|
|
|
let Inst{3-0} = Rm{3-0};
|
|
|
|
}
|
|
|
|
|
2010-11-15 18:45:17 +00:00
|
|
|
|
|
|
|
class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string opc, string asm, list<dag> pattern>
|
|
|
|
: T2I<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
bits<4> Rd;
|
|
|
|
bits<4> Rm;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{3-0} = Rm{3-0};
|
|
|
|
}
|
|
|
|
|
2010-11-14 05:37:38 +00:00
|
|
|
class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
|
2010-11-12 21:12:40 +00:00
|
|
|
string opc, string asm, list<dag> pattern>
|
|
|
|
: T2sI<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
bits<4> Rd;
|
|
|
|
bits<4> Rn;
|
|
|
|
bits<12> imm;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{19-16} = Rn{3-0};
|
|
|
|
let Inst{26} = imm{11};
|
|
|
|
let Inst{14-12} = imm{10-8};
|
|
|
|
let Inst{7-0} = imm{7-0};
|
|
|
|
}
|
|
|
|
|
2010-11-15 19:58:36 +00:00
|
|
|
class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string opc, string asm, list<dag> pattern>
|
|
|
|
: T2I<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
bits<4> Rd;
|
|
|
|
bits<4> Rm;
|
|
|
|
bits<5> imm;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{3-0} = Rm{3-0};
|
|
|
|
let Inst{14-12} = imm{4-2};
|
|
|
|
let Inst{7-6} = imm{1-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string opc, string asm, list<dag> pattern>
|
|
|
|
: T2sI<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
bits<4> Rd;
|
|
|
|
bits<4> Rm;
|
|
|
|
bits<5> imm;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{3-0} = Rm{3-0};
|
|
|
|
let Inst{14-12} = imm{4-2};
|
|
|
|
let Inst{7-6} = imm{1-0};
|
|
|
|
}
|
|
|
|
|
2010-11-12 21:12:40 +00:00
|
|
|
class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string opc, string asm, list<dag> pattern>
|
2010-11-14 05:37:38 +00:00
|
|
|
: T2I<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
bits<4> Rd;
|
|
|
|
bits<4> Rn;
|
|
|
|
bits<4> Rm;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{19-16} = Rn{3-0};
|
|
|
|
let Inst{3-0} = Rm{3-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string opc, string asm, list<dag> pattern>
|
2010-11-12 21:12:40 +00:00
|
|
|
: T2sI<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
bits<4> Rd;
|
|
|
|
bits<4> Rn;
|
|
|
|
bits<4> Rm;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{19-16} = Rn{3-0};
|
|
|
|
let Inst{3-0} = Rm{3-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string opc, string asm, list<dag> pattern>
|
2010-11-14 05:37:38 +00:00
|
|
|
: T2I<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
bits<4> Rd;
|
|
|
|
bits<4> Rn;
|
|
|
|
bits<12> ShiftedRm;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{19-16} = Rn{3-0};
|
|
|
|
let Inst{3-0} = ShiftedRm{3-0};
|
|
|
|
let Inst{5-4} = ShiftedRm{6-5};
|
|
|
|
let Inst{14-12} = ShiftedRm{11-9};
|
|
|
|
let Inst{7-6} = ShiftedRm{8-7};
|
|
|
|
}
|
|
|
|
|
|
|
|
class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string opc, string asm, list<dag> pattern>
|
2010-11-12 21:12:40 +00:00
|
|
|
: T2sI<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
bits<4> Rd;
|
|
|
|
bits<4> Rn;
|
|
|
|
bits<12> ShiftedRm;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{19-16} = Rn{3-0};
|
|
|
|
let Inst{3-0} = ShiftedRm{3-0};
|
|
|
|
let Inst{5-4} = ShiftedRm{6-5};
|
|
|
|
let Inst{14-12} = ShiftedRm{11-9};
|
|
|
|
let Inst{7-6} = ShiftedRm{8-7};
|
|
|
|
}
|
|
|
|
|
2009-06-23 19:39:13 +00:00
|
|
|
/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
|
2009-06-25 02:08:06 +00:00
|
|
|
/// unary operation that produces a value. These are predicable and can be
|
|
|
|
/// changed to modify CPSR.
|
2010-09-29 00:49:25 +00:00
|
|
|
multiclass T2I_un_irs<bits<4> opcod, string opc,
|
|
|
|
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
|
|
|
|
PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
|
2009-06-23 19:39:13 +00:00
|
|
|
// shifted imm
|
2010-11-15 18:45:17 +00:00
|
|
|
def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
|
|
|
|
opc, "\t$Rd, $imm",
|
|
|
|
[(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
|
2009-06-23 19:39:13 +00:00
|
|
|
let isAsCheapAsAMove = Cheap;
|
|
|
|
let isReMaterializable = ReMat;
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15} = 0;
|
2009-06-23 19:39:13 +00:00
|
|
|
}
|
|
|
|
// register
|
2010-11-15 18:45:17 +00:00
|
|
|
def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
|
|
|
|
opc, ".w\t$Rd, $Rm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{14-12} = 0b000; // imm3
|
|
|
|
let Inst{7-6} = 0b00; // imm2
|
|
|
|
let Inst{5-4} = 0b00; // type
|
|
|
|
}
|
2009-06-23 19:39:13 +00:00
|
|
|
// shifted register
|
2010-11-15 18:45:17 +00:00
|
|
|
def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
|
|
|
|
opc, ".w\t$Rd, $ShiftedRm",
|
|
|
|
[(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
}
|
2009-06-23 19:39:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
|
2010-05-25 04:43:08 +00:00
|
|
|
/// binary operation that produces a value. These are predicable and can be
|
2009-06-25 02:08:06 +00:00
|
|
|
/// changed to modify CPSR.
|
2010-09-29 00:27:46 +00:00
|
|
|
multiclass T2I_bin_irs<bits<4> opcod, string opc,
|
|
|
|
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
|
|
|
|
PatFrag opnode, bit Commutable = 0, string wide = ""> {
|
2009-06-23 17:48:47 +00:00
|
|
|
// shifted imm
|
2010-11-14 05:37:38 +00:00
|
|
|
def ri : T2sTwoRegImm<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
|
|
|
|
opc, "\t$Rd, $Rn, $imm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = opcod;
|
2010-08-30 01:47:35 +00:00
|
|
|
let Inst{20} = ?; // The S bit.
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-23 19:39:13 +00:00
|
|
|
// register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
|
|
|
|
opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
|
2009-06-26 00:19:44 +00:00
|
|
|
let isCommutable = Commutable;
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
2010-08-30 01:47:35 +00:00
|
|
|
let Inst{20} = ?; // The S bit.
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{14-12} = 0b000; // imm3
|
|
|
|
let Inst{7-6} = 0b00; // imm2
|
|
|
|
let Inst{5-4} = 0b00; // type
|
2009-06-26 00:19:44 +00:00
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
// shifted register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rs : T2sTwoRegShiftedReg<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
|
|
|
|
opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
2010-08-30 01:47:35 +00:00
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-07-27 23:34:12 +00:00
|
|
|
/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
|
|
|
|
// the ".w" prefix to indicate that they are wide.
|
2010-09-29 00:27:46 +00:00
|
|
|
multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
|
|
|
|
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
|
|
|
|
PatFrag opnode, bit Commutable = 0> :
|
|
|
|
T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w">;
|
2010-08-29 03:55:31 +00:00
|
|
|
|
2009-06-25 20:59:23 +00:00
|
|
|
/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
|
2010-08-13 23:24:25 +00:00
|
|
|
/// reversed. The 'rr' form is only defined for the disassembler; for codegen
|
|
|
|
/// it is equivalent to the T2I_bin_irs counterpart.
|
|
|
|
multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
|
2009-06-17 18:13:58 +00:00
|
|
|
// shifted imm
|
2010-11-14 05:37:38 +00:00
|
|
|
def ri : T2sTwoRegImm<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
|
|
|
|
opc, ".w\t$Rd, $Rn, $imm",
|
|
|
|
[(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = opcod;
|
2010-05-25 04:43:08 +00:00
|
|
|
let Inst{20} = ?; // The S bit.
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2010-08-13 23:24:25 +00:00
|
|
|
// register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rr : T2sThreeReg<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
|
|
|
|
opc, "\t$Rd, $Rn, $Rm",
|
2010-08-14 03:18:29 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
2010-08-13 23:24:25 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
let Inst{14-12} = 0b000; // imm3
|
|
|
|
let Inst{7-6} = 0b00; // imm2
|
|
|
|
let Inst{5-4} = 0b00; // type
|
|
|
|
}
|
2009-06-17 18:13:58 +00:00
|
|
|
// shifted register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rs : T2sTwoRegShiftedReg<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
|
|
|
|
IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
|
|
|
|
[(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
2010-05-25 04:43:08 +00:00
|
|
|
let Inst{20} = ?; // The S bit.
|
2009-12-15 17:24:14 +00:00
|
|
|
}
|
2009-06-17 18:13:58 +00:00
|
|
|
}
|
|
|
|
|
2009-06-23 19:39:13 +00:00
|
|
|
/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
|
2009-06-17 18:13:58 +00:00
|
|
|
/// instruction modifies the CPSR register.
|
|
|
|
let Defs = [CPSR] in {
|
2010-09-29 00:27:46 +00:00
|
|
|
multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
|
|
|
|
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
|
|
|
|
PatFrag opnode, bit Commutable = 0> {
|
2009-06-23 17:48:47 +00:00
|
|
|
// shifted imm
|
2010-11-14 05:37:38 +00:00
|
|
|
def ri : T2TwoRegImm<
|
|
|
|
(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
|
|
|
|
!strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
|
|
|
|
[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-23 19:39:13 +00:00
|
|
|
// register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rr : T2ThreeReg<
|
|
|
|
(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
|
|
|
|
!strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
|
|
|
|
[(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
|
2009-06-26 00:19:44 +00:00
|
|
|
let isCommutable = Commutable;
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
let Inst{14-12} = 0b000; // imm3
|
|
|
|
let Inst{7-6} = 0b00; // imm2
|
|
|
|
let Inst{5-4} = 0b00; // type
|
2009-06-26 00:19:44 +00:00
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
// shifted register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rs : T2TwoRegShiftedReg<
|
|
|
|
(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
|
|
|
|
!strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
|
|
|
|
[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-23 19:39:13 +00:00
|
|
|
/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
|
|
|
|
/// patterns for a binary operation that produces a value.
|
2009-12-15 17:24:14 +00:00
|
|
|
multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
|
|
|
|
bit Commutable = 0> {
|
2009-06-17 18:13:58 +00:00
|
|
|
// shifted imm
|
2010-08-30 19:49:58 +00:00
|
|
|
// The register-immediate version is re-materializable. This is useful
|
|
|
|
// in particular for taking the address of a local.
|
|
|
|
let isReMaterializable = 1 in {
|
2010-11-14 05:37:38 +00:00
|
|
|
def ri : T2sTwoRegImm<
|
|
|
|
(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
|
|
|
|
opc, ".w\t$Rd, $Rn, $imm",
|
|
|
|
[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24} = 1;
|
|
|
|
let Inst{23-21} = op23_21;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2010-08-30 19:49:58 +00:00
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
// 12-bit imm
|
2010-11-14 05:37:38 +00:00
|
|
|
def ri12 : T2TwoRegImm<
|
|
|
|
(outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
|
|
|
|
!strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
|
|
|
|
[(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24} = 0;
|
|
|
|
let Inst{23-21} = op23_21;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-23 19:39:13 +00:00
|
|
|
// register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
|
|
|
|
opc, ".w\t$Rd, $Rn, $Rm",
|
|
|
|
[(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
|
2009-06-26 00:19:44 +00:00
|
|
|
let isCommutable = Commutable;
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24} = 1;
|
|
|
|
let Inst{23-21} = op23_21;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{14-12} = 0b000; // imm3
|
|
|
|
let Inst{7-6} = 0b00; // imm2
|
|
|
|
let Inst{5-4} = 0b00; // type
|
2009-06-26 00:19:44 +00:00
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
// shifted register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rs : T2sTwoRegShiftedReg<
|
|
|
|
(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
|
|
|
|
IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
|
|
|
|
[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
2010-01-08 17:41:33 +00:00
|
|
|
let Inst{24} = 1;
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{23-21} = op23_21;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
}
|
2009-06-17 18:13:58 +00:00
|
|
|
|
2009-11-24 00:20:27 +00:00
|
|
|
/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
|
2010-02-16 20:42:29 +00:00
|
|
|
/// for a binary operation that produces a value and use the carry
|
2009-11-24 00:20:27 +00:00
|
|
|
/// bit. It's not predicable.
|
2009-06-25 23:34:10 +00:00
|
|
|
let Uses = [CPSR] in {
|
2010-02-16 21:23:02 +00:00
|
|
|
multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
|
|
|
|
bit Commutable = 0> {
|
2009-06-23 17:48:47 +00:00
|
|
|
// shifted imm
|
2010-11-14 05:37:38 +00:00
|
|
|
def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
|
2010-11-12 21:12:40 +00:00
|
|
|
IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
|
2010-02-16 20:42:29 +00:00
|
|
|
Requires<[IsThumb2]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-23 19:39:13 +00:00
|
|
|
// register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
|
2010-11-12 21:12:40 +00:00
|
|
|
opc, ".w\t$Rd, $Rn, $Rm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
|
2010-02-16 20:42:29 +00:00
|
|
|
Requires<[IsThumb2]> {
|
2009-06-26 00:19:44 +00:00
|
|
|
let isCommutable = Commutable;
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{14-12} = 0b000; // imm3
|
|
|
|
let Inst{7-6} = 0b00; // imm2
|
|
|
|
let Inst{5-4} = 0b00; // type
|
2009-06-26 00:19:44 +00:00
|
|
|
}
|
2009-06-17 18:13:58 +00:00
|
|
|
// shifted register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rs : T2sTwoRegShiftedReg<
|
2010-11-12 21:12:40 +00:00
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
|
|
|
|
IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
|
2010-02-16 20:42:29 +00:00
|
|
|
Requires<[IsThumb2]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
}
|
2010-02-16 20:42:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Carry setting variants
|
|
|
|
let Defs = [CPSR] in {
|
2010-02-16 21:23:02 +00:00
|
|
|
multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
|
|
|
|
bit Commutable = 0> {
|
2009-06-25 23:34:10 +00:00
|
|
|
// shifted imm
|
2010-11-14 05:37:38 +00:00
|
|
|
def ri : T2sTwoRegImm<
|
2010-11-12 21:12:40 +00:00
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
|
|
|
|
opc, "\t$Rd, $Rn, $imm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
|
2010-03-02 19:38:59 +00:00
|
|
|
Requires<[IsThumb2]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-25 23:34:10 +00:00
|
|
|
// register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
|
2010-11-12 21:12:40 +00:00
|
|
|
opc, ".w\t$Rd, $Rn, $Rm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
|
2010-03-02 19:38:59 +00:00
|
|
|
Requires<[IsThumb2]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let isCommutable = Commutable;
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
let Inst{14-12} = 0b000; // imm3
|
|
|
|
let Inst{7-6} = 0b00; // imm2
|
|
|
|
let Inst{5-4} = 0b00; // type
|
2009-06-26 00:19:44 +00:00
|
|
|
}
|
2009-06-25 23:34:10 +00:00
|
|
|
// shifted register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rs : T2sTwoRegShiftedReg<
|
2010-11-12 21:12:40 +00:00
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
|
|
|
|
IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
|
2010-03-02 19:38:59 +00:00
|
|
|
Requires<[IsThumb2]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
2009-06-26 00:19:44 +00:00
|
|
|
}
|
2009-06-17 18:13:58 +00:00
|
|
|
}
|
|
|
|
}
|
2010-02-16 20:42:29 +00:00
|
|
|
}
|
2009-06-17 18:13:58 +00:00
|
|
|
|
2010-08-13 23:24:25 +00:00
|
|
|
/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
|
|
|
|
/// version is not needed since this is only for codegen.
|
2009-06-25 20:59:23 +00:00
|
|
|
let Defs = [CPSR] in {
|
2009-12-15 17:24:14 +00:00
|
|
|
multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
|
2009-06-25 20:59:23 +00:00
|
|
|
// shifted imm
|
2010-11-14 05:37:38 +00:00
|
|
|
def ri : T2TwoRegImm<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
|
|
|
|
!strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
|
|
|
|
[(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-25 20:59:23 +00:00
|
|
|
// shifted register
|
2010-11-14 05:37:38 +00:00
|
|
|
def rs : T2TwoRegShiftedReg<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
|
|
|
|
IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
|
|
|
|
[(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-23 19:39:13 +00:00
|
|
|
/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
|
|
|
|
// rotate operation that produces a value.
|
2009-12-15 17:24:14 +00:00
|
|
|
multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
|
2009-06-23 19:39:13 +00:00
|
|
|
// 5-bit imm
|
2010-11-15 19:58:36 +00:00
|
|
|
def ri : T2sTwoRegShiftImm<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
|
|
|
|
opc, ".w\t$Rd, $Rm, $imm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-21} = 0b010010;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{5-4} = opcod;
|
|
|
|
}
|
2009-06-23 19:39:13 +00:00
|
|
|
// register
|
2010-11-15 19:58:36 +00:00
|
|
|
def rr : T2sThreeReg<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
|
|
|
|
opc, ".w\t$Rd, $Rn, $Rm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-21} = opcod;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7-4} = 0b0000;
|
|
|
|
}
|
2009-06-23 19:39:13 +00:00
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
|
2009-06-23 19:39:13 +00:00
|
|
|
/// patterns. Similar to T2I_bin_irs except the instruction does not produce
|
2009-06-23 17:48:47 +00:00
|
|
|
/// a explicit result, only implicitly set CPSR.
|
2010-08-19 00:05:48 +00:00
|
|
|
let isCompare = 1, Defs = [CPSR] in {
|
2010-09-29 00:49:25 +00:00
|
|
|
multiclass T2I_cmp_irs<bits<4> opcod, string opc,
|
|
|
|
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
|
|
|
|
PatFrag opnode> {
|
2009-06-23 17:48:47 +00:00
|
|
|
// shifted imm
|
2010-11-15 19:58:36 +00:00
|
|
|
def ri : T2OneRegCmpImm<
|
|
|
|
(outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
|
|
|
|
opc, ".w\t$Rn, $imm",
|
|
|
|
[(opnode GPR:$Rn, t2_so_imm:$imm)]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
let Inst{15} = 0;
|
|
|
|
let Inst{11-8} = 0b1111; // Rd
|
|
|
|
}
|
2009-06-23 19:39:13 +00:00
|
|
|
// register
|
2010-11-15 19:58:36 +00:00
|
|
|
def rr : T2TwoRegCmp<
|
|
|
|
(outs), (ins GPR:$lhs, rGPR:$rhs), iir,
|
2009-10-27 00:08:59 +00:00
|
|
|
opc, ".w\t$lhs, $rhs",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(opnode GPR:$lhs, rGPR:$rhs)]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
let Inst{14-12} = 0b000; // imm3
|
|
|
|
let Inst{11-8} = 0b1111; // Rd
|
|
|
|
let Inst{7-6} = 0b00; // imm2
|
|
|
|
let Inst{5-4} = 0b00; // type
|
|
|
|
}
|
2009-06-17 18:13:58 +00:00
|
|
|
// shifted register
|
2010-11-15 19:58:36 +00:00
|
|
|
def rs : T2OneRegCmpShiftedReg<
|
|
|
|
(outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
|
|
|
|
opc, ".w\t$Rn, $ShiftedRm",
|
|
|
|
[(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = opcod;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
let Inst{11-8} = 0b1111; // Rd
|
|
|
|
}
|
2009-06-17 18:13:58 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-30 02:15:48 +00:00
|
|
|
/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
|
2010-09-30 01:08:25 +00:00
|
|
|
multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
|
2010-10-28 06:47:08 +00:00
|
|
|
InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
|
2010-09-30 01:08:25 +00:00
|
|
|
def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), iii,
|
2009-10-27 00:08:59 +00:00
|
|
|
opc, ".w\t$dst, $addr",
|
2009-12-15 17:24:14 +00:00
|
|
|
[(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24} = signed;
|
|
|
|
let Inst{23} = 1;
|
|
|
|
let Inst{22-21} = opcod;
|
|
|
|
let Inst{20} = 1; // load
|
|
|
|
}
|
2010-09-30 01:08:25 +00:00
|
|
|
def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), iii,
|
2009-10-27 00:08:59 +00:00
|
|
|
opc, "\t$dst, $addr",
|
2009-12-15 17:24:14 +00:00
|
|
|
[(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24} = signed;
|
|
|
|
let Inst{23} = 0;
|
|
|
|
let Inst{22-21} = opcod;
|
|
|
|
let Inst{20} = 1; // load
|
|
|
|
let Inst{11} = 1;
|
|
|
|
// Offset: index==TRUE, wback==FALSE
|
|
|
|
let Inst{10} = 1; // The P bit.
|
|
|
|
let Inst{8} = 0; // The W bit.
|
|
|
|
}
|
2010-10-28 06:47:08 +00:00
|
|
|
def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), iis,
|
2009-10-27 00:08:59 +00:00
|
|
|
opc, ".w\t$dst, $addr",
|
2009-12-15 17:24:14 +00:00
|
|
|
[(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24} = signed;
|
|
|
|
let Inst{23} = 0;
|
|
|
|
let Inst{22-21} = opcod;
|
|
|
|
let Inst{20} = 1; // load
|
|
|
|
let Inst{11-6} = 0b000000;
|
|
|
|
}
|
2010-11-03 05:14:24 +00:00
|
|
|
|
|
|
|
// FIXME: Is the pci variant actually needed?
|
2010-09-30 01:08:25 +00:00
|
|
|
def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), iii,
|
2009-10-27 00:08:59 +00:00
|
|
|
opc, ".w\t$dst, $addr",
|
2009-10-31 03:39:36 +00:00
|
|
|
[(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
|
|
|
|
let isReMaterializable = 1;
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24} = signed;
|
|
|
|
let Inst{23} = ?; // add = (U == '1')
|
|
|
|
let Inst{22-21} = opcod;
|
|
|
|
let Inst{20} = 1; // load
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
2009-10-31 03:39:36 +00:00
|
|
|
}
|
2009-06-30 02:15:48 +00:00
|
|
|
}
|
|
|
|
|
2009-06-30 22:11:34 +00:00
|
|
|
/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
|
2010-09-30 01:08:25 +00:00
|
|
|
multiclass T2I_st<bits<2> opcod, string opc,
|
2010-10-28 06:47:08 +00:00
|
|
|
InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
|
2010-09-30 01:08:25 +00:00
|
|
|
def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), iii,
|
2009-10-27 00:08:59 +00:00
|
|
|
opc, ".w\t$src, $addr",
|
2009-12-15 17:24:14 +00:00
|
|
|
[(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0001;
|
|
|
|
let Inst{22-21} = opcod;
|
|
|
|
let Inst{20} = 0; // !load
|
|
|
|
}
|
2010-09-30 01:08:25 +00:00
|
|
|
def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), iii,
|
2009-10-27 00:08:59 +00:00
|
|
|
opc, "\t$src, $addr",
|
2009-12-15 17:24:14 +00:00
|
|
|
[(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0000;
|
|
|
|
let Inst{22-21} = opcod;
|
|
|
|
let Inst{20} = 0; // !load
|
|
|
|
let Inst{11} = 1;
|
|
|
|
// Offset: index==TRUE, wback==FALSE
|
|
|
|
let Inst{10} = 1; // The P bit.
|
|
|
|
let Inst{8} = 0; // The W bit.
|
|
|
|
}
|
2010-10-28 06:47:08 +00:00
|
|
|
def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), iis,
|
2009-10-27 00:08:59 +00:00
|
|
|
opc, ".w\t$src, $addr",
|
2009-12-15 17:24:14 +00:00
|
|
|
[(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0000;
|
|
|
|
let Inst{22-21} = opcod;
|
|
|
|
let Inst{20} = 0; // !load
|
|
|
|
let Inst{11-6} = 0b000000;
|
|
|
|
}
|
2009-06-30 22:11:34 +00:00
|
|
|
}
|
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
|
2009-07-03 01:43:10 +00:00
|
|
|
/// register and one whose operand is a register rotated by 8/16/24.
|
2010-09-30 01:08:25 +00:00
|
|
|
multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
|
2010-11-15 21:12:05 +00:00
|
|
|
def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
|
|
|
|
opc, ".w\t$Rd, $Rm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-20} = opcod;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 1;
|
|
|
|
let Inst{5-4} = 0b00; // rotate
|
|
|
|
}
|
2010-11-15 21:12:05 +00:00
|
|
|
def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
|
|
|
|
opc, ".w\t$Rd, $Rm, ror $rot",
|
|
|
|
[(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-20} = opcod;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 1;
|
2010-11-15 21:12:05 +00:00
|
|
|
|
|
|
|
bits<2> rot;
|
|
|
|
let Inst{5-4} = rot{1-0}; // rotate
|
2009-12-15 17:24:14 +00:00
|
|
|
}
|
2009-07-03 01:43:10 +00:00
|
|
|
}
|
|
|
|
|
2010-06-24 18:20:04 +00:00
|
|
|
// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
|
2010-09-30 01:08:25 +00:00
|
|
|
multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
|
2010-11-15 21:12:05 +00:00
|
|
|
def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
|
|
|
|
opc, "\t$Rd, $Rm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
|
2010-11-01 15:59:52 +00:00
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]> {
|
2010-03-04 22:24:41 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-20} = opcod;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 1;
|
|
|
|
let Inst{5-4} = 0b00; // rotate
|
|
|
|
}
|
2010-11-15 21:12:05 +00:00
|
|
|
def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
|
|
|
|
opc, "\t$dst, $Rm, ror $rot",
|
|
|
|
[(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
|
2010-11-01 15:59:52 +00:00
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]> {
|
2010-03-04 22:24:41 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-20} = opcod;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 1;
|
2010-11-15 21:12:05 +00:00
|
|
|
|
|
|
|
bits<2> rot;
|
|
|
|
let Inst{5-4} = rot{1-0}; // rotate
|
2010-03-04 22:24:41 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-06-24 18:20:04 +00:00
|
|
|
// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
|
|
|
|
// supported yet.
|
2010-09-30 01:08:25 +00:00
|
|
|
multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
|
2010-11-15 21:12:05 +00:00
|
|
|
def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
|
|
|
|
opc, "\t$Rd, $Rm", []> {
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-20} = opcod;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 1;
|
|
|
|
let Inst{5-4} = 0b00; // rotate
|
|
|
|
}
|
2010-11-15 21:12:05 +00:00
|
|
|
def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
|
|
|
|
opc, "\t$Rd, $Rm, ror $rot", []> {
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-20} = opcod;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 1;
|
2010-11-15 21:12:05 +00:00
|
|
|
|
|
|
|
bits<2> rot;
|
|
|
|
let Inst{5-4} = rot{1-0}; // rotate
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
|
2009-07-03 01:43:10 +00:00
|
|
|
/// register and one whose operand is a register rotated by 8/16/24.
|
2010-09-30 01:08:25 +00:00
|
|
|
multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
|
2010-11-15 21:12:05 +00:00
|
|
|
def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
|
|
|
|
opc, "\t$Rd, $Rn, $Rm",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
|
2010-11-01 15:59:52 +00:00
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-20} = opcod;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 1;
|
|
|
|
let Inst{5-4} = 0b00; // rotate
|
|
|
|
}
|
2010-11-15 21:12:05 +00:00
|
|
|
def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
|
|
|
|
IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
|
|
|
|
[(set rGPR:$Rd, (opnode rGPR:$Rn,
|
|
|
|
(rotr rGPR:$Rm, rot_imm:$rot)))]>,
|
2010-11-01 15:59:52 +00:00
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-20} = opcod;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 1;
|
2010-11-15 21:12:05 +00:00
|
|
|
|
|
|
|
bits<2> rot;
|
|
|
|
let Inst{5-4} = rot{1-0}; // rotate
|
2009-12-15 17:24:14 +00:00
|
|
|
}
|
2009-07-03 01:43:10 +00:00
|
|
|
}
|
|
|
|
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
// DO variant - disassembly only, no pattern
|
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
|
2010-11-15 21:12:05 +00:00
|
|
|
def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
|
|
|
|
opc, "\t$Rd, $Rn, $Rm", []> {
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-20} = opcod;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 1;
|
|
|
|
let Inst{5-4} = 0b00; // rotate
|
|
|
|
}
|
2010-11-15 21:12:05 +00:00
|
|
|
def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
|
|
|
|
IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0100;
|
|
|
|
let Inst{22-20} = opcod;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 1;
|
2010-11-15 21:12:05 +00:00
|
|
|
|
|
|
|
bits<2> rot;
|
|
|
|
let Inst{5-4} = rot{1-0}; // rotate
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-27 02:26:13 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Instructions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2009-06-24 23:47:58 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Miscellaneous Instructions.
|
|
|
|
//
|
|
|
|
|
2010-11-15 21:30:39 +00:00
|
|
|
class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string asm, list<dag> pattern>
|
|
|
|
: T2XI<oops, iops, itin, asm, pattern> {
|
|
|
|
bits<4> Rd;
|
|
|
|
bits<12> label;
|
|
|
|
|
|
|
|
let Inst{11-8} = Rd{3-0};
|
|
|
|
let Inst{26} = label{11};
|
|
|
|
let Inst{14-12} = label{10-8};
|
|
|
|
let Inst{7-0} = label{7-0};
|
|
|
|
}
|
|
|
|
|
2009-06-24 23:47:58 +00:00
|
|
|
// LEApcrel - Load a pc-relative address into a register without offending the
|
|
|
|
// assembler.
|
2010-05-19 01:52:25 +00:00
|
|
|
let neverHasSideEffects = 1 in {
|
2010-05-19 07:28:01 +00:00
|
|
|
let isReMaterializable = 1 in
|
2010-11-15 21:30:39 +00:00
|
|
|
def t2LEApcrel : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
|
|
|
|
"adr${p}.w\t$Rd, #$label", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25-24} = 0b10;
|
|
|
|
// Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
|
|
|
|
let Inst{22} = 0;
|
|
|
|
let Inst{20} = 0;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15} = 0;
|
2010-11-15 21:30:39 +00:00
|
|
|
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
}
|
2010-06-21 21:27:27 +00:00
|
|
|
} // neverHasSideEffects
|
2010-11-15 21:30:39 +00:00
|
|
|
def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
|
2009-08-21 21:58:55 +00:00
|
|
|
(ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
|
2010-11-15 21:30:39 +00:00
|
|
|
"adr${p}.w\t$Rd, #${label}_${id}", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25-24} = 0b10;
|
|
|
|
// Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
|
|
|
|
let Inst{22} = 0;
|
|
|
|
let Inst{20} = 0;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-24 23:47:58 +00:00
|
|
|
|
2009-08-07 00:34:42 +00:00
|
|
|
// ADD r, sp, {so_imm|i12}
|
2010-11-15 21:30:39 +00:00
|
|
|
def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
|
|
|
|
IIC_iALUi, "add", ".w\t$Rd, $sp, $imm", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = 0b1000;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
2010-11-12 23:36:03 +00:00
|
|
|
let Inst{19-16} = 0b1101; // Rn = sp
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2010-11-15 21:30:39 +00:00
|
|
|
def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
|
|
|
|
IIC_iALUi, "addw", "\t$Rd, $sp, $imm", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-21} = 0b0000;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1101; // Rn = sp
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-08-07 00:34:42 +00:00
|
|
|
|
|
|
|
// ADD r, sp, so_reg
|
2010-11-15 21:30:39 +00:00
|
|
|
def t2ADDrSPs : T2sTwoRegShiftedReg<
|
|
|
|
(outs GPR:$Rd), (ins GPR:$sp, t2_so_reg:$ShiftedRm),
|
|
|
|
IIC_iALUsi, "add", ".w\t$Rd, $sp, $ShiftedRm", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = 0b1000;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1101; // Rn = sp
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-08-07 00:34:42 +00:00
|
|
|
|
|
|
|
// SUB r, sp, {so_imm|i12}
|
2010-11-15 21:30:39 +00:00
|
|
|
def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
|
|
|
|
IIC_iALUi, "sub", ".w\t$Rd, $sp, $imm", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = 0b1101;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1101; // Rn = sp
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2010-11-15 21:30:39 +00:00
|
|
|
def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
|
|
|
|
IIC_iALUi, "subw", "\t$Rd, $sp, $imm", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-21} = 0b0101;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1101; // Rn = sp
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-08-07 00:34:42 +00:00
|
|
|
|
|
|
|
// SUB r, sp, so_reg
|
2009-08-19 18:00:44 +00:00
|
|
|
def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
|
|
|
|
IIC_iALUsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
"sub", "\t$dst, $sp, $rhs", []> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = 0b1101;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1101; // Rn = sp
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-08-07 00:34:42 +00:00
|
|
|
|
2010-05-05 20:44:35 +00:00
|
|
|
// Signed and unsigned division on v7-M
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
|
2010-05-05 20:44:35 +00:00
|
|
|
"sdiv", "\t$dst, $a, $b",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (sdiv rGPR:$a, rGPR:$b))]>,
|
2010-05-05 23:44:43 +00:00
|
|
|
Requires<[HasDivide]> {
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-21} = 0b011100;
|
|
|
|
let Inst{20} = 0b1;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7-4} = 0b1111;
|
|
|
|
}
|
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
|
2010-05-05 20:44:35 +00:00
|
|
|
"udiv", "\t$dst, $a, $b",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (udiv rGPR:$a, rGPR:$b))]>,
|
2010-05-05 23:44:43 +00:00
|
|
|
Requires<[HasDivide]> {
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-21} = 0b011101;
|
|
|
|
let Inst{20} = 0b1;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7-4} = 0b1111;
|
|
|
|
}
|
|
|
|
|
2009-06-27 02:26:13 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Load / store Instructions.
|
|
|
|
//
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
// Load
|
2010-02-27 23:47:46 +00:00
|
|
|
let canFoldAsLoad = 1, isReMaterializable = 1 in
|
2010-10-28 06:47:08 +00:00
|
|
|
defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
|
2010-09-30 01:08:25 +00:00
|
|
|
UnOpFrag<(load node:$Src)>>;
|
2009-06-30 02:15:48 +00:00
|
|
|
|
|
|
|
// Loads with zero extension
|
2010-10-28 06:47:08 +00:00
|
|
|
defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
|
2010-09-30 01:08:25 +00:00
|
|
|
UnOpFrag<(zextloadi16 node:$Src)>>;
|
2010-10-28 06:47:08 +00:00
|
|
|
defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
|
2010-09-30 01:08:25 +00:00
|
|
|
UnOpFrag<(zextloadi8 node:$Src)>>;
|
2009-06-30 02:15:48 +00:00
|
|
|
|
|
|
|
// Loads with sign extension
|
2010-10-28 06:47:08 +00:00
|
|
|
defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
|
2010-09-30 01:08:25 +00:00
|
|
|
UnOpFrag<(sextloadi16 node:$Src)>>;
|
2010-10-28 06:47:08 +00:00
|
|
|
defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
|
2010-09-30 01:08:25 +00:00
|
|
|
UnOpFrag<(sextloadi8 node:$Src)>>;
|
2009-06-30 02:15:48 +00:00
|
|
|
|
2010-11-02 23:40:41 +00:00
|
|
|
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
|
|
|
|
isCodeGenOnly = 1 in { // $dst doesn't exist in asmstring?
|
2009-06-30 02:15:48 +00:00
|
|
|
// Load doubleword
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
|
2009-09-27 09:46:04 +00:00
|
|
|
(ins t2addrmode_imm8s4:$addr),
|
2010-09-30 01:08:25 +00:00
|
|
|
IIC_iLoad_d_i, "ldrd", "\t$dst1, $addr", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
|
2010-09-30 01:08:25 +00:00
|
|
|
(ins i32imm:$addr), IIC_iLoad_d_i,
|
2010-01-05 22:37:28 +00:00
|
|
|
"ldrd", "\t$dst1, $addr", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
}
|
2010-05-19 06:07:03 +00:00
|
|
|
} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
|
2009-06-30 02:15:48 +00:00
|
|
|
|
|
|
|
// zextload i1 -> zextload i8
|
|
|
|
def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
|
|
|
|
(t2LDRBi12 t2addrmode_imm12:$addr)>;
|
|
|
|
def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
|
|
|
|
(t2LDRBi8 t2addrmode_imm8:$addr)>;
|
|
|
|
def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
|
|
|
|
(t2LDRBs t2addrmode_so_reg:$addr)>;
|
|
|
|
def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
|
|
|
|
(t2LDRBpci tconstpool:$addr)>;
|
|
|
|
|
|
|
|
// extload -> zextload
|
|
|
|
// FIXME: Reduce the number of patterns by legalizing extload to zextload
|
|
|
|
// earlier?
|
|
|
|
def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
|
|
|
|
(t2LDRBi12 t2addrmode_imm12:$addr)>;
|
|
|
|
def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
|
|
|
|
(t2LDRBi8 t2addrmode_imm8:$addr)>;
|
|
|
|
def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
|
|
|
|
(t2LDRBs t2addrmode_so_reg:$addr)>;
|
|
|
|
def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
|
|
|
|
(t2LDRBpci tconstpool:$addr)>;
|
|
|
|
|
|
|
|
def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
|
|
|
|
(t2LDRBi12 t2addrmode_imm12:$addr)>;
|
|
|
|
def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
|
|
|
|
(t2LDRBi8 t2addrmode_imm8:$addr)>;
|
|
|
|
def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
|
|
|
|
(t2LDRBs t2addrmode_so_reg:$addr)>;
|
|
|
|
def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
|
|
|
|
(t2LDRBpci tconstpool:$addr)>;
|
|
|
|
|
|
|
|
def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
|
|
|
|
(t2LDRHi12 t2addrmode_imm12:$addr)>;
|
|
|
|
def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
|
|
|
|
(t2LDRHi8 t2addrmode_imm8:$addr)>;
|
|
|
|
def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
|
|
|
|
(t2LDRHs t2addrmode_so_reg:$addr)>;
|
|
|
|
def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
|
|
|
|
(t2LDRHpci tconstpool:$addr)>;
|
2009-06-29 07:51:04 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
// FIXME: The destination register of the loads and stores can't be PC, but
|
|
|
|
// can be SP. We need another regclass (similar to rGPR) to represent
|
|
|
|
// that. Not a pressing issue since these are selected manually,
|
|
|
|
// not via pattern.
|
|
|
|
|
2009-07-02 07:28:31 +00:00
|
|
|
// Indexed loads
|
2010-05-19 06:07:03 +00:00
|
|
|
let mayLoad = 1, neverHasSideEffects = 1 in {
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
|
2009-07-02 07:28:31 +00:00
|
|
|
(ins t2addrmode_imm8:$addr),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
|
2009-07-02 07:28:31 +00:00
|
|
|
[]>;
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
|
2009-07-02 07:28:31 +00:00
|
|
|
(ins GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
|
2009-07-02 07:28:31 +00:00
|
|
|
[]>;
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
|
2009-07-02 07:28:31 +00:00
|
|
|
(ins t2addrmode_imm8:$addr),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
|
2009-07-02 07:28:31 +00:00
|
|
|
[]>;
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
|
2009-07-02 07:28:31 +00:00
|
|
|
(ins GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
|
2009-07-02 07:28:31 +00:00
|
|
|
[]>;
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
|
2009-07-02 07:28:31 +00:00
|
|
|
(ins t2addrmode_imm8:$addr),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
|
2009-07-02 07:28:31 +00:00
|
|
|
[]>;
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
|
2009-07-02 07:28:31 +00:00
|
|
|
(ins GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
|
2009-07-02 07:28:31 +00:00
|
|
|
[]>;
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
|
2009-07-02 23:16:11 +00:00
|
|
|
(ins t2addrmode_imm8:$addr),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
|
2009-07-02 23:16:11 +00:00
|
|
|
[]>;
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
|
2009-07-02 23:16:11 +00:00
|
|
|
(ins GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
|
2009-07-02 23:16:11 +00:00
|
|
|
[]>;
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
|
2009-07-02 23:16:11 +00:00
|
|
|
(ins t2addrmode_imm8:$addr),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
|
2009-07-02 23:16:11 +00:00
|
|
|
[]>;
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
|
2009-07-02 23:16:11 +00:00
|
|
|
(ins GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
|
2009-07-02 23:16:11 +00:00
|
|
|
[]>;
|
2010-05-19 06:07:03 +00:00
|
|
|
} // mayLoad = 1, neverHasSideEffects = 1
|
2009-07-02 23:16:11 +00:00
|
|
|
|
2010-03-03 18:45:36 +00:00
|
|
|
// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
|
|
|
|
// for disassembly only.
|
|
|
|
// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
|
2010-09-30 01:08:25 +00:00
|
|
|
class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
|
|
|
|
: T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), ii, opc,
|
2010-03-03 18:45:36 +00:00
|
|
|
"\t$dst, $addr", []> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24} = signed;
|
|
|
|
let Inst{23} = 0;
|
|
|
|
let Inst{22-21} = type;
|
|
|
|
let Inst{20} = 1; // load
|
|
|
|
let Inst{11} = 1;
|
|
|
|
let Inst{10-8} = 0b110; // PUW.
|
|
|
|
}
|
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
|
|
|
|
def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
|
|
|
|
def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
|
|
|
|
def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
|
|
|
|
def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
|
2010-03-03 18:45:36 +00:00
|
|
|
|
2009-06-30 22:11:34 +00:00
|
|
|
// Store
|
2010-10-28 06:47:08 +00:00
|
|
|
defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
|
2010-09-30 01:08:25 +00:00
|
|
|
BinOpFrag<(store node:$LHS, node:$RHS)>>;
|
2010-10-28 06:47:08 +00:00
|
|
|
defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
|
2010-09-30 01:08:25 +00:00
|
|
|
BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
|
2010-10-28 06:47:08 +00:00
|
|
|
defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
|
2010-09-30 01:08:25 +00:00
|
|
|
BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
|
2009-06-30 22:11:34 +00:00
|
|
|
|
2009-06-30 22:50:01 +00:00
|
|
|
// Store doubleword
|
2010-11-02 23:40:41 +00:00
|
|
|
let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
|
|
|
|
isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
|
2009-09-27 09:46:04 +00:00
|
|
|
(ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
|
2010-09-30 01:08:25 +00:00
|
|
|
IIC_iStore_d_r, "strd", "\t$src1, $addr", []>;
|
2009-06-30 22:50:01 +00:00
|
|
|
|
2009-07-03 00:06:39 +00:00
|
|
|
// Indexed stores
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
|
2009-07-03 00:06:39 +00:00
|
|
|
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"str", "\t$src, [$base, $offset]!", "$base = $base_wb",
|
2009-07-03 00:06:39 +00:00
|
|
|
[(set GPR:$base_wb,
|
|
|
|
(pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
|
2009-07-03 00:06:39 +00:00
|
|
|
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"str", "\t$src, [$base], $offset", "$base = $base_wb",
|
2009-07-03 00:06:39 +00:00
|
|
|
[(set GPR:$base_wb,
|
2009-11-24 00:20:27 +00:00
|
|
|
(post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
|
2009-07-03 00:06:39 +00:00
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
|
2009-07-03 00:06:39 +00:00
|
|
|
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
|
2009-07-03 00:06:39 +00:00
|
|
|
[(set GPR:$base_wb,
|
|
|
|
(pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
|
2009-07-03 00:06:39 +00:00
|
|
|
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"strh", "\t$src, [$base], $offset", "$base = $base_wb",
|
2009-07-03 00:06:39 +00:00
|
|
|
[(set GPR:$base_wb,
|
|
|
|
(post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
|
2009-07-03 00:06:39 +00:00
|
|
|
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
|
2009-07-03 00:06:39 +00:00
|
|
|
[(set GPR:$base_wb,
|
|
|
|
(pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
|
2009-07-03 00:06:39 +00:00
|
|
|
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
|
2010-09-30 01:08:25 +00:00
|
|
|
AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
|
2009-10-27 00:08:59 +00:00
|
|
|
"strb", "\t$src, [$base], $offset", "$base = $base_wb",
|
2009-07-03 00:06:39 +00:00
|
|
|
[(set GPR:$base_wb,
|
|
|
|
(post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
|
|
|
|
|
2010-03-03 18:45:36 +00:00
|
|
|
// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
|
|
|
|
// only.
|
|
|
|
// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
|
2010-09-30 01:08:25 +00:00
|
|
|
class T2IstT<bits<2> type, string opc, InstrItinClass ii>
|
|
|
|
: T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), ii, opc,
|
2010-03-03 18:45:36 +00:00
|
|
|
"\t$src, $addr", []> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24} = 0; // not signed
|
|
|
|
let Inst{23} = 0;
|
|
|
|
let Inst{22-21} = type;
|
|
|
|
let Inst{20} = 0; // store
|
|
|
|
let Inst{11} = 1;
|
|
|
|
let Inst{10-8} = 0b110; // PUW
|
|
|
|
}
|
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
|
|
|
|
def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
|
|
|
|
def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
|
2009-07-01 00:01:13 +00:00
|
|
|
|
2010-03-11 01:13:36 +00:00
|
|
|
// ldrd / strd pre / post variants
|
|
|
|
// For disassembly only.
|
|
|
|
|
|
|
|
def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
|
2010-09-30 01:08:25 +00:00
|
|
|
(ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
|
2010-03-11 01:13:36 +00:00
|
|
|
"ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
|
|
|
|
|
|
|
|
def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
|
2010-09-30 01:08:25 +00:00
|
|
|
(ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
|
2010-03-11 01:13:36 +00:00
|
|
|
"ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
|
|
|
|
|
|
|
|
def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
|
|
|
|
(ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
|
2010-09-30 01:08:25 +00:00
|
|
|
IIC_iStore_d_ru, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
|
2010-03-11 01:13:36 +00:00
|
|
|
|
|
|
|
def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
|
|
|
|
(ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
|
2010-09-30 01:08:25 +00:00
|
|
|
IIC_iStore_d_ru, "strd", "\t$src1, $src2, [$base], $imm", []>;
|
2009-07-03 00:18:36 +00:00
|
|
|
|
2010-03-04 17:40:44 +00:00
|
|
|
// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
|
|
|
|
// data/instruction access. These are for disassembly only.
|
2010-11-03 06:34:55 +00:00
|
|
|
// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
|
|
|
|
// (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
|
2010-11-04 05:19:35 +00:00
|
|
|
multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
|
2010-03-04 17:40:44 +00:00
|
|
|
|
2010-11-03 06:34:55 +00:00
|
|
|
def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
|
2010-11-03 05:14:24 +00:00
|
|
|
"\t$addr",
|
2010-11-04 05:19:35 +00:00
|
|
|
[(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{31-25} = 0b1111100;
|
2010-11-04 05:19:35 +00:00
|
|
|
let Inst{24} = instr;
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{23} = 1; // U = 1
|
|
|
|
let Inst{22} = 0;
|
2010-11-04 05:19:35 +00:00
|
|
|
let Inst{21} = write;
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{20} = 1;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
}
|
|
|
|
|
2010-11-03 06:34:55 +00:00
|
|
|
def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
|
2010-11-03 05:14:24 +00:00
|
|
|
"\t$addr",
|
2010-11-04 05:19:35 +00:00
|
|
|
[(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{31-25} = 0b1111100;
|
2010-11-04 05:19:35 +00:00
|
|
|
let Inst{24} = instr;
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{23} = 0; // U = 0
|
|
|
|
let Inst{22} = 0;
|
2010-11-04 05:19:35 +00:00
|
|
|
let Inst{21} = write;
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{20} = 1;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{11-8} = 0b1100;
|
|
|
|
}
|
|
|
|
|
2010-11-03 06:34:55 +00:00
|
|
|
def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
|
2010-11-03 05:14:24 +00:00
|
|
|
"\t$addr",
|
2010-11-04 05:19:35 +00:00
|
|
|
[(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{31-25} = 0b1111100;
|
2010-11-04 05:19:35 +00:00
|
|
|
let Inst{24} = instr;
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{23} = 0; // add = TRUE for T1
|
|
|
|
let Inst{22} = 0;
|
2010-11-04 05:19:35 +00:00
|
|
|
let Inst{21} = write;
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{20} = 1;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{11-6} = 0000000;
|
|
|
|
}
|
|
|
|
|
2010-11-03 05:14:24 +00:00
|
|
|
let isCodeGenOnly = 1 in
|
2010-11-03 06:34:55 +00:00
|
|
|
def pci : T2Ipc<(outs), (ins i32imm:$addr), IIC_Preload, opc,
|
2010-11-03 05:14:24 +00:00
|
|
|
"\t$addr",
|
|
|
|
[]> {
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{31-25} = 0b1111100;
|
2010-11-04 05:19:35 +00:00
|
|
|
let Inst{24} = write;
|
2010-11-03 05:14:24 +00:00
|
|
|
let Inst{23} = ?; // add = (U == 1)
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{22} = 0;
|
2010-11-04 05:19:35 +00:00
|
|
|
let Inst{21} = instr;
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{20} = 1;
|
2010-11-03 05:14:24 +00:00
|
|
|
let Inst{19-16} = 0b1111; // Rn = 0b1111
|
2010-03-04 17:40:44 +00:00
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-11-04 05:19:35 +00:00
|
|
|
defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
|
|
|
|
defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
|
|
|
|
defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
|
2010-03-04 17:40:44 +00:00
|
|
|
|
2009-07-03 00:18:36 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Load / store multiple Instructions.
|
|
|
|
//
|
|
|
|
|
2010-11-13 09:09:38 +00:00
|
|
|
multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
|
|
|
|
InstrItinClass itin_upd, bit L_bit> {
|
2010-11-13 10:43:34 +00:00
|
|
|
def ia :
|
2010-11-13 09:09:38 +00:00
|
|
|
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
|
|
|
|
itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
|
|
|
|
bits<4> Rn;
|
|
|
|
bits<16> regs;
|
|
|
|
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24-23} = 0b01; // Increment After
|
|
|
|
let Inst{22} = 0;
|
|
|
|
let Inst{21} = 0; // No writeback
|
|
|
|
let Inst{20} = L_bit;
|
|
|
|
let Inst{19-16} = Rn;
|
|
|
|
let Inst{15-0} = regs;
|
|
|
|
}
|
2010-11-13 10:43:34 +00:00
|
|
|
def ia_UPD :
|
2010-11-13 09:09:38 +00:00
|
|
|
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
|
|
|
|
itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
|
|
|
|
bits<4> Rn;
|
|
|
|
bits<16> regs;
|
|
|
|
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24-23} = 0b01; // Increment After
|
|
|
|
let Inst{22} = 0;
|
|
|
|
let Inst{21} = 1; // Writeback
|
|
|
|
let Inst{20} = L_bit;
|
|
|
|
let Inst{19-16} = Rn;
|
|
|
|
let Inst{15-0} = regs;
|
|
|
|
}
|
2010-11-13 10:43:34 +00:00
|
|
|
def db :
|
2010-11-13 09:09:38 +00:00
|
|
|
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
|
|
|
|
itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
|
|
|
|
bits<4> Rn;
|
|
|
|
bits<16> regs;
|
|
|
|
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24-23} = 0b10; // Decrement Before
|
|
|
|
let Inst{22} = 0;
|
|
|
|
let Inst{21} = 0; // No writeback
|
|
|
|
let Inst{20} = L_bit;
|
|
|
|
let Inst{19-16} = Rn;
|
|
|
|
let Inst{15-0} = regs;
|
|
|
|
}
|
2010-11-13 10:43:34 +00:00
|
|
|
def db_UPD :
|
2010-11-13 09:09:38 +00:00
|
|
|
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
|
|
|
|
itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
|
|
|
|
bits<4> Rn;
|
|
|
|
bits<16> regs;
|
|
|
|
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24-23} = 0b10; // Decrement Before
|
|
|
|
let Inst{22} = 0;
|
|
|
|
let Inst{21} = 1; // Writeback
|
|
|
|
let Inst{20} = L_bit;
|
|
|
|
let Inst{19-16} = Rn;
|
|
|
|
let Inst{15-0} = regs;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-11-13 11:20:05 +00:00
|
|
|
/* TODO:
|
|
|
|
let neverHasSideEffects = 1 in {
|
2010-11-13 10:57:02 +00:00
|
|
|
|
|
|
|
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
|
|
|
|
defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
|
|
|
|
|
|
|
|
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
|
|
|
|
defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
|
|
|
|
|
|
|
|
} // neverHasSideEffects
|
2010-11-13 11:20:05 +00:00
|
|
|
*/
|
2010-11-13 10:57:02 +00:00
|
|
|
|
2010-10-31 19:10:56 +00:00
|
|
|
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
|
|
|
|
isCodeGenOnly = 1 in {
|
2010-11-03 01:01:43 +00:00
|
|
|
def t2LDM : T2XI<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
|
2010-10-06 06:27:31 +00:00
|
|
|
reglist:$dsts, variable_ops), IIC_iLoad_m,
|
2010-11-03 01:01:43 +00:00
|
|
|
"ldm${amode}${p}.w\t$Rn, $dsts", []> {
|
2010-03-13 01:08:20 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
|
|
|
|
let Inst{22} = 0;
|
|
|
|
let Inst{21} = 0; // The W bit.
|
|
|
|
let Inst{20} = 1; // Load
|
|
|
|
}
|
|
|
|
|
2010-11-03 01:01:43 +00:00
|
|
|
def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
|
2010-10-06 06:27:31 +00:00
|
|
|
reglist:$dsts, variable_ops),
|
|
|
|
IIC_iLoad_mu,
|
2010-11-03 01:01:43 +00:00
|
|
|
"ldm${amode}${p}.w\t$Rn!, $dsts",
|
|
|
|
"$Rn = $wb", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
|
|
|
|
let Inst{22} = 0;
|
2010-03-13 01:08:20 +00:00
|
|
|
let Inst{21} = 1; // The W bit.
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{20} = 1; // Load
|
|
|
|
}
|
2010-05-19 06:07:03 +00:00
|
|
|
} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
|
2010-03-13 01:08:20 +00:00
|
|
|
|
2010-10-31 19:10:56 +00:00
|
|
|
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
|
|
|
|
isCodeGenOnly = 1 in {
|
2010-11-03 01:01:43 +00:00
|
|
|
def t2STM : T2XI<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
|
2010-10-06 06:27:31 +00:00
|
|
|
reglist:$srcs, variable_ops), IIC_iStore_m,
|
2010-11-03 01:01:43 +00:00
|
|
|
"stm${amode}${p}.w\t$Rn, $srcs", []> {
|
2010-03-13 01:08:20 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
|
|
|
|
let Inst{22} = 0;
|
|
|
|
let Inst{21} = 0; // The W bit.
|
|
|
|
let Inst{20} = 0; // Store
|
|
|
|
}
|
2009-07-03 00:18:36 +00:00
|
|
|
|
2010-11-03 01:01:43 +00:00
|
|
|
def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
|
2010-03-13 01:08:20 +00:00
|
|
|
reglist:$srcs, variable_ops),
|
2010-10-06 06:27:31 +00:00
|
|
|
IIC_iStore_m,
|
2010-11-03 01:01:43 +00:00
|
|
|
"stm${amode}${p}.w\t$Rn!, $srcs",
|
|
|
|
"$Rn = $wb", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
|
|
|
|
let Inst{22} = 0;
|
2010-03-13 01:08:20 +00:00
|
|
|
let Inst{21} = 1; // The W bit.
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{20} = 0; // Store
|
|
|
|
}
|
2010-05-19 06:07:03 +00:00
|
|
|
} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
|
2009-07-03 00:18:36 +00:00
|
|
|
|
2009-06-17 18:13:58 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Move Instructions.
|
|
|
|
//
|
|
|
|
|
2009-06-23 17:48:47 +00:00
|
|
|
let neverHasSideEffects = 1 in
|
2009-08-19 18:00:44 +00:00
|
|
|
def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
|
2009-12-15 17:24:14 +00:00
|
|
|
"mov", ".w\t$dst, $src", []> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = 0b0010;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{14-12} = 0b000;
|
|
|
|
let Inst{7-4} = 0b0000;
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-09-28 09:14:39 +00:00
|
|
|
// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MOVi : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
|
2009-10-27 00:08:59 +00:00
|
|
|
"mov", ".w\t$dst, $src",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, t2_so_imm:$src)]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = 0b0010;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-26 16:10:07 +00:00
|
|
|
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MOVi16 : T2I<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
|
2009-10-27 00:08:59 +00:00
|
|
|
"movw", "\t$dst, $src",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, imm0_65535:$src)]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-21} = 0b0010;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
|
|
|
|
let Constraints = "$src = $dst" in
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MOVTi16 : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
|
2009-10-27 00:08:59 +00:00
|
|
|
"movt", "\t$dst, $imm",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst,
|
|
|
|
(or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-21} = 0b0110;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-17 18:13:58 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
|
2009-10-21 08:15:52 +00:00
|
|
|
|
2009-07-03 01:43:10 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Extend Instructions.
|
|
|
|
//
|
|
|
|
|
|
|
|
// Sign extenders
|
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2SXTB : T2I_ext_rrot<0b100, "sxtb",
|
2009-12-15 17:24:14 +00:00
|
|
|
UnOpFrag<(sext_inreg node:$Src, i8)>>;
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2SXTH : T2I_ext_rrot<0b000, "sxth",
|
2009-12-15 17:24:14 +00:00
|
|
|
UnOpFrag<(sext_inreg node:$Src, i16)>>;
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
|
2009-07-03 01:43:10 +00:00
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
|
2009-07-03 01:43:10 +00:00
|
|
|
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
|
2009-07-03 01:43:10 +00:00
|
|
|
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
|
2009-07-03 01:43:10 +00:00
|
|
|
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
// TODO: SXT(A){B|H}16 - done for disassembly only
|
2009-07-03 01:43:10 +00:00
|
|
|
|
|
|
|
// Zero extenders
|
|
|
|
|
|
|
|
let AddedComplexity = 16 in {
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2UXTB : T2I_ext_rrot<0b101, "uxtb",
|
2009-12-15 17:24:14 +00:00
|
|
|
UnOpFrag<(and node:$Src, 0x000000FF)>>;
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2UXTH : T2I_ext_rrot<0b001, "uxth",
|
2009-12-15 17:24:14 +00:00
|
|
|
UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
|
2009-12-15 17:24:14 +00:00
|
|
|
UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
|
2009-07-03 01:43:10 +00:00
|
|
|
|
2010-07-28 23:17:45 +00:00
|
|
|
// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
|
|
|
|
// The transformation should probably be done as a combiner action
|
|
|
|
// instead so we can include a check for masking back in the upper
|
|
|
|
// eight bits of the source into the lower eight bits of the result.
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
|
2010-11-01 15:59:52 +00:00
|
|
|
// (t2UXTB16r_rot rGPR:$Src, 24)>,
|
|
|
|
// Requires<[HasT2ExtractPack, IsThumb2]>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
|
2010-11-01 15:59:52 +00:00
|
|
|
(t2UXTB16r_rot rGPR:$Src, 8)>,
|
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]>;
|
2009-07-03 01:43:10 +00:00
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
|
2009-11-24 00:20:27 +00:00
|
|
|
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
|
2009-11-24 00:20:27 +00:00
|
|
|
BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
|
2010-09-30 01:08:25 +00:00
|
|
|
defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
|
2009-07-03 01:43:10 +00:00
|
|
|
}
|
|
|
|
|
2009-06-17 18:13:58 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Arithmetic Instructions.
|
|
|
|
//
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
defm t2ADD : T2I_bin_ii12rs<0b000, "add",
|
|
|
|
BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
|
|
|
|
defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
|
|
|
|
BinOpFrag<(sub node:$LHS, node:$RHS)>>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
|
|
|
// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
|
2009-12-15 17:24:14 +00:00
|
|
|
defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
|
2010-09-29 00:27:46 +00:00
|
|
|
IIC_iALUi, IIC_iALUr, IIC_iALUsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
|
|
|
|
defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
|
2010-09-29 00:27:46 +00:00
|
|
|
IIC_iALUi, IIC_iALUr, IIC_iALUsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
|
2010-02-16 20:42:29 +00:00
|
|
|
BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
|
2009-12-15 17:24:14 +00:00
|
|
|
defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
|
2010-02-16 20:42:29 +00:00
|
|
|
BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
|
2010-03-02 19:38:59 +00:00
|
|
|
defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
|
2010-02-16 20:42:29 +00:00
|
|
|
BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
|
2010-03-02 19:38:59 +00:00
|
|
|
defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
|
2010-02-16 20:42:29 +00:00
|
|
|
BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-07-27 16:39:05 +00:00
|
|
|
// RSB
|
2010-08-13 23:24:25 +00:00
|
|
|
defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(sub node:$LHS, node:$RHS)>>;
|
|
|
|
defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
|
|
|
|
BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
|
|
|
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
|
2010-07-14 17:45:16 +00:00
|
|
|
// The assume-no-carry-in form uses the negation of the input since add/sub
|
|
|
|
// assume opposite meanings of the carry flag (i.e., carry == !borrow).
|
|
|
|
// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
|
|
|
|
// details.
|
|
|
|
// The AddedComplexity preferences the first variant over the others since
|
|
|
|
// it can be shrunk to a 16-bit wide encoding, while the others cannot.
|
|
|
|
let AddedComplexity = 1 in
|
|
|
|
def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
|
|
|
|
(t2SUBri GPR:$src, imm0_255_neg:$imm)>;
|
|
|
|
def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
|
|
|
|
(t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
|
|
|
|
def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
|
|
|
|
(t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
|
|
|
|
let AddedComplexity = 1 in
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
|
|
|
|
(t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
|
|
|
|
def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
|
|
|
|
(t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
|
2010-07-14 17:45:16 +00:00
|
|
|
// The with-carry-in form matches bitwise not instead of the negation.
|
|
|
|
// Effectively, the inverse interpretation of the carry flag already accounts
|
|
|
|
// for part of the negation.
|
2009-08-04 01:41:15 +00:00
|
|
|
let AddedComplexity = 1 in
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
|
|
|
|
(t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
|
|
|
|
def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
|
|
|
|
(t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
// Select Bytes -- for disassembly only
|
|
|
|
|
|
|
|
def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
|
|
|
|
"\t$dst, $a, $b", []> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-24} = 0b010;
|
|
|
|
let Inst{23} = 0b1;
|
|
|
|
let Inst{22-20} = 0b010;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7} = 0b1;
|
|
|
|
let Inst{6-4} = 0b000;
|
|
|
|
}
|
|
|
|
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
|
|
|
|
// And Miscellaneous operations -- for disassembly only
|
2010-07-29 17:56:55 +00:00
|
|
|
class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
|
|
|
|
list<dag> pat = [/* For disassembly only; pattern left blank */]>
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), NoItinerary, opc,
|
2010-07-29 17:56:55 +00:00
|
|
|
"\t$dst, $a, $b", pat> {
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0101;
|
|
|
|
let Inst{22-20} = op22_20;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7-4} = op7_4;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Saturating add/subtract -- for disassembly only
|
|
|
|
|
2010-07-29 17:56:55 +00:00
|
|
|
def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (int_arm_qadd rGPR:$a, rGPR:$b))]>;
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
|
|
|
|
def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
|
|
|
|
def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
|
|
|
|
def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
|
|
|
|
def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
|
|
|
|
def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
|
2010-07-29 17:56:55 +00:00
|
|
|
def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (int_arm_qsub rGPR:$a, rGPR:$b))]>;
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
|
|
|
|
def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
|
|
|
|
def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
|
|
|
|
def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
|
|
|
|
def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
|
|
|
|
def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
|
|
|
|
def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
|
|
|
|
def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
|
|
|
|
|
|
|
|
// Signed/Unsigned add/subtract -- for disassembly only
|
|
|
|
|
|
|
|
def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
|
|
|
|
def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
|
|
|
|
def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
|
|
|
|
def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
|
|
|
|
def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
|
|
|
|
def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
|
|
|
|
def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
|
|
|
|
def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
|
|
|
|
def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
|
|
|
|
def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
|
|
|
|
def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
|
|
|
|
def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
|
|
|
|
|
|
|
|
// Signed/Unsigned halving add/subtract -- for disassembly only
|
|
|
|
|
|
|
|
def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
|
|
|
|
def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
|
|
|
|
def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
|
|
|
|
def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
|
|
|
|
def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
|
|
|
|
def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
|
|
|
|
def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
|
|
|
|
def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
|
|
|
|
def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
|
|
|
|
def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
|
|
|
|
def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
|
|
|
|
def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
|
|
|
|
|
|
|
|
// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
|
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
|
|
|
|
(ins rGPR:$a, rGPR:$b),
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
NoItinerary, "usad8", "\t$dst, $a, $b", []> {
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
}
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
|
|
|
|
(ins rGPR:$a, rGPR:$b, rGPR:$acc), NoItinerary, "usada8",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"\t$dst, $a, $b, $acc", []>;
|
|
|
|
|
|
|
|
// Signed/Unsigned saturate -- for disassembly only
|
|
|
|
|
2010-08-16 18:27:34 +00:00
|
|
|
def t2SSAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
|
2010-08-13 21:48:10 +00:00
|
|
|
NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh",
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25-22} = 0b1100;
|
|
|
|
let Inst{20} = 0;
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SSAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"ssat16", "\t$dst, $bit_pos, $a",
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25-22} = 0b1100;
|
|
|
|
let Inst{20} = 0;
|
|
|
|
let Inst{15} = 0;
|
|
|
|
let Inst{21} = 1; // sh = '1'
|
|
|
|
let Inst{14-12} = 0b000; // imm3 = '000'
|
|
|
|
let Inst{7-6} = 0b00; // imm2 = '00'
|
|
|
|
}
|
|
|
|
|
2010-08-16 18:27:34 +00:00
|
|
|
def t2USAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
|
2010-08-13 21:48:10 +00:00
|
|
|
NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh",
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25-22} = 0b1110;
|
|
|
|
let Inst{20} = 0;
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2USAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"usat16", "\t$dst, $bit_pos, $a",
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25-22} = 0b1110;
|
|
|
|
let Inst{20} = 0;
|
|
|
|
let Inst{15} = 0;
|
|
|
|
let Inst{21} = 1; // sh = '1'
|
|
|
|
let Inst{14-12} = 0b000; // imm3 = '000'
|
|
|
|
let Inst{7-6} = 0b00; // imm2 = '00'
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2010-08-13 21:48:10 +00:00
|
|
|
def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
|
|
|
|
def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
|
2010-07-29 22:48:09 +00:00
|
|
|
|
2009-06-23 19:39:13 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Shift and rotate Instructions.
|
|
|
|
//
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
|
|
|
|
defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
|
|
|
|
defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
|
|
|
|
defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
|
2009-06-23 19:39:13 +00:00
|
|
|
|
2009-09-01 18:32:09 +00:00
|
|
|
let Uses = [CPSR] in {
|
2010-10-14 20:43:44 +00:00
|
|
|
def t2RRX : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
|
2009-10-27 00:08:59 +00:00
|
|
|
"rrx", "\t$dst, $src",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (ARMrrx rGPR:$src))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = 0b0010;
|
|
|
|
let Inst{20} = ?; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{14-12} = 0b000;
|
|
|
|
let Inst{7-4} = 0b0011;
|
|
|
|
}
|
2009-09-01 18:32:09 +00:00
|
|
|
}
|
2009-06-23 19:39:13 +00:00
|
|
|
|
2009-07-28 17:06:49 +00:00
|
|
|
let Defs = [CPSR] in {
|
2010-11-15 19:58:36 +00:00
|
|
|
def t2MOVsrl_flag : T2TwoRegShiftImm<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
|
|
|
|
"lsrs", ".w\t$Rd, $Rm, #1",
|
|
|
|
[(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = 0b0010;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{5-4} = 0b01; // Shift type.
|
|
|
|
// Shift amount = Inst{14-12:7-6} = 1.
|
|
|
|
let Inst{14-12} = 0b000;
|
|
|
|
let Inst{7-6} = 0b01;
|
|
|
|
}
|
2010-11-15 19:58:36 +00:00
|
|
|
def t2MOVsra_flag : T2TwoRegShiftImm<
|
|
|
|
(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
|
|
|
|
"asrs", ".w\t$Rd, $Rm, #1",
|
|
|
|
[(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = 0b0010;
|
|
|
|
let Inst{20} = 1; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{5-4} = 0b10; // Shift type.
|
|
|
|
// Shift amount = Inst{14-12:7-6} = 1.
|
|
|
|
let Inst{14-12} = 0b000;
|
|
|
|
let Inst{7-6} = 0b01;
|
|
|
|
}
|
2009-07-28 17:06:49 +00:00
|
|
|
}
|
|
|
|
|
2009-06-23 17:48:47 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Bitwise Instructions.
|
|
|
|
//
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
defm t2AND : T2I_bin_w_irs<0b0000, "and",
|
2010-09-29 00:27:46 +00:00
|
|
|
IIC_iBITi, IIC_iBITr, IIC_iBITsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
|
|
|
|
defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
|
2010-09-29 00:27:46 +00:00
|
|
|
IIC_iBITi, IIC_iBITr, IIC_iBITsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
|
|
|
|
defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
|
2010-09-29 00:27:46 +00:00
|
|
|
IIC_iBITi, IIC_iBITr, IIC_iBITsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
|
2010-09-29 00:27:46 +00:00
|
|
|
IIC_iBITi, IIC_iBITr, IIC_iBITsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-07-06 22:23:46 +00:00
|
|
|
let Constraints = "$src = $dst" in
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
|
2009-11-02 17:28:36 +00:00
|
|
|
IIC_iUNAsi, "bfc", "\t$dst, $imm",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-20} = 0b10110;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
|
2010-09-30 01:08:25 +00:00
|
|
|
IIC_iUNAsi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-20} = 0b10100;
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-10-13 18:59:48 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
|
2010-09-30 01:08:25 +00:00
|
|
|
IIC_iUNAsi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-20} = 0b11100;
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-10-13 18:59:48 +00:00
|
|
|
|
2010-02-02 19:31:58 +00:00
|
|
|
// A8.6.18 BFI - Bitfield insert (Encoding T1)
|
2010-07-16 23:05:05 +00:00
|
|
|
let Constraints = "$src = $dst" in
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2BFI : T2I<(outs rGPR:$dst),
|
|
|
|
(ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm),
|
2010-09-29 00:27:46 +00:00
|
|
|
IIC_iBITi, "bfi", "\t$dst, $val, $imm",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val,
|
2010-07-16 23:05:05 +00:00
|
|
|
bf_inv_mask_imm:$imm))]> {
|
2010-02-02 19:31:58 +00:00
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-20} = 0b10110;
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2010-09-29 00:27:46 +00:00
|
|
|
defm t2ORN : T2I_bin_irs<0b0011, "orn",
|
|
|
|
IIC_iBITi, IIC_iBITr, IIC_iBITsi,
|
|
|
|
BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-06-26 23:13:13 +00:00
|
|
|
// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
|
|
|
|
let AddedComplexity = 1 in
|
2010-09-29 00:49:25 +00:00
|
|
|
defm t2MVN : T2I_un_irs <0b0011, "mvn",
|
2010-09-29 22:42:35 +00:00
|
|
|
IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
|
2010-09-29 00:49:25 +00:00
|
|
|
UnOpFrag<(not node:$Src)>, 1, 1>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-06-25 23:11:21 +00:00
|
|
|
|
2010-07-20 16:07:04 +00:00
|
|
|
let AddedComplexity = 1 in
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
|
|
|
|
(t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-08-01 06:13:52 +00:00
|
|
|
// FIXME: Disable this pattern on Darwin to workaround an assembler bug.
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
|
|
|
|
(t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
|
2009-08-12 01:56:42 +00:00
|
|
|
Requires<[IsThumb2]>;
|
2009-07-06 22:23:46 +00:00
|
|
|
|
|
|
|
def : T2Pat<(t2_so_imm_not:$src),
|
|
|
|
(t2MVNi t2_so_imm_not:$src)>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Multiply Instructions.
|
|
|
|
//
|
2009-06-26 00:19:44 +00:00
|
|
|
let isCommutable = 1 in
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MUL: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
|
2009-10-27 00:08:59 +00:00
|
|
|
"mul", "\t$dst, $a, $b",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (mul rGPR:$a, rGPR:$b))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b000;
|
|
|
|
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
|
|
|
|
let Inst{7-4} = 0b0000; // Multiply
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MLA: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
|
2010-10-29 23:23:15 +00:00
|
|
|
"mla", "\t$dst, $a, $b, $c",
|
|
|
|
[(set rGPR:$dst, (add (mul rGPR:$a, rGPR:$b), rGPR:$c))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b000;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-4} = 0b0000; // Multiply
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MLS: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
|
2010-10-29 23:23:15 +00:00
|
|
|
"mls", "\t$dst, $a, $b, $c",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (sub rGPR:$c, (mul rGPR:$a, rGPR:$b)))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b000;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-4} = 0b0001; // Multiply and Subtract
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-07-07 01:17:28 +00:00
|
|
|
// Extra precision multiplies with low / high results
|
|
|
|
let neverHasSideEffects = 1 in {
|
|
|
|
let isCommutable = 1 in {
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
|
|
|
|
(ins rGPR:$a, rGPR:$b), IIC_iMUL64,
|
2009-12-15 17:24:14 +00:00
|
|
|
"smull", "\t$ldst, $hdst, $a, $b", []> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0111;
|
|
|
|
let Inst{22-20} = 0b000;
|
|
|
|
let Inst{7-4} = 0b0000;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
|
|
|
|
(ins rGPR:$a, rGPR:$b), IIC_iMUL64,
|
2009-12-15 17:24:14 +00:00
|
|
|
"umull", "\t$ldst, $hdst, $a, $b", []> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0111;
|
|
|
|
let Inst{22-20} = 0b010;
|
|
|
|
let Inst{7-4} = 0b0000;
|
2009-07-07 01:17:28 +00:00
|
|
|
}
|
2009-12-15 17:24:14 +00:00
|
|
|
} // isCommutable
|
2009-07-07 01:17:28 +00:00
|
|
|
|
|
|
|
// Multiply + accumulate
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
|
|
|
|
(ins rGPR:$a, rGPR:$b), IIC_iMAC64,
|
2009-12-15 17:24:14 +00:00
|
|
|
"smlal", "\t$ldst, $hdst, $a, $b", []>{
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0111;
|
|
|
|
let Inst{22-20} = 0b100;
|
|
|
|
let Inst{7-4} = 0b0000;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
|
|
|
|
(ins rGPR:$a, rGPR:$b), IIC_iMAC64,
|
2009-12-15 17:24:14 +00:00
|
|
|
"umlal", "\t$ldst, $hdst, $a, $b", []>{
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0111;
|
|
|
|
let Inst{22-20} = 0b110;
|
|
|
|
let Inst{7-4} = 0b0000;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
|
|
|
|
(ins rGPR:$a, rGPR:$b), IIC_iMAC64,
|
2009-12-15 17:24:14 +00:00
|
|
|
"umaal", "\t$ldst, $hdst, $a, $b", []>{
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0111;
|
|
|
|
let Inst{22-20} = 0b110;
|
|
|
|
let Inst{7-4} = 0b0110;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
} // neverHasSideEffects
|
|
|
|
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
// Rounding variants of the below included for disassembly only
|
|
|
|
|
2009-07-07 01:17:28 +00:00
|
|
|
// Most significant word multiply
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMMUL : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
|
2009-10-27 00:08:59 +00:00
|
|
|
"smmul", "\t$dst, $a, $b",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (mulhs rGPR:$a, rGPR:$b))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b101;
|
|
|
|
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
|
|
|
|
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMMULR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
"smmulr", "\t$dst, $a, $b", []> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b101;
|
|
|
|
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
|
|
|
|
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
|
|
|
|
}
|
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMMLA : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
|
2009-10-27 00:08:59 +00:00
|
|
|
"smmla", "\t$dst, $a, $b, $c",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (add (mulhs rGPR:$a, rGPR:$b), rGPR:$c))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b101;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2SMMLAR: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
"smmlar", "\t$dst, $a, $b, $c", []> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b101;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2SMMLS: T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
|
2009-10-27 00:08:59 +00:00
|
|
|
"smmls", "\t$dst, $a, $b, $c",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b110;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2SMMLSR:T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
"smmlsr", "\t$dst, $a, $b, $c", []> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b110;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
|
|
|
|
}
|
|
|
|
|
2009-07-07 01:17:28 +00:00
|
|
|
multiclass T2I_smul<string opc, PatFrag opnode> {
|
2010-09-30 01:08:25 +00:00
|
|
|
def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "bb"), "\t$dst, $a, $b",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
|
|
|
|
(sext_inreg rGPR:$b, i16)))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b001;
|
|
|
|
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b00;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "bt"), "\t$dst, $a, $b",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
|
|
|
|
(sra rGPR:$b, (i32 16))))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b001;
|
|
|
|
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b01;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "tb"), "\t$dst, $a, $b",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
|
|
|
|
(sext_inreg rGPR:$b, i16)))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b001;
|
|
|
|
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b10;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
2010-09-30 01:08:25 +00:00
|
|
|
def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "tt"), "\t$dst, $a, $b",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
|
|
|
|
(sra rGPR:$b, (i32 16))))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b001;
|
|
|
|
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b11;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "wb"), "\t$dst, $a, $b",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (sra (opnode rGPR:$a,
|
|
|
|
(sext_inreg rGPR:$b, i16)), (i32 16)))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b011;
|
|
|
|
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b00;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "wt"), "\t$dst, $a, $b",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (sra (opnode rGPR:$a,
|
|
|
|
(sra rGPR:$b, (i32 16))), (i32 16)))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b011;
|
|
|
|
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b01;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
multiclass T2I_smla<string opc, PatFrag opnode> {
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (add rGPR:$acc,
|
|
|
|
(opnode (sext_inreg rGPR:$a, i16),
|
|
|
|
(sext_inreg rGPR:$b, i16))))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b001;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b00;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16),
|
2010-08-17 18:39:16 +00:00
|
|
|
(sra rGPR:$b, (i32 16)))))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b001;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b01;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
|
2010-08-17 18:39:16 +00:00
|
|
|
(sext_inreg rGPR:$b, i16))))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b001;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b10;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
|
2010-08-17 18:39:16 +00:00
|
|
|
(sra rGPR:$b, (i32 16)))))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b001;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b11;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
|
2010-08-17 18:39:16 +00:00
|
|
|
(sext_inreg rGPR:$b, i16)), (i32 16))))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b011;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b00;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
|
2009-10-27 00:08:59 +00:00
|
|
|
!strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
|
2010-08-17 18:39:16 +00:00
|
|
|
(sra rGPR:$b, (i32 16))), (i32 16))))]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-23} = 0b0110;
|
|
|
|
let Inst{22-20} = 0b011;
|
|
|
|
let Inst{15-12} = {?, ?, ?, ?}; // Ra
|
|
|
|
let Inst{7-6} = 0b00;
|
|
|
|
let Inst{5-4} = 0b01;
|
|
|
|
}
|
2009-07-07 01:17:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
|
|
|
|
defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
|
|
|
|
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst),
|
2010-08-17 18:39:16 +00:00
|
|
|
(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst),
|
2010-08-17 18:39:16 +00:00
|
|
|
(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst),
|
2010-08-17 18:39:16 +00:00
|
|
|
(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst),
|
2010-08-17 18:39:16 +00:00
|
|
|
(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]>;
|
|
|
|
|
|
|
|
// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
|
|
|
|
// These are for disassembly only.
|
|
|
|
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2SMUAD: T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
|
|
|
|
IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
}
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2SMUADX:T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
|
|
|
|
IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
}
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2SMUSD: T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
|
|
|
|
IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
}
|
2010-08-17 18:39:16 +00:00
|
|
|
def t2SMUSDX:T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
|
|
|
|
IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
}
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst),
|
|
|
|
(ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlad",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"\t$dst, $a, $b, $acc", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst),
|
|
|
|
(ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smladx",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"\t$dst, $a, $b, $acc", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst),
|
|
|
|
(ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsd",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"\t$dst, $a, $b, $acc", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst),
|
|
|
|
(ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsdx",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"\t$dst, $a, $b, $acc", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
|
|
|
|
(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlald",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"\t$ldst, $hdst, $a, $b", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
|
|
|
|
(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaldx",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"\t$ldst, $hdst, $a, $b", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
|
|
|
|
(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsld",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"\t$ldst, $hdst, $a, $b", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
|
|
|
|
(ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsldx",
|
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26 22:04:29 +00:00
|
|
|
"\t$ldst, $hdst, $a, $b", []>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Misc. Arithmetic Instructions.
|
|
|
|
//
|
|
|
|
|
2010-02-16 21:23:02 +00:00
|
|
|
class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
|
|
|
|
InstrItinClass itin, string opc, string asm, list<dag> pattern>
|
2009-12-15 17:24:14 +00:00
|
|
|
: T2I<oops, iops, itin, opc, asm, pattern> {
|
|
|
|
let Inst{31-27} = 0b11111;
|
|
|
|
let Inst{26-22} = 0b01010;
|
|
|
|
let Inst{21-20} = op1;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{7-6} = 0b10;
|
|
|
|
let Inst{5-4} = op2;
|
|
|
|
}
|
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
|
|
|
|
"clz", "\t$dst, $src", [(set rGPR:$dst, (ctlz rGPR:$src))]>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
|
2010-01-19 00:44:15 +00:00
|
|
|
"rbit", "\t$dst, $src",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
|
2010-01-18 19:58:49 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
|
2010-08-17 18:39:16 +00:00
|
|
|
"rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
|
2009-12-15 17:24:14 +00:00
|
|
|
"rev16", ".w\t$dst, $src",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst,
|
|
|
|
(or (and (srl rGPR:$src, (i32 8)), 0xFF),
|
|
|
|
(or (and (shl rGPR:$src, (i32 8)), 0xFF00),
|
|
|
|
(or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
|
2010-08-17 18:39:16 +00:00
|
|
|
(and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
|
2009-12-15 17:24:14 +00:00
|
|
|
"revsh", ".w\t$dst, $src",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst,
|
2009-06-23 17:48:47 +00:00
|
|
|
(sext_inreg
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
(or (srl (and rGPR:$src, 0xFF00), (i32 8)),
|
|
|
|
(shl rGPR:$src, (i32 8))), i16))]>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2010-08-17 17:23:19 +00:00
|
|
|
def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
|
2010-09-29 00:27:46 +00:00
|
|
|
IIC_iBITsi, "pkhbt", "\t$dst, $src1, $src2$sh",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF),
|
2010-08-17 17:23:19 +00:00
|
|
|
(and (shl rGPR:$src2, lsl_amt:$sh),
|
2010-05-05 20:44:35 +00:00
|
|
|
0xFFFF0000)))]>,
|
2010-11-01 15:59:52 +00:00
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-20} = 0b01100;
|
|
|
|
let Inst{5} = 0; // BT form
|
|
|
|
let Inst{4} = 0;
|
|
|
|
}
|
2009-07-07 05:35:52 +00:00
|
|
|
|
|
|
|
// Alternate cases for PKHBT where identities eliminate some nodes.
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
|
|
|
|
(t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
|
2010-11-01 15:59:52 +00:00
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]>;
|
2010-08-17 17:23:19 +00:00
|
|
|
def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
|
|
|
|
(t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
|
2010-11-01 15:59:52 +00:00
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]>;
|
2009-07-07 05:35:52 +00:00
|
|
|
|
2010-08-16 22:26:55 +00:00
|
|
|
// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
|
|
|
|
// will match the pattern below.
|
2010-08-17 17:23:19 +00:00
|
|
|
def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
|
2010-09-29 00:27:46 +00:00
|
|
|
IIC_iBITsi, "pkhtb", "\t$dst, $src1, $src2$sh",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
|
2010-08-17 17:23:19 +00:00
|
|
|
(and (sra rGPR:$src2, asr_amt:$sh),
|
|
|
|
0xFFFF)))]>,
|
2010-11-01 15:59:52 +00:00
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-20} = 0b01100;
|
|
|
|
let Inst{5} = 1; // TB form
|
|
|
|
let Inst{4} = 0;
|
|
|
|
}
|
2009-07-07 05:35:52 +00:00
|
|
|
|
|
|
|
// Alternate cases for PKHTB where identities eliminate some nodes. Note that
|
|
|
|
// a shift amount of 0 is *not legal* here, it is PKHBT instead.
|
2010-08-16 22:26:55 +00:00
|
|
|
def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
|
2010-08-17 17:23:19 +00:00
|
|
|
(t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
|
2010-11-01 15:59:52 +00:00
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
|
2010-08-17 17:23:19 +00:00
|
|
|
(and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
|
|
|
|
(t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
|
2010-11-01 15:59:52 +00:00
|
|
|
Requires<[HasT2ExtractPack, IsThumb2]>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Comparison Instructions...
|
|
|
|
//
|
2009-12-15 17:24:14 +00:00
|
|
|
defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
|
2010-09-29 00:49:25 +00:00
|
|
|
IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
|
|
|
|
defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
|
2010-09-29 00:49:25 +00:00
|
|
|
IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2010-08-26 15:50:25 +00:00
|
|
|
//FIXME: Disable CMN, as CCodes are backwards from compare expectations
|
|
|
|
// Compare-to-zero still works out, just not the relationals
|
2010-01-22 00:08:13 +00:00
|
|
|
//defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
|
|
|
|
// BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
|
2010-08-26 15:50:25 +00:00
|
|
|
defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
|
2010-09-29 00:49:25 +00:00
|
|
|
IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
|
2010-08-26 15:50:25 +00:00
|
|
|
BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
|
|
|
|
|
2010-01-22 00:08:13 +00:00
|
|
|
//def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
|
|
|
|
// (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
|
2010-08-26 15:50:25 +00:00
|
|
|
|
|
|
|
def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
|
|
|
|
(t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
defm t2TST : T2I_cmp_irs<0b0000, "tst",
|
2010-09-29 00:49:25 +00:00
|
|
|
IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
|
|
|
|
defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
|
2010-09-29 00:49:25 +00:00
|
|
|
IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
|
2009-12-15 17:24:14 +00:00
|
|
|
BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-07-07 20:39:03 +00:00
|
|
|
// Conditional moves
|
|
|
|
// FIXME: should be able to write a pattern for ARMcmov, but can't use
|
2010-02-16 21:07:46 +00:00
|
|
|
// a two-value operand where a dag node expects two operands. :(
|
2010-11-13 02:25:14 +00:00
|
|
|
let neverHasSideEffects = 1 in {
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
|
2009-10-27 00:08:59 +00:00
|
|
|
"mov", ".w\t$dst, $true",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
|
2009-12-15 17:24:14 +00:00
|
|
|
RegConstraint<"$false = $dst"> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = 0b0010;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{14-12} = 0b000;
|
|
|
|
let Inst{7-4} = 0b0000;
|
|
|
|
}
|
2009-07-07 20:39:03 +00:00
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
|
2009-10-27 00:08:59 +00:00
|
|
|
IIC_iCMOVi, "mov", ".w\t$dst, $true",
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
|
2009-12-15 17:24:14 +00:00
|
|
|
RegConstraint<"$false = $dst"> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = 0b0010;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
|
|
|
|
2010-10-07 00:53:56 +00:00
|
|
|
def t2MOVCCi16 : T2I<(outs rGPR:$dst), (ins rGPR:$false, i32imm:$src),
|
2010-11-12 22:42:47 +00:00
|
|
|
IIC_iCMOVi,
|
2010-10-07 00:53:56 +00:00
|
|
|
"movw", "\t$dst, $src", []>,
|
|
|
|
RegConstraint<"$false = $dst"> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 1;
|
|
|
|
let Inst{24-21} = 0b0010;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
|
|
|
|
2010-11-13 02:25:14 +00:00
|
|
|
def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
|
|
|
|
(ins rGPR:$false, i32imm:$src, pred:$p),
|
2010-11-13 05:14:20 +00:00
|
|
|
IIC_iCMOVix2, "", []>, RegConstraint<"$false = $dst">;
|
2010-11-13 02:25:14 +00:00
|
|
|
|
2010-11-12 22:42:47 +00:00
|
|
|
def t2MVNCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
|
|
|
|
IIC_iCMOVi, "mvn", ".w\t$dst, $true",
|
|
|
|
[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm_not:$true,
|
|
|
|
imm:$cc, CCR:$ccr))*/]>,
|
|
|
|
RegConstraint<"$false = $dst"> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{25} = 0;
|
|
|
|
let Inst{24-21} = 0b0011;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{15} = 0;
|
|
|
|
}
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
|
|
|
|
string opc, string asm, list<dag> pattern>
|
2010-11-15 19:58:36 +00:00
|
|
|
: T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b01;
|
|
|
|
let Inst{24-21} = 0b0010;
|
|
|
|
let Inst{20} = 0; // The S bit.
|
|
|
|
let Inst{19-16} = 0b1111; // Rn
|
|
|
|
let Inst{5-4} = opcod; // Shift type.
|
|
|
|
}
|
2010-11-15 19:58:36 +00:00
|
|
|
def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
|
|
|
|
(ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
|
|
|
|
IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
|
|
|
|
RegConstraint<"$false = $Rd">;
|
|
|
|
def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
|
|
|
|
(ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
|
|
|
|
IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
|
|
|
|
RegConstraint<"$false = $Rd">;
|
|
|
|
def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
|
|
|
|
(ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
|
|
|
|
IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
|
|
|
|
RegConstraint<"$false = $Rd">;
|
|
|
|
def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
|
|
|
|
(ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
|
|
|
|
IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
|
|
|
|
RegConstraint<"$false = $Rd">;
|
2010-09-23 23:45:25 +00:00
|
|
|
} // neverHasSideEffects
|
2009-08-01 01:43:45 +00:00
|
|
|
|
2009-12-14 18:56:47 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Atomic operations intrinsics
|
|
|
|
//
|
|
|
|
|
|
|
|
// memory barriers protect the atomic sequences
|
|
|
|
let hasSideEffects = 1 in {
|
2010-10-30 00:54:37 +00:00
|
|
|
def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
|
|
|
|
"dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
|
|
|
|
Requires<[IsThumb, HasDB]> {
|
|
|
|
bits<4> opt;
|
|
|
|
let Inst{31-4} = 0xf3bf8f5;
|
|
|
|
let Inst{3-0} = opt;
|
2009-12-14 18:56:47 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-10-30 00:54:37 +00:00
|
|
|
def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
|
|
|
|
"dsb", "\t$opt",
|
|
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
|
|
Requires<[IsThumb, HasDB]> {
|
|
|
|
bits<4> opt;
|
|
|
|
let Inst{31-4} = 0xf3bf8f4;
|
|
|
|
let Inst{3-0} = opt;
|
2010-03-03 00:16:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// ISB has only full system option -- for disassembly only
|
2010-10-30 00:54:37 +00:00
|
|
|
def t2ISB : T2I<(outs), (ins), NoItinerary, "isb", "",
|
|
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
|
|
Requires<[IsThumb2, HasV7]> {
|
|
|
|
let Inst{31-4} = 0xf3bf8f6;
|
2010-03-03 00:16:28 +00:00
|
|
|
let Inst{3-0} = 0b1111;
|
|
|
|
}
|
|
|
|
|
2009-12-15 17:24:14 +00:00
|
|
|
class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
|
|
InstrItinClass itin, string opc, string asm, string cstr,
|
|
|
|
list<dag> pattern, bits<4> rt2 = 0b1111>
|
|
|
|
: Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0001101;
|
|
|
|
let Inst{11-8} = rt2;
|
|
|
|
let Inst{7-6} = 0b01;
|
|
|
|
let Inst{5-4} = opcod;
|
|
|
|
let Inst{3-0} = 0b1111;
|
|
|
|
}
|
|
|
|
class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
|
|
|
|
InstrItinClass itin, string opc, string asm, string cstr,
|
|
|
|
list<dag> pattern, bits<4> rt2 = 0b1111>
|
|
|
|
: Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0001100;
|
|
|
|
let Inst{11-8} = rt2;
|
|
|
|
let Inst{7-6} = 0b01;
|
|
|
|
let Inst{5-4} = opcod;
|
|
|
|
}
|
|
|
|
|
2009-12-14 18:56:47 +00:00
|
|
|
let mayLoad = 1 in {
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
|
2009-12-15 17:24:14 +00:00
|
|
|
Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
|
|
|
|
"", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
|
2009-12-15 17:24:14 +00:00
|
|
|
Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
|
|
|
|
"", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2LDREX : Thumb2I<(outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
|
2009-12-15 17:24:14 +00:00
|
|
|
Size4Bytes, NoItinerary,
|
|
|
|
"ldrex", "\t$dest, [$ptr]", "",
|
|
|
|
[]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0000101;
|
|
|
|
let Inst{11-8} = 0b1111;
|
|
|
|
let Inst{7-0} = 0b00000000; // imm8 = 0
|
|
|
|
}
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$dest, rGPR:$dest2), (ins rGPR:$ptr),
|
2009-12-15 17:24:14 +00:00
|
|
|
AddrModeNone, Size4Bytes, NoItinerary,
|
|
|
|
"ldrexd", "\t$dest, $dest2, [$ptr]", "",
|
|
|
|
[], {?, ?, ?, ?}>;
|
2009-12-14 18:56:47 +00:00
|
|
|
}
|
|
|
|
|
2009-12-16 19:44:06 +00:00
|
|
|
let mayStore = 1, Constraints = "@earlyclobber $success" in {
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2STREXB : T2I_strex<0b00, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
|
2009-12-15 17:24:14 +00:00
|
|
|
AddrModeNone, Size4Bytes, NoItinerary,
|
|
|
|
"strexb", "\t$success, $src, [$ptr]", "", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2STREXH : T2I_strex<0b01, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
|
2009-12-15 17:24:14 +00:00
|
|
|
AddrModeNone, Size4Bytes, NoItinerary,
|
|
|
|
"strexh", "\t$success, $src, [$ptr]", "", []>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2STREX : Thumb2I<(outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
|
2009-12-15 17:24:14 +00:00
|
|
|
AddrModeNone, Size4Bytes, NoItinerary,
|
|
|
|
"strex", "\t$success, $src, [$ptr]", "",
|
|
|
|
[]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0000100;
|
|
|
|
let Inst{7-0} = 0b00000000; // imm8 = 0
|
|
|
|
}
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2STREXD : T2I_strex<0b11, (outs rGPR:$success),
|
|
|
|
(ins rGPR:$src, rGPR:$src2, rGPR:$ptr),
|
2009-12-15 17:24:14 +00:00
|
|
|
AddrModeNone, Size4Bytes, NoItinerary,
|
|
|
|
"strexd", "\t$success, $src, $src2, [$ptr]", "", [],
|
|
|
|
{?, ?, ?, ?}>;
|
2009-12-14 18:56:47 +00:00
|
|
|
}
|
|
|
|
|
2010-03-02 22:11:06 +00:00
|
|
|
// Clear-Exclusive is for disassembly only.
|
|
|
|
def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
|
|
|
|
[/* For disassembly only; pattern left blank */]>,
|
|
|
|
Requires<[IsARM, HasV7]> {
|
|
|
|
let Inst{31-20} = 0xf3b;
|
|
|
|
let Inst{15-14} = 0b10;
|
|
|
|
let Inst{12} = 0;
|
|
|
|
let Inst{7-4} = 0b0010;
|
|
|
|
}
|
|
|
|
|
2009-07-08 16:09:28 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// TLS Instructions
|
|
|
|
//
|
|
|
|
|
|
|
|
// __aeabi_read_tp preserves the registers r1-r3.
|
|
|
|
let isCall = 1,
|
|
|
|
Defs = [R0, R12, LR, CPSR] in {
|
2009-08-06 16:52:47 +00:00
|
|
|
def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
|
2009-10-27 00:08:59 +00:00
|
|
|
"bl\t__aeabi_read_tp",
|
2009-12-15 17:24:14 +00:00
|
|
|
[(set R0, ARMthread_pointer)]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{15-14} = 0b11;
|
|
|
|
let Inst{12} = 1;
|
|
|
|
}
|
2009-07-08 16:09:28 +00:00
|
|
|
}
|
|
|
|
|
2009-08-11 19:42:21 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SJLJ Exception handling intrinsics
|
2009-08-13 15:11:43 +00:00
|
|
|
// eh_sjlj_setjmp() is an instruction sequence to store the return
|
2009-08-11 19:42:21 +00:00
|
|
|
// address and save #0 in R0 for the non-longjmp case.
|
|
|
|
// Since by its nature we may be coming from some other function to get
|
|
|
|
// here, and we're using the stack frame for the containing function to
|
|
|
|
// save/restore registers, we can't keep anything live in regs across
|
|
|
|
// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
|
|
|
|
// when we get here from a longjmp(). We force everthing out of registers
|
|
|
|
// except for our own input by listing the relevant registers in Defs. By
|
|
|
|
// doing so, we also cause the prologue/epilogue code to actively preserve
|
|
|
|
// all of the callee-saved resgisters, which is exactly what we want.
|
2010-05-27 23:49:24 +00:00
|
|
|
// $val is a scratch register for our use.
|
2010-02-08 23:22:00 +00:00
|
|
|
let Defs =
|
2009-08-13 16:59:44 +00:00
|
|
|
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
|
|
|
|
D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
|
2009-08-11 19:42:21 +00:00
|
|
|
D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
|
2010-10-31 19:15:18 +00:00
|
|
|
D31 ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
|
2010-08-26 17:02:47 +00:00
|
|
|
def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
|
2010-09-30 16:56:53 +00:00
|
|
|
AddrModeNone, SizeSpecial, NoItinerary, "", "",
|
2010-08-26 17:02:47 +00:00
|
|
|
[(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
|
2010-04-09 20:41:18 +00:00
|
|
|
Requires<[IsThumb2, HasVFP2]>;
|
2009-08-11 19:42:21 +00:00
|
|
|
}
|
|
|
|
|
2010-04-09 20:41:18 +00:00
|
|
|
let Defs =
|
2010-05-28 17:37:40 +00:00
|
|
|
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
|
2010-10-31 19:15:18 +00:00
|
|
|
hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
|
2010-08-26 17:02:47 +00:00
|
|
|
def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
|
2010-09-30 16:56:53 +00:00
|
|
|
AddrModeNone, SizeSpecial, NoItinerary, "", "",
|
2010-08-26 17:02:47 +00:00
|
|
|
[(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
|
2010-04-09 20:41:18 +00:00
|
|
|
Requires<[IsThumb2, NoVFP]>;
|
|
|
|
}
|
2009-08-11 19:42:21 +00:00
|
|
|
|
|
|
|
|
2009-06-30 18:04:13 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Control-Flow Instructions
|
|
|
|
//
|
|
|
|
|
2009-07-09 22:58:39 +00:00
|
|
|
// FIXME: remove when we have a way to marking a MI with these properties.
|
|
|
|
// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
|
|
|
|
// operand list.
|
|
|
|
// FIXME: Should pc be an implicit operand like PICADD, etc?
|
2009-10-01 08:22:27 +00:00
|
|
|
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
|
2010-10-31 19:10:56 +00:00
|
|
|
hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
|
2010-11-03 01:01:43 +00:00
|
|
|
def t2LDM_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
|
|
|
|
reglist:$dsts, variable_ops),
|
2010-10-06 06:27:31 +00:00
|
|
|
IIC_iLoad_mBr,
|
2010-11-03 01:01:43 +00:00
|
|
|
"ldm${amode}${p}.w\t$Rn!, $dsts",
|
|
|
|
"$Rn = $wb", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-25} = 0b00;
|
|
|
|
let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
|
|
|
|
let Inst{22} = 0;
|
2010-03-13 01:08:20 +00:00
|
|
|
let Inst{21} = 1; // The W bit.
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{20} = 1; // Load
|
|
|
|
}
|
2009-07-09 22:58:39 +00:00
|
|
|
|
2009-06-30 18:04:13 +00:00
|
|
|
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
|
|
|
|
let isPredicable = 1 in
|
2009-08-06 16:52:47 +00:00
|
|
|
def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
|
2009-10-27 00:08:59 +00:00
|
|
|
"b.w\t$target",
|
2009-12-15 17:24:14 +00:00
|
|
|
[(br bb:$target)]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{15-14} = 0b10;
|
|
|
|
let Inst{12} = 1;
|
|
|
|
}
|
2009-06-30 18:04:13 +00:00
|
|
|
|
2010-11-02 23:40:41 +00:00
|
|
|
let isNotDuplicable = 1, isIndirectBranch = 1,
|
|
|
|
isCodeGenOnly = 1 in { // $id doesn't exist in asmstring, should be lowered.
|
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:33:29 +00:00
|
|
|
def t2BR_JT :
|
2009-07-29 02:18:14 +00:00
|
|
|
T2JTI<(outs),
|
|
|
|
(ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
|
2010-07-31 06:28:10 +00:00
|
|
|
IIC_Br, "mov\tpc, $target$jt",
|
2009-12-15 17:24:14 +00:00
|
|
|
[(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0100100;
|
|
|
|
let Inst{19-16} = 0b1111;
|
|
|
|
let Inst{14-12} = 0b000;
|
|
|
|
let Inst{11-8} = 0b1111; // Rd = pc
|
|
|
|
let Inst{7-4} = 0b0000;
|
|
|
|
}
|
2009-07-29 02:18:14 +00:00
|
|
|
|
2009-08-01 06:13:52 +00:00
|
|
|
// FIXME: Add a non-pc based case that can be predicated.
|
2010-11-02 23:40:41 +00:00
|
|
|
let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered.
|
2009-07-29 02:18:14 +00:00
|
|
|
def t2TBB :
|
2009-08-01 06:13:52 +00:00
|
|
|
T2JTI<(outs),
|
2009-07-29 02:18:14 +00:00
|
|
|
(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
|
2010-07-31 06:28:10 +00:00
|
|
|
IIC_Br, "tbb\t$index$jt", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0001101;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
|
|
|
|
let Inst{15-8} = 0b11110000;
|
|
|
|
let Inst{7-4} = 0b0000; // B form
|
|
|
|
}
|
2009-07-29 02:18:14 +00:00
|
|
|
|
2010-11-02 23:40:41 +00:00
|
|
|
let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered.
|
2009-07-29 02:18:14 +00:00
|
|
|
def t2TBH :
|
2009-08-01 06:13:52 +00:00
|
|
|
T2JTI<(outs),
|
2009-07-29 02:18:14 +00:00
|
|
|
(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
|
2010-07-31 06:28:10 +00:00
|
|
|
IIC_Br, "tbh\t$index$jt", []> {
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0001101;
|
|
|
|
let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
|
|
|
|
let Inst{15-8} = 0b11110000;
|
|
|
|
let Inst{7-4} = 0b0001; // H form
|
|
|
|
}
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
|
|
|
|
// Generic versions of the above two instructions, for disassembly only
|
|
|
|
|
|
|
|
def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
|
|
|
|
"tbb", "\t[$a, $b]", []>{
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0001101;
|
|
|
|
let Inst{15-8} = 0b11110000;
|
|
|
|
let Inst{7-4} = 0b0000; // B form
|
|
|
|
}
|
|
|
|
|
|
|
|
def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
|
|
|
|
"tbh", "\t[$a, $b, lsl #1]", []> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0001101;
|
|
|
|
let Inst{15-8} = 0b11110000;
|
|
|
|
let Inst{7-4} = 0b0001; // H form
|
|
|
|
}
|
2009-07-29 02:18:14 +00:00
|
|
|
} // isNotDuplicable, isIndirectBranch
|
|
|
|
|
2009-06-30 19:50:22 +00:00
|
|
|
} // isBranch, isTerminator, isBarrier
|
2009-06-30 18:04:13 +00:00
|
|
|
|
|
|
|
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
|
|
|
|
// a two-value operand where a dag node expects two operands. :(
|
|
|
|
let isBranch = 1, isTerminator = 1 in
|
2009-08-06 16:52:47 +00:00
|
|
|
def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
|
2009-10-27 00:08:59 +00:00
|
|
|
"b", ".w\t$target",
|
2009-12-15 17:24:14 +00:00
|
|
|
[/*(ARMbrcond bb:$target, imm:$cc)*/]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{15-14} = 0b10;
|
|
|
|
let Inst{12} = 0;
|
|
|
|
}
|
2009-06-23 17:48:47 +00:00
|
|
|
|
2009-07-10 01:54:42 +00:00
|
|
|
|
|
|
|
// IT block
|
2010-06-18 23:09:54 +00:00
|
|
|
let Defs = [ITSTATE] in
|
2009-07-10 01:54:42 +00:00
|
|
|
def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
|
2009-08-19 18:00:44 +00:00
|
|
|
AddrModeNone, Size2Bytes, IIC_iALUx,
|
2009-12-15 17:24:14 +00:00
|
|
|
"it$mask\t$cc", "", []> {
|
|
|
|
// 16-bit instruction.
|
2009-12-16 02:32:54 +00:00
|
|
|
let Inst{31-16} = 0x0000;
|
2009-12-15 17:24:14 +00:00
|
|
|
let Inst{15-8} = 0b10111111;
|
|
|
|
}
|
2009-07-10 01:54:42 +00:00
|
|
|
|
2010-02-25 19:05:29 +00:00
|
|
|
// Branch and Exchange Jazelle -- for disassembly only
|
|
|
|
// Rm = Inst{19-16}
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
|
2010-02-25 19:05:29 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{26} = 0;
|
|
|
|
let Inst{25-20} = 0b111100;
|
|
|
|
let Inst{15-14} = 0b10;
|
|
|
|
let Inst{12} = 0;
|
|
|
|
}
|
|
|
|
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
// Change Processor State is a system instruction -- for disassembly only.
|
|
|
|
// The singleton $opt operand contains the following information:
|
|
|
|
// opt{4-0} = mode from Inst{4-0}
|
|
|
|
// opt{5} = changemode from Inst{17}
|
|
|
|
// opt{8-6} = AIF from Inst{8-6}
|
|
|
|
// opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
|
2010-03-10 18:59:38 +00:00
|
|
|
def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
|
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:14:57 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{26} = 0;
|
|
|
|
let Inst{25-20} = 0b111010;
|
|
|
|
let Inst{15-14} = 0b10;
|
|
|
|
let Inst{12} = 0;
|
|
|
|
}
|
|
|
|
|
2010-03-03 02:09:43 +00:00
|
|
|
// A6.3.4 Branches and miscellaneous control
|
|
|
|
// Table A6-14 Change Processor State, and hint instructions
|
|
|
|
// Helper class for disassembly only.
|
|
|
|
class T2I_hint<bits<8> op7_0, string opc, string asm>
|
|
|
|
: T2I<(outs), (ins), NoItinerary, opc, asm,
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-20} = 0xf3a;
|
|
|
|
let Inst{15-14} = 0b10;
|
|
|
|
let Inst{12} = 0;
|
|
|
|
let Inst{10-8} = 0b000;
|
|
|
|
let Inst{7-0} = op7_0;
|
|
|
|
}
|
|
|
|
|
|
|
|
def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
|
|
|
|
def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
|
|
|
|
def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
|
|
|
|
def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
|
|
|
|
def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
|
|
|
|
|
|
|
|
def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-20} = 0xf3a;
|
|
|
|
let Inst{15-14} = 0b10;
|
|
|
|
let Inst{12} = 0;
|
|
|
|
let Inst{10-8} = 0b000;
|
|
|
|
let Inst{7-4} = 0b1111;
|
|
|
|
}
|
|
|
|
|
2010-02-25 20:25:24 +00:00
|
|
|
// Secure Monitor Call is a system instruction -- for disassembly only
|
|
|
|
// Option = Inst{19-16}
|
|
|
|
def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{26-20} = 0b1111111;
|
|
|
|
let Inst{15-12} = 0b1000;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Store Return State is a system instruction -- for disassembly only
|
|
|
|
def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0000010; // W = 1
|
|
|
|
}
|
|
|
|
|
|
|
|
def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0000000; // W = 0
|
|
|
|
}
|
|
|
|
|
|
|
|
def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0011010; // W = 1
|
|
|
|
}
|
|
|
|
|
|
|
|
def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
|
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0011000; // W = 0
|
|
|
|
}
|
|
|
|
|
|
|
|
// Return From Exception is a system instruction -- for disassembly only
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2RFEDBW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfedb", "\t$base!",
|
2010-02-25 20:25:24 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0000011; // W = 1
|
|
|
|
}
|
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2RFEDB : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeab", "\t$base",
|
2010-02-25 20:25:24 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0000001; // W = 0
|
|
|
|
}
|
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2RFEIAW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base!",
|
2010-02-25 20:25:24 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0011011; // W = 1
|
|
|
|
}
|
|
|
|
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2RFEIA : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base",
|
2010-02-25 20:25:24 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11101;
|
|
|
|
let Inst{26-20} = 0b0011001; // W = 0
|
|
|
|
}
|
|
|
|
|
2009-06-23 17:48:47 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Non-Instruction Patterns
|
|
|
|
//
|
|
|
|
|
2009-10-21 20:44:34 +00:00
|
|
|
// Two piece so_imms.
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(or rGPR:$LHS, t2_so_imm2part:$RHS),
|
|
|
|
(t2ORRri (t2ORRri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
|
2009-10-21 20:44:34 +00:00
|
|
|
(t2_so_imm2part_2 imm:$RHS))>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(xor rGPR:$LHS, t2_so_imm2part:$RHS),
|
|
|
|
(t2EORri (t2EORri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
|
2009-10-21 20:44:34 +00:00
|
|
|
(t2_so_imm2part_2 imm:$RHS))>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def : T2Pat<(add rGPR:$LHS, t2_so_imm2part:$RHS),
|
|
|
|
(t2ADDri (t2ADDri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
|
2009-10-21 20:44:34 +00:00
|
|
|
(t2_so_imm2part_2 imm:$RHS))>;
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
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def : T2Pat<(add rGPR:$LHS, t2_so_neg_imm2part:$RHS),
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(t2SUBri (t2SUBri rGPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
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2009-11-23 20:35:53 +00:00
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(t2_so_neg_imm2part_2 imm:$RHS))>;
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2009-10-21 20:44:34 +00:00
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2009-09-28 09:14:39 +00:00
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// 32-bit immediate using movw + movt.
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2010-09-24 22:03:46 +00:00
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// This is a single pseudo instruction to make it re-materializable.
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// FIXME: Remove this when we can do generalized remat.
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2009-09-28 09:14:39 +00:00
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let isReMaterializable = 1 in
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2010-10-06 22:01:26 +00:00
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def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
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"", [(set rGPR:$dst, (i32 imm:$src))]>,
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Requires<[IsThumb, HasV6T2]>;
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2009-11-06 23:52:48 +00:00
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2009-11-24 00:44:37 +00:00
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// ConstantPool, GlobalAddress, and JumpTable
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def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
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Requires<[IsThumb2, DontUseMovt]>;
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def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
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def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
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Requires<[IsThumb2, UseMovt]>;
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def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
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(t2LEApcrelJT tjumptable:$dst, imm:$id)>;
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2009-11-06 23:52:48 +00:00
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// Pseudo instruction that combines ldr from constpool and add pc. This should
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// be expanded into two instructions late to allow if-conversion and
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// scheduling.
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2010-02-27 23:47:46 +00:00
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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2009-11-06 23:52:48 +00:00
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def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
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2010-10-01 23:21:38 +00:00
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IIC_iLoadiALU, "",
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2009-11-06 23:52:48 +00:00
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[(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
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imm:$cp))]>,
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Requires<[IsThumb2]>;
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2010-02-25 18:46:43 +00:00
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//===----------------------------------------------------------------------===//
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// Move between special register and ARM core register -- for disassembly only
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//
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// Rd = Instr{11-8}
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
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def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
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2010-02-25 18:46:43 +00:00
|
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|
[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{26} = 0;
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let Inst{25-21} = 0b11111;
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let Inst{20} = 0; // The R bit.
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let Inst{15-14} = 0b10;
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let Inst{12} = 0;
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}
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|
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|
|
// Rd = Instr{11-8}
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
|
2010-02-25 18:46:43 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{26} = 0;
|
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|
let Inst{25-21} = 0b11111;
|
|
|
|
let Inst{20} = 1; // The R bit.
|
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|
let Inst{15-14} = 0b10;
|
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|
let Inst{12} = 0;
|
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|
|
}
|
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|
|
|
|
|
|
// Rn = Inst{19-16}
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
|
2010-03-10 18:59:38 +00:00
|
|
|
"\tcpsr$mask, $src",
|
2010-02-25 18:46:43 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{26} = 0;
|
|
|
|
let Inst{25-21} = 0b11100;
|
|
|
|
let Inst{20} = 0; // The R bit.
|
|
|
|
let Inst{15-14} = 0b10;
|
|
|
|
let Inst{12} = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Rn = Inst{19-16}
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
def t2MSRsys : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
|
2010-03-10 18:59:38 +00:00
|
|
|
"\tspsr$mask, $src",
|
2010-02-25 18:46:43 +00:00
|
|
|
[/* For disassembly only; pattern left blank */]> {
|
|
|
|
let Inst{31-27} = 0b11110;
|
|
|
|
let Inst{26} = 0;
|
|
|
|
let Inst{25-21} = 0b11100;
|
|
|
|
let Inst{20} = 1; // The R bit.
|
|
|
|
let Inst{15-14} = 0b10;
|
|
|
|
let Inst{12} = 0;
|
|
|
|
}
|