Chris Lattner
59f8a6a666
fix PR7465, mishandling of lcall and ljmp: intersegment long
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call and jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 01:18:43 +00:00
Daniel Dunbar
c983b20661
MC/ELF: Allow null values in virtual sections, ELF doesn't use special
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directives for putting contents in .bss, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 18:22:37 +00:00
Bob Wilson
f955f290c9
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
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printing "lsl #0 ". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 17:23:19 +00:00
Bob Wilson
20d8e4e7aa
Add a Thumb2 t2RSBrr instruction for disassembly only.
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This fixes another part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 23:24:25 +00:00
Bob Wilson
38aa2871fc
Move the Thumb2 SSAT and USAT optional shift operator out of the
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instruction opcode. This fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 21:48:10 +00:00
Johnny Chen
1adc40cac3
Cleaned up the for-disassembly-only entries in the arm instruction table so that
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the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:46:17 +00:00
Johnny Chen
270159fcc2
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
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entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 01:40:54 +00:00
Daniel Dunbar
09062b1672
MC/X86/AsmParser: Give an explicit error message when we reject an instruction
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because it could have an ambiguous suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 00:55:42 +00:00
Johnny Chen
7def14f40f
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
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Added two test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:35:12 +00:00
Bob Wilson
eaf1c98a7c
Move the ARM SSAT and USAT optional shift amount operand out of the
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instruction opcode. This also fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:10:46 +00:00
Daniel Dunbar
345a9a6269
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:20 +00:00
Daniel Dunbar
e25c6b95ce
MC/AsmParser: Fix a bug in macro argument parsing, which was dropping
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parentheses from argument lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 17:38:52 +00:00
Bob Wilson
a1d410d512
Add an ARM RSCrr instruction for disassembly only.
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Partial fix for PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 18:59:36 +00:00
Bob Wilson
cff7178844
Add an ARM RSBrr instruction for disassembly only.
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Partial fix for PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 18:23:43 +00:00
Daniel Dunbar
079515f382
tests: Mark MC/AsmParser tests as requiring x86 for now -- almost all of them
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rely on using a specific x86 triple to test what they want to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110337 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 15:44:15 +00:00
Bob Wilson
1d9125a6ff
ARM "rrx" shift operands do not have an immediate. PR7790.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110292 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 00:34:42 +00:00
Michael J. Spencer
237f8fe5df
MC: Fix symbol fragment offsets in COFF.
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Patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-03 05:02:46 +00:00
Bob Wilson
98e1479575
Add support for disassembling VMVN (immediate) instructions. PR7747.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-31 05:57:44 +00:00
Michael J. Spencer
dfd30187c6
Make MC use Windows COFF on Windows and add tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-27 06:46:15 +00:00
Bruno Cardoso Lopes
3c8e1bee63
Support x86 "eiz" and "riz" pseudo index registers in the assembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24 00:06:39 +00:00
Matt Fleming
19d92fcae2
Consolidate the ELF section directive tests into a single file as
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suggested by Chris Lattner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109290 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 23:40:41 +00:00
Bruno Cardoso Lopes
6d7019bcc4
Move AVX encoding tests to different files
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109269 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 21:25:26 +00:00
Bruno Cardoso Lopes
f528d2b438
Add AVX version of CLMUL instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109248 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 18:41:12 +00:00
Bruno Cardoso Lopes
6b7e9168a4
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 00:54:35 +00:00
Bruno Cardoso Lopes
fb583a9842
Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:18:49 +00:00
Bruno Cardoso Lopes
2b69143083
Add more 256-bit forms for a bunch of regular AVX instructions
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Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 23:53:50 +00:00
Bruno Cardoso Lopes
e29f37f6a1
Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 21:37:59 +00:00
Bruno Cardoso Lopes
cf6ca03128
Add AVX only vzeroall and vzeroupper instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109002 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes
7d7d15a159
Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes
4b13f3cf3d
Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
1154f426d7
Add new AVX vextractf128 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 23:19:02 +00:00
Matt Fleming
a7f9563c01
Include some tests for the recently committed ELF section directive
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handlers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 21:37:30 +00:00
Bruno Cardoso Lopes
e1c29be6f0
Add new AVX instruction vinsertf128
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 19:44:51 +00:00
Bruno Cardoso Lopes
7a2b701ef6
x86_32 tests for vbroadcast
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 00:11:50 +00:00
Bruno Cardoso Lopes
43945d99de
Add AVX vbroadcast new instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 00:11:13 +00:00
Bruno Cardoso Lopes
94143ee625
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 23:32:44 +00:00
Daniel Dunbar
77e2dd7bb2
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
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instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 20:44:16 +00:00
Daniel Dunbar
926f2bb3d8
X86-64: Mark WINCALL and more tail call instructions as code gen only.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 07:21:07 +00:00
Daniel Dunbar
90b374cded
MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
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assembling; remove crufty custom cleanup code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108681 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 06:14:54 +00:00
Daniel Dunbar
9ece46d172
tests: Force another triple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108666 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 00:43:58 +00:00
Daniel Dunbar
030794bd87
tests: Force triples.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108658 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 21:16:10 +00:00
Daniel Dunbar
6a46d571b4
MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary token
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sequences, not just strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 20:15:59 +00:00
Daniel Dunbar
7a570d09ac
MC/AsmParser: Add macro argument substitution support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 19:00:10 +00:00
Daniel Dunbar
c64a0d7c3e
MC/AsmParser: Add basic support for macro instantiation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 18:54:11 +00:00
Daniel Dunbar
6d8cf082f6
MC/AsmParser: Add basic parsing support for .macro definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 18:47:21 +00:00
Daniel Dunbar
3c802de01a
MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't
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support macros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108649 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 18:38:02 +00:00
Eli Friedman
879259faa3
Test for ELF .size directive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108607 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17 03:15:24 +00:00
Bruno Cardoso Lopes
7dbf7d8b1c
Add AVX 256-bit compare instructions and a bunch of testcases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108286 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 22:06:38 +00:00
Bruno Cardoso Lopes
87a85c7ef0
AVX 256-bit conversion instructions
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Add the x86 VEX_L form to handle special cases where VEX_L must be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 21:07:28 +00:00
Chris Lattner
37a746bc85
my work on adding segment registers to LEA missed the
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disassembler. Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 04:23:55 +00:00
Bruno Cardoso Lopes
fd920fa59a
Add AVX 256-bit packed logical forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108224 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 02:38:35 +00:00
Bruno Cardoso Lopes
6991623dd7
Add AVX 256-bit unop arithmetic instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108223 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 01:53:31 +00:00
Bruno Cardoso Lopes
a0d09a85e2
Add AVX 256 binary arithmetic instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108207 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 23:04:15 +00:00
Bruno Cardoso Lopes
aa099be71f
Add AVX 256-bit MOVMSK forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108184 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 20:06:32 +00:00
Daniel Dunbar
b6c3a607ac
MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108180 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 19:37:35 +00:00
Daniel Dunbar
492b7a21cb
MC/AsmParser: Move .desc parsing to Darwin specific parser.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 19:22:53 +00:00
Daniel Dunbar
9ac66b008d
MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108174 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 18:49:22 +00:00
Bruno Cardoso Lopes
d52e78efac
Add AVX 256-bit packed MOVNT variants
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:42:42 +00:00
Bruno Cardoso Lopes
2bfb8f6ef8
Add AVX 256-bit unpack and interleave
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:20:35 +00:00
Bruno Cardoso Lopes
e86b01c153
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
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notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 18:27:43 +00:00
Chris Lattner
834df19452
Rework segment prefix emission code to handle segments
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in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:28:12 +00:00
Chris Lattner
9fc05227a2
Implement the major chunk of PR7195: support for 'callw'
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in the integrated assembler. Still some discussion to be
done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
cc69e13a36
Add more assembly opcodes for SSE compare instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:24:03 +00:00
Bruno Cardoso Lopes
ced9ec9bac
Add AVX AES instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:24:20 +00:00
Bruno Cardoso Lopes
4f6bdf9042
Add AVX SSE4.2 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
09df2ae0d0
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
3c14822312
Add AVX SSE4.1 extractps and pinsr instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:01:13 +00:00
Bruno Cardoso Lopes
4fd32db6a6
Add AVX SSE4.1 Extract Integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 00:07:24 +00:00
Bruno Cardoso Lopes
ee94e8297e
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
36869b69b0
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
07de40629f
Add AVX vblendvpd, vblendvps and vpblendvb instructions
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Update VEX encoding to support those new instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:36:24 +00:00
Bruno Cardoso Lopes
68b559e5f3
Add AVX SSE4.1 blend, mpsadbw and vdp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
4a544be3a8
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107558 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
c607570563
Add AVX SSE4.1 Horizontal Minimum and Position instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:49:21 +00:00
Bruno Cardoso Lopes
2c70d4ad35
Add AVX SSE4.1 round instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
f5cd8c51e3
- Add support for the rest of AVX SSE3 instructions
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- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 22:06:54 +00:00
Bruno Cardoso Lopes
c6fcdeb8f9
Move SSE3 Move patterns to a more appropriate section
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Add AVX SSE3 packed horizontal and & sub instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
7144821c61
Add AVX SSE3 packed addsub instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 17:08:18 +00:00
Bruno Cardoso Lopes
79b634c244
Add AVX SSE3 replicate and convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:33:39 +00:00
Bruno Cardoso Lopes
6596a62076
- Add AVX SSE2 Move doubleword and quadword instructions.
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- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
e26f14d150
Add AVX SSE2 mask creation and conditional store instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
1e4b723b20
Add AVX SSE2 packed integer extract/insert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 17:03:03 +00:00
Bruno Cardoso Lopes
876085dcfa
Add AVX SSE2 integer unpack instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
d252fec7ae
Add AVX SSE2 packed integer shuffle instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
6d5d2b5de2
Add AVX SSE2 pack with saturation integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c0ea94a37c
Add AVX SSE2 integer packed compare instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
5a3a476750
- Add AVX form of all SSE2 logical instructions
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- Add VEX encoding bits to x86 MRM0r-MRM7r
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
6c9fa43716
Add *several* AVX integer packed binop instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes
147b7cad2f
Add AVX ld/st XCSR register.
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Add VEX encoding bits for MRMXm x86 form
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
721ef73d88
Add AVX non-temporal stores
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107178 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
ea86423cbd
Add sqrt, rsqrt and rcp AVX instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107166 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:26:30 +00:00
Bruno Cardoso Lopes
4548260ab5
Described the missing AVX forms of SSE2 convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 00:36:02 +00:00
Bruno Cardoso Lopes
bdffc16d65
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes
161476ec34
Reapply r106896:
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Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
95325b08a3
revert this now, it's using avx instead of sse :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes
544a95d716
Add several AVX MOV flavors
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Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:27:51 +00:00
Bruno Cardoso Lopes
a0ae87fd5d
Add some AVX convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
788184365a
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
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- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 20:48:23 +00:00
Chris Lattner
645b209c4a
Teach the x86 mc assembler that %dr6 = %db6, this implements
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rdar://8013734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106725 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 07:29:18 +00:00
Bruno Cardoso Lopes
6539dc6e6c
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
e93e300ad0
Add AVX MOVMSK{PS,PD}rr instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
428256b818
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 21:10:57 +00:00
Bruno Cardoso Lopes
7dbfd07e32
Add AVX SHUF{PS,PD}{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106672 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:07:15 +00:00
Nico Weber
50b9efc2a8
Add support for the x86 instructions "pusha" and "popa".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:00:58 +00:00
Bruno Cardoso Lopes
62a76c6401
Add AVX compare packed instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
0caca3967b
Reapply support for AVX unpack and interleave instructions, with
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testcases this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
c3d57b179c
Add AVX MOV{SS,SD}{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:38:56 +00:00
Eric Christopher
97994e0262
Move a 64-bit test to the 64-bit file. Fixes an llvm-mc assertion
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during test runs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 21:11:51 +00:00
Bruno Cardoso Lopes
f4f4bad696
Refactor aliased packed logical instructions, also add
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AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 02:44:01 +00:00
Bruno Cardoso Lopes
be4d595afd
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:37:31 +00:00
Chris Lattner
1cf44fc051
fix rdar://7873482 by teaching the instruction encoder to emit
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segment prefixes. Daniel wrote most of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:34:00 +00:00
Bruno Cardoso Lopes
d7f9cc4de7
Add {mix,max}{ss,sd}{rr,rm} AVX forms.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:12:56 +00:00
Bruno Cardoso Lopes
cf125d02a0
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105870 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 01:53:48 +00:00
Bruno Cardoso Lopes
7be0d2c8e9
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr
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Handle OpSize TSFlag for AVX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 01:23:26 +00:00
Bruno Cardoso Lopes
c902a59f4c
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
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Introduce the VEX_X field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 23:50:47 +00:00
Bruno Cardoso Lopes
99405df044
Reapply r105521, this time appending "LLU" to 64 bit
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immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:51:23 +00:00
Chris Lattner
1087f54ddb
revert r105521, which is breaking the buildbots with stuff like this:
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In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
3eca98bb3a
Initial AVX support for some instructions. No patterns matched
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yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 03:53:24 +00:00
Kevin Enderby
31cc9655b6
MC/X86: Add alias for movzx.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 21:20:21 +00:00
Kevin Enderby
5e394429ab
MC/X86: Add alias for fwait.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 20:59:10 +00:00
Kevin Enderby
31b6c5b2f3
Fix the use of x86 control and debug registers so that the assertion failure in
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getX86RegNum() does not happen. Patch by Shantonu Sen!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 19:01:27 +00:00
Kevin Enderby
bd658918df
MC/X86: Add aliases for Jcc variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 21:33:19 +00:00
Eric Christopher
bd3ba537cd
Add a quick test of relocations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 00:53:40 +00:00
Kevin Enderby
b106543592
Fix the x86 move to/from segment register instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:10:45 +00:00
Eric Christopher
02b46bc942
Add support for initialized global data for darwin tls. Update comments
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and testcases accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:28:50 +00:00
Kevin Enderby
cf50a5390c
Changed the encoding of X86 floating point stack operations where both operands
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are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 20:52:34 +00:00
Daniel Dunbar
39e2dd7bab
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:32 +00:00
Daniel Dunbar
79373680ed
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:40:53 +00:00
Kevin Enderby
04ac770be9
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
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for the 64-bit version of the Bit Test instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:16:58 +00:00
Eric Christopher
7e2f5aaa67
Make sure aeskeygenassist uses an unsigned immediate field.
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Fixes rdar://8017638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:33:22 +00:00
Dan Gohman
e350690e3b
Fix an mmx movd encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:51:08 +00:00
Kevin Enderby
ca956dc0f6
MC/X86: Add aliases for CMOVcc variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:32:23 +00:00
Daniel Dunbar
62e4c671b6
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
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addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:33 +00:00
Daniel Dunbar
4c361972fd
MC/X86: Add alias for setz, setnz, jz, jnz.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 06:37:33 +00:00
Kevin Enderby
9d31d79493
Added retl for 32-bit x86 and added retq for 64-bit x86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:01:38 +00:00
Daniel Dunbar
4e7f8390c0
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:36:29 +00:00
Dan Gohman
e5e4ff974d
Fix assembly parsing and encoding of the pushf and popf family of
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:16:00 +00:00
Dan Gohman
14aaeac5cf
Define the x86 pause instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:35:50 +00:00
Dan Gohman
ee5673b622
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
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doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:23:41 +00:00
Chris Lattner
a7f1354eb5
fix rdar://7986634 - match instruction opcodes case insensitively.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:34:33 +00:00
Eric Christopher
591466baff
A more combo tls testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:19:42 +00:00
Eric Christopher
aa6c72ec95
Few more simple tls testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104148 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:35:15 +00:00
Eric Christopher
b4e876e37e
Quick test to make sure we're emitting the tbss section correctly.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:40:20 +00:00
Kevin Enderby
d8ba292c9b
Fixed the problem with a branch to "0b" that was not parsed by llvm-mc
...
correctly. The Lexer was incorrectly eating the newline casusing it to branch
to address 0. Updated the test case to use a "0:" label and a branch to "0b".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104038 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:51:35 +00:00
Daniel Dunbar
2ae4bfd769
MC/Mach-O: Implement support for setting indirect symbol table offset in section header.
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Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:28:24 +00:00
Kevin Enderby
ebe7fcd041
Added support in MC for Directional Local Labels.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103989 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:08:19 +00:00
Eric Christopher
c6177a4531
More data/parsing support for tls directives. Add a few more testcases
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and cleanup comments as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 22:53:55 +00:00
Daniel Dunbar
648ac5153e
MC/Mach-O/x86: Optimal nop sequences should only be used for the .text sections, not all sections in the text segment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:54:30 +00:00
Daniel Dunbar
db9014dd8b
MC/Mach-O: Reverse order of SymbolData scanning when emitting instructions.
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- This fixes a string table mismatch with 'as' when two new symbols are defined
in a single instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103979 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:19:59 +00:00
Daniel Dunbar
b18d2dd115
MC/Mach-O: Fix some differences in symbol flag handling.
...
- Don't clear weak reference flag, 'as' was only "trying" to do this, it wasn't
actually succeeding.
- Clear the "lazy bound" bit when we mark something external. This corresponds
roughly to the lazy clearing of the bit that 'as' implements in
symbol_table_lookup.
- The exact meaning of these flags appears pretty loose, since 'as' isn't very
consistent. For now we just try to match 'as', we will clean this up one day
hopefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:12:31 +00:00
Daniel Dunbar
525a3a67c1
llvm-mc: Support reassignment of variables in one special case, when the
...
variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 17:46:23 +00:00
Eric Christopher
d04d98d24f
Assume that we'll handle mangling the symbols earlier and just put the
...
symbol to the file as we have it. Simplifies out tbss handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103928 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 02:13:02 +00:00
Kevin Enderby
c3ce05c594
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an
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argument, like "int $4", to not get an Assertion error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 19:16:02 +00:00
Daniel Dunbar
f0f6cdb6b4
MC/Mach-O/x86_64: Darwin's special "signed_N" relocation types should only be
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used to replace a normal relocation, not a reference to a GOT entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 18:53:40 +00:00
Eric Christopher
482eba054a
Add AsmParser support for darwin tbss directive.
...
Nothing uses this yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 01:50:28 +00:00
Daniel Dunbar
2f93667f0b
MC/Mach-O: Add another zerofill test to improve coverage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 01:10:28 +00:00
Chris Lattner
7bb7c55a61
fix rdar://7965971 and a fixme: use ParseIdentifier in
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ParseDirectiveDarwinZerofill instead of hard coding the
check for identifier. This allows quoted symbol names to
be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103682 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 00:10:34 +00:00
Chris Lattner
b5505d0ee3
reapply r103668 with a fix. Never make "minor syntax changes"
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after testing before committing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103681 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 00:02:47 +00:00
Chris Lattner
3519f9d7d1
revert r103668 for now, it is apparently breaking things.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 23:40:59 +00:00
Chris Lattner
0de8e3f10a
moffset forms of moves are x86-32 only, make the parser
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lower them to the correct x86-64 instructions since we
don't have a clean way to handle this in td files yet.
rdar://7947184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103668 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 23:13:36 +00:00
Chris Lattner
2745f6e920
fix the encoding of the obscure "moffset" forms of moves, i386
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part first. rdar://7947184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 22:48:24 +00:00
Daniel Dunbar
0481449a05
MC/X86: Extend suffix matching hack to match 'q' suffix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103535 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 00:54:20 +00:00
Daniel Dunbar
a5f1d57f65
MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can
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be diced into atoms, and adjust getAtom() to take this into account.
- This fixes relocations to symbols in fixed size literal sections, for
example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103532 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 00:38:17 +00:00
Daniel Dunbar
db4c7e606f
MC/Mach-O/x86_64: Fix PCrel adjustment for x86_64, which was using the fixup
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offset instead of the fixup address as intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 23:53:11 +00:00
Daniel Dunbar
651804c3d6
MC/Mach-O x86_64: Switch to using fragment atom symbol.
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- This eliminates getAtomForAddress() (which was a linear search) and
simplifies getAtom().
- This also fixes some correctness problems where local labels at the same
address as non-local labels could be assigned to the wrong atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 17:22:50 +00:00
Daniel Dunbar
a8251fac10
MC/Mach-O: Fix another mismatch with .weak_definition, we shouldn't use a
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scattered relocation entry with a .weak_definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 23:15:20 +00:00
Kevin Enderby
a6eeb6e226
Fix i386 relocations to Weak Definitions. The relocation entries should be
...
external and the item to be relocated should not have the address of the
symbol added in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103302 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 21:44:23 +00:00
Daniel Dunbar
c26ae5ab7e
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand.
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- This fixes "leal 0, %eax", for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 22:39:14 +00:00
Chris Lattner
e1611f26e3
fix rdar://7947167 - llvm-mc doesn't match movsq
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 21:48:14 +00:00
Sean Callanan
1a8b789a4b
Eliminated the classification of control registers into %ecr_
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and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
Daniel Dunbar
5fe03c023c
Revert r103137, fix for $ in labels. It looks like we can't actually handle this
...
at the token level. Consider the following horrible test case:
a = 1
.globl $a
movl ($a), %eax
movl $a, %eax
movl $$a, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103178 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 14:46:38 +00:00
Chris Lattner
851f87c6c9
fix rdar://7946934 - in some limited cases, the assembler should
...
allow $ at the start of a symbol name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103137 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 23:51:28 +00:00
Daniel Dunbar
2d7fd61e94
MC/Mach-O: Mark absolute variable's appropriately, and add Mach-O support for
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writing them.
- <rdar://problem/7885351> integrated assembler broken for i386 objc code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 19:01:05 +00:00
Daniel Dunbar
ae7fb0b03e
MC/Mach-O/x86_64: Relocations in debug sections should use local relocations
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when possible.
- <rdar://problem/7934873>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103092 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 17:22:39 +00:00
Daniel Dunbar
e9f0fb4179
MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of
...
instructions which have no direct register usage.
Darwin 'as' accepts:
add $0, (%rax)
but rejects
mov $0, (%rax)
for example.
Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103015 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 17:31:02 +00:00
Daniel Dunbar
c918d6043b
MC/X86: Add "support" for matching ATT style mnemonic prefixes.
...
- The idea is that when a match fails, we just try to match each of +'b', +'w',
+'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
it. If all match, we assume it is width generic, and take the 'l' form.
- This would be a horrible hack, if it weren't so simple. Therefore it is an
elegant solution! Chris gets the credit for this particular elegant
solution. :)
- Next step to making this more robust is to have the X86 matcher generate the
mnemonic prefix information. Ideally we would also compute up-front exactly
which mnemonic to attempt to match, but this may require more custom code in
the matcher than is really worth it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 16:12:42 +00:00
Kevin Enderby
9d0838fba8
Changed llvm-mc to use the same suffixes with floating point compare
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instructions as the Mac OS X darwin assembler. Some of which like 'fcoml'
assembled to different opcodes. While some of the suffixes were just different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102958 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 21:31:40 +00:00
Kevin Enderby
eb612347f4
Fixed the encoding of two of the X86 movq instuctions. The Move quadword from
...
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 21:03:31 +00:00
Kevin Enderby
3c979b06c0
Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value
...
caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value. Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte. Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 20:45:05 +00:00
Kevin Enderby
9ac7282117
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the
...
Operand size override prefix to be part of their records.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102556 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 23:20:40 +00:00
Johnny Chen
52d2b0ed00
Thumb instructions which have reglist operands at the end and predicate operands
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before reglist were not properly handled with respect to IT Block. Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:01:19 +00:00
Johnny Chen
56a1afb6b0
When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12,
...
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 18:45:24 +00:00
Johnny Chen
ef37e3abb7
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
...
transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 17:28:50 +00:00
Johnny Chen
22e401f5d4
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
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Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed. That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.
Also add a test case for condition field '1111'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 21:19:52 +00:00
Johnny Chen
4b7df442a8
ARM disassembler did not react to recent changes to the NEON instruction table.
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VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 16:20:34 +00:00
Chris Lattner
eef6d78be1
teach the x86 asm parser how to handle segment prefixes
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in memory operands. rdar://7874844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 18:56:34 +00:00
Chris Lattner
0fb372a497
testcase for r101538, patch by Nico Schmidt!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 17:22:06 +00:00
Chris Lattner
65de1b9eb3
a bunch of ssse3 instructions are misencoded to think they have an
...
i8 field when they really do not. This fixes rdar://7840289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101629 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 07:38:24 +00:00
Johnny Chen
f7e2bc80d1
Minor change to make the test case comply with Vd<0> == '0' when Q == '1'.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101559 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 22:48:31 +00:00
Johnny Chen
c7b65914e0
Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a
...
case. Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.
Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 22:40:20 +00:00
Johnny Chen
16fda6982b
In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),
...
this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 19:57:21 +00:00
Johnny Chen
2fb10f17d8
Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
...
to the UAL syntax of LDCL<c>, instead.
Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 19:33:23 +00:00
Johnny Chen
cd52932dce
Added another test case for am3offset operand, testing Rn, #+/-imm8.
...
Previous checkin tested Rn, #+/-Rm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101418 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 23:23:40 +00:00
Johnny Chen
1cfa094562
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
...
am2offset. Modified the instruction table entry and added a new test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 23:12:47 +00:00
Daniel Dunbar
4c7276a4eb
tests: MC/Disassembler tests depend on ARM support being compiler in.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101337 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 03:47:20 +00:00
Chris Lattner
d305035155
implement mc asmparser support for '.', which gets the
...
current PC. rdar://7834775
We now produce an identical .o file compared to the cctools
assembler for something like this:
_f0:
L0:
jmp L1
.long . - L0
L1:
jmp A
.long . - L1
.zerofill __DATA,_bss,A,0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 04:40:28 +00:00
Johnny Chen
bb6e9d8cf7
Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after calling
...
ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2.
Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from
ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V).
[12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc
GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done
(gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
(gdb) r
Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
Reading symbols for shared libraries ++. done
0xf5 0x71 0xf0 0x53
Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1|
-------------------------------------------------------------------------------------------------
mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229.
Program received signal SIGABRT, Aborted.
0x00007fff88c65886 in __kill ()
(gdb) bt
#0 0x00007fff88c65886 in __kill ()
#1 0x00007fff88d05eae in abort ()
#2 0x00007fff88cf2ef0 in __assert_rtn ()
#3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229
#4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254
#5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236
#6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182
#7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65
#8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153
#9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347
#10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374
(gdb) q
The program is running. Exit anyway? (y or n) y
[13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-12 18:46:53 +00:00
Benjamin Kramer
447b19543b
unXFAIL, arm disassembler was reenabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 21:19:41 +00:00
Evan Cheng
1b0194d646
Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 01:04:27 +00:00
Johnny Chen
b68a3ee82a
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
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backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Reviewed by Chris Latter and Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
Daniel Dunbar
1de558b71f
MC/Mach-O/x86_64: Support @GOTPCREL on symbols, even for non-PCrel relocations!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99853 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 23:56:40 +00:00
Bob Wilson
86afec7730
Reapply Kevin's change 94440, now that Chris has fixed the limitation on
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opcode values fitting in one byte (svn r99494).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 16:36:14 +00:00
Daniel Dunbar
e9cfd685f5
MC: Fix refacto in MCExpr evaluation, I mistakenly replaced a fragment address with a symbol address.
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- This fixes the integrated-as nightly test regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 01:03:17 +00:00
Bob Wilson
014dc4e720
Speculatively revert this to see if it fixes buildbot failures.
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--- Reverse-merging r99440 into '.':
U test/MC/AsmParser/X86/x86_32-bit_cat.s
U test/MC/AsmParser/X86/x86_32-encoding.s
U include/llvm/IntrinsicsX86.td
U include/llvm/CodeGen/SelectionDAGNodes.h
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 23:26:29 +00:00
Kevin Enderby
760c2f34d9
Added the Advanced Encryption Standard (AES) Instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99440 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 22:33:33 +00:00
Kevin Enderby
044be39090
Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does
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not get an "Unknown immediate size" assert failure when used. All instructions
of this form have an 8-bit immediate. Also added a test case of an example
instruction that is of this form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 22:28:42 +00:00
Daniel Dunbar
78fcf53a18
MC/Mach-O: Remove Darwin host specific tests, we don't need them anymore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99100 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 22:36:32 +00:00
Daniel Dunbar
57a49a202f
MC/Mach-O: Tweak optimal_nop test to be host independent.
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- This also avoids us running valgrind on /usr/bin/as, which has leaks. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 22:36:29 +00:00
Kevin Enderby
b46b03b36f
Fixed the encoding problems of the crc32 instructions. All had the Operand size
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override prefix and only the r/m16 forms should have had that. Also for variant
one, the AT&T syntax, added suffixes to all forms. Also added the missing
64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 20:04:42 +00:00
Daniel Dunbar
602b40f0d0
MC/Mach-O/x86_64: Add relocation support.
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- This is "extraordinarily" Darwin 'as' compatible. See the litany of FIXMEs littered about for more information.
- There are a few cases which seem to clearly be 'as' bugs which I have left unsupported, and there is one cases where we diverge but should fix if it blocks diffing .o files (Darwin 'as' ends up widening a jump unnecessarily).
- 403.gcc build, runs, and diffs equivalently to the 'as' built version now (using llvm-mc). However, it builds so slowly that I wouldn't recommend trying it quite yet. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 18:07:55 +00:00
Daniel Dunbar
0180daee02
MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98972 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 18:07:48 +00:00
Daniel Dunbar
939f8d7ca2
MC/Mach-O: Factor out isScatteredFixupFullyResolvedSimple predicate, and fix some corner cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98924 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 03:18:12 +00:00
Daniel Dunbar
c28c7689fc
X86: Fix encoding for TEST64rr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:15:03 +00:00
Daniel Dunbar
9fdac902d4
X86MCCodeEmitter: Fix two minor issues with reloc_riprel_4byte_movq_load, we
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were missing it on some movq instructions and were not including the appropriate
PCrel bias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:53:54 +00:00
Daniel Dunbar
f98bc6320b
MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement a
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temporary workaround for matching inc/dec on x86_64 to the correct instruction.
- This hack will eventually be replaced with a robust mechanism for handling
matching instructions based on the available target features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:06:02 +00:00
Chris Lattner
618d0ed4bc
fix an x86-64 encoding bug Daniel found.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:04:36 +00:00
Chris Lattner
0f53cf2236
add a special relocation type for movq loads for object
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files that produce special relocation types where the
linker changes movq's into lea's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98839 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 18:10:56 +00:00
Daniel Dunbar
d6e59084d0
MC/Mach-O/x86_64: Temporary labels in cstring sections require symbols (and external relocations, but we don't have x86_64 relocations yet).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-15 21:56:50 +00:00
Chris Lattner
3b39f89006
xfail properly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98479 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 07:55:34 +00:00
Chris Lattner
9e2dab7dbe
xfail these tests temporarily to get teh buildbots back to happy land.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98476 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 07:32:48 +00:00
Daniel Dunbar
859c9dc867
X86: Fix ADD64i32 encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 22:49:39 +00:00
Daniel Dunbar
5691e74f97
MC/X86_64: Symbol support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 22:49:35 +00:00
Daniel Dunbar
ee0d89245e
MC/Mach-O: Initial x86_64 support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 22:10:17 +00:00
Daniel Dunbar
96e2cec9c7
MC/X86_64: Fix matching of leaq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98444 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 19:31:44 +00:00
Daniel Dunbar
989ac72981
MC/X86_64: Fix matching of callq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 19:31:38 +00:00
Daniel Dunbar
da3e9f760c
MC/Mach-O: PCrel relocations weren't using the right base address, they are
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relative to the fragment address, not its offset. This was masked by the text
section normally being at address 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 02:38:00 +00:00
Daniel Dunbar
d5e7705a05
MC/X86: Add temporary hack to match shrl $1,%eax correctly, to support testing
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other functionality on 403.gcc compiled at -O0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 00:47:29 +00:00
Daniel Dunbar
69c695ee47
MC/X86: Add an XFAIL test where we aren't matching the correct instruction
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because we don't understand how the specific instruction is doing sign
extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 00:47:25 +00:00
Daniel Dunbar
f08fde41f3
MC/Mach-O: Implement initial support for relaxation.
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- The implementation is currently very brain dead and inefficient, but I have a
clear plan on how to fix it.
- The good news is, it works and correctly assembles 403.gcc (when built with
Clang, at '-Os', '-Os -g', and '-O3'). Even better, at '-Os' and '-Os -g',
the resulting binary is exactly equivalent to that when built with the system
assembler. So it probably works! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-12 22:07:14 +00:00
Daniel Dunbar
979ba5b3c7
MC/Mach-O: Implement "absolutizing" semantics of .set, by evaluating the assembly time value of variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-11 05:53:37 +00:00
Daniel Dunbar
a015c1c876
MC/Mach-O: Use the SECTDIFF relocation type for (A - B + constant) where A is external.
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- I'm not sure why, but this is what 'as' does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 00:58:25 +00:00
Daniel Dunbar
f291be3159
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 22:50:46 +00:00
Daniel Dunbar
1e8ee89c21
MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 22:50:40 +00:00
Daniel Dunbar
f3a066f7c3
MC/Mach-O: For PCrel relocations, we need to compensate for the PCrel adjustment when determining if we need a scattered relocation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 21:27:58 +00:00
Kevin Enderby
0e822407b2
Fix the vmxon entry in the X86InstrInfo.td so it has the correct prefix bytes
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for the encoding and is not the same as vmptrld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 22:17:26 +00:00
Daniel Dunbar
b2b4acd757
MC/Macho-O: Align the zerofill section itself to the maximum alignment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 22:03:42 +00:00
Daniel Dunbar
37fad5ce4d
MC/Mach-O: Fix address compution for zero fill sections.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 21:10:42 +00:00
Daniel Dunbar
b93c72cda4
X86: Fix encoding for TEST{8,16,32}rr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 21:10:36 +00:00
Kevin Enderby
d74acb0c78
This is a patch to the assembler frontend to detect when aligning a text
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section with TextAlignFillValue and calls EmitCodeAlignment() instead of
calling EmitValueToAlignment(). This allows x86 assembly code to be aligned
with optimal nops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97158 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25 18:46:04 +00:00
Chris Lattner
a08b587494
make pcrel immediate values relative to the start of the field,
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not the end of the field, fixing rdar://7651978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 05:03:17 +00:00
Chris Lattner
b779033a23
add encoder support and tests for rdtscp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 03:42:24 +00:00
Daniel Dunbar
e9a60eb498
MC/AsmParser: Attempt to constant fold expressions up-front. This ensures we avoid fixups for obvious cases like '-(16)'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 01:28:07 +00:00
Chris Lattner
f068304b1f
rip out the 'heinous' x86 MCCodeEmitter implementation.
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We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:49:29 +00:00
Chris Lattner
a599de2410
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs
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fix swapgs to be spelled right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:41:14 +00:00
Daniel Dunbar
9c60f534cb
MC/X86: Push immediate operands as immediates not expressions when possible.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:17:21 +00:00
Chris Lattner
ca3eeb33a8
add some disassemble testcases for weird instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96045 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 23:46:48 +00:00
Chris Lattner
4a2e5edb94
implement the rest of correct x86-64 encoder support for
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rip-relative addresses, and add a testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 23:24:09 +00:00
Chris Lattner
c4d3f662fc
fix the encodings of monitor and mwait, which were completely
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busted in both encoders. I'm not bothering to fix it in the
old one at this point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 01:06:22 +00:00
Kevin Enderby
1c5bcac7d5
Remove the few # TAILCALL comments that snuck in. As they may fail on linux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95827 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-11 00:18:12 +00:00
Kevin Enderby
ac175e251d
Update the X86 assembler matcher test case now that a few more things match
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with some of the recent changes that have gone into llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-11 00:13:43 +00:00