Jim Grosbach
6b15639e26
Trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 21:39:08 +00:00
Owen Anderson
d2fbdb7f5c
Provide correct encodings for the get_lane and set_lane variants of vmov.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 21:28:09 +00:00
Jim Grosbach
ccf72caa92
JIT imm12 encoding for constant pool entry references.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:39:40 +00:00
Bob Wilson
f20700ca77
SelectionDAG shuffle nodes do not allow operands with different numbers of
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elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:38:28 +00:00
Jim Grosbach
f31430f6ec
ARM JIT fix for LDRi12 and company.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 19:55:59 +00:00
Owen Anderson
f587a9352a
Provide correct NEON encodings for vdup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 19:25:54 +00:00
Jim Grosbach
093177d5cd
The new LDR* instruction patterns should handle the necessary encoding of
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operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 17:52:51 +00:00
Owen Anderson
0745c389d9
Add correct NEON encodings for vsli and vsri.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 17:40:08 +00:00
Owen Anderson
dd31ed67e6
Add correct NEON encodings for vsra and vrsra.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 17:29:29 +00:00
Jim Grosbach
063efbf569
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
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encoding tricks. Handle the 'imm doesn't fit in the insn' case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 16:50:31 +00:00
Jim Grosbach
77aee8e22c
LDRi12 machine instructions handle negative offset operands normally (simple
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integer values), not with the addrmode2 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 01:19:41 +00:00
Jim Grosbach
f85dd04bfa
One more spot where the new arm mode LDR instruction representation
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doesn't need the additional addrmode2 register operand. Missed it the first
time around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:38:16 +00:00
Jim Grosbach
c1d30212e9
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
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rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:19:44 +00:00
Jim Grosbach
28e3fe961f
Since I parameterized this bit, I should probably actually use said parameter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117418 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 23:58:04 +00:00
Owen Anderson
86ed2324a6
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 22:50:46 +00:00
Jim Grosbach
3e55612472
First part of refactoring ARM addrmode2 (load/store) instructions to be more
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explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 22:37:02 +00:00
Owen Anderson
632c235a31
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 21:58:41 +00:00
Owen Anderson
ac92262b61
Simplify classes for shift instructions, which are never commutable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 21:13:59 +00:00
Owen Anderson
3557d00a38
Provide correct NEON encodings for vshl, register and immediate forms.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 20:56:57 +00:00
Jim Grosbach
0eb7d06ab1
Grammar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117388 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 19:34:41 +00:00
Jim Grosbach
c3baf62800
Nuke extraneous comment. It's applicable elsewhere, but not in this func.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 19:22:23 +00:00
Owen Anderson
bc4118bd36
Add correct NEON encoding for vpadal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 18:18:03 +00:00
Owen Anderson
a88ea03bf2
Add NEON encodings for vmov and vmvn of immediates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 17:40:54 +00:00
Evan Cheng
c8141dfc7f
Use instruction itinerary to determine what instructions are 'cheap'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 02:08:50 +00:00
Evan Cheng
0e9996ca94
NEON vmov's are in Neon domain.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 02:03:05 +00:00
Bob Wilson
b3a6817d06
Tidy up redundant check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 00:02:19 +00:00
Rafael Espindola
3336384239
Produce the headers directly in the Finish method. This allows us to use
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the existing streamer methods that are endian safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 22:26:55 +00:00
Owen Anderson
5258b61966
Add correct encodings for NEON vabal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117315 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 21:29:04 +00:00
Owen Anderson
410aebc670
Add correct NEON encodings for vaba.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:52:57 +00:00
Owen Anderson
31e6ed890a
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117294 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:17:22 +00:00
Owen Anderson
4110b4325d
Provide correct NEON encodings for vbsl.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:13:13 +00:00
Jim Grosbach
458f2dc5d1
imm12 operands aren't Thumb2 only, so rename the printer helper function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:00:01 +00:00
Owen Anderson
162875a9f3
Add correct instruction encodings for vbic, vorn, and vmvn.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:43:52 +00:00
Rafael Espindola
4921e2356e
Add a virtual destructor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:38:32 +00:00
Owen Anderson
8c71eff594
Provide correct NEON encodings for vand, veor, and vorr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:28:30 +00:00
Owen Anderson
d0c5b6170f
Add NEON encoding tests for vcgt and vacgt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:03:59 +00:00
Rafael Espindola
cecbc3d282
Add support for emitting ARM file attributes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:50:35 +00:00
Owen Anderson
10c15e5d58
Add tests for NEON encodings of vcge and vacge.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:49:32 +00:00
Owen Anderson
4fe20bbd66
Add a warning about our inability to test the encoding of vceq with immediate zero.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117273 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:33:02 +00:00
Eric Christopher
a4633f5d74
Move rejection of NEON parameters earlier in fast isel call processing,
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note that we can actually handle some f64 arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 09:37:17 +00:00
Chandler Carruth
19e57025d4
Move the remaining attribute macros to systematic names based on the attribute
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name and prefixed with 'LLVM_'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 08:40:19 +00:00
Chandler Carruth
100c267249
Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
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until other LLVM projects using these are cleaned up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 08:10:43 +00:00
Evan Cheng
5c2d428f43
Enable ARM fastcc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 02:19:37 +00:00
Evan Cheng
dd9dd6f857
Latency between CPSR def and branch is zero.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 02:04:38 +00:00
Jim Grosbach
a9a968d1ef
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117188 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 23:48:29 +00:00
Gabor Greif
41f31ef28e
fix memory-layout assumption which only holds on little-endian systems
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 23:16:11 +00:00
Jim Grosbach
f8da5f5dfa
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 22:12:16 +00:00
Evan Cheng
b179b46cc5
Transfer implicit ops when forming load multiple and return instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 21:29:58 +00:00
Owen Anderson
9b26497273
Add correct NEON encodings for vqdmlal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:35:48 +00:00
Jim Grosbach
385e136dce
Add the encoding information for the rest of the ARM mode multiply instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:15:30 +00:00
Owen Anderson
92205842ca
Provide correct encodings for NEON vmlal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117131 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:05:25 +00:00
Evan Cheng
1f8b40d51c
Silence compiler warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:57:05 +00:00
Owen Anderson
18341e9e31
Provide correct NEON encodings for vmla.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:54:37 +00:00
Jim Grosbach
3870b750e6
More ARM multiply instuction binary encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:35:16 +00:00
Evan Cheng
76f920d316
Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:23:05 +00:00
Jim Grosbach
929a7056d8
Parameterize a bit of ARM encoding information, simplifying some instruction
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definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 17:42:06 +00:00
Jim Grosbach
9463d0e400
More ARM multiply instruction encoding information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 17:16:17 +00:00
Wesley Peck
eecb858ca8
Making the e_machine configurable by the target backend in ELFObjectWriter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 15:52:49 +00:00
Eric Christopher
4f512efee9
Add some basic ret instruction support to arm fast-isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117085 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 01:28:00 +00:00
Jim Grosbach
f50af8b5b8
ARM binary encoding for some of the multiply instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:52:30 +00:00
Jim Grosbach
3686046a2c
ARM binary encodings for MVN variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:19:32 +00:00
Jim Grosbach
3fea19105d
ARM Binary encoding information for BFC/BFI instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:03:21 +00:00
Eric Christopher
1778772d1b
These don't need to be virtual.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 21:47:51 +00:00
Owen Anderson
90d4cf9314
Move the encoding logic for Q registers into getMachineOpValue().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:49:13 +00:00
Owen Anderson
d451f888b8
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
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half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:21:49 +00:00
Eric Christopher
5b924809e4
Handle storing args to the stack for calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:09:54 +00:00
Eric Christopher
212ae937bb
More load/store refactoring, call reg+offset simplification from within
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the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 19:40:30 +00:00
Jim Grosbach
3ab5658a12
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 19:38:40 +00:00
Owen Anderson
1e93466c3a
Add correct NEON encodings for vhadd and vrhadd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:55:04 +00:00
Owen Anderson
9d50559bae
Add correct encodings for NEON vaddw.s* and vaddw.u*.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:20:25 +00:00
Owen Anderson
e0e6dc3f4e
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:09:17 +00:00
Duncan Sands
dbbd99faf1
The return value of this call is not used, so no point
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in assigning it to a variable (gcc-4.6 warning).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 16:06:28 +00:00
Andrew Trick
5b7a825ec5
putback r116983 and fix simple-fp-encoding.ll tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:40:16 +00:00
Owen Anderson
d9707e3d85
Revert r116983, which is breaking all the buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:11:16 +00:00
Evan Cheng
d6865de2d2
Add missing scheduling itineraries for transfers between core registers and VFP registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 01:12:00 +00:00
Owen Anderson
d7795540d0
Implement correct encodings for NEON vadd, both integer and floating point.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 00:48:00 +00:00
Eric Christopher
2d8f6fe610
Custom lower f64 args passed in integer registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 00:01:47 +00:00
Bill Wendling
01aabdac44
Add encoding for moving a value between two ARM core registers and a doublework
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extension register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116970 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 23:37:40 +00:00
Bill Wendling
7d31a169af
Add encodings for movement between ARM core registers and single-precision
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registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 22:44:54 +00:00
Dale Johannesen
e4d31593c5
Fix crash introduced in 116852. 8573915.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 22:03:37 +00:00
Chandler Carruth
1cd9708f5c
Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three
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#includes in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 08:27:02 +00:00
Eric Christopher
3659ac22c0
Fix a TODO by removing some unnecesary copies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 08:02:24 +00:00
Jim Grosbach
b8e67fc92b
Fix backwards conditional.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 01:10:01 +00:00
Jim Grosbach
8b95c3ebfb
Add dynamic realignment when rematerializing the base register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 00:02:50 +00:00
Jim Grosbach
f6d7df6f21
Nuke a commented out bit that got missed a while back.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 23:48:47 +00:00
Jim Grosbach
e4ad387a5a
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
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setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 23:27:08 +00:00
Jim Grosbach
8155ea4c3a
Update comments to remove obsolete references.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 21:34:47 +00:00
Dale Johannesen
575cd148ce
Enable using vdup for vector constants which are splat of
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integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 20:00:17 +00:00
Evan Cheng
2312842de0
Re-enable register pressure aware machine licm with fixes. Hoist() may have
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erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 18:58:51 +00:00
Daniel Dunbar
9869413802
Revert r116781 "- Add a hook for target to determine whether an instruction def
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is", which breaks some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 17:14:24 +00:00
Evan Cheng
11e8b74a7a
- Add a hook for target to determine whether an instruction def is
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"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:55:07 +00:00
Bob Wilson
3454ed9545
Support alignment for NEON vld-lane and vst-lane instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:16:32 +00:00
Jim Grosbach
70987fbc60
ARM encoding information for [SU]SAT* instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 23:35:38 +00:00
Eric Christopher
6e5367d6a3
Revert r116220 - thus turning arm fast isel back on by default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 22:53:53 +00:00
Bill Wendling
b41ee96d76
Don't recompute MachineRegisterInfo in the Optimize* method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 21:22:31 +00:00
Jim Grosbach
5c57639c28
For Thumb2, try to use frame pointer references for stack slots even when a
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base register is available. rdar://8525298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116729 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 18:39:46 +00:00
Jim Grosbach
0f0127f4a6
ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate
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offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 16:48:59 +00:00
Jim Grosbach
e038a206df
Grammar tweak.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 16:38:50 +00:00
Eric Christopher
4cf34c6c04
Remove the check for invalid calling conventions. Testing shows that they're
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working just fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116698 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 06:49:12 +00:00
Eric Christopher
fa87d66752
Lift arg promotion from the X86 backend. This should be unified at some point.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 02:17:53 +00:00
Eric Christopher
404be0c04f
Now that we handle all allocas via a non-SP reg offset remove all of the
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special case handling for ARM::SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 11:08:44 +00:00
Eric Christopher
ec8bf972f5
Allow more load types to be materialized through the allocas.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 06:07:26 +00:00
Eric Christopher
d56d61af01
Optimize GEP off of intermediate allocas.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116681 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:51:42 +00:00
Eric Christopher
7208dbf2d5
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116680 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:42:53 +00:00
Eric Christopher
dc0b0ef6cd
Turn on AddOperator folding in GEP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116679 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:41:46 +00:00
Eric Christopher
45c607134b
Use the i12 immediate versions of the load instructions - they're handled
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more in the post-passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:40:27 +00:00
Rafael Espindola
f230df9af4
Add a MCObjectFormat class so that code common to all targets that use a
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single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116675 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-16 18:23:53 +00:00
Eric Christopher
47650ece37
Fix some funky formatting that got through.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-16 01:10:35 +00:00
Bill Wendling
07fda9f9b6
ARMCodeEmitter::emitMiscInstruction is dead. Long live
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ARMCodeEmitter::emitMiscInstruction!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 23:35:12 +00:00
Eric Christopher
c9a91fdaf9
Make sure offset is 0 for load/store register to the stack call.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 23:07:10 +00:00
Eric Christopher
00ed59a968
Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 22:49:28 +00:00
Eric Christopher
315030ca74
Fix else if -> if in store machinery.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 22:32:37 +00:00
Bill Wendling
2695d8edd1
Reformatting. No functionalogicality changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116625 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 21:50:45 +00:00
Eric Christopher
a322425642
Refactor ARM fast-isel reg + offset to be a base + offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 21:32:12 +00:00
Jim Grosbach
5ad01c7728
Encoding information for the various ARM saturating add/sub instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116612 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 19:49:46 +00:00
Jim Grosbach
84760885e1
ARM binary encoding information for RSB and RSC instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116604 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 18:42:41 +00:00
Jim Grosbach
fd52906478
Don't mark argument value stores as immutable, as otherwise the post-RA
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scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116602 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 18:34:47 +00:00
Bob Wilson
01b35c25de
Use simple RegState::Define flag instead of getDefRegState(true).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 18:25:59 +00:00
Eric Christopher
2896df897c
Expand GEP handling for constant offsets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 18:02:07 +00:00
Jim Grosbach
6bdc8ae291
When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes
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an explicit def. Make sure to capture that properly. rdar://8556556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116591 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 17:35:17 +00:00
Jim Grosbach
8abe32af38
ARM mode encoding information for UBFX and SBFX instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 17:15:16 +00:00
Bob Wilson
1dd5a2f4e1
Remove unused ARMISD::AND selection DAG node.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 04:34:40 +00:00
Bob Wilson
cfbece50f6
ARM instructions that are both predicated and set the condition codes
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have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 03:23:44 +00:00
Jim Grosbach
197a8df640
Encoding info for extension instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 02:29:58 +00:00
Jim Grosbach
58456c0b04
Add missing Rd encoding for MOVs instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116537 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 23:28:31 +00:00
Jim Grosbach
7032f922b1
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
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and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 22:57:13 +00:00
Jim Grosbach
792e9796b3
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
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pseudonym.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 20:43:44 +00:00
Jim Grosbach
1de588df69
MOVi16 and MOVT ARM mode encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 18:54:27 +00:00
Jim Grosbach
2d294f564b
Simplify encoding information and add 'dst' operand info for TAILJMP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 17:24:28 +00:00
Oscar Fuentes
7bd698153d
Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
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creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 15:54:46 +00:00
Eric Christopher
eae8439771
Handle more complex GEP based loads and add a few TODOs to deal with
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GEP + alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 09:29:41 +00:00
Bill Wendling
bbbdcd453d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
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here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 02:33:26 +00:00
Bill Wendling
946a2740a5
Add encoding for 'fmstat'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 01:19:34 +00:00
Bill Wendling
88cf038436
- Add encodings for multiply add/subtract instructions in all their glory.
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- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 01:02:08 +00:00
Jim Grosbach
bd38acfa6f
Regenerate. No functional change, just cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 00:15:18 +00:00
Jim Grosbach
55561d1882
Detabify and clean up 80 column violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 23:47:11 +00:00
Jim Grosbach
95369599c6
A few 80 column fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 23:34:31 +00:00
Jim Grosbach
3a37866e53
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 23:12:26 +00:00
Jim Grosbach
b4b07b93ea
Add a FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 22:55:33 +00:00
Jim Grosbach
06ef444e5c
Add operand encoding bits for SMC and SVC in ARM mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 22:38:23 +00:00
Jim Grosbach
832859d062
More encoding cleanup. Also add register Rd operands for indirect branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 22:09:34 +00:00
Jim Grosbach
a7dbc1ead7
Simplify some ARM encoding information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:48:54 +00:00
Eric Christopher
a9c575110f
Update comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:41:51 +00:00
Jim Grosbach
6c354fd3f5
Add a FIXME. The ADR instruction is a bit odd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:32:30 +00:00
Jim Grosbach
b3af5de2d9
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
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and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:00:04 +00:00
Bill Wendling
67a704de03
Add MC encodings for VCVT* instrunctions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:58:46 +00:00
Jim Grosbach
596307e133
Add a FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:38:04 +00:00
Jim Grosbach
fa7d2cb680
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
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wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:30:55 +00:00
Jim Grosbach
b35ad41fef
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 19:56:10 +00:00
Jim Grosbach
e822f94509
Fix encoding for compares. No Rd register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 18:05:25 +00:00