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152 Commits

Author SHA1 Message Date
Evan Cheng
f81bf15552 Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations. 
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89706 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 21:57:23 +00:00
Johnny Chen
da1aea4d75 Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying 
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup.  VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89699 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 21:00:43 +00:00
Johnny Chen
b16ed11cb4 Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify 
{?,?,?,?} as op11_8 for VEXTd and VEXTq.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89693 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 20:09:13 +00:00
Johnny Chen
7ebd32a1b8 Partially revert r89377 by removing NLdStLN class definition from 
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89684 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 18:16:16 +00:00
Johnny Chen
131c4a5257 Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane 
should be left unspecified now that Bob Wilson has fixed pr5470.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89676 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 17:48:17 +00:00
Evan Cheng
ac0869dc8a Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89542 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-21 06:21:52 +00:00
Johnny Chen
5c376ff9f0 Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not 
fully specified at this level.  Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89377 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-19 19:20:17 +00:00
Evan Cheng
b9d2c03d20 Use table to separate opcode from operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86965 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-12 07:16:34 +00:00
Jim Grosbach
e5165490b7 Use Unified Assembly Syntax for the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 00:11:35 +00:00
Bob Wilson
54c78ef2fe Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86301 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:33:28 +00:00
Anton Korobeynikov
3a639a07ea Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:39 +00:00
Jim Grosbach
8cd0a8cb82 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 22:57:36 +00:00
Bob Wilson
b27b51aaa6 Fix NEON VST2LN instruction encoding. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 17:54:01 +00:00
Bob Wilson
407d57489f Revert 84732. It was the wrong fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 17:52:34 +00:00
Bob Wilson
b3c8359360 Fix some more NEON instruction encoding problems. 
Thanks to Johnny Chen for discovering the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84732 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 02:27:20 +00:00
Bob Wilson
507df402b0 Leave some NEON instruction encoding bits unspecified instead of setting 
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84730 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 02:15:46 +00:00
Jim Grosbach
1fc1dc0682 Refs: A8-598. 
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84572 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:38:19 +00:00
Bob Wilson
1dd4348408 Fix more NEON instruction encodings. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84243 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 03:58:44 +00:00
Bob Wilson
6f122625dd Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84206 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 21:57:47 +00:00
Bob Wilson
b3642dccee Fix instruction encoding bits for NEON VPADAL. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84146 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 21:43:17 +00:00
Jim Grosbach
b9d319b585 Inst{11-8} for vshl should be 0b0101, not 0b1111. 
Refs: A7-17 & A8-750.

Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84131 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 20:31:01 +00:00
Bob Wilson
5631139a69 Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 00:01:36 +00:00
Bob Wilson
8cdb269686 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 23:51:31 +00:00
Bob Wilson
c5c6edb74f Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83596 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 23:38:24 +00:00
Bob Wilson
62e053e5a1 Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83590 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 22:53:57 +00:00
Bob Wilson
0bf7d998b4 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 22:27:33 +00:00
Bob Wilson
30aea9d96e Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 18:56:10 +00:00
Bob Wilson
deb3141cf5 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 05:18:18 +00:00
Bob Wilson
5adf60c03b Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:28:28 +00:00
Bob Wilson
24e04c535f Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 00:21:01 +00:00
Bob Wilson
0ea38bb939 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 23:54:04 +00:00
Bob Wilson
c67160c010 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 23:39:57 +00:00
Bob Wilson
a4288080e6 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 22:57:01 +00:00
Bob Wilson
b07c171624 Add some instruction encoding bits for NEON load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83490 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 21:53:04 +00:00
Bob Wilson
63c9063434 Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 20:49:18 +00:00
Bob Wilson
66a70639da Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 20:30:08 +00:00
Bob Wilson
d285575f87 Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:47:39 +00:00
Bob Wilson
7708c22baa Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 18:09:32 +00:00
Bob Wilson
ff8952e8a9 Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-07 17:24:55 +00:00
Bob Wilson
3bf12ab860 Add codegen support for NEON vld2 operations on quad registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 22:01:59 +00:00
Bob Wilson
916ac5b069 Add a comment to describe letters used in multiclass name suffixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83257 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-03 04:44:16 +00:00
Bob Wilson
8f07b9e8a9 Fix encoding problem for VMLS instruction. 
Thanks to Johnny Chen for pointing this out!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83256 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-03 04:41:21 +00:00
Evan Cheng
0d92f5f768 Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 08:22:27 +00:00
David Goodwin
658ea60997 Finish scheduling itineraries for NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82788 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-25 18:38:29 +00:00
David Goodwin
127221fbdc Checkpoint NEON scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-23 21:38:08 +00:00
Anton Korobeynikov
e56f9085b1 Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to 
constraint the register usage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81635 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-12 22:21:08 +00:00
Anton Korobeynikov
2ba62ef7f2 Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81262 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-08 22:51:43 +00:00
Anton Korobeynikov
6ca0b9e722 Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and 
makes the code faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81220 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-08 15:22:32 +00:00
Anton Korobeynikov
69d1c1aebf More missed vdup patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80838 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-02 21:21:28 +00:00
Bob Wilson
8a3198b770 Add support for generating code for vst{234}lane intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80707 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-01 18:51:56 +00:00
Bob Wilson
243fcc5a69 Generate code for vld{234}_lane intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80656 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-01 04:26:28 +00:00
Anton Korobeynikov
d91aafd005 Add missed pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80502 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-30 19:06:39 +00:00
Anton Korobeynikov
2324bdc1ee Add missed extract_element pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80408 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-28 23:41:26 +00:00
Anton Korobeynikov
b5cdf873bc Forgot about actual change :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80250 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-27 16:10:17 +00:00
Anton Korobeynikov
fdf189ac97 Transform float scalar_to_vector into subreg accesses. 
No idea whether this is profitable or not.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80245 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-27 14:38:44 +00:00
Bob Wilson
a123239a5f Remove some unused SDNode definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80015 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-25 17:52:39 +00:00
Bob Wilson
2a9df47abd Expose the instruction contraint string as an argument to the NLdSt class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-25 17:46:06 +00:00
Bob Wilson
4f38b383d5 Rename ARM "lane_cst" operands to "nohash_imm" since they are used for 
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 21:58:55 +00:00
Anton Korobeynikov
051cfd683f Fix some typos and use type-based isel for VZIP/VUZP/VTRN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79625 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 12:41:42 +00:00
Anton Korobeynikov
62e84f177d Add nodes & dummy matchers for some v{zip,uzp,trn} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 12:40:50 +00:00
Anton Korobeynikov
5da894f5c4 Provide vext.{16,32} 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79620 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 12:40:21 +00:00
Bob Wilson
de95c1b88b Add support for Neon VEXT (vector extract) shuffles. 
This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79428 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-19 17:03:43 +00:00
Bob Wilson
c1d287b4b7 Create a new ARM-specific DAG node, VDUP, to represent a splat from a 
scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78994 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 05:13:08 +00:00
Bob Wilson
0ce3710825 During legalization, change Neon vdup_lane operations from shuffles to 
target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78993 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-14 05:08:32 +00:00
Bob Wilson
bab812b4b0 Revert r78852 for now. I want to do this differently, but I don't have time 
to fix it tonight.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78896 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 05:58:56 +00:00
Bob Wilson
af385baa1d Recognize Neon VDUP shuffles during legalization instead of selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78852 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 22:54:19 +00:00
Bob Wilson
d8e1757eac Recognize Neon VREV shuffles during legalization instead of selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 22:31:50 +00:00
Bob Wilson
114a266c94 Generate Neon VTBL and VTBX instructions from the corresponding intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78835 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 20:51:55 +00:00
Bob Wilson
9f7d60f460 Fix TableGen warnings. This partly reverts my previous change to this file, 
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78815 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 17:04:56 +00:00
Bob Wilson
dbd3c0e06d Add missing chain operands for VLD* and VST* instructions. 
Set "mayLoad" and "mayStore" on the load/store instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78761 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 00:49:01 +00:00
Owen Anderson
825b72b057 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 20:47:22 +00:00
Bob Wilson
b0abb4dc42 Use vAny type to get rid of Neon intrinsics that differed only in whether 
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78646 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 05:39:44 +00:00
Bob Wilson
f24bd401eb Use new EVT::vAny type to combine Neon intrinsics for VPADD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 01:15:26 +00:00
David Goodwin
f35290ce8d Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78629 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 01:07:38 +00:00
Owen Anderson
e50ed30282 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 22:56:29 +00:00
David Goodwin
338268c67f Use NEON for single-precision int<->FP conversions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78604 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 22:17:39 +00:00
Anton Korobeynikov
8e9ece75db Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 23:10:41 +00:00
Anton Korobeynikov
06af2ba809 Add insert_elt / extract_elt patterns for v4f32 stuff. 
Did anyone tests v4f32 ever?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78470 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 14:06:07 +00:00
Anton Korobeynikov
3405201bce Lane number should be printed w/o hash 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78469 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 14:05:53 +00:00
Anton Korobeynikov
baf31088f1 Use VLDM / VSTM to spill/reload 128-bit Neon registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 13:35:48 +00:00
Bob Wilson
b6ab51e829 Implement Neon VZIP and VUZP instructions. These are very similar to VTRN, 
so I generalized the class for VTRN in the .td file to handle all 3 of them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78460 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 06:13:25 +00:00
Bob Wilson
64efd90f8c Implement Neon VTRN instructions. For now, anyway, these are selected 
directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78459 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 05:53:00 +00:00
Anton Korobeynikov
a55fd4a23f Unbreak the stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78425 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 22:51:13 +00:00
Anton Korobeynikov
32a1b25781 2 more vdup.32 cases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78419 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 22:36:50 +00:00
Evan Cheng
1d2426c470 Fix support to use NEON for single precision fp math. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78397 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 19:30:41 +00:00
Bob Wilson
b36ec86c01 Implement Neon VST[234] operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 18:47:44 +00:00
David Goodwin
8b7d7ade85 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 16:52:47 +00:00
Bob Wilson
0cedab9a0d Neon does not actually have VLD{234}.64 instructions. 
These operations will have to be synthesized from other instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78263 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 00:24:27 +00:00
David Goodwin
7bfdca0206 When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 21:02:22 +00:00
Evan Cheng
61f4b721b2 80 col violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78175 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 06:41:25 +00:00
Bob Wilson
4a3d35abef Change DAG nodes for Neon VLD2/3/4 operations to return multiple results. 
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 00:49:09 +00:00
Bob Wilson
c00479253b Replace dregsingle operand modifier with explicit escaped curly brackets. 
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78109 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 21:39:33 +00:00
David Goodwin
53e4471adc Add NEON single-precision FP support for fabs and fneg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 20:39:05 +00:00
David Goodwin
b84f3d427c Match common pattern for FNMAC. Add NEON SP support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78085 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 18:44:29 +00:00
David Goodwin
42a83f2d15 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 17:53:06 +00:00
Bob Wilson
a599bff101 Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the 
results to fixed registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78025 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 00:36:16 +00:00
Bob Wilson
b7d0c90c44 Change Neon VLDn intrinsics to return multiple values instead of really 
wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 16:39:22 +00:00
Bob Wilson
8bb9e48752 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 00:39:34 +00:00
Evan Cheng
dda0f4cb79 - Add some NEON ld / st instruction static encoding. 
- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75065 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 22:51:32 +00:00
Bob Wilson
2ed334694f Implement NEON vst1 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75037 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 20:32:02 +00:00