6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-21 03:29:40 +00:00
Code Issues Projects Releases Wiki Activity
23,974 Commits 39 Branches 0 Tags 277 MiB
d25db20f1a
Commit Graph

1310 Commits

Author SHA1 Message Date
Chris Lattner
8768bf6ee3 Add the rest of the vmul instructions and the vmulsum* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27268 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 23:39:06 +00:00
Chris Lattner
3c4f4e9f1b Use a new tblgen feature to significantly shrinkify instruction definitions that 
directly correspond to intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27266 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 23:21:27 +00:00
Chris Lattner
30a6abaef0 Add a bunch of new instructions for intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27265 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 23:07:36 +00:00
Chris Lattner
f3a627262c add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27243 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 00:24:13 +00:00
Chris Lattner
d732a2915b add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27227 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 18:56:23 +00:00
Jim Laskey
a99791886d Expose base register for DwarfWriter. Refactor code accordingly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 13:48:33 +00:00
Nate Begeman
816cee2216 Fix a couple typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27216 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 04:18:18 +00:00
Nate Begeman
98e70cc124 Add a few more altivec intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27215 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 04:15:58 +00:00
Chris Lattner
ecc219b8d4 implement a bunch more intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27209 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:29:37 +00:00
Chris Lattner
7f20b13518 Use normal lvx for scalar_to_vector instead of lve*x. They do the exact 
same thing and we have a dag node for the former.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27205 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 01:43:22 +00:00
Chris Lattner
48b61a729d Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27201 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 00:40:33 +00:00
Jim Laskey
414e682bac Translate llvm target registers to dwarf register numbers properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27180 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 20:18:45 +00:00
Chris Lattner
3ee9ffb0e5 Add a bunch of notes from my journey thus far. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27170 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 07:41:00 +00:00
Chris Lattner
b86bd2cee2 Split out altivec notes into their own README 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27168 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 07:04:16 +00:00
Chris Lattner
fb143ce459 Fix the JIT encoding of VSEL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27160 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 03:34:17 +00:00
Chris Lattner
eeaf72af39 Fix the JIT encoding of VSPLTI* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27159 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 03:28:57 +00:00
Nate Begeman
f15485a8d0 SelectionDAGISel can now natively handle Switch instructions, in the same 
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 01:32:24 +00:00
Chris Lattner
bd6be6f52d add vsel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27153 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 22:38:43 +00:00
Chris Lattner
6d92caddc4 Codegen vector predicate compares. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27151 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 10:06:40 +00:00
Evan Cheng
5b6a01b59c Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27149 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 09:52:32 +00:00
Chris Lattner
b8a45c2798 Add all of the altivec comparison instructions. Add patterns for the 
non-predicate altivec compare intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27143 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 04:57:17 +00:00
Chris Lattner
5d72907e00 Add and 8/16-bit adds, add all integer subtracts, add saturating subtract 
intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27142 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 02:39:02 +00:00
Chris Lattner
e7d959c069 implement the vsldoi intrinsic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27139 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 00:41:48 +00:00
Chris Lattner
af9136bc0c fix the pattern for vandc, it's NOT vnand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27136 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 23:10:40 +00:00
Chris Lattner
6509ae859a add patterns for VANDC/VNOR, implementing 
CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27135 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 23:05:29 +00:00
Chris Lattner
2430a5f0c7 Add some logical operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27127 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 22:16:05 +00:00
Chris Lattner
984f38bf4f implement a bunch of intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27118 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 08:01:02 +00:00
Chris Lattner
b22a04d881 Move all Altivec stuff out into a new PPCInstrAltivec.td file. 
Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27117 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 07:51:43 +00:00
Chris Lattner
8d052bc711 Add some basic patterns for other datatypes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27116 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 07:39:07 +00:00
Chris Lattner
150ffa7842 add all supported formats to the vector register file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27115 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 07:36:56 +00:00
Chris Lattner
5a2025465b Add support for __builtin_altivec_vnmsubfp /vmaddfp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27112 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 07:05:55 +00:00
Chris Lattner
420736dc85 #include Intrinsics.h into all dag isels 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 06:47:10 +00:00
Chris Lattner
9c61dcf1aa Codegen things like: 
<int -1, int -1, int -1, int -1>
and
 <int 65537, int 65537, int 65537, int 65537>

Using things like:
  vspltisb v0, -1
and:
  vspltish v0, 1

instead of using constant pool loads.

This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27106 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 06:12:06 +00:00
Jim Laskey
47622e3721 Add dwarf register numbering to register data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 21:15:58 +00:00
Chris Lattner
057f09bc0b add another note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27077 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 20:04:27 +00:00
Chris Lattner
8edd11f33d Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ?? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27069 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 18:24:43 +00:00
Chris Lattner
54e869e18c Like the comment says, prefer to use the implicit add done by [r+r] addressing 
modes than emitting an explicit add and using a base of r0.  This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27068 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 17:58:06 +00:00
Chris Lattner
7fbcef7102 Disable the i32->float G5 optimization. It is unsafe, as documented in the 
comment.

This fixes 177.mesa, and McCat/09-vor with the td scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27060 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 07:53:47 +00:00
Chris Lattner
64b3a08bc6 add support for using vxor to build zero vectors. This implements 
Regression/CodeGen/PowerPC/vec_zero.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27059 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 07:48:08 +00:00
Chris Lattner
9d5da1d96c Gabor points out that we can't spell. :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 07:12:19 +00:00
Chris Lattner
716aefcd91 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27000 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 21:28:44 +00:00
Chris Lattner
dc6af72781 Add PPC vector bit-convert support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26995 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 19:54:27 +00:00
Jim Laskey
f1d78e8335 Add support to locate local variables in frames (early version.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26994 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 18:12:57 +00:00
Jim Laskey
99db0442f0 Change interface to DwarfWriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26991 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 18:09:44 +00:00
Chris Lattner
bc641b9d8b Eliminate IntrinsicLowering from TargetMachine. 
Make the CBE and V9 backends create their own, since they're the only ones that use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26974 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 05:43:16 +00:00
Chris Lattner
9d86a9dff2 This has been implemented. Tweak it into another note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26944 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 05:33:23 +00:00
Chris Lattner
ecfe55e65b When possible, custom lower 32-bit SINT_TO_FP to this: 
_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 05:30:33 +00:00
Chris Lattner
e5ba580ab0 Add support for "ri" addressing modes where the immediate is a 14-bit field 
which is shifted left two bits before use.  Instructions like STD use this
addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26942 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 05:26:03 +00:00
Chris Lattner
eb8b09f69f Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 01:44:36 +00:00
Chris Lattner
9b3bd467d0 These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 20:51:05 +00:00
Chris Lattner
f3ce43210a Don't emit pseudo instructions! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26926 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 20:19:37 +00:00
Nate Begeman
c0a8b6df2a Update readme 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26924 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 18:58:20 +00:00
Chris Lattner
13feb58aa1 Print absolute memory references like this: 
lwz r2, 8(0)
instead of this:
       lwz r2, 8(r0)

This fixes the llc/llc-beta failures on PPC last night.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26922 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 17:21:13 +00:00
Chris Lattner
8151914321 With Evan's latest tblgen patch, this code is obsolete, thanks Evan! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26917 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 06:37:40 +00:00
Chris Lattner
8593f9891d When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26913 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:51:38 +00:00
Chris Lattner
ef040dd4a3 minor note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26912 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:47:09 +00:00
Chris Lattner
d97964457e Handle constant addresses more efficiently, folding the low bits into the 
disp field of the load/store if possible.  This compiles
CodeGen/PowerPC/load-constant-addr.ll to:

_test:
        lis r2, 2838
        lfs f1, 26848(r2)
        blr

instead of:

_test:
        lis r2, 2838
        ori r2, r2, 26848
        lfs f1, 0(r2)
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26908 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 22:38:22 +00:00
Chris Lattner
23baa1b310 remove dead variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26907 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 22:37:23 +00:00
Chris Lattner
bd83afd3cd Fix a couple of bugs in permute/splat generate, thanks to Nate for actually 
figuring these out! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26904 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 18:26:51 +00:00
Chris Lattner
e376e00247 reenable this hack, the tblgen version isn't quite ready 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26902 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 17:54:43 +00:00
Chris Lattner
32f57d9e26 Fix the pattern for VADDUWM, add i32 splat 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26901 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 17:51:58 +00:00
Evan Cheng
e63d746ef6 Use tblgen'd VECTOR_SHUFFLE selection code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 08:14:16 +00:00
Chris Lattner
dd4d2d0e40 Add support for generating vspltw, instead of a vperm instruction with a 
constant pool load.  This generates significantly nicer code for splats.

When tblgen gets bugfixed, we can remove the custom selection code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26898 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:51:10 +00:00
Chris Lattner
88a99ef7cc Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26897 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:37:44 +00:00
Chris Lattner
ef819f8fbb fix duplicate definition errors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26896 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:33:01 +00:00
Chris Lattner
3c0f9cc90c Check in some intermediate code that adds a skeleton for matching vsplt* 
instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26894 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:15:45 +00:00
Chris Lattner
08e25de4d3 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26889 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 05:05:55 +00:00
Chris Lattner
556aae0df0 add vsplat instructions, fix sched description for vperm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26888 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 04:47:33 +00:00
Chris Lattner
f1d0b2beda Custom lower arbitrary VECTOR_SHUFFLE's to VPERM. 
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26887 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:53:53 +00:00
Chris Lattner
2bc6dc27e9 Claim to have v16i8 for perm masks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26886 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:53:02 +00:00
Chris Lattner
abdff1ee6d add the vperm instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26883 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:00:56 +00:00
Chris Lattner
28097d086f Add a note about the MUL -> FMADD vector bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26874 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 22:08:08 +00:00
Chris Lattner
b2177b9405 Custom lower SCALAR_TO_VECTOR into lve*x. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26868 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:55:52 +00:00
Chris Lattner
ab515b09bf PPC doesn't have SCALAR_TO_VECTOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26865 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:17:19 +00:00
Chris Lattner
528180ed7b add support for vector undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26863 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:10:09 +00:00
Chris Lattner
a17409dfd6 minor fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26857 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 05:43:01 +00:00
Chris Lattner
28b1a0b532 notes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26856 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 05:33:30 +00:00
Chris Lattner
0a7bff01d0 we don't use lmw/stmw. When we want them they are easy enough to add 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26853 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 04:33:37 +00:00
Chris Lattner
a064d28843 rename these nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26848 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 01:13:28 +00:00
Nate Begeman
79691bc1f3 Fix subfic to match subc by default instead of sub so that it is correctly 
cost-modeled as producing a flag.  This fixes the test I just added for neg


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26835 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 22:41:37 +00:00
Nate Begeman
81e8097377 Remove BRTWOWAY* 
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 01:40:33 +00:00
Chris Lattner
e261c474ca remove dead variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26813 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 23:52:08 +00:00
Nate Begeman
1ad9b3a3cc Notes on how to kill the eeevil brtwoway, and make ppc branch selector 
more target independant, generate better code, and be less conservative.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26809 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:37:48 +00:00
Chris Lattner
be80fc8d09 Strangely, calls clobber call-clobbered vector regs. Whodathoughtit? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26808 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:35:59 +00:00
Chris Lattner
ed51169cd8 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26807 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:25:55 +00:00
Chris Lattner
9c09c9ec9d teach the ppc backend how to spill/reload vector regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:24:02 +00:00
Chris Lattner
419ed53006 add callee saved vector regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26805 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:07:06 +00:00
Evan Cheng
714554d707 Added a way for TargetLowering to specify what values can be used as the 
scale component of the target addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 21:47:42 +00:00
Chris Lattner
8aa777d5ea in functions that use a lot of callee saved regs, this can be more than 
5 instructions away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26801 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 21:31:45 +00:00
Chris Lattner
335fd3c7c2 Add support for copying registers. still needed: spilling and reloading them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 20:03:58 +00:00
Nate Begeman
2df992883b Another case we could do better on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26795 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 18:50:44 +00:00
Chris Lattner
4bb1895072 Save/restore VRSAVE once per function, not once per block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26793 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 18:25:23 +00:00
Nate Begeman
133decdceb Update scheduling info for vrsave instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26776 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-15 05:25:05 +00:00
Chris Lattner
a08610c8a5 Fix an off by one error that caused PPC LLC failures last night. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26758 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-14 17:56:49 +00:00
Evan Cheng
9c543b2299 PPC LSR pass should use target lowering hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26743 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:56:51 +00:00
Evan Cheng
c4c6257c1a Added getTargetLowering() to TargetMachine. Refactored targets to support this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:20:37 +00:00
Chris Lattner
1877ec9b02 For functions that use vector registers, save VRSAVE, mark used 
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 21:52:10 +00:00
Chris Lattner
64ce964673 Fix a couple of bugs that broke the alpha tester build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26722 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 05:23:59 +00:00
Chris Lattner
3faad495bc Handle cracked instructions in dispatch group formation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26721 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 05:20:04 +00:00
Chris Lattner
fd97734f36 Mark instructions that are cracked by the PPC970 decoder as such. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 05:15:10 +00:00