Evan Cheng
e3de85b447
Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
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flag so it can be flagged to a FST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25953 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-04 02:20:30 +00:00
Evan Cheng
78376d59ab
Rearrange code to my liking. :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25887 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 23:01:57 +00:00
Evan Cheng
3c55c54a87
- Use xor to clear integer registers (set R, 0).
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- Added a new format for instructions where the source register is implied
and it is same as the destination register. Used for pseudo instructions
that clear the destination register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25872 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 06:13:50 +00:00
Evan Cheng
223547ab31
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
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- Use XORP* to implement fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25857 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 22:28:30 +00:00
Chris Lattner
259e97cc72
* Fix 80-column violations
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* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25854 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 19:43:35 +00:00
Evan Cheng
ef6ffb17c7
Added custom lowering of fabs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25831 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 03:14:29 +00:00
Evan Cheng
6dab05363f
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
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conversions. SSE does not have instructions to handle these tasks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25817 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 08:02:57 +00:00
Chris Lattner
44d9b9bb86
The FP stack doesn't support UNDEF, ask the legalizer to legalize it
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instead of lying and saying we have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25775 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 06:44:22 +00:00
Evan Cheng
85214ba3cc
AT&T assembly convention: registers are in lower case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25714 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 22:53:29 +00:00
Evan Cheng
559806f575
x86 CPU detection and proper subtarget support
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 08:10:46 +00:00
Chris Lattner
cedc6f4b30
PHI and INLINEASM are now built-in instructions provided by Target.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 01:46:15 +00:00
Evan Cheng
71fb9ad5d9
Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
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SDNPOutFlag, and SDNPOptInFlag instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25629 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-26 00:29:36 +00:00
Chris Lattner
af63bb03c5
Emit the copies out of call return registers *after* the ISD::CALLSEQ_END
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node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25580 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-24 05:17:12 +00:00
Evan Cheng
86556a5f42
Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual).
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Some assemblers can't recognize the aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25494 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-21 02:55:41 +00:00
Evan Cheng
21d5443934
A few more SH{L|R}D peepholes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25473 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-20 01:13:30 +00:00
Evan Cheng
956044cf03
Added i16 SH{L|R}D patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25468 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-19 23:26:24 +00:00
Evan Cheng
41b6dc8dbe
adc and sbb need an incoming flag to ensure it reads the carry flag
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from add / sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25444 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-19 06:53:20 +00:00
Evan Cheng
68b951a5e5
Two peepholes:
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(or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
(or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25438 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-19 01:56:29 +00:00
Evan Cheng
e5d9343377
Zero extending load from i1 to i8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25391 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-17 07:02:46 +00:00
Evan Cheng
42ef0bc6fb
Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should
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read a flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25378 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-17 00:19:47 +00:00
Evan Cheng
b5d0b0bae5
More typo's
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25375 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-16 23:26:53 +00:00
Evan Cheng
8a3f4c75fa
Some typo's
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25374 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-16 22:48:46 +00:00
Evan Cheng
0cc3945efe
Fix FP_TO_INT**_IN_MEM lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25368 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-16 21:21:29 +00:00
Evan Cheng
cf74a7c762
Added patterns for 8-bit multiply
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25338 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-15 10:05:20 +00:00
Nate Begeman
d88fc03602
bswap implementation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25312 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-14 03:14:10 +00:00
Evan Cheng
e3703d44e9
A typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25307 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-14 01:18:49 +00:00
Evan Cheng
b8414333ac
Add truncstore i1 patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25296 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-13 21:45:19 +00:00
Evan Cheng
a3195e8643
Fix sint_to_fp (fild*) support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25257 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-12 22:54:21 +00:00
Evan Cheng
77e9043b84
Specify transformation from GlobalAddress to TargetGlobalAddress and
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ExternalSymbol to TargetExternalSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25253 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-12 19:36:31 +00:00
Evan Cheng
5ee4ccce5b
X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
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linked together).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-12 08:27:59 +00:00
Evan Cheng
002fe9baf2
* Materialize GlobalAddress and ExternalSym with MOV32ri rather than
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LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25246 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-12 07:56:47 +00:00
Evan Cheng
eb422a7234
Added ROTL and ROTR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25232 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-11 23:20:05 +00:00
Evan Cheng
67f92a7649
Support for MEMCPY and MEMSET.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25226 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-11 22:15:48 +00:00
Evan Cheng
8700e14ba1
* Add special entry code main() (to set x87 to 64-bit precision).
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* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25207 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-11 06:09:51 +00:00
Evan Cheng
4a46080fe0
SSE cmov support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25190 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-11 00:33:36 +00:00
Evan Cheng
f710062bfb
* fp to sint patterns.
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* fiadd, fisub, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25189 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-10 22:22:02 +00:00
Evan Cheng
aaca22ca91
FP_TO_INT*_IN_MEM and x87 FP Select support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25188 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-10 20:26:56 +00:00
Evan Cheng
510e478098
* Added undef patterns.
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* Some reorg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25163 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-09 23:10:28 +00:00
Evan Cheng
e3413160ca
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25158 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-09 18:33:28 +00:00
Evan Cheng
cfa260b2ab
Addd (shl x, 1) ==> (shl x, x) peepholes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25123 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-06 02:31:59 +00:00
Evan Cheng
d9558e0ba6
* Fast call support.
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* FP cmp, setcc, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25117 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-06 00:43:03 +00:00
Evan Cheng
650d688db6
Added ConstantFP patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25108 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-05 02:08:37 +00:00
Evan Cheng
d90eb7fb24
DAG based isel call support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25103 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-05 00:27:02 +00:00
Evan Cheng
2b4ea795a2
Added field noResults to Instruction.
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Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-26 09:11:45 +00:00
Evan Cheng
171049d10f
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
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* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24997 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 22:14:32 +00:00
Evan Cheng
38bcbaf23e
More X86 floating point patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24990 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 07:31:11 +00:00
Evan Cheng
5bc4da4893
Bye bye HACKTROCITY.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24935 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-22 02:26:21 +00:00
Evan Cheng
3a03ebb377
* Fix a GlobalAddress lowering bug.
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* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24921 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 23:05:39 +00:00
Evan Cheng
793ca4caa4
Oops. Accidentally deleted RET pattern. It's still needed for return void;
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24920 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 22:22:16 +00:00
Evan Cheng
d5781fca4f
* Added support for X86 RET with an additional operand to specify number of
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bytes to pop off stack.
* Added support for X86 SETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24917 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 20:21:51 +00:00
Chris Lattner
c515ad18f8
This was meant to go in
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24900 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 07:50:26 +00:00
Chris Lattner
58fe459e36
Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
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that were overloaded to work before and after the stackifier runs. With the
new clean world, it is possible to write patterns for these instructions: woo!
This also adds a few simple patterns here and there, though there are a lot
still missing. These should be easy to add though. :)
See the comments under "Floating Point Stack Support" for more details on
the new world order.
This patch as absolutely no effect on the generated code, woo!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24899 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 07:47:04 +00:00
Chris Lattner
9fb2422c49
Wrap some long lines: no functionality change
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24898 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 05:34:58 +00:00
Evan Cheng
b077b842b6
* Added lowering hook for external weak global address. It inserts a load
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for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24888 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-21 02:39:21 +00:00
Evan Cheng
bbc8ddbea3
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24886 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 22:59:51 +00:00
Evan Cheng
a5386b0823
Added X86 readport patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24879 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 07:38:38 +00:00
Evan Cheng
898101c15f
X86 conditional branch support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24870 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-19 23:12:38 +00:00
Chris Lattner
4543251834
eliminate some redundancy
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24781 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 19:47:05 +00:00
Evan Cheng
1aabc4ea15
Added anyext, modelled as zext on X86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24759 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 01:47:57 +00:00
Evan Cheng
aed7c721df
Added support for cmp, test, and conditional move instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24756 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 01:24:02 +00:00
Evan Cheng
cb17bac3a3
* Promote all 1 bit entities to 8 bit.
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* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24726 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-15 19:49:23 +00:00
Evan Cheng
502c5bb428
Added frameindex, constpool, globaladdr, and externalsym as root nodes of
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leaaddr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24724 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-15 08:31:04 +00:00
Evan Cheng
f6036a3f1b
Use MOV8rm to load 1 bit value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24721 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-15 00:59:17 +00:00
Evan Cheng
7a7e8375a9
Added sext and zext patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24705 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-14 02:22:27 +00:00
Evan Cheng
85dd889ed6
Add load + store folding srl and sra patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24696 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 07:24:22 +00:00
Evan Cheng
c937ffafba
Beautify a few patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24690 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 02:40:18 +00:00
Evan Cheng
763b029b28
Some shl patterns which do load + store folding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24689 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 02:34:51 +00:00
Evan Cheng
605c415046
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24688 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 01:57:51 +00:00
Evan Cheng
0ef3a77bdf
Add and, or, and xor patterns which fold load + stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24687 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 01:41:36 +00:00
Evan Cheng
6cad276c90
Add inc + dec patterns which fold load + stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24686 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 01:02:47 +00:00
Evan Cheng
5ce4edb967
Add neg and not patterns which fold load + stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24685 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 00:54:44 +00:00
Evan Cheng
5a38e0210d
Missed a couple redundant explicit type casts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24684 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 00:25:07 +00:00
Evan Cheng
9b6b642647
Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24683 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 00:14:11 +00:00
Evan Cheng
b3558540b6
* Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands.
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This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24682 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-13 00:01:09 +00:00
Evan Cheng
f281e02cbd
Add some integer mul patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24681 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-12 23:47:46 +00:00
Evan Cheng
d160d48a2b
Add some sub patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24675 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-12 21:54:05 +00:00
Evan Cheng
ee93f9db87
Add a few more add / store patterns. e.g. ADD32mi8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24670 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-12 19:45:23 +00:00
Evan Cheng
b51a059b2c
* Added X86 store patterns.
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* Added X86 dec patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24654 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-10 00:48:20 +00:00
Evan Cheng
ab24ed2a32
Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24648 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-09 22:48:48 +00:00
Evan Cheng
670fd8f8dd
Added explicit type field to ComplexPattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24637 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-08 02:15:07 +00:00
Evan Cheng
ec693f77c0
* Added intelligence to X86 LEA addressing mode matching routine so it returns
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false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24635 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-08 02:01:35 +00:00
Evan Cheng
8d202230b4
Remove unnecessary let hasCtrlDep=1 now it can be inferred.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24611 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 23:09:43 +00:00
Chris Lattner
3d36a9f6f4
Several things:
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1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly. The port number really
*is* a 16-bit value, but the patterns should only match if the number
is 0-255. Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
i8, not an i16 as they were believed to be before. This previous fib
stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24599 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 02:40:25 +00:00
Evan Cheng
d35b8c1adb
Added isel patterns for RET, JMP, and WRITEPORT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24588 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-04 08:19:43 +00:00
Evan Cheng
640f299b44
Proper support for shifts with register shift value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24559 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 00:43:55 +00:00
Nate Begeman
391c5d231a
No longer track value types for asm printer operands, and remove them as
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an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24541 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 18:54:35 +00:00
Chris Lattner
5b9bbc8792
Fix a bug in a recent patch that broke shifts
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24526 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-30 05:11:18 +00:00
Evan Cheng
f0701842f7
Add more X86 ISel patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24520 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29 19:38:52 +00:00
Chris Lattner
441b223c9b
encode rdtsc correctly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24435 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-20 22:13:18 +00:00
Andrew Lenharth
b873ff322c
The second patch of X86 support for read cycle counter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24430 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-20 21:41:10 +00:00
Chris Lattner
6adaf79ad7
Teach the x86 backend about the register constraints of its addressing mode.
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Patch by Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24423 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-19 07:01:30 +00:00
Chris Lattner
f124d5e500
add more patterns, patch by Evan Cheng.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24406 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-18 01:04:42 +00:00
Chris Lattner
78432feff8
Add patterns for some 16-bit immediate instructions, patch contributed by
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Evan Cheng.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24384 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-17 02:01:55 +00:00
Chris Lattner
7a12537843
Add patterns for several simple instructions that take i32 immediates.
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Patch contributed by Evan Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24382 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-16 22:59:19 +00:00
Nate Begeman
14e2cf62f4
Properly split f32 and f64 into separate register classes for scalar sse fp
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fixing a bunch of nasty hackery
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23735 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14 22:06:00 +00:00
Chris Lattner
43ef1318c6
give all operands names
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23356 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-14 21:10:24 +00:00
Chris Lattner
9d9dc816d0
add a few missing cases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22891 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 00:41:29 +00:00
Chris Lattner
b822abade7
Give ADJCALLSTACKDOWN/UP the correct operands.
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Give a whole bunch of other stuff variable operands, particularly FP. The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable. This will have to be fixed before we can dag->dag
the X86 backend. The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22890 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 00:38:22 +00:00
Nate Begeman
1c73c7be9d
Scalar SSE: load +0.0 -> xorps/xorpd
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Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22637 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-03 23:26:28 +00:00
Nate Begeman
16b04f3d5e
Get closer to fully working scalar FP in SSE regs. This gets singlesource
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working, and Olden/power.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22441 91177308-0d34-0410-b5e6-96231b3b80d8
2005-07-15 00:38:55 +00:00