2009-10-19 20:20:46 +00:00
|
|
|
//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
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//
|
2006-05-14 22:18:28 +00:00
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// The LLVM Compiler Infrastructure
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//
|
2007-12-29 20:36:04 +00:00
|
|
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// This file is distributed under the University of Illinois Open Source
|
2006-05-14 22:18:28 +00:00
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format ARM assembly language.
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//
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//===----------------------------------------------------------------------===//
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2011-01-11 21:46:47 +00:00
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#include "ARMAsmPrinter.h"
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2012-03-17 07:33:42 +00:00
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#include "ARM.h"
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2007-01-19 07:51:42 +00:00
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#include "ARMConstantPoolValue.h"
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[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
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#include "ARMFPUName.h"
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2009-10-19 20:20:46 +00:00
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#include "ARMMachineFunctionInfo.h"
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#include "ARMTargetMachine.h"
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2010-10-11 23:01:44 +00:00
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#include "ARMTargetObjectFile.h"
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2011-01-11 21:46:47 +00:00
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#include "InstPrinter/ARMInstPrinter.h"
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2011-07-20 23:34:39 +00:00
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "MCTargetDesc/ARMMCExpr.h"
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2012-10-04 21:33:24 +00:00
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/SmallString.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2007-01-19 07:51:42 +00:00
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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2013-01-02 11:36:10 +00:00
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DataLayout.h"
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2014-03-06 00:46:21 +00:00
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#include "llvm/IR/DebugInfo.h"
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2014-01-07 21:19:40 +00:00
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#include "llvm/IR/Mangler.h"
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2013-01-02 11:36:10 +00:00
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#include "llvm/IR/Module.h"
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#include "llvm/IR/Type.h"
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2009-10-19 18:38:33 +00:00
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#include "llvm/MC/MCAsmInfo.h"
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2010-10-25 17:50:35 +00:00
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#include "llvm/MC/MCAssembler.h"
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2009-10-19 18:38:33 +00:00
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#include "llvm/MC/MCContext.h"
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2013-01-30 02:24:33 +00:00
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#include "llvm/MC/MCELFStreamer.h"
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2009-10-19 20:20:46 +00:00
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#include "llvm/MC/MCInst.h"
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2012-11-26 13:34:22 +00:00
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#include "llvm/MC/MCInstBuilder.h"
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2010-10-25 17:50:35 +00:00
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#include "llvm/MC/MCObjectStreamer.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/MC/MCSectionMachO.h"
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2009-08-19 05:49:37 +00:00
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#include "llvm/MC/MCStreamer.h"
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2009-09-13 17:14:04 +00:00
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#include "llvm/MC/MCSymbol.h"
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2014-01-19 08:25:27 +00:00
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#include "llvm/Support/ARMBuildAttributes.h"
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2014-04-30 06:14:25 +00:00
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#include "llvm/Support/COFF.h"
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2009-10-19 20:20:46 +00:00
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#include "llvm/Support/CommandLine.h"
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2010-08-04 22:39:39 +00:00
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#include "llvm/Support/Debug.h"
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2013-01-30 02:24:33 +00:00
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#include "llvm/Support/ELF.h"
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2009-07-08 20:55:50 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2011-08-24 18:08:43 +00:00
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#include "llvm/Support/TargetRegistry.h"
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2010-04-04 08:18:47 +00:00
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#include "llvm/Support/raw_ostream.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/Target/TargetMachine.h"
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2006-05-14 22:18:28 +00:00
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#include <cctype>
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using namespace llvm;
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2014-04-22 02:41:26 +00:00
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#define DEBUG_TYPE "asm-printer"
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2012-05-18 19:12:01 +00:00
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void ARMAsmPrinter::EmitFunctionBodyEnd() {
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// Make sure to terminate any constant pools that were at the end
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// of the function.
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if (!InConstantPool)
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return;
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InConstantPool = false;
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OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
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}
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2011-10-04 23:26:17 +00:00
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2012-05-18 19:12:01 +00:00
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void ARMAsmPrinter::EmitFunctionEntryLabel() {
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2010-01-27 23:58:11 +00:00
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if (AFI->isThumbFunction()) {
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2010-11-05 22:08:08 +00:00
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OutStreamer.EmitAssemblerFlag(MCAF_Code16);
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2011-05-16 16:17:21 +00:00
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OutStreamer.EmitThumbFunc(CurrentFnSym);
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2010-01-27 23:58:11 +00:00
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|
}
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2010-09-02 01:02:06 +00:00
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2010-01-27 23:58:11 +00:00
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OutStreamer.EmitLabel(CurrentFnSym);
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}
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2012-01-26 09:25:43 +00:00
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void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
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2014-08-04 21:25:23 +00:00
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uint64_t Size =
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TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(CV->getType());
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2012-01-26 09:25:43 +00:00
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assert(Size && "C++ constructor pointer had zero size!");
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|
2012-02-15 09:14:08 +00:00
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const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
|
2012-01-26 09:25:43 +00:00
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assert(GV && "C++ constructor pointer was not a GlobalValue!");
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|
2014-07-07 05:18:22 +00:00
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const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
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ARMII::MO_NO_FLAG),
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2014-01-06 14:28:05 +00:00
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|
(Subtarget->isTargetELF()
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|
|
|
? MCSymbolRefExpr::VK_ARM_TARGET1
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|
|
|
: MCSymbolRefExpr::VK_None),
|
2012-01-26 09:25:43 +00:00
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|
OutContext);
|
2014-04-03 23:43:18 +00:00
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|
2012-01-26 09:25:43 +00:00
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|
OutStreamer.EmitValue(E, Size);
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|
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|
}
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|
|
2010-09-30 01:57:53 +00:00
|
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|
/// runOnMachineFunction - This uses the EmitInstruction()
|
2006-05-14 22:18:28 +00:00
|
|
|
/// method to print assembly for each instruction.
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|
|
|
///
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|
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|
bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
|
2007-01-19 07:51:42 +00:00
|
|
|
AFI = MF.getInfo<ARMFunctionInfo>();
|
2008-09-18 07:27:23 +00:00
|
|
|
MCP = MF.getConstantPool();
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2014-04-30 06:14:25 +00:00
|
|
|
SetupMachineFunction(MF);
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|
|
|
|
if (Subtarget->isTargetCOFF()) {
|
|
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|
bool Internal = MF.getFunction()->hasInternalLinkage();
|
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|
|
COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
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|
|
|
: COFF::IMAGE_SYM_CLASS_EXTERNAL;
|
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|
int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
|
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|
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|
OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
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|
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|
OutStreamer.EmitCOFFSymbolStorageClass(Scl);
|
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|
OutStreamer.EmitCOFFSymbolType(Type);
|
|
|
|
OutStreamer.EndCOFFSymbolDef();
|
|
|
|
}
|
|
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|
|
|
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|
// Have common code print out the function header with linkage info etc.
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|
EmitFunctionHeader();
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// Emit the rest of the function body.
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|
EmitFunctionBody();
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|
// We didn't modify anything.
|
|
|
|
return false;
|
2006-10-17 18:04:53 +00:00
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
|
2010-04-04 04:47:45 +00:00
|
|
|
raw_ostream &O, const char *Modifier) {
|
2009-06-29 07:51:04 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
2009-11-24 00:44:37 +00:00
|
|
|
unsigned TF = MO.getTargetFlags();
|
|
|
|
|
2006-05-25 12:57:06 +00:00
|
|
|
switch (MO.getType()) {
|
2012-02-07 02:50:20 +00:00
|
|
|
default: llvm_unreachable("<unknown operand type>");
|
2009-06-22 23:27:02 +00:00
|
|
|
case MachineOperand::MO_Register: {
|
|
|
|
unsigned Reg = MO.getReg();
|
2009-10-19 20:59:55 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
|
2010-10-06 21:22:32 +00:00
|
|
|
assert(!MO.getSubReg() && "Subregs should be eliminated!");
|
2013-02-14 18:10:21 +00:00
|
|
|
if(ARM::GPRPairRegClass.contains(Reg)) {
|
|
|
|
const MachineFunction &MF = *MI->getParent()->getParent();
|
2014-08-05 02:39:49 +00:00
|
|
|
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
2013-02-14 18:10:21 +00:00
|
|
|
Reg = TRI->getSubReg(Reg, ARM::gsub_0);
|
|
|
|
}
|
2010-10-06 21:22:32 +00:00
|
|
|
O << ARMInstPrinter::getRegisterName(Reg);
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2009-06-22 23:27:02 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
case MachineOperand::MO_Immediate: {
|
2009-09-28 09:14:39 +00:00
|
|
|
int64_t Imm = MO.getImm();
|
2009-10-08 20:43:22 +00:00
|
|
|
O << '#';
|
2009-11-24 00:44:37 +00:00
|
|
|
if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
|
2011-01-12 23:21:49 +00:00
|
|
|
(TF == ARMII::MO_LO16))
|
2009-11-24 00:44:37 +00:00
|
|
|
O << ":lower16:";
|
|
|
|
else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
|
2011-01-12 23:21:49 +00:00
|
|
|
(TF == ARMII::MO_HI16))
|
2009-11-24 00:44:37 +00:00
|
|
|
O << ":upper16:";
|
2009-10-08 20:43:22 +00:00
|
|
|
O << Imm;
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2006-05-25 12:57:06 +00:00
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
2010-03-13 21:04:28 +00:00
|
|
|
O << *MO.getMBB()->getSymbol();
|
2006-05-25 12:57:06 +00:00
|
|
|
return;
|
2006-07-16 01:02:57 +00:00
|
|
|
case MachineOperand::MO_GlobalAddress: {
|
2010-04-15 01:51:59 +00:00
|
|
|
const GlobalValue *GV = MO.getGlobal();
|
2009-11-24 00:44:37 +00:00
|
|
|
if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
|
|
|
|
(TF & ARMII::MO_LO16))
|
|
|
|
O << ":lower16:";
|
|
|
|
else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
|
|
|
|
(TF & ARMII::MO_HI16))
|
|
|
|
O << ":upper16:";
|
2014-07-07 05:18:22 +00:00
|
|
|
O << *GetARMGVSymbol(GV, TF);
|
2008-11-22 16:15:34 +00:00
|
|
|
|
2010-04-03 22:28:33 +00:00
|
|
|
printOffset(MO.getOffset(), O);
|
2010-10-06 21:36:43 +00:00
|
|
|
if (TF == ARMII::MO_PLT)
|
2007-04-22 00:04:12 +00:00
|
|
|
O << "(PLT)";
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2006-05-25 12:57:06 +00:00
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
2010-01-23 07:00:21 +00:00
|
|
|
O << *GetCPISymbol(MO.getIndex());
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
|
|
|
}
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
2010-01-25 19:51:38 +00:00
|
|
|
MCSymbol *ARMAsmPrinter::
|
|
|
|
GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
|
2014-08-04 21:25:23 +00:00
|
|
|
const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
|
2010-01-25 19:51:38 +00:00
|
|
|
SmallString<60> Name;
|
2014-01-03 19:21:54 +00:00
|
|
|
raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
|
2010-01-25 23:28:03 +00:00
|
|
|
<< getFunctionNumber() << '_' << uid << '_' << uid2;
|
2010-03-30 18:10:53 +00:00
|
|
|
return OutContext.GetOrCreateSymbol(Name.str());
|
2010-01-25 19:39:52 +00:00
|
|
|
}
|
|
|
|
|
2010-09-24 20:47:58 +00:00
|
|
|
|
2012-11-15 16:51:49 +00:00
|
|
|
MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
|
2014-08-04 21:25:23 +00:00
|
|
|
const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
|
2010-09-24 20:47:58 +00:00
|
|
|
SmallString<60> Name;
|
2014-01-03 19:21:54 +00:00
|
|
|
raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
|
2010-09-24 20:47:58 +00:00
|
|
|
<< getFunctionNumber();
|
|
|
|
return OutContext.GetOrCreateSymbol(Name.str());
|
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
|
2010-04-04 05:29:35 +00:00
|
|
|
unsigned AsmVariant, const char *ExtraCode,
|
|
|
|
raw_ostream &O) {
|
2007-01-19 07:51:42 +00:00
|
|
|
// Does this asm operand have a single letter operand modifier?
|
|
|
|
if (ExtraCode && ExtraCode[0]) {
|
|
|
|
if (ExtraCode[1] != 0) return true; // Unknown modifier.
|
2009-08-08 23:10:41 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
switch (ExtraCode[0]) {
|
2012-06-26 13:49:27 +00:00
|
|
|
default:
|
|
|
|
// See if this is a generic print operand
|
|
|
|
return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
|
2009-07-09 23:54:51 +00:00
|
|
|
case 'a': // Print as a memory address.
|
|
|
|
if (MI->getOperand(OpNum).isReg()) {
|
2010-09-30 15:25:22 +00:00
|
|
|
O << "["
|
|
|
|
<< ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
|
|
|
|
<< "]";
|
2009-07-09 23:54:51 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
// Fallthrough
|
|
|
|
case 'c': // Don't print "#" before an immediate operand.
|
2009-08-21 21:58:55 +00:00
|
|
|
if (!MI->getOperand(OpNum).isImm())
|
|
|
|
return true;
|
2010-09-30 01:57:53 +00:00
|
|
|
O << MI->getOperand(OpNum).getImm();
|
2009-04-06 21:46:51 +00:00
|
|
|
return false;
|
2007-04-04 00:13:29 +00:00
|
|
|
case 'P': // Print a VFP double precision register.
|
2009-12-08 23:06:22 +00:00
|
|
|
case 'q': // Print a NEON quad precision register.
|
2010-04-04 04:47:45 +00:00
|
|
|
printOperand(MI, OpNum, O);
|
2007-03-08 22:42:46 +00:00
|
|
|
return false;
|
2011-05-24 22:10:34 +00:00
|
|
|
case 'y': // Print a VFP single precision register as indexed double.
|
|
|
|
if (MI->getOperand(OpNum).isReg()) {
|
|
|
|
unsigned Reg = MI->getOperand(OpNum).getReg();
|
2014-08-05 02:39:49 +00:00
|
|
|
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
|
2012-05-30 23:00:43 +00:00
|
|
|
// Find the 'd' register that has this 's' register as a sub-register,
|
|
|
|
// and determine the lane number.
|
|
|
|
for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
|
|
|
|
if (!ARM::DPRRegClass.contains(*SR))
|
|
|
|
continue;
|
|
|
|
bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
|
|
|
|
O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
|
|
|
|
return false;
|
|
|
|
}
|
2011-05-24 22:10:34 +00:00
|
|
|
}
|
2011-05-24 23:27:13 +00:00
|
|
|
return true;
|
2011-05-24 22:27:43 +00:00
|
|
|
case 'B': // Bitwise inverse of integer or symbol without a preceding #.
|
2011-05-24 23:15:43 +00:00
|
|
|
if (!MI->getOperand(OpNum).isImm())
|
|
|
|
return true;
|
|
|
|
O << ~(MI->getOperand(OpNum).getImm());
|
|
|
|
return false;
|
2011-05-24 22:27:43 +00:00
|
|
|
case 'L': // The low 16 bits of an immediate constant.
|
2011-05-24 23:27:13 +00:00
|
|
|
if (!MI->getOperand(OpNum).isImm())
|
|
|
|
return true;
|
|
|
|
O << (MI->getOperand(OpNum).getImm() & 0xffff);
|
|
|
|
return false;
|
2011-05-28 01:40:44 +00:00
|
|
|
case 'M': { // A register range suitable for LDM/STM.
|
|
|
|
if (!MI->getOperand(OpNum).isReg())
|
|
|
|
return true;
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
unsigned RegBegin = MO.getReg();
|
|
|
|
// This takes advantage of the 2 operand-ness of ldm/stm and that we've
|
|
|
|
// already got the operands in registers that are operands to the
|
|
|
|
// inline asm statement.
|
2013-06-28 17:26:02 +00:00
|
|
|
O << "{";
|
|
|
|
if (ARM::GPRPairRegClass.contains(RegBegin)) {
|
2014-08-05 02:39:49 +00:00
|
|
|
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
|
2013-06-28 17:26:02 +00:00
|
|
|
unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
|
2014-04-19 23:56:35 +00:00
|
|
|
O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
|
2013-06-28 17:26:02 +00:00
|
|
|
RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
|
|
|
|
}
|
|
|
|
O << ARMInstPrinter::getRegisterName(RegBegin);
|
2011-09-02 18:46:15 +00:00
|
|
|
|
2011-05-28 01:40:44 +00:00
|
|
|
// FIXME: The register allocator not only may not have given us the
|
|
|
|
// registers in sequence, but may not be in ascending registers. This
|
|
|
|
// will require changes in the register allocator that'll need to be
|
|
|
|
// propagated down here if the operands change.
|
|
|
|
unsigned RegOps = OpNum + 1;
|
|
|
|
while (MI->getOperand(RegOps).isReg()) {
|
2011-09-02 18:46:15 +00:00
|
|
|
O << ", "
|
2011-05-28 01:40:44 +00:00
|
|
|
<< ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
|
|
|
|
RegOps++;
|
|
|
|
}
|
|
|
|
|
|
|
|
O << "}";
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
2011-08-10 16:26:42 +00:00
|
|
|
case 'R': // The most significant register of a pair.
|
|
|
|
case 'Q': { // The least significant register of a pair.
|
|
|
|
if (OpNum == 0)
|
|
|
|
return true;
|
|
|
|
const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
|
|
|
|
if (!FlagsOP.isImm())
|
|
|
|
return true;
|
|
|
|
unsigned Flags = FlagsOP.getImm();
|
2013-08-22 06:51:04 +00:00
|
|
|
|
|
|
|
// This operand may not be the one that actually provides the register. If
|
|
|
|
// it's tied to a previous one then we should refer instead to that one
|
|
|
|
// for registers and their classes.
|
|
|
|
unsigned TiedIdx;
|
|
|
|
if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
|
|
|
|
for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
|
|
|
|
unsigned OpFlags = MI->getOperand(OpNum).getImm();
|
|
|
|
OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
|
|
|
|
}
|
|
|
|
Flags = MI->getOperand(OpNum).getImm();
|
|
|
|
|
|
|
|
// Later code expects OpNum to be pointing at the register rather than
|
|
|
|
// the flags.
|
|
|
|
OpNum += 1;
|
|
|
|
}
|
|
|
|
|
2011-08-10 16:26:42 +00:00
|
|
|
unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
|
2013-06-28 17:26:02 +00:00
|
|
|
unsigned RC;
|
|
|
|
InlineAsm::hasRegClassConstraint(Flags, RC);
|
|
|
|
if (RC == ARM::GPRPairRegClassID) {
|
|
|
|
if (NumVals != 1)
|
|
|
|
return true;
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
if (!MO.isReg())
|
|
|
|
return true;
|
2014-08-05 02:39:49 +00:00
|
|
|
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
|
2013-06-28 17:26:02 +00:00
|
|
|
unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
|
|
|
|
ARM::gsub_0 : ARM::gsub_1);
|
|
|
|
O << ARMInstPrinter::getRegisterName(Reg);
|
|
|
|
return false;
|
|
|
|
}
|
2011-08-10 16:26:42 +00:00
|
|
|
if (NumVals != 2)
|
|
|
|
return true;
|
|
|
|
unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
|
|
|
|
if (RegOp >= MI->getNumOperands())
|
|
|
|
return true;
|
|
|
|
const MachineOperand &MO = MI->getOperand(RegOp);
|
|
|
|
if (!MO.isReg())
|
|
|
|
return true;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
O << ARMInstPrinter::getRegisterName(Reg);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2011-05-24 22:27:43 +00:00
|
|
|
case 'e': // The low doubleword register of a NEON quad register.
|
2011-12-12 21:45:15 +00:00
|
|
|
case 'f': { // The high doubleword register of a NEON quad register.
|
|
|
|
if (!MI->getOperand(OpNum).isReg())
|
|
|
|
return true;
|
|
|
|
unsigned Reg = MI->getOperand(OpNum).getReg();
|
|
|
|
if (!ARM::QPRRegClass.contains(Reg))
|
|
|
|
return true;
|
2014-08-05 02:39:49 +00:00
|
|
|
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
|
2011-12-12 21:45:15 +00:00
|
|
|
unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
|
|
|
|
ARM::dsub_0 : ARM::dsub_1);
|
|
|
|
O << ARMInstPrinter::getRegisterName(SubReg);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-08-13 18:18:52 +00:00
|
|
|
// This modifier is not yet supported.
|
2011-05-24 22:27:43 +00:00
|
|
|
case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
|
2010-05-27 20:23:42 +00:00
|
|
|
return true;
|
2012-08-14 23:32:15 +00:00
|
|
|
case 'H': { // The highest-numbered register of a pair.
|
2012-08-13 18:18:52 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
if (!MO.isReg())
|
|
|
|
return true;
|
|
|
|
const MachineFunction &MF = *MI->getParent()->getParent();
|
2014-08-05 02:39:49 +00:00
|
|
|
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
2013-02-14 18:10:21 +00:00
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if(!ARM::GPRPairRegClass.contains(Reg))
|
|
|
|
return false;
|
|
|
|
Reg = TRI->getSubReg(Reg, ARM::gsub_1);
|
2012-08-13 18:18:52 +00:00
|
|
|
O << ARMInstPrinter::getRegisterName(Reg);
|
|
|
|
return false;
|
2010-05-27 22:08:38 +00:00
|
|
|
}
|
2012-08-14 23:32:15 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2010-04-04 04:47:45 +00:00
|
|
|
printOperand(MI, OpNum, O);
|
2007-01-19 07:51:42 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-05-19 05:53:42 +00:00
|
|
|
bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
2009-06-29 07:51:04 +00:00
|
|
|
unsigned OpNum, unsigned AsmVariant,
|
2010-04-04 05:29:35 +00:00
|
|
|
const char *ExtraCode,
|
|
|
|
raw_ostream &O) {
|
2011-05-25 20:51:58 +00:00
|
|
|
// Does this asm operand have a single letter operand modifier?
|
|
|
|
if (ExtraCode && ExtraCode[0]) {
|
|
|
|
if (ExtraCode[1] != 0) return true; // Unknown modifier.
|
2011-09-02 18:46:15 +00:00
|
|
|
|
2011-05-25 20:51:58 +00:00
|
|
|
switch (ExtraCode[0]) {
|
2011-05-26 18:22:26 +00:00
|
|
|
case 'A': // A memory operand for a VLD1/VST1 instruction.
|
2011-05-25 20:51:58 +00:00
|
|
|
default: return true; // Unknown modifier.
|
|
|
|
case 'm': // The base register of a memory operand.
|
|
|
|
if (!MI->getOperand(OpNum).isReg())
|
|
|
|
return true;
|
|
|
|
O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2011-09-02 18:46:15 +00:00
|
|
|
|
2009-10-13 20:50:28 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
assert(MO.isReg() && "unexpected inline asm memory operand");
|
2010-09-30 01:57:53 +00:00
|
|
|
O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
|
2009-05-19 05:53:42 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-01-24 15:47:54 +00:00
|
|
|
static bool isThumb(const MCSubtargetInfo& STI) {
|
|
|
|
return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
|
2014-02-06 18:19:40 +00:00
|
|
|
const MCSubtargetInfo *EndInfo) const {
|
2014-01-24 15:47:54 +00:00
|
|
|
// If either end mode is unknown (EndInfo == NULL) or different than
|
|
|
|
// the start mode, then restore the start mode.
|
|
|
|
const bool WasThumb = isThumb(StartInfo);
|
2014-04-25 05:30:21 +00:00
|
|
|
if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
|
2014-01-24 15:47:54 +00:00
|
|
|
OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-09-30 22:06:26 +00:00
|
|
|
void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
|
2014-01-06 14:28:05 +00:00
|
|
|
if (Subtarget->isTargetMachO()) {
|
2009-09-30 00:23:42 +00:00
|
|
|
Reloc::Model RelocM = TM.getRelocationModel();
|
|
|
|
if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
|
|
|
|
// Declare all the text sections up front (before the DWARF sections
|
|
|
|
// emitted by AsmPrinter::doInitialization) so the assembler will keep
|
|
|
|
// them together at the beginning of the object file. This helps
|
|
|
|
// avoid out-of-range branches that are due a fundamental limitation of
|
|
|
|
// the way symbol offsets are encoded with the current Darwin ARM
|
|
|
|
// relocations.
|
2010-09-02 01:02:06 +00:00
|
|
|
const TargetLoweringObjectFileMachO &TLOFMacho =
|
2010-04-17 16:44:48 +00:00
|
|
|
static_cast<const TargetLoweringObjectFileMachO &>(
|
|
|
|
getObjFileLowering());
|
2012-10-04 21:33:24 +00:00
|
|
|
|
|
|
|
// Collect the set of sections our functions will go into.
|
|
|
|
SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
|
|
|
|
SmallPtrSet<const MCSection *, 8> > TextSections;
|
|
|
|
// Default text section comes first.
|
|
|
|
TextSections.insert(TLOFMacho.getTextSection());
|
|
|
|
// Now any user defined text sections from function attributes.
|
|
|
|
for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
|
|
|
|
if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
|
2014-02-08 14:53:28 +00:00
|
|
|
TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
|
2012-10-04 21:33:24 +00:00
|
|
|
// Now the coalescable sections.
|
|
|
|
TextSections.insert(TLOFMacho.getTextCoalSection());
|
|
|
|
TextSections.insert(TLOFMacho.getConstTextCoalSection());
|
|
|
|
|
|
|
|
// Emit the sections in the .s file header to fix the order.
|
|
|
|
for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
|
|
|
|
OutStreamer.SwitchSection(TextSections[i]);
|
|
|
|
|
2009-09-30 22:25:37 +00:00
|
|
|
if (RelocM == Reloc::DynamicNoPIC) {
|
|
|
|
const MCSection *sect =
|
2010-04-08 20:40:11 +00:00
|
|
|
OutContext.getMachOSection("__TEXT", "__symbol_stub4",
|
2014-03-07 07:36:05 +00:00
|
|
|
MachO::S_SYMBOL_STUBS,
|
2010-04-08 20:40:11 +00:00
|
|
|
12, SectionKind::getText());
|
2009-09-30 22:25:37 +00:00
|
|
|
OutStreamer.SwitchSection(sect);
|
|
|
|
} else {
|
|
|
|
const MCSection *sect =
|
2010-04-08 20:40:11 +00:00
|
|
|
OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
|
2014-03-07 07:36:05 +00:00
|
|
|
MachO::S_SYMBOL_STUBS,
|
2010-04-08 20:40:11 +00:00
|
|
|
16, SectionKind::getText());
|
2009-09-30 22:25:37 +00:00
|
|
|
OutStreamer.SwitchSection(sect);
|
|
|
|
}
|
2010-07-30 19:55:47 +00:00
|
|
|
const MCSection *StaticInitSect =
|
|
|
|
OutContext.getMachOSection("__TEXT", "__StaticInit",
|
2014-03-07 07:36:05 +00:00
|
|
|
MachO::S_REGULAR |
|
|
|
|
MachO::S_ATTR_PURE_INSTRUCTIONS,
|
2010-07-30 19:55:47 +00:00
|
|
|
SectionKind::getText());
|
|
|
|
OutStreamer.SwitchSection(StaticInitSect);
|
2009-09-30 00:23:42 +00:00
|
|
|
}
|
2014-01-20 19:15:59 +00:00
|
|
|
|
|
|
|
// Compiling with debug info should not affect the code
|
|
|
|
// generation. Ensure the cstring section comes before the
|
|
|
|
// optional __DWARF secion. Otherwise, PC-relative loads would
|
|
|
|
// have to use different instruction sequences at "-g" in order to
|
|
|
|
// reach global data in the same object file.
|
|
|
|
OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
|
2009-09-30 00:23:42 +00:00
|
|
|
}
|
|
|
|
|
2009-11-09 00:11:35 +00:00
|
|
|
// Use unified assembler syntax.
|
2010-09-30 02:45:56 +00:00
|
|
|
OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
|
2009-06-17 23:43:18 +00:00
|
|
|
|
2009-05-23 19:51:20 +00:00
|
|
|
// Emit ARM Build Attributes
|
2012-02-21 20:46:00 +00:00
|
|
|
if (Subtarget->isTargetELF())
|
2010-10-06 22:36:46 +00:00
|
|
|
emitAttributes();
|
2014-07-25 05:12:49 +00:00
|
|
|
|
|
|
|
if (!M.getModuleInlineAsm().empty() && Subtarget->isThumb())
|
|
|
|
OutStreamer.EmitAssemblerFlag(MCAF_Code16);
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
|
|
|
|
2014-04-29 10:06:05 +00:00
|
|
|
static void
|
|
|
|
emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
|
|
|
|
MachineModuleInfoImpl::StubValueTy &MCSym) {
|
|
|
|
// L_foo$stub:
|
|
|
|
OutStreamer.EmitLabel(StubLabel);
|
|
|
|
// .indirect_symbol _foo
|
|
|
|
OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
|
|
|
|
|
|
|
|
if (MCSym.getInt())
|
|
|
|
// External to current translation unit.
|
|
|
|
OutStreamer.EmitIntValue(0, 4/*size*/);
|
|
|
|
else
|
|
|
|
// Internal to current translation unit.
|
|
|
|
//
|
|
|
|
// When we place the LSDA into the TEXT section, the type info
|
|
|
|
// pointers need to be indirect and pc-rel. We accomplish this by
|
|
|
|
// using NLPs; however, sometimes the types are local to the file.
|
|
|
|
// We need to fill in the value for the NLP in those cases.
|
|
|
|
OutStreamer.EmitValue(
|
|
|
|
MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
|
|
|
|
4 /*size*/);
|
|
|
|
}
|
|
|
|
|
2008-08-07 09:54:23 +00:00
|
|
|
|
2009-10-19 17:59:19 +00:00
|
|
|
void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
|
2014-01-06 14:28:05 +00:00
|
|
|
if (Subtarget->isTargetMachO()) {
|
2009-08-03 22:18:15 +00:00
|
|
|
// All darwin targets use mach-o.
|
2010-04-17 16:44:48 +00:00
|
|
|
const TargetLoweringObjectFileMachO &TLOFMacho =
|
|
|
|
static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
|
2009-10-19 18:38:33 +00:00
|
|
|
MachineModuleInfoMachO &MMIMacho =
|
|
|
|
MMI->getObjFileInfo<MachineModuleInfoMachO>();
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
// Output non-lazy-pointers for external and common global variables.
|
2009-10-19 18:38:33 +00:00
|
|
|
MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
|
2010-03-10 22:34:10 +00:00
|
|
|
|
2009-10-19 18:38:33 +00:00
|
|
|
if (!Stubs.empty()) {
|
2009-08-10 01:39:42 +00:00
|
|
|
// Switch with ".non_lazy_symbol_pointer" directive.
|
2009-08-19 05:49:37 +00:00
|
|
|
OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
|
2009-08-10 18:01:34 +00:00
|
|
|
EmitAlignment(2);
|
2014-04-29 10:06:05 +00:00
|
|
|
|
|
|
|
for (auto &Stub : Stubs)
|
|
|
|
emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
|
2010-03-09 00:40:17 +00:00
|
|
|
|
|
|
|
Stubs.clear();
|
|
|
|
OutStreamer.AddBlankLine();
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2009-10-19 18:44:38 +00:00
|
|
|
Stubs = MMIMacho.GetHiddenGVStubList();
|
|
|
|
if (!Stubs.empty()) {
|
2014-04-29 10:06:05 +00:00
|
|
|
OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
|
2009-08-10 18:02:16 +00:00
|
|
|
EmitAlignment(2);
|
2014-04-29 10:06:05 +00:00
|
|
|
|
|
|
|
for (auto &Stub : Stubs)
|
|
|
|
emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
|
2010-03-09 00:43:34 +00:00
|
|
|
|
|
|
|
Stubs.clear();
|
|
|
|
OutStreamer.AddBlankLine();
|
2008-12-05 01:06:39 +00:00
|
|
|
}
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
// Funny Darwin hack: This flag tells the linker that no global symbols
|
|
|
|
// contain code that falls through to other global symbols (e.g. the obvious
|
|
|
|
// implementation of multiple entry points). If this doesn't occur, the
|
|
|
|
// linker can safely perform dead code stripping. Since LLVM never
|
|
|
|
// generates code that does this, it is always safe to set.
|
2010-01-23 06:39:22 +00:00
|
|
|
OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
|
2006-07-27 11:38:51 +00:00
|
|
|
}
|
2014-05-01 00:25:15 +00:00
|
|
|
|
|
|
|
// Emit a .data.rel section containing any stubs that were created.
|
|
|
|
if (Subtarget->isTargetELF()) {
|
|
|
|
const TargetLoweringObjectFileELF &TLOFELF =
|
|
|
|
static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
|
|
|
|
|
|
|
|
MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
|
|
|
|
|
|
|
|
// Output stubs for external and common global variables.
|
|
|
|
MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
|
|
|
|
if (!Stubs.empty()) {
|
|
|
|
OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
|
2014-08-04 21:25:23 +00:00
|
|
|
const DataLayout *TD = TM.getSubtargetImpl()->getDataLayout();
|
2014-05-01 00:25:15 +00:00
|
|
|
|
|
|
|
for (auto &stub: Stubs) {
|
|
|
|
OutStreamer.EmitLabel(stub.first);
|
|
|
|
OutStreamer.EmitSymbolValue(stub.second.getPointer(),
|
|
|
|
TD->getPointerSize(0));
|
|
|
|
}
|
|
|
|
Stubs.clear();
|
|
|
|
}
|
|
|
|
}
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
2008-08-17 13:55:10 +00:00
|
|
|
|
2010-10-06 22:36:46 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
|
|
|
|
// FIXME:
|
|
|
|
// The following seem like one-off assembler flags, but they actually need
|
2010-10-06 22:46:47 +00:00
|
|
|
// to appear in the .ARM.attributes section in ELF.
|
2010-10-06 22:36:46 +00:00
|
|
|
// Instead of subclassing the MCELFStreamer, we do the work here.
|
|
|
|
|
2013-10-07 16:55:23 +00:00
|
|
|
static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
|
|
|
|
const ARMSubtarget *Subtarget) {
|
|
|
|
if (CPU == "xscale")
|
|
|
|
return ARMBuildAttrs::v5TEJ;
|
|
|
|
|
|
|
|
if (Subtarget->hasV8Ops())
|
|
|
|
return ARMBuildAttrs::v8;
|
|
|
|
else if (Subtarget->hasV7Ops()) {
|
|
|
|
if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
|
|
|
|
return ARMBuildAttrs::v7E_M;
|
|
|
|
return ARMBuildAttrs::v7;
|
|
|
|
} else if (Subtarget->hasV6T2Ops())
|
|
|
|
return ARMBuildAttrs::v6T2;
|
|
|
|
else if (Subtarget->hasV6MOps())
|
|
|
|
return ARMBuildAttrs::v6S_M;
|
|
|
|
else if (Subtarget->hasV6Ops())
|
|
|
|
return ARMBuildAttrs::v6;
|
|
|
|
else if (Subtarget->hasV5TEOps())
|
|
|
|
return ARMBuildAttrs::v5TE;
|
|
|
|
else if (Subtarget->hasV5TOps())
|
|
|
|
return ARMBuildAttrs::v5T;
|
|
|
|
else if (Subtarget->hasV4TOps())
|
|
|
|
return ARMBuildAttrs::v4T;
|
|
|
|
else
|
|
|
|
return ARMBuildAttrs::v4;
|
|
|
|
}
|
|
|
|
|
2010-10-06 22:36:46 +00:00
|
|
|
void ARMAsmPrinter::emitAttributes() {
|
2014-01-14 01:21:46 +00:00
|
|
|
MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
|
2010-10-06 22:46:47 +00:00
|
|
|
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.switchVendor("aeabi");
|
2010-10-25 17:50:35 +00:00
|
|
|
|
2010-10-06 22:36:46 +00:00
|
|
|
std::string CPUString = Subtarget->getCPUString();
|
2011-02-07 00:49:53 +00:00
|
|
|
|
2013-12-06 22:48:17 +00:00
|
|
|
// FIXME: remove krait check when GNU tools support krait cpu
|
|
|
|
if (CPUString != "generic" && CPUString != "krait")
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
|
2013-10-07 16:55:23 +00:00
|
|
|
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
|
|
|
|
getArchForCPU(CPUString, Subtarget));
|
2013-10-07 16:55:23 +00:00
|
|
|
|
2014-01-10 16:42:55 +00:00
|
|
|
// Tag_CPU_arch_profile must have the default value of 0 when "Architecture
|
2014-04-03 23:43:18 +00:00
|
|
|
// profile is not applicable (e.g. pre v7, or cross-profile code)".
|
2014-01-10 16:42:55 +00:00
|
|
|
if (Subtarget->hasV7Ops()) {
|
|
|
|
if (Subtarget->isAClass()) {
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
|
|
|
|
ARMBuildAttrs::ApplicationProfile);
|
|
|
|
} else if (Subtarget->isRClass()) {
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
|
|
|
|
ARMBuildAttrs::RealTimeProfile);
|
|
|
|
} else if (Subtarget->isMClass()) {
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
|
|
|
|
ARMBuildAttrs::MicroControllerProfile);
|
|
|
|
}
|
2013-10-07 16:55:23 +00:00
|
|
|
}
|
|
|
|
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
|
|
|
|
ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
|
2013-10-07 16:55:23 +00:00
|
|
|
if (Subtarget->isThumb1Only()) {
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
|
|
|
|
ARMBuildAttrs::Allowed);
|
2013-10-07 16:55:23 +00:00
|
|
|
} else if (Subtarget->hasThumb2()) {
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
|
|
|
|
ARMBuildAttrs::AllowThumb32);
|
2013-10-07 16:55:23 +00:00
|
|
|
}
|
2010-10-06 22:36:46 +00:00
|
|
|
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
if (Subtarget->hasNEON()) {
|
2011-02-28 22:04:27 +00:00
|
|
|
/* NEON is not exactly a VFP architecture, but GAS emit one of
|
2013-09-13 11:51:52 +00:00
|
|
|
* neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
|
2013-10-07 16:55:23 +00:00
|
|
|
if (Subtarget->hasFPARMv8()) {
|
|
|
|
if (Subtarget->hasCrypto())
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
|
2013-10-07 16:55:23 +00:00
|
|
|
else
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitFPU(ARM::NEON_FP_ARMV8);
|
2013-10-07 16:55:23 +00:00
|
|
|
}
|
2013-09-13 11:51:52 +00:00
|
|
|
else if (Subtarget->hasVFP4())
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitFPU(ARM::NEON_VFPV4);
|
2012-01-22 12:07:33 +00:00
|
|
|
else
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitFPU(ARM::NEON);
|
|
|
|
// Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
|
2013-06-27 11:49:26 +00:00
|
|
|
if (Subtarget->hasV8Ops())
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
|
|
|
|
ARMBuildAttrs::AllowNeonARMv8);
|
|
|
|
} else {
|
|
|
|
if (Subtarget->hasFPARMv8())
|
2014-10-01 09:02:17 +00:00
|
|
|
// FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
|
|
|
|
// FPU, but there are two different names for it depending on the CPU.
|
|
|
|
ATS.emitFPU(Subtarget->hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
else if (Subtarget->hasVFP4())
|
|
|
|
ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
|
|
|
|
else if (Subtarget->hasVFP3())
|
|
|
|
ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
|
|
|
|
else if (Subtarget->hasVFP2())
|
|
|
|
ATS.emitFPU(ARM::VFPV2);
|
2011-02-28 22:04:27 +00:00
|
|
|
}
|
2010-10-06 22:36:46 +00:00
|
|
|
|
2014-05-27 13:30:21 +00:00
|
|
|
if (TM.getRelocationModel() == Reloc::PIC_) {
|
|
|
|
// PIC specific attributes.
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
|
|
|
|
ARMBuildAttrs::AddressRWPCRel);
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
|
|
|
|
ARMBuildAttrs::AddressROPCRel);
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
|
|
|
|
ARMBuildAttrs::AddressGOT);
|
|
|
|
} else {
|
|
|
|
// Allow direct addressing of imported data for all other relocation models.
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
|
|
|
|
ARMBuildAttrs::AddressDirect);
|
|
|
|
}
|
|
|
|
|
2010-10-06 22:36:46 +00:00
|
|
|
// Signal various FP modes.
|
2013-10-11 16:03:43 +00:00
|
|
|
if (!TM.Options.UnsafeFPMath) {
|
2014-12-02 08:22:29 +00:00
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
|
|
|
|
ARMBuildAttrs::IEEEDenormals);
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
|
|
|
|
ARMBuildAttrs::Allowed);
|
2014-12-02 08:22:29 +00:00
|
|
|
} else {
|
|
|
|
if (!Subtarget->hasVFP2()) {
|
|
|
|
// When the target doesn't have an FPU (by design or
|
|
|
|
// intention), the assumptions made on the software support
|
|
|
|
// mirror that of the equivalent hardware support *if it
|
|
|
|
// existed*. For v7 and better we indicate that denormals are
|
|
|
|
// flushed preserving sign, and for V6 we indicate that
|
|
|
|
// denormals are flushed to positive zero.
|
|
|
|
if (Subtarget->hasV7Ops())
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
|
|
|
|
ARMBuildAttrs::PreserveFPSign);
|
|
|
|
} else if (Subtarget->hasVFP3()) {
|
|
|
|
// In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
|
|
|
|
// the sign bit of the zero matches the sign bit of the input or
|
|
|
|
// result that is being flushed to zero.
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
|
|
|
|
ARMBuildAttrs::PreserveFPSign);
|
|
|
|
}
|
|
|
|
// For VFPv2 implementations it is implementation defined as
|
|
|
|
// to whether denormals are flushed to positive zero or to
|
|
|
|
// whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
|
|
|
|
// LLVM has chosen to flush this to positive zero (most likely for
|
|
|
|
// GCC compatibility), so that's the chosen value here (the
|
|
|
|
// absence of its emission implies zero).
|
2013-10-07 16:55:23 +00:00
|
|
|
}
|
2010-10-06 22:36:46 +00:00
|
|
|
|
2013-10-11 16:03:43 +00:00
|
|
|
if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
|
|
|
|
ARMBuildAttrs::Allowed);
|
2013-10-11 16:03:43 +00:00
|
|
|
else
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
|
|
|
|
ARMBuildAttrs::AllowIEE754);
|
2013-10-11 16:03:43 +00:00
|
|
|
|
2014-10-08 12:26:22 +00:00
|
|
|
if (Subtarget->allowsUnalignedMem())
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
|
|
|
|
ARMBuildAttrs::Allowed);
|
|
|
|
else
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
|
|
|
|
ARMBuildAttrs::Not_Allowed);
|
|
|
|
|
2014-01-19 08:25:27 +00:00
|
|
|
// FIXME: add more flags to ARMBuildAttributes.h
|
2010-10-06 22:36:46 +00:00
|
|
|
// 8-bytes alignment stuff.
|
2014-01-19 08:25:35 +00:00
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
|
2010-10-06 22:36:46 +00:00
|
|
|
|
2013-11-01 11:21:16 +00:00
|
|
|
// ABI_HardFP_use attribute to indicate single precision FP.
|
|
|
|
if (Subtarget->isFPOnlySP())
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
|
|
|
|
ARMBuildAttrs::HardFPSinglePrecision);
|
|
|
|
|
2010-10-06 22:36:46 +00:00
|
|
|
// Hard float. Use both S and D registers and conform to AAPCS-VFP.
|
2013-11-01 11:21:16 +00:00
|
|
|
if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
|
|
|
|
|
2010-10-06 22:36:46 +00:00
|
|
|
// FIXME: Should we signal R9 usage?
|
2010-10-25 17:50:35 +00:00
|
|
|
|
2013-11-12 10:38:05 +00:00
|
|
|
if (Subtarget->hasFP16())
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
|
|
|
|
|
2013-11-01 13:27:35 +00:00
|
|
|
if (Subtarget->hasMPExtension())
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
|
|
|
|
|
2014-01-20 10:18:42 +00:00
|
|
|
// Hardware divide in ARM mode is part of base arch, starting from ARMv8.
|
|
|
|
// If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
|
|
|
|
// It is not possible to produce DisallowDIV: if hwdiv is present in the base
|
|
|
|
// arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
|
|
|
|
// AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
|
|
|
|
// otherwise, the default value (AllowDIVIfExists) applies.
|
|
|
|
if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
|
2010-10-25 17:50:35 +00:00
|
|
|
|
2014-06-20 10:08:11 +00:00
|
|
|
if (MMI) {
|
|
|
|
if (const Module *SourceModule = MMI->getModule()) {
|
|
|
|
// ABI_PCS_wchar_t to indicate wchar_t width
|
|
|
|
// FIXME: There is no way to emit value 0 (wchar_t prohibited).
|
|
|
|
if (auto WCharWidthValue = cast_or_null<ConstantInt>(
|
|
|
|
SourceModule->getModuleFlag("wchar_size"))) {
|
|
|
|
int WCharWidth = WCharWidthValue->getZExtValue();
|
|
|
|
assert((WCharWidth == 2 || WCharWidth == 4) &&
|
|
|
|
"wchar_t width must be 2 or 4 bytes");
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
|
|
|
|
}
|
|
|
|
|
|
|
|
// ABI_enum_size to indicate enum width
|
|
|
|
// FIXME: There is no way to emit value 0 (enums prohibited) or value 3
|
|
|
|
// (all enums contain a value needing 32 bits to encode).
|
|
|
|
if (auto EnumWidthValue = cast_or_null<ConstantInt>(
|
|
|
|
SourceModule->getModuleFlag("min_enum_size"))) {
|
|
|
|
int EnumWidth = EnumWidthValue->getZExtValue();
|
|
|
|
assert((EnumWidth == 1 || EnumWidth == 4) &&
|
|
|
|
"Minimum enum width must be 1 or 4 bytes");
|
|
|
|
int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-25 14:03:14 +00:00
|
|
|
// TODO: We currently only support either reserving the register, or treating
|
|
|
|
// it as another callee-saved register, but not as SB or a TLS pointer; It
|
|
|
|
// would instead be nicer to push this from the frontend as metadata, as we do
|
|
|
|
// for the wchar and enum size tags
|
|
|
|
if (Subtarget->isR9Reserved())
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
|
|
|
|
ARMBuildAttrs::R9Reserved);
|
|
|
|
else
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
|
|
|
|
ARMBuildAttrs::R9IsGPR);
|
|
|
|
|
2013-11-01 13:27:35 +00:00
|
|
|
if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
|
|
|
|
ARMBuildAttrs::AllowTZVirtualization);
|
|
|
|
else if (Subtarget->hasTrustZone())
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
|
|
|
|
ARMBuildAttrs::AllowTZ);
|
|
|
|
else if (Subtarget->hasVirtualization())
|
|
|
|
ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
|
|
|
|
ARMBuildAttrs::AllowVirtualization);
|
|
|
|
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ATS.finishAttributeSection();
|
2010-10-06 22:36:46 +00:00
|
|
|
}
|
|
|
|
|
2009-10-19 20:20:46 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2010-09-18 00:05:05 +00:00
|
|
|
static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
|
|
|
|
unsigned LabelId, MCContext &Ctx) {
|
|
|
|
|
|
|
|
MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
|
|
|
|
+ "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
|
|
|
|
return Label;
|
|
|
|
}
|
|
|
|
|
2010-11-10 03:26:07 +00:00
|
|
|
static MCSymbolRefExpr::VariantKind
|
|
|
|
getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
|
|
|
|
switch (Modifier) {
|
|
|
|
case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
|
2013-12-04 22:43:20 +00:00
|
|
|
case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
|
|
|
|
case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
|
|
|
|
case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
|
|
|
|
case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
|
|
|
|
case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
|
2010-11-10 03:26:07 +00:00
|
|
|
}
|
2012-01-20 21:51:11 +00:00
|
|
|
llvm_unreachable("Invalid ARMCPModifier!");
|
2010-11-10 03:26:07 +00:00
|
|
|
}
|
|
|
|
|
2013-11-25 16:24:52 +00:00
|
|
|
MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
|
|
|
|
unsigned char TargetFlags) {
|
2014-07-07 05:18:30 +00:00
|
|
|
if (Subtarget->isTargetMachO()) {
|
|
|
|
bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
|
|
|
|
Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
|
|
|
|
|
|
|
|
if (!IsIndirect)
|
|
|
|
return getSymbol(GV);
|
2011-01-17 08:03:18 +00:00
|
|
|
|
2014-07-07 05:18:30 +00:00
|
|
|
// FIXME: Remove this when Darwin transition to @GOT like syntax.
|
|
|
|
MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
|
|
|
|
MachineModuleInfoMachO &MMIMachO =
|
|
|
|
MMI->getObjFileInfo<MachineModuleInfoMachO>();
|
|
|
|
MachineModuleInfoImpl::StubValueTy &StubSym =
|
|
|
|
GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
|
|
|
|
: MMIMachO.getGVStubEntry(MCSym);
|
|
|
|
if (!StubSym.getPointer())
|
|
|
|
StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
|
|
|
|
!GV->hasInternalLinkage());
|
|
|
|
return MCSym;
|
|
|
|
} else if (Subtarget->isTargetCOFF()) {
|
|
|
|
assert(Subtarget->isTargetWindows() &&
|
|
|
|
"Windows is the only supported COFF target");
|
|
|
|
|
|
|
|
bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
|
|
|
|
if (!IsIndirect)
|
|
|
|
return getSymbol(GV);
|
|
|
|
|
|
|
|
SmallString<128> Name;
|
|
|
|
Name = "__imp_";
|
|
|
|
getNameWithPrefix(Name, GV);
|
|
|
|
|
|
|
|
return OutContext.GetOrCreateSymbol(Name);
|
|
|
|
} else if (Subtarget->isTargetELF()) {
|
|
|
|
return getSymbol(GV);
|
|
|
|
}
|
|
|
|
llvm_unreachable("unexpected target");
|
2011-01-17 08:03:18 +00:00
|
|
|
}
|
|
|
|
|
2010-11-09 18:45:04 +00:00
|
|
|
void ARMAsmPrinter::
|
|
|
|
EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
|
2014-08-04 21:25:23 +00:00
|
|
|
const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
|
|
|
|
int Size =
|
|
|
|
TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(MCPV->getType());
|
2010-11-09 18:45:04 +00:00
|
|
|
|
|
|
|
ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
|
|
|
|
|
2010-11-10 17:59:10 +00:00
|
|
|
MCSymbol *MCSym;
|
2010-11-09 18:45:04 +00:00
|
|
|
if (ACPV->isLSDA()) {
|
2010-11-10 17:59:10 +00:00
|
|
|
SmallString<128> Str;
|
|
|
|
raw_svector_ostream OS(Str);
|
2014-01-03 19:21:54 +00:00
|
|
|
OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
|
2010-11-10 17:59:10 +00:00
|
|
|
MCSym = OutContext.GetOrCreateSymbol(OS.str());
|
2010-11-09 18:45:04 +00:00
|
|
|
} else if (ACPV->isBlockAddress()) {
|
2011-10-01 08:00:54 +00:00
|
|
|
const BlockAddress *BA =
|
|
|
|
cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
|
|
|
|
MCSym = GetBlockAddressSymbol(BA);
|
2010-11-09 18:45:04 +00:00
|
|
|
} else if (ACPV->isGlobalValue()) {
|
2011-10-01 08:00:54 +00:00
|
|
|
const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
|
2013-11-25 16:24:52 +00:00
|
|
|
|
|
|
|
// On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
|
|
|
|
// flag the global as MO_NONLAZY.
|
2014-01-06 14:28:05 +00:00
|
|
|
unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
|
2013-11-25 17:04:35 +00:00
|
|
|
MCSym = GetARMGVSymbol(GV, TF);
|
2011-09-29 23:50:42 +00:00
|
|
|
} else if (ACPV->isMachineBasicBlock()) {
|
2011-10-01 09:30:42 +00:00
|
|
|
const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
|
2011-09-29 23:50:42 +00:00
|
|
|
MCSym = MBB->getSymbol();
|
2010-11-09 18:45:04 +00:00
|
|
|
} else {
|
|
|
|
assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
|
2011-10-01 08:58:29 +00:00
|
|
|
const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
|
|
|
|
MCSym = GetExternalSymbolSymbol(Sym);
|
2010-11-09 18:45:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Create an MCSymbol for the reference.
|
2010-11-10 03:26:07 +00:00
|
|
|
const MCExpr *Expr =
|
|
|
|
MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
|
|
|
|
OutContext);
|
|
|
|
|
|
|
|
if (ACPV->getPCAdjustment()) {
|
2014-01-03 19:21:54 +00:00
|
|
|
MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
|
2010-11-10 03:26:07 +00:00
|
|
|
getFunctionNumber(),
|
|
|
|
ACPV->getLabelId(),
|
|
|
|
OutContext);
|
|
|
|
const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
|
|
|
|
PCRelExpr =
|
|
|
|
MCBinaryExpr::CreateAdd(PCRelExpr,
|
|
|
|
MCConstantExpr::Create(ACPV->getPCAdjustment(),
|
|
|
|
OutContext),
|
|
|
|
OutContext);
|
|
|
|
if (ACPV->mustAddCurrentAddress()) {
|
|
|
|
// We want "(<expr> - .)", but MC doesn't have a concept of the '.'
|
|
|
|
// label, so just emit a local label end reference that instead.
|
|
|
|
MCSymbol *DotSym = OutContext.CreateTempSymbol();
|
|
|
|
OutStreamer.EmitLabel(DotSym);
|
|
|
|
const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
|
|
|
|
PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
|
2010-11-09 18:45:04 +00:00
|
|
|
}
|
2010-11-10 03:26:07 +00:00
|
|
|
Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
|
2010-11-09 18:45:04 +00:00
|
|
|
}
|
2010-11-10 03:26:07 +00:00
|
|
|
OutStreamer.EmitValue(Expr, Size);
|
2010-11-09 18:45:04 +00:00
|
|
|
}
|
|
|
|
|
2010-09-22 17:39:48 +00:00
|
|
|
void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
|
|
|
|
unsigned Opcode = MI->getOpcode();
|
|
|
|
int OpNum = 1;
|
|
|
|
if (Opcode == ARM::BR_JTadd)
|
|
|
|
OpNum = 2;
|
|
|
|
else if (Opcode == ARM::BR_JTm)
|
|
|
|
OpNum = 3;
|
|
|
|
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
|
|
|
|
unsigned JTI = MO1.getIndex();
|
|
|
|
|
|
|
|
// Emit a label for the jump table.
|
|
|
|
MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
|
|
|
|
OutStreamer.EmitLabel(JTISymbol);
|
|
|
|
|
2012-05-18 19:12:01 +00:00
|
|
|
// Mark the jump table as data-in-code.
|
|
|
|
OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
|
|
|
|
|
2010-09-22 17:39:48 +00:00
|
|
|
// Emit each entry of the table.
|
|
|
|
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
|
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
|
|
|
|
MachineBasicBlock *MBB = JTBBs[i];
|
|
|
|
// Construct an MCExpr for the entry. We want a value of the form:
|
|
|
|
// (BasicBlockAddr - TableBeginAddr)
|
|
|
|
//
|
|
|
|
// For example, a table with entries jumping to basic blocks BB0 and BB1
|
|
|
|
// would look like:
|
|
|
|
// LJTI_0_0:
|
|
|
|
// .word (LBB0 - LJTI_0_0)
|
|
|
|
// .word (LBB1 - LJTI_0_0)
|
|
|
|
const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
|
|
|
|
|
|
|
|
if (TM.getRelocationModel() == Reloc::PIC_)
|
|
|
|
Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
|
|
|
|
OutContext),
|
|
|
|
OutContext);
|
2011-08-31 22:23:09 +00:00
|
|
|
// If we're generating a table of Thumb addresses in static relocation
|
|
|
|
// model, we need to add one to keep interworking correctly.
|
|
|
|
else if (AFI->isThumbFunction())
|
|
|
|
Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
|
|
|
|
OutContext);
|
2010-09-22 17:39:48 +00:00
|
|
|
OutStreamer.EmitValue(Expr, 4);
|
|
|
|
}
|
2012-05-18 19:12:01 +00:00
|
|
|
// Mark the end of jump table data-in-code region.
|
|
|
|
OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
|
2010-09-22 17:39:48 +00:00
|
|
|
}
|
|
|
|
|
2010-09-21 23:28:16 +00:00
|
|
|
void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
|
|
|
|
unsigned Opcode = MI->getOpcode();
|
|
|
|
int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
|
|
|
|
unsigned JTI = MO1.getIndex();
|
|
|
|
|
|
|
|
MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
|
|
|
|
OutStreamer.EmitLabel(JTISymbol);
|
|
|
|
|
|
|
|
// Emit each entry of the table.
|
|
|
|
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
|
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
2010-09-22 17:15:35 +00:00
|
|
|
unsigned OffsetWidth = 4;
|
2012-05-18 19:12:01 +00:00
|
|
|
if (MI->getOpcode() == ARM::t2TBB_JT) {
|
2010-09-22 17:15:35 +00:00
|
|
|
OffsetWidth = 1;
|
2012-05-18 19:12:01 +00:00
|
|
|
// Mark the jump table as data-in-code.
|
|
|
|
OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
|
|
|
|
} else if (MI->getOpcode() == ARM::t2TBH_JT) {
|
2010-09-22 17:15:35 +00:00
|
|
|
OffsetWidth = 2;
|
2012-05-18 19:12:01 +00:00
|
|
|
// Mark the jump table as data-in-code.
|
|
|
|
OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
|
|
|
|
}
|
2010-09-21 23:28:16 +00:00
|
|
|
|
|
|
|
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
|
|
|
|
MachineBasicBlock *MBB = JTBBs[i];
|
2010-09-22 17:15:35 +00:00
|
|
|
const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
|
2014-07-07 05:18:22 +00:00
|
|
|
OutContext);
|
2010-09-21 23:28:16 +00:00
|
|
|
// If this isn't a TBB or TBH, the entries are direct branch instructions.
|
2010-09-22 17:15:35 +00:00
|
|
|
if (OffsetWidth == 4) {
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addExpr(MBBSymbolExpr)
|
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2010-09-21 23:28:16 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// Otherwise it's an offset from the dispatch instruction. Construct an
|
2010-09-22 17:15:35 +00:00
|
|
|
// MCExpr for the entry. We want a value of the form:
|
|
|
|
// (BasicBlockAddr - TableBeginAddr) / 2
|
|
|
|
//
|
|
|
|
// For example, a TBB table with entries jumping to basic blocks BB0 and BB1
|
|
|
|
// would look like:
|
|
|
|
// LJTI_0_0:
|
|
|
|
// .byte (LBB0 - LJTI_0_0) / 2
|
|
|
|
// .byte (LBB1 - LJTI_0_0) / 2
|
|
|
|
const MCExpr *Expr =
|
|
|
|
MCBinaryExpr::CreateSub(MBBSymbolExpr,
|
|
|
|
MCSymbolRefExpr::Create(JTISymbol, OutContext),
|
|
|
|
OutContext);
|
|
|
|
Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
|
|
|
|
OutContext);
|
|
|
|
OutStreamer.EmitValue(Expr, OffsetWidth);
|
2010-09-21 23:28:16 +00:00
|
|
|
}
|
2012-05-21 23:34:42 +00:00
|
|
|
// Mark the end of jump table data-in-code region. 32-bit offsets use
|
|
|
|
// actual branch instructions here, so we don't mark those as a data-region
|
|
|
|
// at all.
|
|
|
|
if (OffsetWidth != 4)
|
|
|
|
OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
|
2010-09-21 23:28:16 +00:00
|
|
|
}
|
|
|
|
|
2011-03-05 18:43:32 +00:00
|
|
|
void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
|
|
|
|
assert(MI->getFlag(MachineInstr::FrameSetup) &&
|
|
|
|
"Only instruction which are involved into frame setup code are allowed");
|
|
|
|
|
2014-01-14 01:21:46 +00:00
|
|
|
MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
|
2013-10-08 13:08:17 +00:00
|
|
|
ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
|
2011-03-05 18:43:32 +00:00
|
|
|
const MachineFunction &MF = *MI->getParent()->getParent();
|
2014-08-05 02:39:49 +00:00
|
|
|
const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
|
2011-03-05 18:43:55 +00:00
|
|
|
const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
|
2011-03-05 18:43:32 +00:00
|
|
|
|
|
|
|
unsigned FramePtr = RegInfo->getFrameRegister(MF);
|
|
|
|
unsigned Opc = MI->getOpcode();
|
2011-03-05 18:43:43 +00:00
|
|
|
unsigned SrcReg, DstReg;
|
|
|
|
|
2011-03-05 18:43:50 +00:00
|
|
|
if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
|
|
|
|
// Two special cases:
|
|
|
|
// 1) tPUSH does not have src/dst regs.
|
|
|
|
// 2) for Thumb1 code we sometimes materialize the constant via constpool
|
|
|
|
// load. Yes, this is pretty fragile, but for now I don't see better
|
|
|
|
// way... :(
|
2011-03-05 18:43:43 +00:00
|
|
|
SrcReg = DstReg = ARM::SP;
|
|
|
|
} else {
|
2011-03-05 18:43:50 +00:00
|
|
|
SrcReg = MI->getOperand(1).getReg();
|
2011-03-05 18:43:43 +00:00
|
|
|
DstReg = MI->getOperand(0).getReg();
|
|
|
|
}
|
2011-03-05 18:43:32 +00:00
|
|
|
|
|
|
|
// Try to figure out the unwinding opcode out of src / dst regs.
|
2011-12-07 07:15:52 +00:00
|
|
|
if (MI->mayStore()) {
|
2011-03-05 18:43:32 +00:00
|
|
|
// Register saves.
|
|
|
|
assert(DstReg == ARM::SP &&
|
|
|
|
"Only stack pointer as a destination reg is supported");
|
|
|
|
|
|
|
|
SmallVector<unsigned, 4> RegList;
|
2011-03-05 18:43:43 +00:00
|
|
|
// Skip src & dst reg, and pred ops.
|
|
|
|
unsigned StartOp = 2 + 2;
|
|
|
|
// Use all the operands.
|
|
|
|
unsigned NumOffset = 0;
|
|
|
|
|
2011-03-05 18:43:32 +00:00
|
|
|
switch (Opc) {
|
|
|
|
default:
|
|
|
|
MI->dump();
|
2012-02-07 02:50:20 +00:00
|
|
|
llvm_unreachable("Unsupported opcode for unwinding information");
|
2011-03-05 18:43:43 +00:00
|
|
|
case ARM::tPUSH:
|
|
|
|
// Special case here: no src & dst reg, but two extra imp ops.
|
|
|
|
StartOp = 2; NumOffset = 2;
|
2011-03-05 18:43:32 +00:00
|
|
|
case ARM::STMDB_UPD:
|
2011-03-05 18:43:43 +00:00
|
|
|
case ARM::t2STMDB_UPD:
|
2011-03-05 18:43:32 +00:00
|
|
|
case ARM::VSTMDDB_UPD:
|
|
|
|
assert(SrcReg == ARM::SP &&
|
|
|
|
"Only stack pointer as a source reg is supported");
|
2011-03-05 18:43:43 +00:00
|
|
|
for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
|
2012-08-04 13:25:58 +00:00
|
|
|
i != NumOps; ++i) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
|
|
// Actually, there should never be any impdef stuff here. Skip it
|
|
|
|
// temporary to workaround PR11902.
|
|
|
|
if (MO.isImplicit())
|
|
|
|
continue;
|
|
|
|
RegList.push_back(MO.getReg());
|
|
|
|
}
|
2011-03-05 18:43:32 +00:00
|
|
|
break;
|
2011-07-26 20:54:26 +00:00
|
|
|
case ARM::STR_PRE_IMM:
|
|
|
|
case ARM::STR_PRE_REG:
|
2012-01-19 12:53:06 +00:00
|
|
|
case ARM::t2STR_PRE:
|
2011-03-05 18:43:32 +00:00
|
|
|
assert(MI->getOperand(2).getReg() == ARM::SP &&
|
|
|
|
"Only stack pointer as a source reg is supported");
|
|
|
|
RegList.push_back(SrcReg);
|
|
|
|
break;
|
|
|
|
}
|
2014-04-30 22:43:13 +00:00
|
|
|
if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
|
|
|
|
ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
|
2011-03-05 18:43:32 +00:00
|
|
|
} else {
|
|
|
|
// Changes of stack / frame pointer.
|
|
|
|
if (SrcReg == ARM::SP) {
|
|
|
|
int64_t Offset = 0;
|
|
|
|
switch (Opc) {
|
|
|
|
default:
|
|
|
|
MI->dump();
|
2012-02-07 02:50:20 +00:00
|
|
|
llvm_unreachable("Unsupported opcode for unwinding information");
|
2011-03-05 18:43:32 +00:00
|
|
|
case ARM::MOVr:
|
2012-01-19 12:53:06 +00:00
|
|
|
case ARM::tMOVr:
|
2011-03-05 18:43:32 +00:00
|
|
|
Offset = 0;
|
|
|
|
break;
|
|
|
|
case ARM::ADDri:
|
|
|
|
Offset = -MI->getOperand(2).getImm();
|
|
|
|
break;
|
|
|
|
case ARM::SUBri:
|
2012-01-19 12:53:06 +00:00
|
|
|
case ARM::t2SUBri:
|
2011-06-29 23:25:04 +00:00
|
|
|
Offset = MI->getOperand(2).getImm();
|
2011-03-05 18:43:32 +00:00
|
|
|
break;
|
2011-03-05 18:43:43 +00:00
|
|
|
case ARM::tSUBspi:
|
2011-06-29 23:25:04 +00:00
|
|
|
Offset = MI->getOperand(2).getImm()*4;
|
2011-03-05 18:43:43 +00:00
|
|
|
break;
|
|
|
|
case ARM::tADDspi:
|
|
|
|
case ARM::tADDrSPi:
|
|
|
|
Offset = -MI->getOperand(2).getImm()*4;
|
|
|
|
break;
|
2011-03-05 18:43:55 +00:00
|
|
|
case ARM::tLDRpci: {
|
|
|
|
// Grab the constpool index and check, whether it corresponds to
|
|
|
|
// original or cloned constpool entry.
|
|
|
|
unsigned CPI = MI->getOperand(1).getIndex();
|
|
|
|
const MachineConstantPool *MCP = MF.getConstantPool();
|
|
|
|
if (CPI >= MCP->getConstants().size())
|
|
|
|
CPI = AFI.getOriginalCPIdx(CPI);
|
|
|
|
assert(CPI != -1U && "Invalid constpool index");
|
|
|
|
|
|
|
|
// Derive the actual offset.
|
|
|
|
const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
|
|
|
|
assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
|
|
|
|
// FIXME: Check for user, it should be "add" instruction!
|
|
|
|
Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
|
2011-03-05 18:43:50 +00:00
|
|
|
break;
|
2011-03-05 18:43:32 +00:00
|
|
|
}
|
2011-03-05 18:43:55 +00:00
|
|
|
}
|
2011-03-05 18:43:32 +00:00
|
|
|
|
2014-04-30 22:43:13 +00:00
|
|
|
if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
|
|
|
|
if (DstReg == FramePtr && FramePtr != ARM::SP)
|
|
|
|
// Set-up of the frame pointer. Positive values correspond to "add"
|
|
|
|
// instruction.
|
|
|
|
ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
|
|
|
|
else if (DstReg == ARM::SP) {
|
|
|
|
// Change of SP by an offset. Positive values correspond to "sub"
|
|
|
|
// instruction.
|
|
|
|
ATS.emitPad(Offset);
|
|
|
|
} else {
|
|
|
|
// Move of SP to a register. Positive values correspond to an "add"
|
|
|
|
// instruction.
|
|
|
|
ATS.emitMovSP(DstReg, -Offset);
|
|
|
|
}
|
2011-03-05 18:43:32 +00:00
|
|
|
}
|
|
|
|
} else if (DstReg == ARM::SP) {
|
|
|
|
MI->dump();
|
2012-02-07 02:50:20 +00:00
|
|
|
llvm_unreachable("Unsupported opcode for unwinding information");
|
2011-03-05 18:43:32 +00:00
|
|
|
}
|
|
|
|
else {
|
|
|
|
MI->dump();
|
2012-02-07 02:50:20 +00:00
|
|
|
llvm_unreachable("Unsupported opcode for unwinding information");
|
2011-03-05 18:43:32 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-07-08 17:40:42 +00:00
|
|
|
// Simple pseudo-instructions have their lowering (with expansion to real
|
|
|
|
// instructions) auto-generated.
|
|
|
|
#include "ARMGenMCPseudoLowering.inc"
|
|
|
|
|
2010-09-29 15:23:40 +00:00
|
|
|
void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
2014-08-04 21:25:23 +00:00
|
|
|
const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
|
2014-01-03 19:21:54 +00:00
|
|
|
|
2012-05-18 19:12:01 +00:00
|
|
|
// If we just ended a constant pool, mark it as such.
|
|
|
|
if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
|
|
|
|
OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
|
|
|
|
InConstantPool = false;
|
|
|
|
}
|
2011-10-04 23:26:17 +00:00
|
|
|
|
2011-08-23 21:32:34 +00:00
|
|
|
// Emit unwinding stuff for frame-related instructions
|
2014-02-07 20:12:49 +00:00
|
|
|
if (Subtarget->isTargetEHABICompatible() &&
|
2014-01-29 11:50:56 +00:00
|
|
|
MI->getFlag(MachineInstr::FrameSetup))
|
2011-08-23 21:32:34 +00:00
|
|
|
EmitUnwindingInstruction(MI);
|
|
|
|
|
2011-07-08 17:40:42 +00:00
|
|
|
// Do any auto-generated pseudo lowerings.
|
|
|
|
if (emitPseudoExpansionLowering(OutStreamer, MI))
|
2011-06-30 18:25:42 +00:00
|
|
|
return;
|
2010-12-09 01:22:19 +00:00
|
|
|
|
2011-09-21 02:20:46 +00:00
|
|
|
assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
|
|
|
|
"Pseudo flag setting opcode should be expanded early");
|
|
|
|
|
2011-07-08 17:40:42 +00:00
|
|
|
// Check for manual lowerings.
|
|
|
|
unsigned Opc = MI->getOpcode();
|
|
|
|
switch (Opc) {
|
2012-02-07 02:50:20 +00:00
|
|
|
case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
|
2013-06-16 20:34:27 +00:00
|
|
|
case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
|
2010-12-14 21:10:47 +00:00
|
|
|
case ARM::LEApcrel:
|
2010-12-14 22:28:03 +00:00
|
|
|
case ARM::tLEApcrel:
|
2010-12-14 21:10:47 +00:00
|
|
|
case ARM::t2LEApcrel: {
|
2010-12-02 00:28:45 +00:00
|
|
|
// FIXME: Need to also handle globals and externals
|
2012-11-26 13:34:22 +00:00
|
|
|
MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
|
2012-11-26 18:05:52 +00:00
|
|
|
ARM::t2LEApcrel ? ARM::t2ADR
|
2012-11-26 13:34:22 +00:00
|
|
|
: (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
|
|
|
|
: ARM::ADR))
|
|
|
|
.addReg(MI->getOperand(0).getReg())
|
|
|
|
.addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
|
|
|
|
// Add predicate operands.
|
|
|
|
.addImm(MI->getOperand(2).getImm())
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(MI->getOperand(3).getReg()));
|
2010-12-02 00:28:45 +00:00
|
|
|
return;
|
|
|
|
}
|
2010-12-14 22:28:03 +00:00
|
|
|
case ARM::LEApcrelJT:
|
|
|
|
case ARM::tLEApcrelJT:
|
|
|
|
case ARM::t2LEApcrelJT: {
|
2012-11-26 13:34:22 +00:00
|
|
|
MCSymbol *JTIPICSymbol =
|
|
|
|
GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
|
|
|
|
MI->getOperand(2).getImm());
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
|
2012-11-26 18:05:52 +00:00
|
|
|
ARM::t2LEApcrelJT ? ARM::t2ADR
|
2012-11-26 13:34:22 +00:00
|
|
|
: (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
|
|
|
|
: ARM::ADR))
|
|
|
|
.addReg(MI->getOperand(0).getReg())
|
|
|
|
.addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
|
|
|
|
// Add predicate operands.
|
|
|
|
.addImm(MI->getOperand(3).getImm())
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(MI->getOperand(4).getReg()));
|
2010-12-01 19:47:31 +00:00
|
|
|
return;
|
|
|
|
}
|
2011-03-12 00:45:26 +00:00
|
|
|
// Darwin call instructions are just normal call instructions with different
|
|
|
|
// clobber semantics (they clobber R9).
|
2010-11-30 18:30:19 +00:00
|
|
|
case ARM::BX_CALL: {
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::LR)
|
|
|
|
.addReg(ARM::PC)
|
2010-11-30 18:30:19 +00:00
|
|
|
// Add predicate operands.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
|
|
|
.addReg(0)
|
2010-11-30 18:30:19 +00:00
|
|
|
// Add 's' bit operand (always reg0 for this)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(MI->getOperand(0).getReg()));
|
2010-11-30 18:30:19 +00:00
|
|
|
return;
|
|
|
|
}
|
2011-05-25 21:53:50 +00:00
|
|
|
case ARM::tBX_CALL: {
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::LR)
|
|
|
|
.addReg(ARM::PC)
|
2011-06-30 22:10:46 +00:00
|
|
|
// Add predicate operands.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(MI->getOperand(0).getReg())
|
2011-05-25 21:53:50 +00:00
|
|
|
// Add predicate operands.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2011-05-25 21:53:50 +00:00
|
|
|
return;
|
|
|
|
}
|
2010-11-30 18:30:19 +00:00
|
|
|
case ARM::BMOVPCRX_CALL: {
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::LR)
|
|
|
|
.addReg(ARM::PC)
|
2010-11-30 18:30:19 +00:00
|
|
|
// Add predicate operands.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
|
|
|
.addReg(0)
|
2010-11-30 18:30:19 +00:00
|
|
|
// Add 's' bit operand (always reg0 for this)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::PC)
|
2013-03-15 17:27:39 +00:00
|
|
|
.addReg(MI->getOperand(0).getReg())
|
2010-11-30 18:30:19 +00:00
|
|
|
// Add predicate operands.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
|
|
|
.addReg(0)
|
2010-11-30 18:30:19 +00:00
|
|
|
// Add 's' bit operand (always reg0 for this)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2010-11-30 18:30:19 +00:00
|
|
|
return;
|
|
|
|
}
|
2012-02-28 18:51:51 +00:00
|
|
|
case ARM::BMOVPCB_CALL: {
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::LR)
|
|
|
|
.addReg(ARM::PC)
|
2012-02-28 18:51:51 +00:00
|
|
|
// Add predicate operands.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
|
|
|
.addReg(0)
|
2012-02-28 18:51:51 +00:00
|
|
|
// Add 's' bit operand (always reg0 for this)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-07-07 05:18:22 +00:00
|
|
|
const MachineOperand &Op = MI->getOperand(0);
|
|
|
|
const GlobalValue *GV = Op.getGlobal();
|
|
|
|
const unsigned TF = Op.getTargetFlags();
|
|
|
|
MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
|
2012-11-26 13:34:22 +00:00
|
|
|
const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addExpr(GVSymExpr)
|
2012-02-28 18:51:51 +00:00
|
|
|
// Add predicate operands.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-02-28 18:51:51 +00:00
|
|
|
return;
|
|
|
|
}
|
2011-01-21 18:55:51 +00:00
|
|
|
case ARM::MOVi16_ga_pcrel:
|
|
|
|
case ARM::t2MOVi16_ga_pcrel: {
|
2011-01-17 08:03:18 +00:00
|
|
|
MCInst TmpInst;
|
2011-01-21 18:55:51 +00:00
|
|
|
TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
|
2011-01-17 08:03:18 +00:00
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
|
|
|
2011-01-21 18:55:51 +00:00
|
|
|
unsigned TF = MI->getOperand(1).getTargetFlags();
|
2011-01-17 08:03:18 +00:00
|
|
|
const GlobalValue *GV = MI->getOperand(1).getGlobal();
|
2013-11-25 16:24:52 +00:00
|
|
|
MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
|
2011-01-17 08:03:18 +00:00
|
|
|
const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
|
2013-11-25 16:24:52 +00:00
|
|
|
|
2014-01-03 19:21:54 +00:00
|
|
|
MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
|
2013-11-25 16:24:52 +00:00
|
|
|
getFunctionNumber(),
|
|
|
|
MI->getOperand(2).getImm(), OutContext);
|
|
|
|
const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
|
|
|
|
unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
|
|
|
|
const MCExpr *PCRelExpr =
|
|
|
|
ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
|
|
|
|
MCBinaryExpr::CreateAdd(LabelSymExpr,
|
2011-01-21 18:55:51 +00:00
|
|
|
MCConstantExpr::Create(PCAdj, OutContext),
|
2013-11-25 16:24:52 +00:00
|
|
|
OutContext), OutContext), OutContext);
|
2011-01-21 18:55:51 +00:00
|
|
|
TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
|
|
|
|
|
2011-01-17 08:03:18 +00:00
|
|
|
// Add predicate operands.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
// Add 's' bit operand (always reg0 for this)
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, TmpInst);
|
2011-01-17 08:03:18 +00:00
|
|
|
return;
|
|
|
|
}
|
2011-01-21 18:55:51 +00:00
|
|
|
case ARM::MOVTi16_ga_pcrel:
|
|
|
|
case ARM::t2MOVTi16_ga_pcrel: {
|
2011-01-17 08:03:18 +00:00
|
|
|
MCInst TmpInst;
|
2011-01-21 18:55:51 +00:00
|
|
|
TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
|
|
|
|
? ARM::MOVTi16 : ARM::t2MOVTi16);
|
2011-01-17 08:03:18 +00:00
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
|
|
|
|
|
2011-01-21 18:55:51 +00:00
|
|
|
unsigned TF = MI->getOperand(2).getTargetFlags();
|
2011-01-17 08:03:18 +00:00
|
|
|
const GlobalValue *GV = MI->getOperand(2).getGlobal();
|
2013-11-25 16:24:52 +00:00
|
|
|
MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
|
2011-01-17 08:03:18 +00:00
|
|
|
const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
|
2013-11-25 16:24:52 +00:00
|
|
|
|
2014-01-03 19:21:54 +00:00
|
|
|
MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
|
2013-11-25 16:24:52 +00:00
|
|
|
getFunctionNumber(),
|
|
|
|
MI->getOperand(3).getImm(), OutContext);
|
|
|
|
const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
|
|
|
|
unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
|
|
|
|
const MCExpr *PCRelExpr =
|
2011-01-21 18:55:51 +00:00
|
|
|
ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
|
|
|
|
MCBinaryExpr::CreateAdd(LabelSymExpr,
|
|
|
|
MCConstantExpr::Create(PCAdj, OutContext),
|
2011-01-17 08:03:18 +00:00
|
|
|
OutContext), OutContext), OutContext);
|
2011-01-21 18:55:51 +00:00
|
|
|
TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
|
2011-01-17 08:03:18 +00:00
|
|
|
// Add predicate operands.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
// Add 's' bit operand (always reg0 for this)
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, TmpInst);
|
2011-01-17 08:03:18 +00:00
|
|
|
return;
|
|
|
|
}
|
2010-09-17 23:41:53 +00:00
|
|
|
case ARM::tPICADD: {
|
|
|
|
// This is a pseudo op for a label + instruction sequence, which looks like:
|
|
|
|
// LPC0:
|
|
|
|
// add r0, pc
|
|
|
|
// This adds the address of LPC0 to r0.
|
|
|
|
|
|
|
|
// Emit the label.
|
2014-01-03 19:21:54 +00:00
|
|
|
OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
|
2010-09-18 00:05:05 +00:00
|
|
|
getFunctionNumber(), MI->getOperand(2).getImm(),
|
|
|
|
OutContext));
|
2010-09-17 23:41:53 +00:00
|
|
|
|
|
|
|
// Form and emit the add.
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(MI->getOperand(0).getReg())
|
|
|
|
.addReg(MI->getOperand(0).getReg())
|
|
|
|
.addReg(ARM::PC)
|
|
|
|
// Add predicate operands.
|
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2010-09-17 23:41:53 +00:00
|
|
|
return;
|
|
|
|
}
|
2010-09-30 19:53:58 +00:00
|
|
|
case ARM::PICADD: {
|
2009-10-19 22:23:04 +00:00
|
|
|
// This is a pseudo op for a label + instruction sequence, which looks like:
|
|
|
|
// LPC0:
|
|
|
|
// add r0, pc, r0
|
|
|
|
// This adds the address of LPC0 to r0.
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-19 22:23:04 +00:00
|
|
|
// Emit the label.
|
2014-01-03 19:21:54 +00:00
|
|
|
OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
|
2010-09-18 00:05:05 +00:00
|
|
|
getFunctionNumber(), MI->getOperand(2).getImm(),
|
|
|
|
OutContext));
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2010-09-14 21:05:34 +00:00
|
|
|
// Form and emit the add.
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(MI->getOperand(0).getReg())
|
|
|
|
.addReg(ARM::PC)
|
|
|
|
.addReg(MI->getOperand(1).getReg())
|
|
|
|
// Add predicate operands.
|
|
|
|
.addImm(MI->getOperand(3).getImm())
|
|
|
|
.addReg(MI->getOperand(4).getReg())
|
|
|
|
// Add 's' bit operand (always reg0 for this)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2009-10-19 22:23:04 +00:00
|
|
|
return;
|
2010-09-16 17:43:25 +00:00
|
|
|
}
|
2010-09-17 16:25:52 +00:00
|
|
|
case ARM::PICSTR:
|
|
|
|
case ARM::PICSTRB:
|
|
|
|
case ARM::PICSTRH:
|
|
|
|
case ARM::PICLDR:
|
|
|
|
case ARM::PICLDRB:
|
|
|
|
case ARM::PICLDRH:
|
|
|
|
case ARM::PICLDRSB:
|
|
|
|
case ARM::PICLDRSH: {
|
2010-09-16 17:43:25 +00:00
|
|
|
// This is a pseudo op for a label + instruction sequence, which looks like:
|
|
|
|
// LPC0:
|
2010-09-17 16:25:52 +00:00
|
|
|
// OP r0, [pc, r0]
|
2010-09-16 17:43:25 +00:00
|
|
|
// The LCP0 label is referenced by a constant pool entry in order to get
|
|
|
|
// a PC-relative address at the ldr instruction.
|
|
|
|
|
|
|
|
// Emit the label.
|
2014-01-03 19:21:54 +00:00
|
|
|
OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
|
2010-09-18 00:05:05 +00:00
|
|
|
getFunctionNumber(), MI->getOperand(2).getImm(),
|
|
|
|
OutContext));
|
2010-09-16 17:43:25 +00:00
|
|
|
|
|
|
|
// Form and emit the load
|
2010-09-17 16:25:52 +00:00
|
|
|
unsigned Opcode;
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected opcode!");
|
2010-10-27 23:12:14 +00:00
|
|
|
case ARM::PICSTR: Opcode = ARM::STRrs; break;
|
|
|
|
case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
|
2010-09-17 16:25:52 +00:00
|
|
|
case ARM::PICSTRH: Opcode = ARM::STRH; break;
|
2010-10-26 22:37:02 +00:00
|
|
|
case ARM::PICLDR: Opcode = ARM::LDRrs; break;
|
2010-10-27 00:19:44 +00:00
|
|
|
case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
|
2010-09-17 16:25:52 +00:00
|
|
|
case ARM::PICLDRH: Opcode = ARM::LDRH; break;
|
|
|
|
case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
|
|
|
|
case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
|
|
|
|
}
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(MI->getOperand(0).getReg())
|
|
|
|
.addReg(ARM::PC)
|
|
|
|
.addReg(MI->getOperand(1).getReg())
|
|
|
|
.addImm(0)
|
|
|
|
// Add predicate operands.
|
|
|
|
.addImm(MI->getOperand(3).getImm())
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(MI->getOperand(4).getReg()));
|
2010-09-16 17:43:25 +00:00
|
|
|
|
|
|
|
return;
|
2009-10-19 22:23:04 +00:00
|
|
|
}
|
2010-09-30 19:53:58 +00:00
|
|
|
case ARM::CONSTPOOL_ENTRY: {
|
2009-10-19 22:33:05 +00:00
|
|
|
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
|
|
|
|
/// in the function. The first operand is the ID# for this instruction, the
|
|
|
|
/// second is the index into the MachineConstantPool that this is, the third
|
|
|
|
/// is the size in bytes of this constant pool entry.
|
2011-12-06 01:43:02 +00:00
|
|
|
/// The required alignment is specified on the basic block holding this MI.
|
2009-10-19 22:33:05 +00:00
|
|
|
unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
|
|
|
|
unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
|
|
|
|
|
2012-05-18 19:12:01 +00:00
|
|
|
// If this is the first entry of the pool, mark it.
|
|
|
|
if (!InConstantPool) {
|
|
|
|
OutStreamer.EmitDataRegion(MCDR_DataRegion);
|
|
|
|
InConstantPool = true;
|
|
|
|
}
|
|
|
|
|
2010-01-23 07:00:21 +00:00
|
|
|
OutStreamer.EmitLabel(GetCPISymbol(LabelId));
|
2009-10-19 22:33:05 +00:00
|
|
|
|
|
|
|
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
|
|
|
|
if (MCPE.isMachineConstantPoolEntry())
|
|
|
|
EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
|
|
|
|
else
|
|
|
|
EmitGlobalConstant(MCPE.Val.ConstVal);
|
|
|
|
return;
|
|
|
|
}
|
2010-09-21 23:28:16 +00:00
|
|
|
case ARM::t2BR_JT: {
|
|
|
|
// Lower and emit the instruction itself, then the jump table following it.
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::PC)
|
|
|
|
.addReg(MI->getOperand(0).getReg())
|
|
|
|
// Add predicate operands.
|
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2010-11-29 22:37:40 +00:00
|
|
|
// Output the data for the jump table itself
|
|
|
|
EmitJump2Table(MI);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
case ARM::t2TBB_JT: {
|
|
|
|
// Lower and emit the instruction itself, then the jump table following it.
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::PC)
|
|
|
|
.addReg(MI->getOperand(0).getReg())
|
|
|
|
// Add predicate operands.
|
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2010-11-29 22:37:40 +00:00
|
|
|
|
|
|
|
// Output the data for the jump table itself
|
|
|
|
EmitJump2Table(MI);
|
|
|
|
// Make sure the next instruction is 2-byte aligned.
|
|
|
|
EmitAlignment(1);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
case ARM::t2TBH_JT: {
|
|
|
|
// Lower and emit the instruction itself, then the jump table following it.
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::PC)
|
|
|
|
.addReg(MI->getOperand(0).getReg())
|
|
|
|
// Add predicate operands.
|
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2010-11-29 22:37:40 +00:00
|
|
|
|
|
|
|
// Output the data for the jump table itself
|
2010-09-21 23:28:16 +00:00
|
|
|
EmitJump2Table(MI);
|
|
|
|
return;
|
|
|
|
}
|
2010-11-29 19:32:47 +00:00
|
|
|
case ARM::tBR_JTr:
|
2010-11-29 18:37:44 +00:00
|
|
|
case ARM::BR_JTr: {
|
|
|
|
// Lower and emit the instruction itself, then the jump table following it.
|
|
|
|
// mov pc, target
|
|
|
|
MCInst TmpInst;
|
2010-11-29 22:37:40 +00:00
|
|
|
unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
|
2011-06-30 23:38:17 +00:00
|
|
|
ARM::MOVr : ARM::tMOVr;
|
2010-11-29 19:32:47 +00:00
|
|
|
TmpInst.setOpcode(Opc);
|
2010-11-29 18:37:44 +00:00
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
|
|
// Add predicate operands.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
2010-11-30 18:30:19 +00:00
|
|
|
// Add 's' bit operand (always reg0 for this)
|
|
|
|
if (Opc == ARM::MOVr)
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, TmpInst);
|
2010-11-29 18:37:44 +00:00
|
|
|
|
2010-11-29 19:32:47 +00:00
|
|
|
// Make sure the Thumb jump table is 4-byte aligned.
|
2011-06-30 23:38:17 +00:00
|
|
|
if (Opc == ARM::tMOVr)
|
2010-11-29 19:32:47 +00:00
|
|
|
EmitAlignment(2);
|
|
|
|
|
2010-11-29 18:37:44 +00:00
|
|
|
// Output the data for the jump table itself
|
|
|
|
EmitJumpTable(MI);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
case ARM::BR_JTm: {
|
|
|
|
// Lower and emit the instruction itself, then the jump table following it.
|
|
|
|
// ldr pc, target
|
|
|
|
MCInst TmpInst;
|
|
|
|
if (MI->getOperand(1).getReg() == 0) {
|
|
|
|
// literal offset
|
|
|
|
TmpInst.setOpcode(ARM::LDRi12);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
|
|
} else {
|
|
|
|
TmpInst.setOpcode(ARM::LDRrs);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
|
|
}
|
|
|
|
// Add predicate operands.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, TmpInst);
|
2010-11-29 18:37:44 +00:00
|
|
|
|
|
|
|
// Output the data for the jump table itself
|
2010-09-22 17:39:48 +00:00
|
|
|
EmitJumpTable(MI);
|
|
|
|
return;
|
|
|
|
}
|
2010-11-17 21:05:55 +00:00
|
|
|
case ARM::BR_JTadd: {
|
|
|
|
// Lower and emit the instruction itself, then the jump table following it.
|
|
|
|
// add pc, target, idx
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::PC)
|
|
|
|
.addReg(MI->getOperand(0).getReg())
|
|
|
|
.addReg(MI->getOperand(1).getReg())
|
|
|
|
// Add predicate operands.
|
|
|
|
.addImm(ARMCC::AL)
|
|
|
|
.addReg(0)
|
|
|
|
// Add 's' bit operand (always reg0 for this)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2010-11-17 21:05:55 +00:00
|
|
|
|
|
|
|
// Output the data for the jump table itself
|
|
|
|
EmitJumpTable(MI);
|
|
|
|
return;
|
|
|
|
}
|
2014-11-13 17:58:48 +00:00
|
|
|
case ARM::SPACE:
|
|
|
|
OutStreamer.EmitZeros(MI->getOperand(1).getImm());
|
|
|
|
return;
|
2010-09-23 18:05:37 +00:00
|
|
|
case ARM::TRAP: {
|
|
|
|
// Non-Darwin binutils don't yet support the "trap" mnemonic.
|
|
|
|
// FIXME: Remove this special case when they do.
|
2014-01-06 14:28:05 +00:00
|
|
|
if (!Subtarget->isTargetMachO()) {
|
2010-10-01 23:21:38 +00:00
|
|
|
//.long 0xe7ffdefe @ trap
|
2010-09-23 19:42:17 +00:00
|
|
|
uint32_t Val = 0xe7ffdefeUL;
|
2010-09-23 18:05:37 +00:00
|
|
|
OutStreamer.AddComment("trap");
|
|
|
|
OutStreamer.EmitIntValue(Val, 4);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2013-01-30 16:30:19 +00:00
|
|
|
case ARM::TRAPNaCl: {
|
|
|
|
//.long 0xe7fedef0 @ trap
|
|
|
|
uint32_t Val = 0xe7fedef0UL;
|
|
|
|
OutStreamer.AddComment("trap");
|
|
|
|
OutStreamer.EmitIntValue(Val, 4);
|
|
|
|
return;
|
|
|
|
}
|
2010-09-23 18:05:37 +00:00
|
|
|
case ARM::tTRAP: {
|
|
|
|
// Non-Darwin binutils don't yet support the "trap" mnemonic.
|
|
|
|
// FIXME: Remove this special case when they do.
|
2014-01-06 14:28:05 +00:00
|
|
|
if (!Subtarget->isTargetMachO()) {
|
2010-10-01 23:21:38 +00:00
|
|
|
//.short 57086 @ trap
|
2010-09-23 18:57:26 +00:00
|
|
|
uint16_t Val = 0xdefe;
|
2010-09-23 18:05:37 +00:00
|
|
|
OutStreamer.AddComment("trap");
|
|
|
|
OutStreamer.EmitIntValue(Val, 2);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2010-09-24 20:47:58 +00:00
|
|
|
case ARM::t2Int_eh_sjlj_setjmp:
|
|
|
|
case ARM::t2Int_eh_sjlj_setjmp_nofp:
|
2010-09-30 19:53:58 +00:00
|
|
|
case ARM::tInt_eh_sjlj_setjmp: {
|
2010-09-24 20:47:58 +00:00
|
|
|
// Two incoming args: GPR:$src, GPR:$val
|
|
|
|
// mov $val, pc
|
|
|
|
// adds $val, #7
|
|
|
|
// str $val, [$src, #4]
|
|
|
|
// movs r0, #0
|
|
|
|
// b 1f
|
|
|
|
// movs r0, #1
|
|
|
|
// 1:
|
|
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ValReg = MI->getOperand(1).getReg();
|
|
|
|
MCSymbol *Label = GetARMSJLJEHLabel();
|
2012-11-26 13:34:22 +00:00
|
|
|
OutStreamer.AddComment("eh_setjmp begin");
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ValReg)
|
|
|
|
.addReg(ARM::PC)
|
2011-06-30 22:10:46 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ValReg)
|
2010-09-24 20:47:58 +00:00
|
|
|
// 's' bit operand
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::CPSR)
|
|
|
|
.addReg(ValReg)
|
|
|
|
.addImm(7)
|
2010-09-24 20:47:58 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ValReg)
|
|
|
|
.addReg(SrcReg)
|
2010-09-24 20:47:58 +00:00
|
|
|
// The offset immediate is #4. The operand value is scaled by 4 for the
|
|
|
|
// tSTR instruction.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(1)
|
2010-09-24 20:47:58 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::R0)
|
|
|
|
.addReg(ARM::CPSR)
|
|
|
|
.addImm(0)
|
2010-09-24 20:47:58 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
|
|
|
const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addExpr(SymbolExpr)
|
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
|
|
|
OutStreamer.AddComment("eh_setjmp end");
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::R0)
|
|
|
|
.addReg(ARM::CPSR)
|
|
|
|
.addImm(1)
|
2010-09-24 20:47:58 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2010-09-24 20:47:58 +00:00
|
|
|
OutStreamer.EmitLabel(Label);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-09-23 23:33:56 +00:00
|
|
|
case ARM::Int_eh_sjlj_setjmp_nofp:
|
2010-09-30 19:53:58 +00:00
|
|
|
case ARM::Int_eh_sjlj_setjmp: {
|
2010-09-23 23:33:56 +00:00
|
|
|
// Two incoming args: GPR:$src, GPR:$val
|
|
|
|
// add $val, pc, #8
|
|
|
|
// str $val, [$src, #+4]
|
|
|
|
// mov r0, #0
|
|
|
|
// add pc, pc, #0
|
|
|
|
// mov r0, #1
|
|
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ValReg = MI->getOperand(1).getReg();
|
|
|
|
|
2012-11-26 13:34:22 +00:00
|
|
|
OutStreamer.AddComment("eh_setjmp begin");
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ValReg)
|
|
|
|
.addReg(ARM::PC)
|
|
|
|
.addImm(8)
|
2010-09-23 23:33:56 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
|
|
|
.addReg(0)
|
2010-09-23 23:33:56 +00:00
|
|
|
// 's' bit operand (always reg0 for this).
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ValReg)
|
|
|
|
.addReg(SrcReg)
|
|
|
|
.addImm(4)
|
2010-09-23 23:33:56 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::R0)
|
|
|
|
.addImm(0)
|
2010-09-23 23:33:56 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
|
|
|
.addReg(0)
|
2010-09-23 23:33:56 +00:00
|
|
|
// 's' bit operand (always reg0 for this).
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::PC)
|
|
|
|
.addReg(ARM::PC)
|
|
|
|
.addImm(0)
|
2010-09-23 23:33:56 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
|
|
|
.addReg(0)
|
2010-09-23 23:33:56 +00:00
|
|
|
// 's' bit operand (always reg0 for this).
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
|
|
|
OutStreamer.AddComment("eh_setjmp end");
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::R0)
|
|
|
|
.addImm(1)
|
2010-09-23 23:33:56 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
|
|
|
.addReg(0)
|
2010-09-23 23:33:56 +00:00
|
|
|
// 's' bit operand (always reg0 for this).
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2010-09-23 23:33:56 +00:00
|
|
|
return;
|
|
|
|
}
|
2010-09-27 21:47:04 +00:00
|
|
|
case ARM::Int_eh_sjlj_longjmp: {
|
|
|
|
// ldr sp, [$src, #8]
|
|
|
|
// ldr $scratch, [$src, #4]
|
|
|
|
// ldr r7, [$src]
|
|
|
|
// bx $scratch
|
|
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ScratchReg = MI->getOperand(1).getReg();
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::SP)
|
|
|
|
.addReg(SrcReg)
|
|
|
|
.addImm(8)
|
2010-09-27 21:47:04 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addReg(SrcReg)
|
|
|
|
.addImm(4)
|
2010-09-27 21:47:04 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::R7)
|
|
|
|
.addReg(SrcReg)
|
|
|
|
.addImm(0)
|
2010-09-27 21:47:04 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ScratchReg)
|
2010-09-27 21:47:04 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2010-09-27 22:28:11 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
case ARM::tInt_eh_sjlj_longjmp: {
|
|
|
|
// ldr $scratch, [$src, #8]
|
|
|
|
// mov sp, $scratch
|
|
|
|
// ldr $scratch, [$src, #4]
|
|
|
|
// ldr r7, [$src]
|
|
|
|
// bx $scratch
|
|
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ScratchReg = MI->getOperand(1).getReg();
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addReg(SrcReg)
|
2010-09-27 22:28:11 +00:00
|
|
|
// The offset immediate is #8. The operand value is scaled by 4 for the
|
2010-12-14 03:36:38 +00:00
|
|
|
// tLDR instruction.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(2)
|
2010-09-27 22:28:11 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::SP)
|
|
|
|
.addReg(ScratchReg)
|
2010-09-27 22:28:11 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ScratchReg)
|
|
|
|
.addReg(SrcReg)
|
|
|
|
.addImm(1)
|
2010-09-27 22:28:11 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ARM::R7)
|
|
|
|
.addReg(SrcReg)
|
|
|
|
.addImm(0)
|
2010-09-27 22:28:11 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2012-11-26 13:34:22 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
|
2012-11-26 13:34:22 +00:00
|
|
|
.addReg(ScratchReg)
|
2010-09-27 22:28:11 +00:00
|
|
|
// Predicate.
|
2012-11-26 13:34:22 +00:00
|
|
|
.addImm(ARMCC::AL)
|
2012-11-26 18:05:52 +00:00
|
|
|
.addReg(0));
|
2010-09-27 21:47:04 +00:00
|
|
|
return;
|
|
|
|
}
|
2009-10-19 20:20:46 +00:00
|
|
|
}
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-19 20:20:46 +00:00
|
|
|
MCInst TmpInst;
|
2010-11-14 21:00:02 +00:00
|
|
|
LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
|
2011-03-05 18:43:32 +00:00
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
EmitToStreamer(OutStreamer, TmpInst);
|
2009-10-19 20:20:46 +00:00
|
|
|
}
|
2009-10-20 05:15:36 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Target Registry Stuff
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
// Force static initialization.
|
|
|
|
extern "C" void LLVMInitializeARMAsmPrinter() {
|
2014-04-01 15:19:30 +00:00
|
|
|
RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
|
|
|
|
RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
|
|
|
|
RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
|
|
|
|
RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
|
2009-10-20 05:15:36 +00:00
|
|
|
}
|