2005-11-16 22:59:19 +00:00
|
|
|
//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
|
2005-11-16 01:54:32 +00:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2005-11-16 01:54:32 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file defines a DAG pattern matching instruction selector for X86,
|
|
|
|
// converting from a legalized dag to a X86 dag.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2006-08-07 22:28:20 +00:00
|
|
|
#define DEBUG_TYPE "x86-isel"
|
2005-11-16 01:54:32 +00:00
|
|
|
#include "X86.h"
|
2006-01-11 06:09:51 +00:00
|
|
|
#include "X86InstrBuilder.h"
|
2008-01-05 00:41:47 +00:00
|
|
|
#include "X86MachineFunctionInfo.h"
|
2006-01-11 01:15:34 +00:00
|
|
|
#include "X86RegisterInfo.h"
|
2005-11-16 01:54:32 +00:00
|
|
|
#include "X86Subtarget.h"
|
2006-03-13 23:20:37 +00:00
|
|
|
#include "X86TargetMachine.h"
|
2012-12-03 16:50:05 +00:00
|
|
|
#include "llvm/ADT/Statistic.h"
|
2006-01-10 20:26:56 +00:00
|
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
2012-12-03 16:50:05 +00:00
|
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
2006-01-11 01:15:34 +00:00
|
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
2007-12-31 04:13:23 +00:00
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
2005-11-16 01:54:32 +00:00
|
|
|
#include "llvm/CodeGen/SelectionDAGISel.h"
|
2013-01-02 11:36:10 +00:00
|
|
|
#include "llvm/IR/Instructions.h"
|
|
|
|
#include "llvm/IR/Intrinsics.h"
|
|
|
|
#include "llvm/IR/Type.h"
|
2006-09-08 06:48:29 +00:00
|
|
|
#include "llvm/Support/Debug.h"
|
2009-07-08 20:53:28 +00:00
|
|
|
#include "llvm/Support/ErrorHandling.h"
|
2006-09-08 06:48:29 +00:00
|
|
|
#include "llvm/Support/MathExtras.h"
|
2009-07-08 20:53:28 +00:00
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2012-12-03 16:50:05 +00:00
|
|
|
#include "llvm/Target/TargetMachine.h"
|
|
|
|
#include "llvm/Target/TargetOptions.h"
|
2005-11-16 01:54:32 +00:00
|
|
|
using namespace llvm;
|
|
|
|
|
2006-12-19 22:59:26 +00:00
|
|
|
STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Pattern Matcher Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
namespace {
|
|
|
|
/// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
|
2008-07-27 21:46:04 +00:00
|
|
|
/// SDValue's instead of register numbers for the leaves of the matched
|
2005-11-19 02:11:08 +00:00
|
|
|
/// tree.
|
|
|
|
struct X86ISelAddressMode {
|
|
|
|
enum {
|
|
|
|
RegBase,
|
2006-05-24 17:04:05 +00:00
|
|
|
FrameIndexBase
|
2005-11-19 02:11:08 +00:00
|
|
|
} BaseType;
|
|
|
|
|
2010-04-29 23:30:41 +00:00
|
|
|
// This is really a union, discriminated by BaseType!
|
|
|
|
SDValue Base_Reg;
|
|
|
|
int Base_FrameIndex;
|
2005-11-19 02:11:08 +00:00
|
|
|
|
|
|
|
unsigned Scale;
|
2012-08-01 18:39:17 +00:00
|
|
|
SDValue IndexReg;
|
2008-11-11 15:52:29 +00:00
|
|
|
int32_t Disp;
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue Segment;
|
2010-04-15 01:51:59 +00:00
|
|
|
const GlobalValue *GV;
|
|
|
|
const Constant *CP;
|
|
|
|
const BlockAddress *BlockAddr;
|
2006-09-08 06:48:29 +00:00
|
|
|
const char *ES;
|
|
|
|
int JT;
|
2006-02-25 10:09:08 +00:00
|
|
|
unsigned Align; // CP alignment.
|
2009-06-26 05:51:45 +00:00
|
|
|
unsigned char SymbolFlags; // X86II::MO_*
|
2005-11-19 02:11:08 +00:00
|
|
|
|
|
|
|
X86ISelAddressMode()
|
2010-04-29 23:30:41 +00:00
|
|
|
: BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
|
2009-11-01 03:25:03 +00:00
|
|
|
Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
|
2009-08-25 17:47:44 +00:00
|
|
|
SymbolFlags(X86II::MO_NO_FLAG) {
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
2009-02-07 00:43:41 +00:00
|
|
|
|
|
|
|
bool hasSymbolicDisplacement() const {
|
2009-11-01 03:25:03 +00:00
|
|
|
return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
|
2009-02-07 00:43:41 +00:00
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
bool hasBaseOrIndexReg() const {
|
2013-09-19 11:33:53 +00:00
|
|
|
return BaseType == FrameIndexBase ||
|
|
|
|
IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
/// isRIPRelative - Return true if this addressing mode is already RIP
|
|
|
|
/// relative.
|
|
|
|
bool isRIPRelative() const {
|
|
|
|
if (BaseType != RegBase) return false;
|
|
|
|
if (RegisterSDNode *RegNode =
|
2010-04-29 23:30:41 +00:00
|
|
|
dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
return RegNode->getReg() == X86::RIP;
|
|
|
|
return false;
|
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
void setBaseReg(SDValue Reg) {
|
|
|
|
BaseType = RegBase;
|
2010-04-29 23:30:41 +00:00
|
|
|
Base_Reg = Reg;
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
}
|
2009-02-07 00:43:41 +00:00
|
|
|
|
2012-09-11 22:23:19 +00:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2008-08-11 23:46:25 +00:00
|
|
|
void dump() {
|
2010-01-05 01:29:08 +00:00
|
|
|
dbgs() << "X86ISelAddressMode " << this << '\n';
|
2010-04-29 23:30:41 +00:00
|
|
|
dbgs() << "Base_Reg ";
|
|
|
|
if (Base_Reg.getNode() != 0)
|
2012-08-01 18:39:17 +00:00
|
|
|
Base_Reg.getNode()->dump();
|
2009-08-07 21:33:25 +00:00
|
|
|
else
|
2010-01-05 01:29:08 +00:00
|
|
|
dbgs() << "nul";
|
2010-04-29 23:30:41 +00:00
|
|
|
dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
|
2009-08-23 11:52:17 +00:00
|
|
|
<< " Scale" << Scale << '\n'
|
|
|
|
<< "IndexReg ";
|
2009-08-07 21:33:25 +00:00
|
|
|
if (IndexReg.getNode() != 0)
|
|
|
|
IndexReg.getNode()->dump();
|
|
|
|
else
|
2012-08-01 18:39:17 +00:00
|
|
|
dbgs() << "nul";
|
2010-01-05 01:29:08 +00:00
|
|
|
dbgs() << " Disp " << Disp << '\n'
|
2009-08-23 11:52:17 +00:00
|
|
|
<< "GV ";
|
2009-08-07 21:33:25 +00:00
|
|
|
if (GV)
|
|
|
|
GV->dump();
|
|
|
|
else
|
2010-01-05 01:29:08 +00:00
|
|
|
dbgs() << "nul";
|
|
|
|
dbgs() << " CP ";
|
2009-08-07 21:33:25 +00:00
|
|
|
if (CP)
|
|
|
|
CP->dump();
|
|
|
|
else
|
2010-01-05 01:29:08 +00:00
|
|
|
dbgs() << "nul";
|
|
|
|
dbgs() << '\n'
|
2009-08-23 11:52:17 +00:00
|
|
|
<< "ES ";
|
2009-08-07 21:33:25 +00:00
|
|
|
if (ES)
|
2010-01-05 01:29:08 +00:00
|
|
|
dbgs() << ES;
|
2009-08-07 21:33:25 +00:00
|
|
|
else
|
2010-01-05 01:29:08 +00:00
|
|
|
dbgs() << "nul";
|
|
|
|
dbgs() << " JT" << JT << " Align" << Align << '\n';
|
2008-08-11 23:46:25 +00:00
|
|
|
}
|
2012-09-06 19:06:06 +00:00
|
|
|
#endif
|
2005-11-19 02:11:08 +00:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
namespace {
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
/// ISel - X86 specific code to select X86 machine instructions for
|
|
|
|
/// SelectionDAG operations.
|
|
|
|
///
|
2009-10-25 06:33:48 +00:00
|
|
|
class X86DAGToDAGISel : public SelectionDAGISel {
|
2005-11-16 01:54:32 +00:00
|
|
|
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
|
|
|
|
/// make the right decision when generating code for different targets.
|
|
|
|
const X86Subtarget *Subtarget;
|
2006-02-18 00:15:05 +00:00
|
|
|
|
2008-09-26 23:41:32 +00:00
|
|
|
/// OptForSize - If true, selector should try to optimize for code size
|
|
|
|
/// instead of performance.
|
|
|
|
bool OptForSize;
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
public:
|
2009-04-29 23:29:43 +00:00
|
|
|
explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
|
2009-04-29 00:15:41 +00:00
|
|
|
: SelectionDAGISel(tm, OptLevel),
|
2009-06-03 20:20:00 +00:00
|
|
|
Subtarget(&tm.getSubtarget<X86Subtarget>()),
|
2008-10-01 23:18:38 +00:00
|
|
|
OptForSize(false) {}
|
2005-11-16 01:54:32 +00:00
|
|
|
|
|
|
|
virtual const char *getPassName() const {
|
|
|
|
return "X86 DAG->DAG Instruction Selection";
|
|
|
|
}
|
|
|
|
|
2010-04-14 20:17:22 +00:00
|
|
|
virtual void EmitFunctionEntryCode();
|
2007-09-25 21:52:30 +00:00
|
|
|
|
2010-02-15 19:41:07 +00:00
|
|
|
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
|
|
|
|
|
2010-03-02 06:34:30 +00:00
|
|
|
virtual void PreprocessISelDAG();
|
|
|
|
|
2010-09-03 00:35:18 +00:00
|
|
|
inline bool immSext8(SDNode *N) const {
|
|
|
|
return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
|
|
|
|
}
|
|
|
|
|
|
|
|
// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
|
|
|
|
// sign extended field.
|
|
|
|
inline bool i64immSExt32(SDNode *N) const {
|
|
|
|
uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
|
|
|
|
return (int64_t)v == (int32_t)v;
|
|
|
|
}
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
// Include the pieces autogenerated from the target description.
|
|
|
|
#include "X86GenDAGISel.inc"
|
|
|
|
|
|
|
|
private:
|
2010-01-05 01:24:18 +00:00
|
|
|
SDNode *Select(SDNode *N);
|
2012-06-26 19:47:59 +00:00
|
|
|
SDNode *SelectGather(SDNode *N, unsigned Opc);
|
2008-10-02 18:53:47 +00:00
|
|
|
SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
|
2013-08-15 05:57:07 +00:00
|
|
|
SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
|
2005-11-16 01:54:32 +00:00
|
|
|
|
2011-07-13 20:44:23 +00:00
|
|
|
bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
|
2010-09-22 04:39:11 +00:00
|
|
|
bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
|
2009-04-12 21:55:03 +00:00
|
|
|
bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
|
2009-07-22 23:26:55 +00:00
|
|
|
bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
|
|
|
|
bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
|
|
|
|
unsigned Depth);
|
2009-03-31 16:16:57 +00:00
|
|
|
bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
|
2010-09-21 22:07:31 +00:00
|
|
|
bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Scale, SDValue &Index, SDValue &Disp,
|
|
|
|
SDValue &Segment);
|
2013-06-01 09:55:14 +00:00
|
|
|
bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
|
2010-09-21 20:31:19 +00:00
|
|
|
bool SelectLEAAddr(SDValue N, SDValue &Base,
|
2010-07-08 23:46:44 +00:00
|
|
|
SDValue &Scale, SDValue &Index, SDValue &Disp,
|
|
|
|
SDValue &Segment);
|
2013-06-10 20:43:49 +00:00
|
|
|
bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
|
|
|
|
SDValue &Scale, SDValue &Index, SDValue &Disp,
|
|
|
|
SDValue &Segment);
|
2010-09-21 20:31:19 +00:00
|
|
|
bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
|
2010-07-08 23:46:44 +00:00
|
|
|
SDValue &Scale, SDValue &Index, SDValue &Disp,
|
|
|
|
SDValue &Segment);
|
2010-03-01 22:51:11 +00:00
|
|
|
bool SelectScalarSSELoad(SDNode *Root, SDValue N,
|
2010-02-16 22:35:06 +00:00
|
|
|
SDValue &Base, SDValue &Scale,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue &Index, SDValue &Disp,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Segment,
|
2010-02-21 03:17:59 +00:00
|
|
|
SDValue &NodeWithChain);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2010-01-05 01:24:18 +00:00
|
|
|
bool TryFoldLoad(SDNode *P, SDValue N,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue &Base, SDValue &Scale,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Index, SDValue &Disp,
|
|
|
|
SDValue &Segment);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2006-06-08 18:03:49 +00:00
|
|
|
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
|
|
|
|
/// inline asm expressions.
|
2008-07-27 21:46:04 +00:00
|
|
|
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
|
2006-06-08 18:03:49 +00:00
|
|
|
char ConstraintCode,
|
2008-08-23 02:25:05 +00:00
|
|
|
std::vector<SDValue> &OutOps);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2007-09-25 21:52:30 +00:00
|
|
|
void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
|
|
|
|
|
2012-08-01 18:39:17 +00:00
|
|
|
inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue &Scale, SDValue &Index,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Disp, SDValue &Segment) {
|
2005-12-12 21:49:40 +00:00
|
|
|
Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
|
2013-06-19 21:36:55 +00:00
|
|
|
CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
|
|
|
|
getTargetLowering()->getPointerTy()) :
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.Base_Reg;
|
2005-12-17 09:13:43 +00:00
|
|
|
Scale = getI8Imm(AM.Scale);
|
2005-12-12 21:49:40 +00:00
|
|
|
Index = AM.IndexReg;
|
2006-09-08 06:48:29 +00:00
|
|
|
// These are 32-bit even in 64-bit mode since RIP relative offset
|
|
|
|
// is 32-bit.
|
|
|
|
if (AM.GV)
|
2013-05-25 02:42:55 +00:00
|
|
|
Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
|
2010-07-06 22:08:15 +00:00
|
|
|
MVT::i32, AM.Disp,
|
2009-06-26 05:51:45 +00:00
|
|
|
AM.SymbolFlags);
|
2006-09-08 06:48:29 +00:00
|
|
|
else if (AM.CP)
|
2009-08-11 20:47:22 +00:00
|
|
|
Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
|
2009-06-26 05:51:45 +00:00
|
|
|
AM.Align, AM.Disp, AM.SymbolFlags);
|
2012-09-12 21:43:09 +00:00
|
|
|
else if (AM.ES) {
|
|
|
|
assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
|
2009-08-11 20:47:22 +00:00
|
|
|
Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
|
2012-09-12 21:43:09 +00:00
|
|
|
} else if (AM.JT != -1) {
|
|
|
|
assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
|
2009-08-11 20:47:22 +00:00
|
|
|
Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
|
2012-09-12 21:43:09 +00:00
|
|
|
} else if (AM.BlockAddr)
|
|
|
|
Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
|
|
|
|
AM.SymbolFlags);
|
2006-09-08 06:48:29 +00:00
|
|
|
else
|
2009-08-11 20:47:22 +00:00
|
|
|
Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
|
2009-04-08 21:14:34 +00:00
|
|
|
|
|
|
|
if (AM.Segment.getNode())
|
|
|
|
Segment = AM.Segment;
|
|
|
|
else
|
2009-08-11 20:47:22 +00:00
|
|
|
Segment = CurDAG->getRegister(0, MVT::i32);
|
2005-12-12 21:49:40 +00:00
|
|
|
}
|
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
/// getI8Imm - Return a target constant with the specified value, of type
|
|
|
|
/// i8.
|
2008-07-27 21:46:04 +00:00
|
|
|
inline SDValue getI8Imm(unsigned Imm) {
|
2009-08-11 20:47:22 +00:00
|
|
|
return CurDAG->getTargetConstant(Imm, MVT::i8);
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
/// getI32Imm - Return a target constant with the specified value, of type
|
|
|
|
/// i32.
|
2008-07-27 21:46:04 +00:00
|
|
|
inline SDValue getI32Imm(unsigned Imm) {
|
2009-08-11 20:47:22 +00:00
|
|
|
return CurDAG->getTargetConstant(Imm, MVT::i32);
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|
2006-02-10 22:24:32 +00:00
|
|
|
|
2008-09-23 18:22:58 +00:00
|
|
|
/// getGlobalBaseReg - Return an SDNode that returns the value of
|
|
|
|
/// the global base register. Output instructions required to
|
|
|
|
/// initialize the global base register, if necessary.
|
|
|
|
///
|
2006-08-26 05:34:46 +00:00
|
|
|
SDNode *getGlobalBaseReg();
|
2006-02-18 00:15:05 +00:00
|
|
|
|
2009-06-03 20:20:00 +00:00
|
|
|
/// getTargetMachine - Return a reference to the TargetMachine, casted
|
|
|
|
/// to the target-specific type.
|
2013-02-19 21:54:59 +00:00
|
|
|
const X86TargetMachine &getTargetMachine() const {
|
2009-06-03 20:20:00 +00:00
|
|
|
return static_cast<const X86TargetMachine &>(TM);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// getInstrInfo - Return a reference to the TargetInstrInfo, casted
|
|
|
|
/// to the target-specific type.
|
2013-02-19 21:54:59 +00:00
|
|
|
const X86InstrInfo *getInstrInfo() const {
|
2009-06-03 20:20:00 +00:00
|
|
|
return getTargetMachine().getInstrInfo();
|
|
|
|
}
|
2005-11-16 01:54:32 +00:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2006-08-08 00:31:00 +00:00
|
|
|
|
2010-02-15 19:41:07 +00:00
|
|
|
bool
|
|
|
|
X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
|
2009-04-29 23:29:43 +00:00
|
|
|
if (OptLevel == CodeGenOpt::None) return false;
|
2006-10-14 08:33:25 +00:00
|
|
|
|
2010-02-15 19:41:07 +00:00
|
|
|
if (!N.hasOneUse())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (N.getOpcode() != ISD::LOAD)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If N is a load, do additional profitability checks.
|
|
|
|
if (U == Root) {
|
2008-11-27 00:49:46 +00:00
|
|
|
switch (U->getOpcode()) {
|
|
|
|
default: break;
|
2010-01-04 20:51:50 +00:00
|
|
|
case X86ISD::ADD:
|
|
|
|
case X86ISD::SUB:
|
|
|
|
case X86ISD::AND:
|
|
|
|
case X86ISD::XOR:
|
|
|
|
case X86ISD::OR:
|
2008-11-27 00:49:46 +00:00
|
|
|
case ISD::ADD:
|
|
|
|
case ISD::ADDC:
|
|
|
|
case ISD::ADDE:
|
|
|
|
case ISD::AND:
|
|
|
|
case ISD::OR:
|
|
|
|
case ISD::XOR: {
|
2009-04-10 10:09:34 +00:00
|
|
|
SDValue Op1 = U->getOperand(1);
|
|
|
|
|
2008-11-27 00:49:46 +00:00
|
|
|
// If the other operand is a 8-bit immediate we should fold the immediate
|
|
|
|
// instead. This reduces code size.
|
|
|
|
// e.g.
|
|
|
|
// movl 4(%esp), %eax
|
|
|
|
// addl $4, %eax
|
|
|
|
// vs.
|
|
|
|
// movl $4, %eax
|
|
|
|
// addl 4(%esp), %eax
|
|
|
|
// The former is 2 bytes shorter. In case where the increment is 1, then
|
|
|
|
// the saving can be 4 bytes (by using incl %eax).
|
2009-04-10 10:09:34 +00:00
|
|
|
if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
|
2009-03-14 02:07:16 +00:00
|
|
|
if (Imm->getAPIntValue().isSignedIntN(8))
|
|
|
|
return false;
|
2009-04-10 10:09:34 +00:00
|
|
|
|
|
|
|
// If the other operand is a TLS address, we should fold it instead.
|
|
|
|
// This produces
|
|
|
|
// movl %gs:0, %eax
|
|
|
|
// leal i@NTPOFF(%eax), %eax
|
|
|
|
// instead of
|
|
|
|
// movl $i@NTPOFF, %eax
|
|
|
|
// addl %gs:0, %eax
|
|
|
|
// if the block also has an access to a second TLS address this will save
|
|
|
|
// a load.
|
2013-12-05 05:44:44 +00:00
|
|
|
// FIXME: This is probably also true for non-TLS addresses.
|
2009-04-10 10:09:34 +00:00
|
|
|
if (Op1.getOpcode() == X86ISD::Wrapper) {
|
|
|
|
SDValue Val = Op1.getOperand(0);
|
|
|
|
if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
|
|
|
|
return false;
|
|
|
|
}
|
2008-11-27 00:49:46 +00:00
|
|
|
}
|
|
|
|
}
|
2010-02-15 19:41:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-03-14 03:48:46 +00:00
|
|
|
/// MoveBelowCallOrigChain - Replace the original chain operand of the call with
|
|
|
|
/// load's chain operand and move load below the call's chain operand.
|
|
|
|
static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
|
2012-10-02 23:49:13 +00:00
|
|
|
SDValue Call, SDValue OrigChain) {
|
2008-08-25 21:27:18 +00:00
|
|
|
SmallVector<SDValue, 8> Ops;
|
2010-03-14 03:48:46 +00:00
|
|
|
SDValue Chain = OrigChain.getOperand(0);
|
2009-01-26 18:43:34 +00:00
|
|
|
if (Chain.getNode() == Load.getNode())
|
|
|
|
Ops.push_back(Load.getOperand(0));
|
|
|
|
else {
|
|
|
|
assert(Chain.getOpcode() == ISD::TokenFactor &&
|
2010-03-14 03:48:46 +00:00
|
|
|
"Unexpected chain operand");
|
2009-01-26 18:43:34 +00:00
|
|
|
for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
|
|
|
|
if (Chain.getOperand(i).getNode() == Load.getNode())
|
|
|
|
Ops.push_back(Load.getOperand(0));
|
|
|
|
else
|
|
|
|
Ops.push_back(Chain.getOperand(i));
|
|
|
|
SDValue NewChain =
|
2013-05-25 02:42:55 +00:00
|
|
|
CurDAG->getNode(ISD::TokenFactor, SDLoc(Load),
|
2009-08-11 20:47:22 +00:00
|
|
|
MVT::Other, &Ops[0], Ops.size());
|
2009-01-26 18:43:34 +00:00
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(NewChain);
|
|
|
|
}
|
2010-03-14 03:48:46 +00:00
|
|
|
for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
|
|
|
|
Ops.push_back(OrigChain.getOperand(i));
|
2010-06-18 15:30:29 +00:00
|
|
|
CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
|
|
|
|
CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
|
2008-08-25 21:27:18 +00:00
|
|
|
Load.getOperand(1), Load.getOperand(2));
|
2012-10-02 23:49:13 +00:00
|
|
|
|
|
|
|
unsigned NumOps = Call.getNode()->getNumOperands();
|
2008-08-25 21:27:18 +00:00
|
|
|
Ops.clear();
|
2008-08-28 21:40:38 +00:00
|
|
|
Ops.push_back(SDValue(Load.getNode(), 1));
|
2012-10-02 23:49:13 +00:00
|
|
|
for (unsigned i = 1, e = NumOps; i != e; ++i)
|
2008-08-25 21:27:18 +00:00
|
|
|
Ops.push_back(Call.getOperand(i));
|
2012-10-05 01:48:22 +00:00
|
|
|
CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], NumOps);
|
2008-08-25 21:27:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// isCalleeLoad - Return true if call address is a load and it can be
|
|
|
|
/// moved below CALLSEQ_START and the chains leading up to the call.
|
|
|
|
/// Return the CALLSEQ_START by reference as a second output.
|
2010-03-14 03:48:46 +00:00
|
|
|
/// In the case of a tail call, there isn't a callseq node between the call
|
|
|
|
/// chain and the load.
|
|
|
|
static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
|
2012-10-05 01:48:22 +00:00
|
|
|
// The transformation is somewhat dangerous if the call's chain was glued to
|
|
|
|
// the call. After MoveBelowOrigChain the load is moved between the call and
|
|
|
|
// the chain, this can create a cycle if the load is not folded. So it is
|
|
|
|
// *really* important that we are sure the load will be folded.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
|
2008-08-25 21:27:18 +00:00
|
|
|
return false;
|
2008-08-28 21:40:38 +00:00
|
|
|
LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
|
2008-08-25 21:27:18 +00:00
|
|
|
if (!LD ||
|
|
|
|
LD->isVolatile() ||
|
|
|
|
LD->getAddressingMode() != ISD::UNINDEXED ||
|
|
|
|
LD->getExtensionType() != ISD::NON_EXTLOAD)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Now let's find the callseq_start.
|
2010-03-14 03:48:46 +00:00
|
|
|
while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
|
2008-08-25 21:27:18 +00:00
|
|
|
if (!Chain.hasOneUse())
|
|
|
|
return false;
|
|
|
|
Chain = Chain.getOperand(0);
|
|
|
|
}
|
2010-03-14 03:48:46 +00:00
|
|
|
|
|
|
|
if (!Chain.getNumOperands())
|
|
|
|
return false;
|
2013-01-06 19:00:15 +00:00
|
|
|
// Since we are not checking for AA here, conservatively abort if the chain
|
|
|
|
// writes to memory. It's not safe to move the callee (a load) across a store.
|
|
|
|
if (isa<MemSDNode>(Chain.getNode()) &&
|
|
|
|
cast<MemSDNode>(Chain.getNode())->writeMem())
|
|
|
|
return false;
|
2009-01-26 18:43:34 +00:00
|
|
|
if (Chain.getOperand(0).getNode() == Callee.getNode())
|
|
|
|
return true;
|
|
|
|
if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
|
2009-09-15 01:22:01 +00:00
|
|
|
Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
|
|
|
|
Callee.getValue(1).hasOneUse())
|
2009-01-26 18:43:34 +00:00
|
|
|
return true;
|
|
|
|
return false;
|
2008-08-25 21:27:18 +00:00
|
|
|
}
|
|
|
|
|
2010-03-02 23:12:51 +00:00
|
|
|
void X86DAGToDAGISel::PreprocessISelDAG() {
|
2010-03-04 01:43:43 +00:00
|
|
|
// OptForSize is used in pattern predicates that isel is matching.
|
2012-12-30 10:32:01 +00:00
|
|
|
OptForSize = MF->getFunction()->getAttributes().
|
|
|
|
hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2008-08-23 02:25:05 +00:00
|
|
|
for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
|
|
|
|
E = CurDAG->allnodes_end(); I != E; ) {
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
|
2010-03-02 23:12:51 +00:00
|
|
|
|
2010-03-14 03:48:46 +00:00
|
|
|
if (OptLevel != CodeGenOpt::None &&
|
2013-03-28 23:13:21 +00:00
|
|
|
// Only does this when target favors doesn't favor register indirect
|
|
|
|
// call.
|
|
|
|
((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
|
2012-10-05 01:48:22 +00:00
|
|
|
(N->getOpcode() == X86ISD::TC_RETURN &&
|
2013-01-13 19:03:55 +00:00
|
|
|
// Only does this if load can be folded into TC_RETURN.
|
2012-10-05 01:48:22 +00:00
|
|
|
(Subtarget->is64Bit() ||
|
|
|
|
getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
|
2010-03-02 23:12:51 +00:00
|
|
|
/// Also try moving call address load from outside callseq_start to just
|
|
|
|
/// before the call to allow it to be folded.
|
|
|
|
///
|
|
|
|
/// [Load chain]
|
|
|
|
/// ^
|
|
|
|
/// |
|
|
|
|
/// [Load]
|
|
|
|
/// ^ ^
|
|
|
|
/// | |
|
|
|
|
/// / \--
|
|
|
|
/// / |
|
|
|
|
///[CALLSEQ_START] |
|
|
|
|
/// ^ |
|
|
|
|
/// | |
|
|
|
|
/// [LOAD/C2Reg] |
|
|
|
|
/// | |
|
|
|
|
/// \ /
|
|
|
|
/// \ /
|
|
|
|
/// [CALL]
|
2010-03-14 03:48:46 +00:00
|
|
|
bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
|
2010-03-02 23:12:51 +00:00
|
|
|
SDValue Chain = N->getOperand(0);
|
|
|
|
SDValue Load = N->getOperand(1);
|
2010-03-14 03:48:46 +00:00
|
|
|
if (!isCalleeLoad(Load, Chain, HasCallSeq))
|
2010-03-02 23:12:51 +00:00
|
|
|
continue;
|
2010-03-14 03:48:46 +00:00
|
|
|
MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
|
2010-03-02 23:12:51 +00:00
|
|
|
++NumLoadMoved;
|
|
|
|
continue;
|
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2010-03-02 23:12:51 +00:00
|
|
|
// Lower fpround and fpextend nodes that target the FP stack to be store and
|
|
|
|
// load to the stack. This is a gross hack. We would like to simply mark
|
|
|
|
// these as being illegal, but when we do that, legalize produces these when
|
|
|
|
// it expands calls, then expands these in the same legalize pass. We would
|
|
|
|
// like dag combine to be able to hack on these between the call expansion
|
|
|
|
// and the node legalization. As such this pass basically does "really
|
|
|
|
// late" legalization of these inline with the X86 isel pass.
|
|
|
|
// FIXME: This should only happen when not compiled with -O0.
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
|
|
|
|
continue;
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2013-08-15 05:57:07 +00:00
|
|
|
MVT SrcVT = N->getOperand(0).getSimpleValueType();
|
|
|
|
MVT DstVT = N->getSimpleValueType(0);
|
2011-08-01 21:54:05 +00:00
|
|
|
|
|
|
|
// If any of the sources are vectors, no fp stack involved.
|
|
|
|
if (SrcVT.isVector() || DstVT.isVector())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// If the source and destination are SSE registers, then this is a legal
|
|
|
|
// conversion that should not be lowered.
|
2013-06-27 11:07:42 +00:00
|
|
|
const X86TargetLowering *X86Lowering =
|
|
|
|
static_cast<const X86TargetLowering *>(getTargetLowering());
|
2013-06-19 21:36:55 +00:00
|
|
|
bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
|
|
|
|
bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
if (SrcIsSSE && DstIsSSE)
|
|
|
|
continue;
|
|
|
|
|
2008-03-09 07:05:32 +00:00
|
|
|
if (!SrcIsSSE && !DstIsSSE) {
|
|
|
|
// If this is an FPStack extension, it is a noop.
|
|
|
|
if (N->getOpcode() == ISD::FP_EXTEND)
|
|
|
|
continue;
|
|
|
|
// If this is a value-preserving FPStack truncation, it is a noop.
|
|
|
|
if (N->getConstantOperandVal(1))
|
|
|
|
continue;
|
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
// Here we could have an FP stack truncation or an FPStack <-> SSE convert.
|
|
|
|
// FPStack has extload and truncstore. SSE can fold direct loads into other
|
|
|
|
// operations. Based on this, decide what we want to do.
|
2013-08-15 05:57:07 +00:00
|
|
|
MVT MemVT;
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
if (N->getOpcode() == ISD::FP_ROUND)
|
|
|
|
MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
|
|
|
|
else
|
|
|
|
MemVT = SrcIsSSE ? SrcVT : DstVT;
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2008-08-23 02:25:05 +00:00
|
|
|
SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc dl(N);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
// FIXME: optimize the case where the src/dest is a load or store?
|
2009-02-03 21:48:12 +00:00
|
|
|
SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
|
2008-08-23 02:25:05 +00:00
|
|
|
N->getOperand(0),
|
2010-09-21 17:04:51 +00:00
|
|
|
MemTmp, MachinePointerInfo(), MemVT,
|
2010-02-15 16:57:43 +00:00
|
|
|
false, false, 0);
|
2011-02-16 16:23:55 +00:00
|
|
|
SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
|
2010-09-21 17:04:51 +00:00
|
|
|
MachinePointerInfo(),
|
|
|
|
MemVT, false, false, 0);
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
|
|
|
|
// We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
|
|
|
|
// extload we created. This will cause general havok on the dag because
|
|
|
|
// anything below the conversion could be folded into other existing nodes.
|
|
|
|
// To avoid invalidating 'I', back it up to the convert node.
|
|
|
|
--I;
|
2008-08-23 02:25:05 +00:00
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
// Now that we did that, the node is dead. Increment the iterator to the
|
|
|
|
// next node to process, then delete N.
|
|
|
|
++I;
|
2008-08-23 02:25:05 +00:00
|
|
|
CurDAG->DeleteNode(N);
|
2012-08-01 18:39:17 +00:00
|
|
|
}
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
}
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
|
2007-09-25 21:52:30 +00:00
|
|
|
/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
|
|
|
|
/// the main function.
|
|
|
|
void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
|
|
|
|
MachineFrameInfo *MFI) {
|
|
|
|
const TargetInstrInfo *TII = TM.getInstrInfo();
|
2011-01-06 00:47:10 +00:00
|
|
|
if (Subtarget->isTargetCygMing()) {
|
|
|
|
unsigned CallOp =
|
2012-02-16 17:56:02 +00:00
|
|
|
Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
|
2010-04-02 20:16:16 +00:00
|
|
|
BuildMI(BB, DebugLoc(),
|
2011-01-06 00:47:10 +00:00
|
|
|
TII->get(CallOp)).addExternalSymbol("__main");
|
|
|
|
}
|
2007-09-25 21:52:30 +00:00
|
|
|
}
|
|
|
|
|
2010-04-14 20:17:22 +00:00
|
|
|
void X86DAGToDAGISel::EmitFunctionEntryCode() {
|
2007-09-25 21:52:30 +00:00
|
|
|
// If this is main, emit special code for main.
|
2010-04-14 20:17:22 +00:00
|
|
|
if (const Function *Fn = MF->getFunction())
|
|
|
|
if (Fn->hasExternalLinkage() && Fn->getName() == "main")
|
|
|
|
EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
|
2007-09-25 21:52:30 +00:00
|
|
|
}
|
|
|
|
|
2011-07-13 21:29:53 +00:00
|
|
|
static bool isDispSafeForFrameIndex(int64_t Val) {
|
|
|
|
// On 64-bit platforms, we can run into an issue where a frame index
|
|
|
|
// includes a displacement that, when added to the explicit displacement,
|
|
|
|
// will overflow the displacement field. Assuming that the frame index
|
|
|
|
// displacement fits into a 31-bit integer (which is only slightly more
|
|
|
|
// aggressive than the current fundamental assumption that it fits into
|
|
|
|
// a 32-bit integer), a 31-bit disp should always be safe.
|
|
|
|
return isInt<31>(Val);
|
|
|
|
}
|
|
|
|
|
2011-07-13 20:44:23 +00:00
|
|
|
bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
|
|
|
|
X86ISelAddressMode &AM) {
|
|
|
|
int64_t Val = AM.Disp + Offset;
|
|
|
|
CodeModel::Model M = TM.getCodeModel();
|
2011-07-13 21:29:53 +00:00
|
|
|
if (Subtarget->is64Bit()) {
|
|
|
|
if (!X86::isOffsetSuitableForCodeModel(Val, M,
|
|
|
|
AM.hasSymbolicDisplacement()))
|
|
|
|
return true;
|
|
|
|
// In addition to the checks required for a register base, check that
|
|
|
|
// we do not try to use an unsafe Disp with a frame index.
|
|
|
|
if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
|
|
|
|
!isDispSafeForFrameIndex(Val))
|
|
|
|
return true;
|
2011-07-13 20:44:23 +00:00
|
|
|
}
|
2011-07-13 21:29:53 +00:00
|
|
|
AM.Disp = Val;
|
|
|
|
return false;
|
|
|
|
|
2011-07-13 20:44:23 +00:00
|
|
|
}
|
2009-04-08 21:14:34 +00:00
|
|
|
|
2010-09-22 04:39:11 +00:00
|
|
|
bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
|
|
|
|
SDValue Address = N->getOperand(1);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2010-09-22 04:39:11 +00:00
|
|
|
// load gs:0 -> GS segment register.
|
|
|
|
// load fs:0 -> FS segment register.
|
|
|
|
//
|
2009-04-08 21:14:34 +00:00
|
|
|
// This optimization is valid because the GNU TLS model defines that
|
|
|
|
// gs:0 (or fs:0 on X86-64) contains its own address.
|
|
|
|
// For more information see http://people.redhat.com/drepper/tls.pdf
|
2010-09-22 04:39:11 +00:00
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
|
|
|
|
if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 &&
|
2012-07-24 20:04:16 +00:00
|
|
|
Subtarget->isTargetLinux())
|
2010-09-22 04:39:11 +00:00
|
|
|
switch (N->getPointerInfo().getAddrSpace()) {
|
|
|
|
case 256:
|
|
|
|
AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
|
|
|
|
return false;
|
|
|
|
case 257:
|
|
|
|
AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
|
|
|
|
return false;
|
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
/// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
|
|
|
|
/// into an addressing mode. These wrap things that will resolve down into a
|
|
|
|
/// symbol reference. If no match is possible, this returns true, otherwise it
|
2009-08-05 23:01:26 +00:00
|
|
|
/// returns false.
|
2009-04-12 21:55:03 +00:00
|
|
|
bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
// If the addressing mode already has a symbol as the displacement, we can
|
|
|
|
// never match another symbol.
|
2009-04-12 21:55:03 +00:00
|
|
|
if (AM.hasSymbolicDisplacement())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
SDValue N0 = N.getOperand(0);
|
2009-08-05 23:01:26 +00:00
|
|
|
CodeModel::Model M = TM.getCodeModel();
|
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
// Handle X86-64 rip-relative addresses. We check this before checking direct
|
|
|
|
// folding because RIP is preferable to non-RIP accesses.
|
Cleanup and relax a restriction on the matching of global offsets into
x86 addressing modes. This allows PIE-based TLS offsets to fit directly
into an addressing mode immediate offset, which is the last remaining
code quality issue from PR12380. With this patch, that PR is completely
fixed.
To understand why this patch is correct to match these offsets into
addressing mode immediates, break it down by cases:
1) 32-bit is trivially correct, and unmodified here.
2) 64-bit non-small mode is unchanged and never matches.
3) 64-bit small PIC code which is RIP-relative is handled specially in
the match to try to fit RIP into the base register. If it fails, it
now early exits. This behavior is unchanged by the patch.
4) 64-bit small non-PIC code which is not RIP-relative continues to work
as it did before. The reason these immediates are safe is because the
ABI ensures they fit in small mode. This behavior is unchanged.
5) 64-bit small PIC code which is *not* using RIP-relative addressing.
This is the only case changed by the patch, and the primary place you
see it is in TLS, either the win64 section offset TLS or Linux
local-exec TLS model in a PIC compilation. Here the ABI again ensures
that the immediates fit because we are in small mode, and any other
operations required due to the PIC relocation model have been handled
externally to the Wrapper node (extra loads etc are made around the
wrapper node in ISelLowering).
I've tested this as much as I can comparing it with GCC's output, and
everything appears safe. I discussed this with Anton and it made sense
to him at least at face value. That said, if there are issues with PIC
code after this patch, yell and we can revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09 02:13:06 +00:00
|
|
|
if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
// Under X86-64 non-small code model, GV (and friends) are 64-bits, so
|
|
|
|
// they cannot be folded into immediate fields.
|
|
|
|
// FIXME: This can be improved for kernel and other models?
|
Cleanup and relax a restriction on the matching of global offsets into
x86 addressing modes. This allows PIE-based TLS offsets to fit directly
into an addressing mode immediate offset, which is the last remaining
code quality issue from PR12380. With this patch, that PR is completely
fixed.
To understand why this patch is correct to match these offsets into
addressing mode immediates, break it down by cases:
1) 32-bit is trivially correct, and unmodified here.
2) 64-bit non-small mode is unchanged and never matches.
3) 64-bit small PIC code which is RIP-relative is handled specially in
the match to try to fit RIP into the base register. If it fails, it
now early exits. This behavior is unchanged by the patch.
4) 64-bit small non-PIC code which is not RIP-relative continues to work
as it did before. The reason these immediates are safe is because the
ABI ensures they fit in small mode. This behavior is unchanged.
5) 64-bit small PIC code which is *not* using RIP-relative addressing.
This is the only case changed by the patch, and the primary place you
see it is in TLS, either the win64 section offset TLS or Linux
local-exec TLS model in a PIC compilation. Here the ABI again ensures
that the immediates fit because we are in small mode, and any other
operations required due to the PIC relocation model have been handled
externally to the Wrapper node (extra loads etc are made around the
wrapper node in ISelLowering).
I've tested this as much as I can comparing it with GCC's output, and
everything appears safe. I discussed this with Anton and it made sense
to him at least at face value. That said, if there are issues with PIC
code after this patch, yell and we can revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09 02:13:06 +00:00
|
|
|
(M == CodeModel::Small || M == CodeModel::Kernel)) {
|
|
|
|
// Base and index reg must be 0 in order to use %rip as base.
|
|
|
|
if (AM.hasBaseOrIndexReg())
|
|
|
|
return true;
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
|
2011-07-13 20:44:23 +00:00
|
|
|
X86ISelAddressMode Backup = AM;
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
AM.GV = G->getGlobal();
|
2009-06-26 05:51:45 +00:00
|
|
|
AM.SymbolFlags = G->getTargetFlags();
|
2011-07-13 20:44:23 +00:00
|
|
|
if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
|
|
|
|
AM = Backup;
|
|
|
|
return true;
|
|
|
|
}
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
|
2011-07-13 20:44:23 +00:00
|
|
|
X86ISelAddressMode Backup = AM;
|
2009-04-12 21:55:03 +00:00
|
|
|
AM.CP = CP->getConstVal();
|
|
|
|
AM.Align = CP->getAlignment();
|
2009-06-26 05:56:49 +00:00
|
|
|
AM.SymbolFlags = CP->getTargetFlags();
|
2011-07-13 20:44:23 +00:00
|
|
|
if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
|
|
|
|
AM = Backup;
|
|
|
|
return true;
|
|
|
|
}
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
|
|
|
|
AM.ES = S->getSymbol();
|
|
|
|
AM.SymbolFlags = S->getTargetFlags();
|
2009-11-01 03:25:03 +00:00
|
|
|
} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
AM.JT = J->getIndex();
|
|
|
|
AM.SymbolFlags = J->getTargetFlags();
|
2012-09-12 21:43:09 +00:00
|
|
|
} else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
|
|
|
|
X86ISelAddressMode Backup = AM;
|
|
|
|
AM.BlockAddr = BA->getBlockAddress();
|
|
|
|
AM.SymbolFlags = BA->getTargetFlags();
|
|
|
|
if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
|
|
|
|
AM = Backup;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
llvm_unreachable("Unhandled symbol reference node.");
|
2009-08-05 23:01:26 +00:00
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (N.getOpcode() == X86ISD::WrapperRIP)
|
2009-08-11 20:47:22 +00:00
|
|
|
AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
|
2009-04-12 21:55:03 +00:00
|
|
|
return false;
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Handle the case when globals fit in our immediate field: This is true for
|
Cleanup and relax a restriction on the matching of global offsets into
x86 addressing modes. This allows PIE-based TLS offsets to fit directly
into an addressing mode immediate offset, which is the last remaining
code quality issue from PR12380. With this patch, that PR is completely
fixed.
To understand why this patch is correct to match these offsets into
addressing mode immediates, break it down by cases:
1) 32-bit is trivially correct, and unmodified here.
2) 64-bit non-small mode is unchanged and never matches.
3) 64-bit small PIC code which is RIP-relative is handled specially in
the match to try to fit RIP into the base register. If it fails, it
now early exits. This behavior is unchanged by the patch.
4) 64-bit small non-PIC code which is not RIP-relative continues to work
as it did before. The reason these immediates are safe is because the
ABI ensures they fit in small mode. This behavior is unchanged.
5) 64-bit small PIC code which is *not* using RIP-relative addressing.
This is the only case changed by the patch, and the primary place you
see it is in TLS, either the win64 section offset TLS or Linux
local-exec TLS model in a PIC compilation. Here the ABI again ensures
that the immediates fit because we are in small mode, and any other
operations required due to the PIC relocation model have been handled
externally to the Wrapper node (extra loads etc are made around the
wrapper node in ISelLowering).
I've tested this as much as I can comparing it with GCC's output, and
everything appears safe. I discussed this with Anton and it made sense
to him at least at face value. That said, if there are issues with PIC
code after this patch, yell and we can revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09 02:13:06 +00:00
|
|
|
// X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
|
|
|
|
// mode, this only applies to a non-RIP-relative computation.
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (!Subtarget->is64Bit() ||
|
Cleanup and relax a restriction on the matching of global offsets into
x86 addressing modes. This allows PIE-based TLS offsets to fit directly
into an addressing mode immediate offset, which is the last remaining
code quality issue from PR12380. With this patch, that PR is completely
fixed.
To understand why this patch is correct to match these offsets into
addressing mode immediates, break it down by cases:
1) 32-bit is trivially correct, and unmodified here.
2) 64-bit non-small mode is unchanged and never matches.
3) 64-bit small PIC code which is RIP-relative is handled specially in
the match to try to fit RIP into the base register. If it fails, it
now early exits. This behavior is unchanged by the patch.
4) 64-bit small non-PIC code which is not RIP-relative continues to work
as it did before. The reason these immediates are safe is because the
ABI ensures they fit in small mode. This behavior is unchanged.
5) 64-bit small PIC code which is *not* using RIP-relative addressing.
This is the only case changed by the patch, and the primary place you
see it is in TLS, either the win64 section offset TLS or Linux
local-exec TLS model in a PIC compilation. Here the ABI again ensures
that the immediates fit because we are in small mode, and any other
operations required due to the PIC relocation model have been handled
externally to the Wrapper node (extra loads etc are made around the
wrapper node in ISelLowering).
I've tested this as much as I can comparing it with GCC's output, and
everything appears safe. I discussed this with Anton and it made sense
to him at least at face value. That said, if there are issues with PIC
code after this patch, yell and we can revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09 02:13:06 +00:00
|
|
|
M == CodeModel::Small || M == CodeModel::Kernel) {
|
|
|
|
assert(N.getOpcode() != X86ISD::WrapperRIP &&
|
|
|
|
"RIP-relative addressing already handled");
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
|
|
|
|
AM.GV = G->getGlobal();
|
|
|
|
AM.Disp += G->getOffset();
|
|
|
|
AM.SymbolFlags = G->getTargetFlags();
|
|
|
|
} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
|
|
|
|
AM.CP = CP->getConstVal();
|
|
|
|
AM.Align = CP->getAlignment();
|
|
|
|
AM.Disp += CP->getOffset();
|
|
|
|
AM.SymbolFlags = CP->getTargetFlags();
|
|
|
|
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
|
|
|
|
AM.ES = S->getSymbol();
|
|
|
|
AM.SymbolFlags = S->getTargetFlags();
|
2009-11-01 03:25:03 +00:00
|
|
|
} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
AM.JT = J->getIndex();
|
|
|
|
AM.SymbolFlags = J->getTargetFlags();
|
2012-09-12 21:43:09 +00:00
|
|
|
} else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
|
|
|
|
AM.BlockAddr = BA->getBlockAddress();
|
|
|
|
AM.Disp += BA->getOffset();
|
|
|
|
AM.SymbolFlags = BA->getTargetFlags();
|
|
|
|
} else
|
|
|
|
llvm_unreachable("Unhandled symbol reference node.");
|
2009-04-12 21:55:03 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
/// MatchAddress - Add the specified node to the specified addressing mode,
|
|
|
|
/// returning true if it cannot be done. This just pattern matches for the
|
2007-12-08 07:22:58 +00:00
|
|
|
/// addressing mode.
|
2009-07-22 23:26:55 +00:00
|
|
|
bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
|
2010-06-18 01:24:29 +00:00
|
|
|
if (MatchAddressRecursively(N, AM, 0))
|
2009-07-22 23:26:55 +00:00
|
|
|
return true;
|
|
|
|
|
|
|
|
// Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
|
|
|
|
// a smaller encoding and avoids a scaled-index.
|
|
|
|
if (AM.Scale == 2 &&
|
|
|
|
AM.BaseType == X86ISelAddressMode::RegBase &&
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.Base_Reg.getNode() == 0) {
|
|
|
|
AM.Base_Reg = AM.IndexReg;
|
2009-07-22 23:26:55 +00:00
|
|
|
AM.Scale = 1;
|
|
|
|
}
|
|
|
|
|
2009-08-20 18:23:44 +00:00
|
|
|
// Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
|
|
|
|
// because it has a smaller encoding.
|
|
|
|
// TODO: Which other code models can use this?
|
|
|
|
if (TM.getCodeModel() == CodeModel::Small &&
|
|
|
|
Subtarget->is64Bit() &&
|
|
|
|
AM.Scale == 1 &&
|
|
|
|
AM.BaseType == X86ISelAddressMode::RegBase &&
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.Base_Reg.getNode() == 0 &&
|
2009-08-20 18:23:44 +00:00
|
|
|
AM.IndexReg.getNode() == 0 &&
|
2009-08-25 17:47:44 +00:00
|
|
|
AM.SymbolFlags == X86II::MO_NO_FLAG &&
|
2009-08-20 18:23:44 +00:00
|
|
|
AM.hasSymbolicDisplacement())
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
|
2009-08-20 18:23:44 +00:00
|
|
|
|
2009-07-22 23:26:55 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-01-11 11:04:36 +00:00
|
|
|
// Insert a node into the DAG at least before the Pos node's position. This
|
|
|
|
// will reposition the node as needed, and will assign it a node ID that is <=
|
|
|
|
// the Pos node's ID. Note that this does *not* preserve the uniqueness of node
|
|
|
|
// IDs! The selection DAG must no longer depend on their uniqueness when this
|
|
|
|
// is used.
|
|
|
|
static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
|
|
|
|
if (N.getNode()->getNodeId() == -1 ||
|
|
|
|
N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
|
|
|
|
DAG.RepositionNode(Pos.getNode(), N.getNode());
|
|
|
|
N.getNode()->setNodeId(Pos.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-01-11 08:48:20 +00:00
|
|
|
// Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This
|
|
|
|
// allows us to convert the shift and and into an h-register extract and
|
|
|
|
// a scaled index. Returns false if the simplification is performed.
|
|
|
|
static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
|
|
|
|
uint64_t Mask,
|
|
|
|
SDValue Shift, SDValue X,
|
|
|
|
X86ISelAddressMode &AM) {
|
|
|
|
if (Shift.getOpcode() != ISD::SRL ||
|
|
|
|
!isa<ConstantSDNode>(Shift.getOperand(1)) ||
|
|
|
|
!Shift.hasOneUse())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
int ScaleLog = 8 - Shift.getConstantOperandVal(1);
|
|
|
|
if (ScaleLog <= 0 || ScaleLog >= 4 ||
|
|
|
|
Mask != (0xffu << ScaleLog))
|
|
|
|
return true;
|
|
|
|
|
2013-08-15 05:57:07 +00:00
|
|
|
MVT VT = N.getSimpleValueType();
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(N);
|
2012-01-11 08:48:20 +00:00
|
|
|
SDValue Eight = DAG.getConstant(8, MVT::i8);
|
|
|
|
SDValue NewMask = DAG.getConstant(0xff, VT);
|
|
|
|
SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
|
|
|
|
SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
|
|
|
|
SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
|
|
|
|
SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
|
|
|
|
|
2012-01-12 01:34:44 +00:00
|
|
|
// Insert the new nodes into the topological ordering. We must do this in
|
|
|
|
// a valid topological ordering as nothing is going to go back and re-sort
|
|
|
|
// these nodes. We continually insert before 'N' in sequence as this is
|
|
|
|
// essentially a pre-flattened and pre-sorted sequence of nodes. There is no
|
|
|
|
// hierarchy left to express.
|
|
|
|
InsertDAGNode(DAG, N, Eight);
|
|
|
|
InsertDAGNode(DAG, N, Srl);
|
|
|
|
InsertDAGNode(DAG, N, NewMask);
|
2012-01-11 11:04:36 +00:00
|
|
|
InsertDAGNode(DAG, N, And);
|
2012-01-12 01:34:44 +00:00
|
|
|
InsertDAGNode(DAG, N, ShlCount);
|
2012-01-11 11:04:36 +00:00
|
|
|
InsertDAGNode(DAG, N, Shl);
|
2012-01-11 08:48:20 +00:00
|
|
|
DAG.ReplaceAllUsesWith(N, Shl);
|
|
|
|
AM.IndexReg = And;
|
|
|
|
AM.Scale = (1 << ScaleLog);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-01-11 09:35:00 +00:00
|
|
|
// Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
|
|
|
|
// allows us to fold the shift into this addressing mode. Returns false if the
|
|
|
|
// transform succeeded.
|
|
|
|
static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
|
|
|
|
uint64_t Mask,
|
|
|
|
SDValue Shift, SDValue X,
|
|
|
|
X86ISelAddressMode &AM) {
|
|
|
|
if (Shift.getOpcode() != ISD::SHL ||
|
|
|
|
!isa<ConstantSDNode>(Shift.getOperand(1)))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Not likely to be profitable if either the AND or SHIFT node has more
|
|
|
|
// than one use (unless all uses are for address computation). Besides,
|
|
|
|
// isel mechanism requires their node ids to be reused.
|
|
|
|
if (!N.hasOneUse() || !Shift.hasOneUse())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Verify that the shift amount is something we can fold.
|
|
|
|
unsigned ShiftAmt = Shift.getConstantOperandVal(1);
|
|
|
|
if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
|
|
|
|
return true;
|
|
|
|
|
2013-08-15 05:57:07 +00:00
|
|
|
MVT VT = N.getSimpleValueType();
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(N);
|
2012-01-11 09:35:00 +00:00
|
|
|
SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
|
|
|
|
SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
|
|
|
|
SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
|
|
|
|
|
2012-01-12 01:34:44 +00:00
|
|
|
// Insert the new nodes into the topological ordering. We must do this in
|
|
|
|
// a valid topological ordering as nothing is going to go back and re-sort
|
|
|
|
// these nodes. We continually insert before 'N' in sequence as this is
|
|
|
|
// essentially a pre-flattened and pre-sorted sequence of nodes. There is no
|
|
|
|
// hierarchy left to express.
|
|
|
|
InsertDAGNode(DAG, N, NewMask);
|
|
|
|
InsertDAGNode(DAG, N, NewAnd);
|
2012-01-11 11:04:36 +00:00
|
|
|
InsertDAGNode(DAG, N, NewShift);
|
2012-01-11 09:35:00 +00:00
|
|
|
DAG.ReplaceAllUsesWith(N, NewShift);
|
|
|
|
|
|
|
|
AM.Scale = 1 << ShiftAmt;
|
|
|
|
AM.IndexReg = NewAnd;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-01-11 08:41:08 +00:00
|
|
|
// Implement some heroics to detect shifts of masked values where the mask can
|
|
|
|
// be replaced by extending the shift and undoing that in the addressing mode
|
|
|
|
// scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
|
|
|
|
// (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
|
|
|
|
// the addressing mode. This results in code such as:
|
|
|
|
//
|
|
|
|
// int f(short *y, int *lookup_table) {
|
|
|
|
// ...
|
|
|
|
// return *y + lookup_table[*y >> 11];
|
|
|
|
// }
|
|
|
|
//
|
|
|
|
// Turning into:
|
|
|
|
// movzwl (%rdi), %eax
|
|
|
|
// movl %eax, %ecx
|
|
|
|
// shrl $11, %ecx
|
|
|
|
// addl (%rsi,%rcx,4), %eax
|
|
|
|
//
|
|
|
|
// Instead of:
|
|
|
|
// movzwl (%rdi), %eax
|
|
|
|
// movl %eax, %ecx
|
|
|
|
// shrl $9, %ecx
|
|
|
|
// andl $124, %rcx
|
|
|
|
// addl (%rsi,%rcx), %eax
|
|
|
|
//
|
2012-01-11 09:35:02 +00:00
|
|
|
// Note that this function assumes the mask is provided as a mask *after* the
|
|
|
|
// value is shifted. The input chain may or may not match that, but computing
|
|
|
|
// such a mask is trivial.
|
2012-01-11 08:41:08 +00:00
|
|
|
static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
|
2012-01-11 09:35:02 +00:00
|
|
|
uint64_t Mask,
|
|
|
|
SDValue Shift, SDValue X,
|
2012-01-11 08:41:08 +00:00
|
|
|
X86ISelAddressMode &AM) {
|
2012-01-11 09:35:02 +00:00
|
|
|
if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
|
|
|
|
!isa<ConstantSDNode>(Shift.getOperand(1)))
|
2012-01-11 08:41:08 +00:00
|
|
|
return true;
|
|
|
|
|
|
|
|
unsigned ShiftAmt = Shift.getConstantOperandVal(1);
|
2013-05-24 22:23:49 +00:00
|
|
|
unsigned MaskLZ = countLeadingZeros(Mask);
|
|
|
|
unsigned MaskTZ = countTrailingZeros(Mask);
|
2012-01-11 08:41:08 +00:00
|
|
|
|
|
|
|
// The amount of shift we're trying to fit into the addressing mode is taken
|
2012-01-11 09:35:02 +00:00
|
|
|
// from the trailing zeros of the mask.
|
|
|
|
unsigned AMShiftAmt = MaskTZ;
|
2012-01-11 08:41:08 +00:00
|
|
|
|
|
|
|
// There is nothing we can do here unless the mask is removing some bits.
|
|
|
|
// Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
|
|
|
|
if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
|
|
|
|
|
|
|
|
// We also need to ensure that mask is a continuous run of bits.
|
|
|
|
if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
|
|
|
|
|
|
|
|
// Scale the leading zero count down based on the actual size of the value.
|
2012-01-11 09:35:02 +00:00
|
|
|
// Also scale it down based on the size of the shift.
|
2013-08-15 05:57:07 +00:00
|
|
|
MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
|
2012-01-11 08:41:08 +00:00
|
|
|
|
|
|
|
// The final check is to ensure that any masked out high bits of X are
|
|
|
|
// already known to be zero. Otherwise, the mask has a semantic impact
|
|
|
|
// other than masking out a couple of low bits. Unfortunately, because of
|
|
|
|
// the mask, zero extensions will be removed from operands in some cases.
|
|
|
|
// This code works extra hard to look through extensions because we can
|
|
|
|
// replace them with zero extensions cheaply if necessary.
|
|
|
|
bool ReplacingAnyExtend = false;
|
|
|
|
if (X.getOpcode() == ISD::ANY_EXTEND) {
|
2013-08-15 05:57:07 +00:00
|
|
|
unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
|
|
|
|
X.getOperand(0).getSimpleValueType().getSizeInBits();
|
2012-01-11 08:41:08 +00:00
|
|
|
// Assume that we'll replace the any-extend with a zero-extend, and
|
|
|
|
// narrow the search to the extended value.
|
|
|
|
X = X.getOperand(0);
|
|
|
|
MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
|
|
|
|
ReplacingAnyExtend = true;
|
|
|
|
}
|
2013-08-15 05:57:07 +00:00
|
|
|
APInt MaskedHighBits =
|
|
|
|
APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
|
2012-01-11 08:41:08 +00:00
|
|
|
APInt KnownZero, KnownOne;
|
2012-04-04 12:51:34 +00:00
|
|
|
DAG.ComputeMaskedBits(X, KnownZero, KnownOne);
|
2012-01-11 08:41:08 +00:00
|
|
|
if (MaskedHighBits != KnownZero) return true;
|
|
|
|
|
|
|
|
// We've identified a pattern that can be transformed into a single shift
|
|
|
|
// and an addressing mode. Make it so.
|
2013-08-15 05:57:07 +00:00
|
|
|
MVT VT = N.getSimpleValueType();
|
2012-01-11 08:41:08 +00:00
|
|
|
if (ReplacingAnyExtend) {
|
|
|
|
assert(X.getValueType() != VT);
|
|
|
|
// We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
|
2013-05-25 02:42:55 +00:00
|
|
|
SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
|
2012-01-11 11:04:36 +00:00
|
|
|
InsertDAGNode(DAG, N, NewX);
|
2012-01-11 08:41:08 +00:00
|
|
|
X = NewX;
|
|
|
|
}
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(N);
|
2012-01-11 08:41:08 +00:00
|
|
|
SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
|
|
|
|
SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
|
|
|
|
SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
|
|
|
|
SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
|
2012-01-12 01:34:44 +00:00
|
|
|
|
|
|
|
// Insert the new nodes into the topological ordering. We must do this in
|
|
|
|
// a valid topological ordering as nothing is going to go back and re-sort
|
|
|
|
// these nodes. We continually insert before 'N' in sequence as this is
|
|
|
|
// essentially a pre-flattened and pre-sorted sequence of nodes. There is no
|
|
|
|
// hierarchy left to express.
|
2012-01-11 11:04:36 +00:00
|
|
|
InsertDAGNode(DAG, N, NewSRLAmt);
|
|
|
|
InsertDAGNode(DAG, N, NewSRL);
|
|
|
|
InsertDAGNode(DAG, N, NewSHLAmt);
|
|
|
|
InsertDAGNode(DAG, N, NewSHL);
|
2012-01-11 08:41:08 +00:00
|
|
|
DAG.ReplaceAllUsesWith(N, NewSHL);
|
|
|
|
|
|
|
|
AM.Scale = 1 << AMShiftAmt;
|
|
|
|
AM.IndexReg = NewSRL;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-07-22 23:26:55 +00:00
|
|
|
bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
|
|
|
|
unsigned Depth) {
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc dl(N);
|
2009-08-07 21:33:25 +00:00
|
|
|
DEBUG({
|
2010-01-05 01:29:08 +00:00
|
|
|
dbgs() << "MatchAddress: ";
|
2009-08-07 21:33:25 +00:00
|
|
|
AM.dump();
|
|
|
|
});
|
2007-08-13 20:03:06 +00:00
|
|
|
// Limit recursion.
|
|
|
|
if (Depth > 5)
|
2009-03-31 16:16:57 +00:00
|
|
|
return MatchAddressBase(N, AM);
|
2009-08-05 23:01:26 +00:00
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
// If this is already a %rip relative address, we can only merge immediates
|
|
|
|
// into it. Instead of handling this in every case, we handle it here.
|
2006-09-08 06:48:29 +00:00
|
|
|
// RIP relative addressing: %rip + 32-bit displacement!
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (AM.isRIPRelative()) {
|
|
|
|
// FIXME: JumpTable and ExternalSymbol address currently don't like
|
|
|
|
// displacements. It isn't very important, but this should be fixed for
|
|
|
|
// consistency.
|
|
|
|
if (!AM.ES && AM.JT != -1) return true;
|
2009-08-05 23:01:26 +00:00
|
|
|
|
2011-07-13 20:44:23 +00:00
|
|
|
if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
|
|
|
|
if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
|
2006-09-08 06:48:29 +00:00
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
switch (N.getOpcode()) {
|
|
|
|
default: break;
|
2006-09-08 06:48:29 +00:00
|
|
|
case ISD::Constant: {
|
2008-11-11 15:52:29 +00:00
|
|
|
uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
|
2011-07-13 20:44:23 +00:00
|
|
|
if (!FoldOffsetIntoAddress(Val, AM))
|
2006-09-08 06:48:29 +00:00
|
|
|
return false;
|
|
|
|
break;
|
|
|
|
}
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2009-04-12 21:55:03 +00:00
|
|
|
case X86ISD::Wrapper:
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
case X86ISD::WrapperRIP:
|
2009-04-12 21:55:03 +00:00
|
|
|
if (!MatchWrapper(N, AM))
|
|
|
|
return false;
|
2005-12-08 02:01:35 +00:00
|
|
|
break;
|
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
case ISD::LOAD:
|
2010-09-22 04:39:11 +00:00
|
|
|
if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
|
2009-04-08 21:14:34 +00:00
|
|
|
return false;
|
|
|
|
break;
|
|
|
|
|
2006-02-25 10:09:08 +00:00
|
|
|
case ISD::FrameIndex:
|
2011-07-13 21:29:53 +00:00
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase &&
|
|
|
|
AM.Base_Reg.getNode() == 0 &&
|
|
|
|
(!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
|
2006-02-25 10:09:08 +00:00
|
|
|
AM.BaseType = X86ISelAddressMode::FrameIndexBase;
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
|
2005-12-17 09:13:43 +00:00
|
|
|
return false;
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
|
|
|
break;
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
case ISD::SHL:
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
|
2007-12-08 07:22:58 +00:00
|
|
|
break;
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2008-08-31 15:37:04 +00:00
|
|
|
if (ConstantSDNode
|
|
|
|
*CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
|
2008-09-12 16:56:44 +00:00
|
|
|
unsigned Val = CN->getZExtValue();
|
2009-07-22 23:26:55 +00:00
|
|
|
// Note that we handle x<<1 as (,x,2) rather than (x,x) here so
|
|
|
|
// that the base operand remains free for further matching. If
|
|
|
|
// the base doesn't end up getting used, a post-processing step
|
|
|
|
// in MatchAddress turns (,x,2) into (x,x), which is cheaper.
|
2007-12-08 07:22:58 +00:00
|
|
|
if (Val == 1 || Val == 2 || Val == 3) {
|
|
|
|
AM.Scale = 1 << Val;
|
2008-08-28 21:40:38 +00:00
|
|
|
SDValue ShVal = N.getNode()->getOperand(0);
|
2007-12-08 07:22:58 +00:00
|
|
|
|
|
|
|
// Okay, we know that we have a scale by now. However, if the scaled
|
|
|
|
// value is an add of something and a constant, we can fold the
|
|
|
|
// constant into the disp field here.
|
2011-02-13 22:25:43 +00:00
|
|
|
if (CurDAG->isBaseWithConstantOffset(ShVal)) {
|
2008-08-28 21:40:38 +00:00
|
|
|
AM.IndexReg = ShVal.getNode()->getOperand(0);
|
2007-12-08 07:22:58 +00:00
|
|
|
ConstantSDNode *AddVal =
|
2008-08-28 21:40:38 +00:00
|
|
|
cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
|
2012-08-24 23:29:28 +00:00
|
|
|
uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
|
2011-07-13 20:44:23 +00:00
|
|
|
if (!FoldOffsetIntoAddress(Disp, AM))
|
|
|
|
return false;
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
2011-07-13 20:44:23 +00:00
|
|
|
|
|
|
|
AM.IndexReg = ShVal;
|
2007-12-08 07:22:58 +00:00
|
|
|
return false;
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
2007-12-08 07:22:58 +00:00
|
|
|
}
|
2013-01-04 23:01:26 +00:00
|
|
|
break;
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2012-01-11 09:35:02 +00:00
|
|
|
case ISD::SRL: {
|
|
|
|
// Scale must not be used already.
|
|
|
|
if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
|
|
|
|
|
|
|
|
SDValue And = N.getOperand(0);
|
|
|
|
if (And.getOpcode() != ISD::AND) break;
|
|
|
|
SDValue X = And.getOperand(0);
|
|
|
|
|
|
|
|
// We only handle up to 64-bit values here as those are what matter for
|
|
|
|
// addressing mode optimizations.
|
2013-08-15 05:57:07 +00:00
|
|
|
if (X.getSimpleValueType().getSizeInBits() > 64) break;
|
2012-01-11 09:35:02 +00:00
|
|
|
|
|
|
|
// The mask used for the transform is expected to be post-shift, but we
|
|
|
|
// found the shift first so just apply the shift to the mask before passing
|
|
|
|
// it down.
|
|
|
|
if (!isa<ConstantSDNode>(N.getOperand(1)) ||
|
|
|
|
!isa<ConstantSDNode>(And.getOperand(1)))
|
|
|
|
break;
|
|
|
|
uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
|
|
|
|
|
2012-01-11 08:41:08 +00:00
|
|
|
// Try to fold the mask and shift into the scale, and return false if we
|
|
|
|
// succeed.
|
2012-01-11 09:35:02 +00:00
|
|
|
if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
|
2012-01-11 08:41:08 +00:00
|
|
|
return false;
|
|
|
|
break;
|
2012-01-11 09:35:02 +00:00
|
|
|
}
|
2012-01-11 08:41:08 +00:00
|
|
|
|
2007-10-22 20:22:24 +00:00
|
|
|
case ISD::SMUL_LOHI:
|
|
|
|
case ISD::UMUL_LOHI:
|
|
|
|
// A mul_lohi where we need the low part can be folded as a plain multiply.
|
2008-08-26 22:36:50 +00:00
|
|
|
if (N.getResNo() != 0) break;
|
2007-10-22 20:22:24 +00:00
|
|
|
// FALL THROUGH
|
2005-11-19 02:11:08 +00:00
|
|
|
case ISD::MUL:
|
2009-03-30 21:36:47 +00:00
|
|
|
case X86ISD::MUL_IMM:
|
2005-11-19 02:11:08 +00:00
|
|
|
// X*[3,5,9] -> X+X*[2,4,8]
|
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase &&
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.Base_Reg.getNode() == 0 &&
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
AM.IndexReg.getNode() == 0) {
|
2008-08-31 15:37:04 +00:00
|
|
|
if (ConstantSDNode
|
|
|
|
*CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
|
2008-09-12 16:56:44 +00:00
|
|
|
if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
|
|
|
|
CN->getZExtValue() == 9) {
|
|
|
|
AM.Scale = unsigned(CN->getZExtValue())-1;
|
2005-11-19 02:11:08 +00:00
|
|
|
|
2008-08-28 21:40:38 +00:00
|
|
|
SDValue MulVal = N.getNode()->getOperand(0);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Reg;
|
2005-11-19 02:11:08 +00:00
|
|
|
|
|
|
|
// Okay, we know that we have a scale by now. However, if the scaled
|
|
|
|
// value is an add of something and a constant, we can fold the
|
|
|
|
// constant into the disp field here.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
|
|
|
|
isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
|
|
|
|
Reg = MulVal.getNode()->getOperand(0);
|
2005-11-19 02:11:08 +00:00
|
|
|
ConstantSDNode *AddVal =
|
2008-08-28 21:40:38 +00:00
|
|
|
cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
|
2011-07-13 20:44:23 +00:00
|
|
|
uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
|
|
|
|
if (FoldOffsetIntoAddress(Disp, AM))
|
2008-08-28 21:40:38 +00:00
|
|
|
Reg = N.getNode()->getOperand(0);
|
2005-11-19 02:11:08 +00:00
|
|
|
} else {
|
2008-08-28 21:40:38 +00:00
|
|
|
Reg = N.getNode()->getOperand(0);
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
|
|
|
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.IndexReg = AM.Base_Reg = Reg;
|
2005-11-19 02:11:08 +00:00
|
|
|
return false;
|
|
|
|
}
|
2007-02-04 20:18:17 +00:00
|
|
|
}
|
2005-11-19 02:11:08 +00:00
|
|
|
break;
|
|
|
|
|
2009-05-11 18:02:53 +00:00
|
|
|
case ISD::SUB: {
|
|
|
|
// Given A-B, if A can be completely folded into the address and
|
|
|
|
// the index field with the index field unused, use -B as the index.
|
|
|
|
// This is a win if a has multiple parts that can be folded into
|
|
|
|
// the address. Also, this saves a mov if the base register has
|
|
|
|
// other uses, since it avoids a two-address sub instruction, however
|
|
|
|
// it costs an additional mov if the index register has other uses.
|
|
|
|
|
2010-06-18 01:24:29 +00:00
|
|
|
// Add an artificial use to this node so that we can keep track of
|
|
|
|
// it if it gets CSE'd with a different node.
|
|
|
|
HandleSDNode Handle(N);
|
|
|
|
|
2009-05-11 18:02:53 +00:00
|
|
|
// Test if the LHS of the sub can be folded.
|
|
|
|
X86ISelAddressMode Backup = AM;
|
2010-06-18 01:24:29 +00:00
|
|
|
if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
|
2009-05-11 18:02:53 +00:00
|
|
|
AM = Backup;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Test if the index field is free for use.
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
|
2009-05-11 18:02:53 +00:00
|
|
|
AM = Backup;
|
|
|
|
break;
|
|
|
|
}
|
2010-03-17 23:58:35 +00:00
|
|
|
|
2009-05-11 18:02:53 +00:00
|
|
|
int Cost = 0;
|
2010-06-18 01:24:29 +00:00
|
|
|
SDValue RHS = Handle.getValue().getNode()->getOperand(1);
|
2009-05-11 18:02:53 +00:00
|
|
|
// If the RHS involves a register with multiple uses, this
|
|
|
|
// transformation incurs an extra mov, due to the neg instruction
|
|
|
|
// clobbering its operand.
|
|
|
|
if (!RHS.getNode()->hasOneUse() ||
|
|
|
|
RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
|
|
|
|
RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
|
|
|
|
RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
|
|
|
|
(RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
|
2009-08-11 20:47:22 +00:00
|
|
|
RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
|
2009-05-11 18:02:53 +00:00
|
|
|
++Cost;
|
|
|
|
// If the base is a register with multiple uses, this
|
|
|
|
// transformation may save a mov.
|
|
|
|
if ((AM.BaseType == X86ISelAddressMode::RegBase &&
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.Base_Reg.getNode() &&
|
|
|
|
!AM.Base_Reg.getNode()->hasOneUse()) ||
|
2009-05-11 18:02:53 +00:00
|
|
|
AM.BaseType == X86ISelAddressMode::FrameIndexBase)
|
|
|
|
--Cost;
|
|
|
|
// If the folded LHS was interesting, this transformation saves
|
|
|
|
// address arithmetic.
|
|
|
|
if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
|
|
|
|
((AM.Disp != 0) && (Backup.Disp == 0)) +
|
|
|
|
(AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
|
|
|
|
--Cost;
|
|
|
|
// If it doesn't look like it may be an overall win, don't do it.
|
|
|
|
if (Cost >= 0) {
|
|
|
|
AM = Backup;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Ok, the transformation is legal and appears profitable. Go for it.
|
|
|
|
SDValue Zero = CurDAG->getConstant(0, N.getValueType());
|
|
|
|
SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
|
|
|
|
AM.IndexReg = Neg;
|
|
|
|
AM.Scale = 1;
|
|
|
|
|
|
|
|
// Insert the new nodes into the topological ordering.
|
2012-01-11 11:04:36 +00:00
|
|
|
InsertDAGNode(*CurDAG, N, Zero);
|
|
|
|
InsertDAGNode(*CurDAG, N, Neg);
|
2009-05-11 18:02:53 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-01-17 07:09:27 +00:00
|
|
|
case ISD::ADD: {
|
2010-06-18 01:24:29 +00:00
|
|
|
// Add an artificial use to this node so that we can keep track of
|
|
|
|
// it if it gets CSE'd with a different node.
|
|
|
|
HandleSDNode Handle(N);
|
|
|
|
|
2009-01-17 07:09:27 +00:00
|
|
|
X86ISelAddressMode Backup = AM;
|
2011-01-16 08:48:11 +00:00
|
|
|
if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
|
|
|
|
!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
|
2010-06-18 01:24:29 +00:00
|
|
|
return false;
|
|
|
|
AM = Backup;
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2010-03-17 23:58:35 +00:00
|
|
|
// Try again after commuting the operands.
|
2011-01-16 08:48:11 +00:00
|
|
|
if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
|
|
|
|
!MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
|
2010-06-18 01:24:29 +00:00
|
|
|
return false;
|
2009-01-17 07:09:27 +00:00
|
|
|
AM = Backup;
|
2009-03-13 02:25:09 +00:00
|
|
|
|
|
|
|
// If we couldn't fold both operands into the address at the same time,
|
|
|
|
// see if we can just put each operand into a register and fold at least
|
|
|
|
// the add.
|
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase &&
|
2010-04-29 23:30:41 +00:00
|
|
|
!AM.Base_Reg.getNode() &&
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
!AM.IndexReg.getNode()) {
|
2011-01-16 08:48:11 +00:00
|
|
|
N = Handle.getValue();
|
|
|
|
AM.Base_Reg = N.getOperand(0);
|
|
|
|
AM.IndexReg = N.getOperand(1);
|
2009-03-13 02:25:09 +00:00
|
|
|
AM.Scale = 1;
|
|
|
|
return false;
|
|
|
|
}
|
2011-01-16 08:48:11 +00:00
|
|
|
N = Handle.getValue();
|
2005-11-19 02:11:08 +00:00
|
|
|
break;
|
2009-01-17 07:09:27 +00:00
|
|
|
}
|
2006-05-30 06:59:36 +00:00
|
|
|
|
2007-02-04 20:18:17 +00:00
|
|
|
case ISD::OR:
|
2012-09-27 10:14:43 +00:00
|
|
|
// Handle "X | C" as "X + C" iff X is known to have C bits clear.
|
2011-02-13 22:25:43 +00:00
|
|
|
if (CurDAG->isBaseWithConstantOffset(N)) {
|
2007-12-08 07:22:58 +00:00
|
|
|
X86ISelAddressMode Backup = AM;
|
teach the x86 address matching stuff to handle
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.
This finishes off PR1135. Before we compiled the block to:
to:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
leaq 2(%rdx), %r9
movl %esi, (%rdi,%r9,4)
leaq 1(%rdx), %r9
movl %esi, (%rdi,%r9,4)
addq $3, %rdx
movl %esi, (%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
Now we produce:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
movl %esi, 8(%rdi,%rdx,4)
movl %esi, 4(%rdi,%rdx,4)
movl %esi, 12(%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101958 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 23:18:40 +00:00
|
|
|
ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
|
2010-03-17 23:58:35 +00:00
|
|
|
|
2007-12-08 07:22:58 +00:00
|
|
|
// Start with the LHS as an addr mode.
|
2010-06-18 01:24:29 +00:00
|
|
|
if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
|
2011-07-13 20:44:23 +00:00
|
|
|
!FoldOffsetIntoAddress(CN->getSExtValue(), AM))
|
2007-12-08 07:22:58 +00:00
|
|
|
return false;
|
|
|
|
AM = Backup;
|
2006-05-30 06:59:36 +00:00
|
|
|
}
|
|
|
|
break;
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2007-12-13 00:43:27 +00:00
|
|
|
case ISD::AND: {
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
// Perform some heroic transforms on an and of a constant-count shift
|
|
|
|
// with a constant to enable use of the scaled offset field.
|
|
|
|
|
2007-12-13 00:43:27 +00:00
|
|
|
// Scale must not be used already.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
|
2012-01-11 09:35:00 +00:00
|
|
|
SDValue Shift = N.getOperand(0);
|
|
|
|
if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
SDValue X = Shift.getOperand(0);
|
2012-01-11 09:35:00 +00:00
|
|
|
|
|
|
|
// We only handle up to 64-bit values here as those are what matter for
|
|
|
|
// addressing mode optimizations.
|
2013-08-15 05:57:07 +00:00
|
|
|
if (X.getSimpleValueType().getSizeInBits() > 64) break;
|
2012-01-11 09:35:00 +00:00
|
|
|
|
2012-01-11 09:35:04 +00:00
|
|
|
if (!isa<ConstantSDNode>(N.getOperand(1)))
|
|
|
|
break;
|
|
|
|
uint64_t Mask = N.getConstantOperandVal(1);
|
2007-12-13 00:43:27 +00:00
|
|
|
|
2012-01-11 08:48:20 +00:00
|
|
|
// Try to fold the mask and shift into an extract and scale.
|
2012-01-11 09:35:04 +00:00
|
|
|
if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
|
2012-01-11 08:48:20 +00:00
|
|
|
return false;
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
|
2012-01-11 08:48:20 +00:00
|
|
|
// Try to fold the mask and shift directly into the scale.
|
2012-01-11 09:35:04 +00:00
|
|
|
if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
|
2012-01-11 08:41:08 +00:00
|
|
|
return false;
|
|
|
|
|
2012-01-11 09:35:00 +00:00
|
|
|
// Try to swap the mask and shift to place shifts which can be done as
|
|
|
|
// a scale on the outside of the mask.
|
2012-01-11 09:35:04 +00:00
|
|
|
if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
|
2012-01-11 09:35:00 +00:00
|
|
|
return false;
|
|
|
|
break;
|
2007-12-13 00:43:27 +00:00
|
|
|
}
|
2006-05-30 06:59:36 +00:00
|
|
|
}
|
2005-11-19 02:11:08 +00:00
|
|
|
|
2009-03-31 16:16:57 +00:00
|
|
|
return MatchAddressBase(N, AM);
|
2007-08-13 20:03:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
|
|
|
|
/// specified addressing mode without any further recursion.
|
2009-03-31 16:16:57 +00:00
|
|
|
bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
|
2005-11-19 02:11:08 +00:00
|
|
|
// Is the base register already occupied?
|
2010-04-29 23:30:41 +00:00
|
|
|
if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
|
2005-11-19 02:11:08 +00:00
|
|
|
// If so, check to see if the scale index register is set.
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (AM.IndexReg.getNode() == 0) {
|
2005-11-19 02:11:08 +00:00
|
|
|
AM.IndexReg = N;
|
|
|
|
AM.Scale = 1;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we cannot select it.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Default, generate it as a register.
|
|
|
|
AM.BaseType = X86ISelAddressMode::RegBase;
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.Base_Reg = N;
|
2005-11-19 02:11:08 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2005-12-08 02:01:35 +00:00
|
|
|
/// SelectAddr - returns true if it is able pattern match an addressing mode.
|
|
|
|
/// It returns the operands which make up the maximal addressing mode it can
|
|
|
|
/// match by reference.
|
2010-09-21 22:07:31 +00:00
|
|
|
///
|
|
|
|
/// Parent is the parent node of the addr operand that is being matched. It
|
|
|
|
/// is always a load, store, atomic node, or null. It is only null when
|
|
|
|
/// checking memory operands for inline asm nodes.
|
|
|
|
bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue &Scale, SDValue &Index,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Disp, SDValue &Segment) {
|
2005-12-08 02:01:35 +00:00
|
|
|
X86ISelAddressMode AM;
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2010-09-21 22:07:31 +00:00
|
|
|
if (Parent &&
|
|
|
|
// This list of opcodes are all the nodes that have an "addr:$ptr" operand
|
|
|
|
// that are not a MemSDNode, and thus don't have proper addrspace info.
|
|
|
|
Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
|
2010-09-22 20:42:08 +00:00
|
|
|
Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
|
2012-10-15 22:39:43 +00:00
|
|
|
Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
|
|
|
|
Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
|
|
|
|
Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
|
2010-09-21 22:07:31 +00:00
|
|
|
unsigned AddrSpace =
|
|
|
|
cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
|
|
|
|
// AddrSpace 256 -> GS, 257 -> FS.
|
|
|
|
if (AddrSpace == 256)
|
2010-09-22 04:39:11 +00:00
|
|
|
AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
|
2010-09-21 22:07:31 +00:00
|
|
|
if (AddrSpace == 257)
|
2010-09-22 04:39:11 +00:00
|
|
|
AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
|
2010-09-21 22:07:31 +00:00
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2010-09-22 04:39:11 +00:00
|
|
|
if (MatchAddress(N, AM))
|
|
|
|
return false;
|
|
|
|
|
2013-08-15 05:57:07 +00:00
|
|
|
MVT VT = N.getSimpleValueType();
|
2010-09-22 04:39:11 +00:00
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase) {
|
|
|
|
if (!AM.Base_Reg.getNode())
|
|
|
|
AM.Base_Reg = CurDAG->getRegister(0, VT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!AM.IndexReg.getNode())
|
|
|
|
AM.IndexReg = CurDAG->getRegister(0, VT);
|
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
|
2006-01-11 06:09:51 +00:00
|
|
|
return true;
|
2005-12-08 02:01:35 +00:00
|
|
|
}
|
|
|
|
|
2006-10-07 21:55:32 +00:00
|
|
|
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
|
|
|
|
/// match a load whose top elements are either undef or zeros. The load flavor
|
|
|
|
/// is derived from the type of N, which is either v4f32 or v2f64.
|
2010-02-17 06:07:47 +00:00
|
|
|
///
|
|
|
|
/// We also return:
|
2010-02-21 03:17:59 +00:00
|
|
|
/// PatternChainNode: this is the matched node that has a chain input and
|
|
|
|
/// output.
|
2010-03-01 22:51:11 +00:00
|
|
|
bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N, SDValue &Base,
|
|
|
|
SDValue &Scale, SDValue &Index,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Disp, SDValue &Segment,
|
2010-02-21 03:17:59 +00:00
|
|
|
SDValue &PatternNodeWithChain) {
|
2006-10-07 21:55:32 +00:00
|
|
|
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
|
2010-02-21 03:17:59 +00:00
|
|
|
PatternNodeWithChain = N.getOperand(0);
|
|
|
|
if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
|
|
|
|
PatternNodeWithChain.hasOneUse() &&
|
2010-02-21 04:53:34 +00:00
|
|
|
IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
|
2010-04-17 15:26:15 +00:00
|
|
|
IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
|
2010-02-21 03:17:59 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
|
2010-09-21 22:07:31 +00:00
|
|
|
if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
|
2006-10-07 21:55:32 +00:00
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 22:09:58 +00:00
|
|
|
|
|
|
|
// Also handle the case where we explicitly require zeros in the top
|
2006-10-07 21:55:32 +00:00
|
|
|
// elements. This is a vector shuffle from the zero vector.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
|
Fix a long standing deficiency in the X86 backend: we would
sometimes emit "zero" and "all one" vectors multiple times,
for example:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
pcmpeqd %mm0, %mm0
movq %mm0, _M2
ret
instead of:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
movq %mm0, _M2
ret
This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type. This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.
This patch makes the following changes:
1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
immAllZerosV in the wrong form now use *_bc to match them with a
bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle
bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
is legal, instead of generating one that is illegal and expecting
a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.
This patch is definite goodness, but has the potential to cause random
code quality regressions. Please be on the lookout for these and let
me know if they happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44310 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-25 00:24:49 +00:00
|
|
|
// Check to see if the top elements are all zeros (or bitcast of zeros).
|
2012-08-01 18:39:17 +00:00
|
|
|
N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
|
2008-08-28 21:40:38 +00:00
|
|
|
N.getOperand(0).getNode()->hasOneUse() &&
|
|
|
|
ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
|
2010-02-16 22:35:06 +00:00
|
|
|
N.getOperand(0).getOperand(0).hasOneUse() &&
|
|
|
|
IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
|
2010-04-17 15:26:15 +00:00
|
|
|
IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
|
2008-05-08 00:57:18 +00:00
|
|
|
// Okay, this is a zero extending load. Fold it.
|
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
|
2010-09-21 22:07:31 +00:00
|
|
|
if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
|
2008-05-08 00:57:18 +00:00
|
|
|
return false;
|
2010-02-21 03:17:59 +00:00
|
|
|
PatternNodeWithChain = SDValue(LD, 0);
|
2008-05-08 00:57:18 +00:00
|
|
|
return true;
|
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 22:09:58 +00:00
|
|
|
}
|
2006-10-07 21:55:32 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-06-01 09:55:14 +00:00
|
|
|
bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
|
|
|
|
if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
|
|
|
|
uint64_t ImmVal = CN->getZExtValue();
|
|
|
|
if ((uint32_t)ImmVal != (uint64_t)ImmVal)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// In static codegen with small code model, we can get the address of a label
|
|
|
|
// into a register with 'movl'. TableGen has already made sure we're looking
|
|
|
|
// at a label of some kind.
|
2013-06-10 20:43:49 +00:00
|
|
|
assert(N->getOpcode() == X86ISD::Wrapper &&
|
|
|
|
"Unexpected node type for MOV32ri64");
|
2013-06-01 09:55:14 +00:00
|
|
|
N = N.getOperand(0);
|
|
|
|
|
|
|
|
if (N->getOpcode() != ISD::TargetConstantPool &&
|
|
|
|
N->getOpcode() != ISD::TargetJumpTable &&
|
|
|
|
N->getOpcode() != ISD::TargetGlobalAddress &&
|
|
|
|
N->getOpcode() != ISD::TargetExternalSymbol &&
|
|
|
|
N->getOpcode() != ISD::TargetBlockAddress)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
Imm = N;
|
|
|
|
return TM.getCodeModel() == CodeModel::Small;
|
|
|
|
}
|
|
|
|
|
2013-06-10 20:43:49 +00:00
|
|
|
bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
|
|
|
|
SDValue &Scale, SDValue &Index,
|
|
|
|
SDValue &Disp, SDValue &Segment) {
|
|
|
|
if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SDLoc DL(N);
|
|
|
|
RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
|
|
|
|
if (RN && RN->getReg() == 0)
|
|
|
|
Base = CurDAG->getRegister(0, MVT::i64);
|
|
|
|
else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(N)) {
|
|
|
|
// Base could already be %rip, particularly in the x32 ABI.
|
|
|
|
Base = SDValue(CurDAG->getMachineNode(
|
|
|
|
TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
|
|
|
|
CurDAG->getTargetConstant(0, MVT::i64),
|
|
|
|
Base,
|
|
|
|
CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
|
|
|
|
0);
|
|
|
|
}
|
|
|
|
|
|
|
|
RN = dyn_cast<RegisterSDNode>(Index);
|
|
|
|
if (RN && RN->getReg() == 0)
|
|
|
|
Index = CurDAG->getRegister(0, MVT::i64);
|
|
|
|
else {
|
|
|
|
assert(Index.getValueType() == MVT::i32 &&
|
|
|
|
"Expect to be extending 32-bit registers for use in LEA");
|
|
|
|
Index = SDValue(CurDAG->getMachineNode(
|
|
|
|
TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
|
|
|
|
CurDAG->getTargetConstant(0, MVT::i64),
|
|
|
|
Index,
|
|
|
|
CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
|
|
|
|
0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-02-25 10:09:08 +00:00
|
|
|
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
|
|
|
|
/// mode it matches can be cost effectively emitted as an LEA instruction.
|
2010-09-21 20:31:19 +00:00
|
|
|
bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue &Base, SDValue &Scale,
|
2010-07-08 23:46:44 +00:00
|
|
|
SDValue &Index, SDValue &Disp,
|
|
|
|
SDValue &Segment) {
|
2006-02-25 10:09:08 +00:00
|
|
|
X86ISelAddressMode AM;
|
|
|
|
|
2009-04-10 10:09:34 +00:00
|
|
|
// Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
|
|
|
|
// segments.
|
|
|
|
SDValue Copy = AM.Segment;
|
2009-08-11 20:47:22 +00:00
|
|
|
SDValue T = CurDAG->getRegister(0, MVT::i32);
|
2009-04-10 10:09:34 +00:00
|
|
|
AM.Segment = T;
|
|
|
|
if (MatchAddress(N, AM))
|
2009-04-08 21:14:34 +00:00
|
|
|
return false;
|
2009-04-10 10:09:34 +00:00
|
|
|
assert (T == AM.Segment);
|
|
|
|
AM.Segment = Copy;
|
2009-04-08 21:14:34 +00:00
|
|
|
|
2013-08-15 05:57:07 +00:00
|
|
|
MVT VT = N.getSimpleValueType();
|
2006-02-25 10:09:08 +00:00
|
|
|
unsigned Complexity = 0;
|
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase)
|
2010-04-29 23:30:41 +00:00
|
|
|
if (AM.Base_Reg.getNode())
|
2006-02-25 10:09:08 +00:00
|
|
|
Complexity = 1;
|
|
|
|
else
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.Base_Reg = CurDAG->getRegister(0, VT);
|
2006-02-25 10:09:08 +00:00
|
|
|
else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
|
|
|
|
Complexity = 4;
|
|
|
|
|
2008-08-28 21:40:38 +00:00
|
|
|
if (AM.IndexReg.getNode())
|
2006-02-25 10:09:08 +00:00
|
|
|
Complexity++;
|
|
|
|
else
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.IndexReg = CurDAG->getRegister(0, VT);
|
2006-02-25 10:09:08 +00:00
|
|
|
|
Two changes:
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
in three-address form.
This gives us asm diffs like:
- leal (,%eax,4), %eax
+ shll $2, %eax
which is faster on some processors and smaller on all of them.
and, more interestingly:
- movl 24(%esi), %eax
- leal (,%eax,4), %edi
+ movl 24(%esi), %edi
+ shll $2, %edi
Without #2, #1 was a significant pessimization in some cases.
This implements CodeGen/X86/shift-codegen.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35204 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20 06:08:29 +00:00
|
|
|
// Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
|
|
|
|
// a simple shift.
|
|
|
|
if (AM.Scale > 1)
|
2006-02-28 21:13:57 +00:00
|
|
|
Complexity++;
|
2006-02-25 10:09:08 +00:00
|
|
|
|
|
|
|
// FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
|
|
|
|
// to a LEA. This is determined with some expermentation but is by no means
|
|
|
|
// optimal (especially for code size consideration). LEA is nice because of
|
|
|
|
// its three-address nature. Tweak the cost function again when we can run
|
|
|
|
// convertToThreeAddress() at register allocation time.
|
2009-02-07 00:43:41 +00:00
|
|
|
if (AM.hasSymbolicDisplacement()) {
|
2006-09-08 06:48:29 +00:00
|
|
|
// For X86-64, we should always use lea to materialize RIP relative
|
|
|
|
// addresses.
|
2006-12-05 22:03:40 +00:00
|
|
|
if (Subtarget->is64Bit())
|
2006-09-08 06:48:29 +00:00
|
|
|
Complexity = 4;
|
|
|
|
else
|
|
|
|
Complexity += 2;
|
|
|
|
}
|
2006-02-25 10:09:08 +00:00
|
|
|
|
2010-04-29 23:30:41 +00:00
|
|
|
if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
|
2006-02-25 10:09:08 +00:00
|
|
|
Complexity++;
|
|
|
|
|
2009-07-11 22:50:33 +00:00
|
|
|
// If it isn't worth using an LEA, reject it.
|
2009-07-11 23:07:30 +00:00
|
|
|
if (Complexity <= 2)
|
2009-07-11 22:50:33 +00:00
|
|
|
return false;
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2009-07-11 22:50:33 +00:00
|
|
|
getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
|
|
|
|
return true;
|
2006-02-25 10:09:08 +00:00
|
|
|
}
|
|
|
|
|
2009-06-20 20:38:48 +00:00
|
|
|
/// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
|
2010-09-21 20:31:19 +00:00
|
|
|
bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
|
2009-06-20 20:38:48 +00:00
|
|
|
SDValue &Scale, SDValue &Index,
|
2010-07-08 23:46:44 +00:00
|
|
|
SDValue &Disp, SDValue &Segment) {
|
2009-06-20 20:38:48 +00:00
|
|
|
assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
|
|
|
|
const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2009-06-20 20:38:48 +00:00
|
|
|
X86ISelAddressMode AM;
|
|
|
|
AM.GV = GA->getGlobal();
|
|
|
|
AM.Disp += GA->getOffset();
|
2010-04-29 23:30:41 +00:00
|
|
|
AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
|
2009-06-26 21:18:37 +00:00
|
|
|
AM.SymbolFlags = GA->getTargetFlags();
|
|
|
|
|
2009-08-11 20:47:22 +00:00
|
|
|
if (N.getValueType() == MVT::i32) {
|
2009-06-20 20:38:48 +00:00
|
|
|
AM.Scale = 1;
|
2009-08-11 20:47:22 +00:00
|
|
|
AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
|
2009-06-20 20:38:48 +00:00
|
|
|
} else {
|
2009-08-11 20:47:22 +00:00
|
|
|
AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
|
2009-06-20 20:38:48 +00:00
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2009-06-20 20:38:48 +00:00
|
|
|
getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-01-05 01:24:18 +00:00
|
|
|
bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue &Base, SDValue &Scale,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Index, SDValue &Disp,
|
|
|
|
SDValue &Segment) {
|
2010-03-02 22:20:06 +00:00
|
|
|
if (!ISD::isNON_EXTLoad(N.getNode()) ||
|
|
|
|
!IsProfitableToFold(N, P, P) ||
|
2010-04-17 15:26:15 +00:00
|
|
|
!IsLegalToFold(N, P, P, OptLevel))
|
2010-03-02 22:20:06 +00:00
|
|
|
return false;
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2010-09-21 22:07:31 +00:00
|
|
|
return SelectAddr(N.getNode(),
|
|
|
|
N.getOperand(1), Base, Scale, Index, Disp, Segment);
|
2006-01-06 20:36:21 +00:00
|
|
|
}
|
|
|
|
|
2008-09-23 18:22:58 +00:00
|
|
|
/// getGlobalBaseReg - Return an SDNode that returns the value of
|
|
|
|
/// the global base register. Output instructions required to
|
|
|
|
/// initialize the global base register, if necessary.
|
2006-02-18 00:15:05 +00:00
|
|
|
///
|
2006-08-26 05:34:46 +00:00
|
|
|
SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
|
2009-06-03 20:20:00 +00:00
|
|
|
unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
|
2013-06-19 21:36:55 +00:00
|
|
|
return CurDAG->getRegister(GlobalBaseReg,
|
|
|
|
getTargetLowering()->getPointerTy()).getNode();
|
2006-02-18 00:15:05 +00:00
|
|
|
}
|
|
|
|
|
2008-10-02 18:53:47 +00:00
|
|
|
SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
|
|
|
|
SDValue Chain = Node->getOperand(0);
|
|
|
|
SDValue In1 = Node->getOperand(1);
|
|
|
|
SDValue In2L = Node->getOperand(2);
|
|
|
|
SDValue In2H = Node->getOperand(3);
|
2012-09-19 19:36:58 +00:00
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
|
2010-09-21 22:07:31 +00:00
|
|
|
if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
|
2008-10-02 18:53:47 +00:00
|
|
|
return NULL;
|
2009-09-25 20:36:54 +00:00
|
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
|
|
MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
|
|
|
|
const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
|
2013-05-25 02:42:55 +00:00
|
|
|
SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node),
|
2013-04-19 22:22:57 +00:00
|
|
|
MVT::i32, MVT::i32, MVT::Other, Ops);
|
2009-09-25 20:36:54 +00:00
|
|
|
cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
|
|
|
|
return ResNode;
|
2008-10-02 18:53:47 +00:00
|
|
|
}
|
2007-08-10 21:48:46 +00:00
|
|
|
|
2012-09-19 19:36:58 +00:00
|
|
|
/// Atomic opcode table
|
|
|
|
///
|
2011-05-17 07:47:55 +00:00
|
|
|
enum AtomicOpc {
|
2012-09-19 19:36:58 +00:00
|
|
|
ADD,
|
|
|
|
SUB,
|
|
|
|
INC,
|
|
|
|
DEC,
|
2011-05-17 07:50:41 +00:00
|
|
|
OR,
|
2011-05-17 08:10:18 +00:00
|
|
|
AND,
|
|
|
|
XOR,
|
2011-05-17 07:50:41 +00:00
|
|
|
AtomicOpcEnd
|
2011-05-17 07:47:55 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
enum AtomicSz {
|
|
|
|
ConstantI8,
|
|
|
|
I8,
|
|
|
|
SextConstantI16,
|
|
|
|
ConstantI16,
|
|
|
|
I16,
|
|
|
|
SextConstantI32,
|
|
|
|
ConstantI32,
|
|
|
|
I32,
|
|
|
|
SextConstantI64,
|
|
|
|
ConstantI64,
|
2011-05-17 07:50:41 +00:00
|
|
|
I64,
|
|
|
|
AtomicSzEnd
|
2011-05-17 07:47:55 +00:00
|
|
|
};
|
|
|
|
|
2012-03-09 07:45:21 +00:00
|
|
|
static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
|
2012-09-19 19:36:58 +00:00
|
|
|
{
|
|
|
|
X86::LOCK_ADD8mi,
|
|
|
|
X86::LOCK_ADD8mr,
|
|
|
|
X86::LOCK_ADD16mi8,
|
|
|
|
X86::LOCK_ADD16mi,
|
|
|
|
X86::LOCK_ADD16mr,
|
|
|
|
X86::LOCK_ADD32mi8,
|
|
|
|
X86::LOCK_ADD32mi,
|
|
|
|
X86::LOCK_ADD32mr,
|
|
|
|
X86::LOCK_ADD64mi8,
|
|
|
|
X86::LOCK_ADD64mi32,
|
|
|
|
X86::LOCK_ADD64mr,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
X86::LOCK_SUB8mi,
|
|
|
|
X86::LOCK_SUB8mr,
|
|
|
|
X86::LOCK_SUB16mi8,
|
|
|
|
X86::LOCK_SUB16mi,
|
|
|
|
X86::LOCK_SUB16mr,
|
|
|
|
X86::LOCK_SUB32mi8,
|
|
|
|
X86::LOCK_SUB32mi,
|
|
|
|
X86::LOCK_SUB32mr,
|
|
|
|
X86::LOCK_SUB64mi8,
|
|
|
|
X86::LOCK_SUB64mi32,
|
|
|
|
X86::LOCK_SUB64mr,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
0,
|
|
|
|
X86::LOCK_INC8m,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
X86::LOCK_INC16m,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
X86::LOCK_INC32m,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
X86::LOCK_INC64m,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
0,
|
|
|
|
X86::LOCK_DEC8m,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
X86::LOCK_DEC16m,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
X86::LOCK_DEC32m,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
X86::LOCK_DEC64m,
|
|
|
|
},
|
2011-05-11 21:44:58 +00:00
|
|
|
{
|
|
|
|
X86::LOCK_OR8mi,
|
|
|
|
X86::LOCK_OR8mr,
|
|
|
|
X86::LOCK_OR16mi8,
|
|
|
|
X86::LOCK_OR16mi,
|
|
|
|
X86::LOCK_OR16mr,
|
|
|
|
X86::LOCK_OR32mi8,
|
|
|
|
X86::LOCK_OR32mi,
|
|
|
|
X86::LOCK_OR32mr,
|
|
|
|
X86::LOCK_OR64mi8,
|
|
|
|
X86::LOCK_OR64mi32,
|
2012-09-19 19:36:58 +00:00
|
|
|
X86::LOCK_OR64mr,
|
2011-05-17 08:10:18 +00:00
|
|
|
},
|
|
|
|
{
|
|
|
|
X86::LOCK_AND8mi,
|
|
|
|
X86::LOCK_AND8mr,
|
|
|
|
X86::LOCK_AND16mi8,
|
|
|
|
X86::LOCK_AND16mi,
|
|
|
|
X86::LOCK_AND16mr,
|
|
|
|
X86::LOCK_AND32mi8,
|
|
|
|
X86::LOCK_AND32mi,
|
|
|
|
X86::LOCK_AND32mr,
|
|
|
|
X86::LOCK_AND64mi8,
|
|
|
|
X86::LOCK_AND64mi32,
|
2012-09-19 19:36:58 +00:00
|
|
|
X86::LOCK_AND64mr,
|
2011-05-17 08:10:18 +00:00
|
|
|
},
|
|
|
|
{
|
|
|
|
X86::LOCK_XOR8mi,
|
|
|
|
X86::LOCK_XOR8mr,
|
|
|
|
X86::LOCK_XOR16mi8,
|
|
|
|
X86::LOCK_XOR16mi,
|
|
|
|
X86::LOCK_XOR16mr,
|
|
|
|
X86::LOCK_XOR32mi8,
|
|
|
|
X86::LOCK_XOR32mi,
|
|
|
|
X86::LOCK_XOR32mr,
|
|
|
|
X86::LOCK_XOR64mi8,
|
|
|
|
X86::LOCK_XOR64mi32,
|
2012-09-19 19:36:58 +00:00
|
|
|
X86::LOCK_XOR64mr,
|
2011-05-11 21:44:58 +00:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2012-09-19 19:36:58 +00:00
|
|
|
// Return the target constant operand for atomic-load-op and do simple
|
|
|
|
// translations, such as from atomic-load-add to lock-sub. The return value is
|
|
|
|
// one of the following 3 cases:
|
|
|
|
// + target-constant, the operand could be supported as a target constant.
|
|
|
|
// + empty, the operand is not needed any more with the new op selected.
|
|
|
|
// + non-empty, otherwise.
|
|
|
|
static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc dl,
|
2013-08-15 05:57:07 +00:00
|
|
|
enum AtomicOpc &Op, MVT NVT,
|
2012-09-19 19:36:58 +00:00
|
|
|
SDValue Val) {
|
|
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
|
|
|
|
int64_t CNVal = CN->getSExtValue();
|
|
|
|
// Quit if not 32-bit imm.
|
|
|
|
if ((int32_t)CNVal != CNVal)
|
|
|
|
return Val;
|
|
|
|
// For atomic-load-add, we could do some optimizations.
|
|
|
|
if (Op == ADD) {
|
|
|
|
// Translate to INC/DEC if ADD by 1 or -1.
|
|
|
|
if ((CNVal == 1) || (CNVal == -1)) {
|
|
|
|
Op = (CNVal == 1) ? INC : DEC;
|
|
|
|
// No more constant operand after being translated into INC/DEC.
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
// Translate to SUB if ADD by negative value.
|
|
|
|
if (CNVal < 0) {
|
|
|
|
Op = SUB;
|
|
|
|
CNVal = -CNVal;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return CurDAG->getTargetConstant(CNVal, NVT);
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the value operand is single-used, try to optimize it.
|
|
|
|
if (Op == ADD && Val.hasOneUse()) {
|
|
|
|
// Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
|
|
|
|
if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
|
|
|
|
Op = SUB;
|
|
|
|
return Val.getOperand(1);
|
|
|
|
}
|
|
|
|
// A special case for i16, which needs truncating as, in most cases, it's
|
|
|
|
// promoted to i32. We will translate
|
|
|
|
// (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
|
|
|
|
if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
|
|
|
|
Val.getOperand(0).getOpcode() == ISD::SUB &&
|
|
|
|
X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
|
|
|
|
Op = SUB;
|
|
|
|
Val = Val.getOperand(0);
|
|
|
|
return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
|
|
|
|
Val.getOperand(1));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return Val;
|
|
|
|
}
|
|
|
|
|
2013-08-15 05:57:07 +00:00
|
|
|
SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
|
2011-05-10 23:57:45 +00:00
|
|
|
if (Node->hasAnyUseOfValue(0))
|
|
|
|
return 0;
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc dl(Node);
|
2012-09-19 19:36:58 +00:00
|
|
|
|
2011-05-17 08:16:14 +00:00
|
|
|
// Optimize common patterns for __sync_or_and_fetch and similar arith
|
|
|
|
// operations where the result is not used. This allows us to use the "lock"
|
|
|
|
// version of the arithmetic instruction.
|
2011-05-10 23:57:45 +00:00
|
|
|
SDValue Chain = Node->getOperand(0);
|
|
|
|
SDValue Ptr = Node->getOperand(1);
|
|
|
|
SDValue Val = Node->getOperand(2);
|
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
|
|
|
|
if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
|
|
|
|
return 0;
|
|
|
|
|
2011-05-17 08:10:18 +00:00
|
|
|
// Which index into the table.
|
|
|
|
enum AtomicOpc Op;
|
|
|
|
switch (Node->getOpcode()) {
|
2012-09-19 19:36:58 +00:00
|
|
|
default:
|
|
|
|
return 0;
|
2011-05-17 08:10:18 +00:00
|
|
|
case ISD::ATOMIC_LOAD_OR:
|
|
|
|
Op = OR;
|
|
|
|
break;
|
|
|
|
case ISD::ATOMIC_LOAD_AND:
|
|
|
|
Op = AND;
|
|
|
|
break;
|
|
|
|
case ISD::ATOMIC_LOAD_XOR:
|
|
|
|
Op = XOR;
|
|
|
|
break;
|
2012-09-19 19:36:58 +00:00
|
|
|
case ISD::ATOMIC_LOAD_ADD:
|
|
|
|
Op = ADD;
|
|
|
|
break;
|
2011-05-10 23:57:45 +00:00
|
|
|
}
|
2013-04-13 06:07:36 +00:00
|
|
|
|
2012-09-19 19:36:58 +00:00
|
|
|
Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val);
|
|
|
|
bool isUnOp = !Val.getNode();
|
|
|
|
bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2011-05-10 23:57:45 +00:00
|
|
|
unsigned Opc = 0;
|
2013-08-15 05:57:07 +00:00
|
|
|
switch (NVT.SimpleTy) {
|
2011-05-10 23:57:45 +00:00
|
|
|
default: return 0;
|
|
|
|
case MVT::i8:
|
|
|
|
if (isCN)
|
2011-05-17 07:47:55 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][ConstantI8];
|
2011-05-10 23:57:45 +00:00
|
|
|
else
|
2011-05-17 07:47:55 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][I8];
|
2011-05-10 23:57:45 +00:00
|
|
|
break;
|
|
|
|
case MVT::i16:
|
|
|
|
if (isCN) {
|
|
|
|
if (immSext8(Val.getNode()))
|
2011-05-17 07:47:55 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][SextConstantI16];
|
2011-05-10 23:57:45 +00:00
|
|
|
else
|
2011-05-17 07:47:55 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][ConstantI16];
|
2011-05-10 23:57:45 +00:00
|
|
|
} else
|
2011-05-17 07:47:55 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][I16];
|
2011-05-10 23:57:45 +00:00
|
|
|
break;
|
|
|
|
case MVT::i32:
|
|
|
|
if (isCN) {
|
|
|
|
if (immSext8(Val.getNode()))
|
2011-05-17 07:47:55 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][SextConstantI32];
|
2011-05-10 23:57:45 +00:00
|
|
|
else
|
2011-05-17 07:47:55 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][ConstantI32];
|
2011-05-10 23:57:45 +00:00
|
|
|
} else
|
2011-05-17 07:47:55 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][I32];
|
2011-05-10 23:57:45 +00:00
|
|
|
break;
|
|
|
|
case MVT::i64:
|
2011-06-30 00:48:30 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][I64];
|
2011-05-10 23:57:45 +00:00
|
|
|
if (isCN) {
|
|
|
|
if (immSext8(Val.getNode()))
|
2011-05-17 07:47:55 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][SextConstantI64];
|
2011-05-10 23:57:45 +00:00
|
|
|
else if (i64immSExt32(Val.getNode()))
|
2011-05-17 07:47:55 +00:00
|
|
|
Opc = AtomicOpcTbl[Op][ConstantI64];
|
2011-06-30 00:48:30 +00:00
|
|
|
}
|
2011-05-10 23:57:45 +00:00
|
|
|
break;
|
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2011-06-30 00:48:30 +00:00
|
|
|
assert(Opc != 0 && "Invalid arith lock transform!");
|
|
|
|
|
2012-09-19 19:36:58 +00:00
|
|
|
SDValue Ret;
|
2011-05-10 23:57:45 +00:00
|
|
|
SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
|
|
|
|
dl, NVT), 0);
|
|
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
|
|
MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
|
2012-09-19 19:36:58 +00:00
|
|
|
if (isUnOp) {
|
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
|
2013-04-19 22:22:57 +00:00
|
|
|
Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
|
2012-09-19 19:36:58 +00:00
|
|
|
} else {
|
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
|
2013-04-19 22:22:57 +00:00
|
|
|
Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
|
2012-09-19 19:36:58 +00:00
|
|
|
}
|
2011-05-10 23:57:45 +00:00
|
|
|
cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
|
|
|
|
SDValue RetVals[] = { Undef, Ret };
|
|
|
|
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
|
|
|
|
}
|
|
|
|
|
2009-10-09 20:35:19 +00:00
|
|
|
/// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
|
|
|
|
/// any uses which require the SF or OF bits to be accurate.
|
|
|
|
static bool HasNoSignedComparisonUses(SDNode *N) {
|
|
|
|
// Examine each user of the node.
|
|
|
|
for (SDNode::use_iterator UI = N->use_begin(),
|
|
|
|
UE = N->use_end(); UI != UE; ++UI) {
|
|
|
|
// Only examine CopyToReg uses.
|
|
|
|
if (UI->getOpcode() != ISD::CopyToReg)
|
|
|
|
return false;
|
|
|
|
// Only examine CopyToReg uses that copy to EFLAGS.
|
|
|
|
if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
|
|
|
|
X86::EFLAGS)
|
|
|
|
return false;
|
|
|
|
// Examine each user of the CopyToReg use.
|
|
|
|
for (SDNode::use_iterator FlagUI = UI->use_begin(),
|
|
|
|
FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
|
|
|
|
// Only examine the Flag result.
|
|
|
|
if (FlagUI.getUse().getResNo() != 1) continue;
|
|
|
|
// Anything unusual: assume conservatively.
|
|
|
|
if (!FlagUI->isMachineOpcode()) return false;
|
|
|
|
// Examine the opcode of the user.
|
|
|
|
switch (FlagUI->getMachineOpcode()) {
|
|
|
|
// These comparisons don't treat the most significant bit specially.
|
|
|
|
case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
|
|
|
|
case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
|
|
|
|
case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
|
|
|
|
case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
|
2010-02-11 19:25:55 +00:00
|
|
|
case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
|
|
|
|
case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
|
2009-10-09 20:35:19 +00:00
|
|
|
case X86::CMOVA16rr: case X86::CMOVA16rm:
|
|
|
|
case X86::CMOVA32rr: case X86::CMOVA32rm:
|
|
|
|
case X86::CMOVA64rr: case X86::CMOVA64rm:
|
|
|
|
case X86::CMOVAE16rr: case X86::CMOVAE16rm:
|
|
|
|
case X86::CMOVAE32rr: case X86::CMOVAE32rm:
|
|
|
|
case X86::CMOVAE64rr: case X86::CMOVAE64rm:
|
|
|
|
case X86::CMOVB16rr: case X86::CMOVB16rm:
|
|
|
|
case X86::CMOVB32rr: case X86::CMOVB32rm:
|
|
|
|
case X86::CMOVB64rr: case X86::CMOVB64rm:
|
2010-10-05 23:00:14 +00:00
|
|
|
case X86::CMOVBE16rr: case X86::CMOVBE16rm:
|
|
|
|
case X86::CMOVBE32rr: case X86::CMOVBE32rm:
|
|
|
|
case X86::CMOVBE64rr: case X86::CMOVBE64rm:
|
2009-10-09 20:35:19 +00:00
|
|
|
case X86::CMOVE16rr: case X86::CMOVE16rm:
|
|
|
|
case X86::CMOVE32rr: case X86::CMOVE32rm:
|
|
|
|
case X86::CMOVE64rr: case X86::CMOVE64rm:
|
|
|
|
case X86::CMOVNE16rr: case X86::CMOVNE16rm:
|
|
|
|
case X86::CMOVNE32rr: case X86::CMOVNE32rm:
|
|
|
|
case X86::CMOVNE64rr: case X86::CMOVNE64rm:
|
|
|
|
case X86::CMOVNP16rr: case X86::CMOVNP16rm:
|
|
|
|
case X86::CMOVNP32rr: case X86::CMOVNP32rm:
|
|
|
|
case X86::CMOVNP64rr: case X86::CMOVNP64rm:
|
|
|
|
case X86::CMOVP16rr: case X86::CMOVP16rm:
|
|
|
|
case X86::CMOVP32rr: case X86::CMOVP32rm:
|
|
|
|
case X86::CMOVP64rr: case X86::CMOVP64rm:
|
|
|
|
continue;
|
|
|
|
// Anything else: assume conservatively.
|
|
|
|
default: return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-03-29 05:45:48 +00:00
|
|
|
/// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
|
|
|
|
/// is suitable for doing the {load; increment or decrement; store} to modify
|
|
|
|
/// transformation.
|
2012-08-01 18:39:17 +00:00
|
|
|
static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
|
2012-04-12 19:14:21 +00:00
|
|
|
SDValue StoredVal, SelectionDAG *CurDAG,
|
|
|
|
LoadSDNode* &LoadNode, SDValue &InputChain) {
|
2012-03-29 05:45:48 +00:00
|
|
|
|
|
|
|
// is the value stored the result of a DEC or INC?
|
|
|
|
if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
|
|
|
|
|
|
|
|
// is the stored value result 0 of the load?
|
|
|
|
if (StoredVal.getResNo() != 0) return false;
|
|
|
|
|
|
|
|
// are there other uses of the loaded value than the inc or dec?
|
|
|
|
if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
|
|
|
|
|
2012-04-12 19:14:21 +00:00
|
|
|
// is the store non-extending and non-indexed?
|
|
|
|
if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
|
2012-03-29 05:45:48 +00:00
|
|
|
return false;
|
|
|
|
|
2012-04-12 19:14:21 +00:00
|
|
|
SDValue Load = StoredVal->getOperand(0);
|
|
|
|
// Is the stored value a non-extending and non-indexed load?
|
|
|
|
if (!ISD::isNormalLoad(Load.getNode())) return false;
|
2012-03-29 05:45:48 +00:00
|
|
|
|
2012-04-12 19:14:21 +00:00
|
|
|
// Return LoadNode by reference.
|
|
|
|
LoadNode = cast<LoadSDNode>(Load);
|
|
|
|
// is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
|
2012-08-01 18:39:17 +00:00
|
|
|
EVT LdVT = LoadNode->getMemoryVT();
|
|
|
|
if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
|
2012-04-12 19:14:21 +00:00
|
|
|
LdVT != MVT::i8)
|
2012-03-29 05:45:48 +00:00
|
|
|
return false;
|
|
|
|
|
2012-04-12 19:14:21 +00:00
|
|
|
// Is store the only read of the loaded value?
|
|
|
|
if (!Load.hasOneUse())
|
2012-03-29 05:45:48 +00:00
|
|
|
return false;
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2012-04-12 19:14:21 +00:00
|
|
|
// Is the address of the store the same as the load?
|
|
|
|
if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
|
|
|
|
LoadNode->getOffset() != StoreNode->getOffset())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Check if the chain is produced by the load or is a TokenFactor with
|
|
|
|
// the load output chain as an operand. Return InputChain by reference.
|
|
|
|
SDValue Chain = StoreNode->getChain();
|
2012-03-29 05:45:48 +00:00
|
|
|
|
2012-04-12 19:14:21 +00:00
|
|
|
bool ChainCheck = false;
|
|
|
|
if (Chain == Load.getValue(1)) {
|
|
|
|
ChainCheck = true;
|
|
|
|
InputChain = LoadNode->getChain();
|
|
|
|
} else if (Chain.getOpcode() == ISD::TokenFactor) {
|
|
|
|
SmallVector<SDValue, 4> ChainOps;
|
|
|
|
for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
|
|
|
|
SDValue Op = Chain.getOperand(i);
|
|
|
|
if (Op == Load.getValue(1)) {
|
|
|
|
ChainCheck = true;
|
|
|
|
continue;
|
|
|
|
}
|
2012-05-16 01:54:27 +00:00
|
|
|
|
|
|
|
// Make sure using Op as part of the chain would not cause a cycle here.
|
|
|
|
// In theory, we could check whether the chain node is a predecessor of
|
|
|
|
// the load. But that can be very expensive. Instead visit the uses and
|
|
|
|
// make sure they all have smaller node id than the load.
|
|
|
|
int LoadId = LoadNode->getNodeId();
|
|
|
|
for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
|
|
|
|
UE = UI->use_end(); UI != UE; ++UI) {
|
|
|
|
if (UI.getUse().getResNo() != 0)
|
|
|
|
continue;
|
|
|
|
if (UI->getNodeId() > LoadId)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-04-12 19:14:21 +00:00
|
|
|
ChainOps.push_back(Op);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ChainCheck)
|
|
|
|
// Make a new TokenFactor with all the other input chains except
|
|
|
|
// for the load.
|
2013-05-25 02:42:55 +00:00
|
|
|
InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
|
2012-04-12 19:14:21 +00:00
|
|
|
MVT::Other, &ChainOps[0], ChainOps.size());
|
|
|
|
}
|
|
|
|
if (!ChainCheck)
|
2012-03-29 05:45:48 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-03-29 12:37:26 +00:00
|
|
|
/// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
|
|
|
|
/// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
|
2012-03-29 05:45:48 +00:00
|
|
|
static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
|
|
|
|
if (Opc == X86ISD::DEC) {
|
|
|
|
if (LdVT == MVT::i64) return X86::DEC64m;
|
|
|
|
if (LdVT == MVT::i32) return X86::DEC32m;
|
|
|
|
if (LdVT == MVT::i16) return X86::DEC16m;
|
|
|
|
if (LdVT == MVT::i8) return X86::DEC8m;
|
2012-03-29 12:37:26 +00:00
|
|
|
} else {
|
|
|
|
assert(Opc == X86ISD::INC && "unrecognized opcode");
|
2012-03-29 05:45:48 +00:00
|
|
|
if (LdVT == MVT::i64) return X86::INC64m;
|
|
|
|
if (LdVT == MVT::i32) return X86::INC32m;
|
|
|
|
if (LdVT == MVT::i16) return X86::INC16m;
|
|
|
|
if (LdVT == MVT::i8) return X86::INC8m;
|
|
|
|
}
|
2012-03-29 12:37:26 +00:00
|
|
|
llvm_unreachable("unrecognized size for LdVT");
|
2012-03-29 05:45:48 +00:00
|
|
|
}
|
|
|
|
|
2012-06-26 19:47:59 +00:00
|
|
|
/// SelectGather - Customized ISel for GATHER operations.
|
|
|
|
///
|
|
|
|
SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
|
|
|
|
// Operands of Gather: VSrc, Base, VIdx, VMask, Scale
|
|
|
|
SDValue Chain = Node->getOperand(0);
|
|
|
|
SDValue VSrc = Node->getOperand(2);
|
|
|
|
SDValue Base = Node->getOperand(3);
|
|
|
|
SDValue VIdx = Node->getOperand(4);
|
|
|
|
SDValue VMask = Node->getOperand(5);
|
|
|
|
ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
|
2012-07-01 02:17:08 +00:00
|
|
|
if (!Scale)
|
|
|
|
return 0;
|
2012-06-26 19:47:59 +00:00
|
|
|
|
2012-07-12 06:52:41 +00:00
|
|
|
SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
|
|
|
|
MVT::Other);
|
|
|
|
|
2012-06-26 19:47:59 +00:00
|
|
|
// Memory Operands: Base, Scale, Index, Disp, Segment
|
|
|
|
SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
|
|
|
|
SDValue Segment = CurDAG->getRegister(0, MVT::i32);
|
|
|
|
const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
|
|
|
|
Disp, Segment, VMask, Chain};
|
2013-05-25 02:42:55 +00:00
|
|
|
SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
|
2012-07-12 06:52:41 +00:00
|
|
|
// Node has 2 outputs: VDst and MVT::Other.
|
|
|
|
// ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
|
|
|
|
// We replace VDst of Node with VDst of ResNode, and Other of Node with Other
|
|
|
|
// of ResNode.
|
|
|
|
ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
|
|
|
|
ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
|
2012-06-26 19:47:59 +00:00
|
|
|
return ResNode;
|
|
|
|
}
|
|
|
|
|
2010-01-05 01:24:18 +00:00
|
|
|
SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
2013-08-15 05:57:07 +00:00
|
|
|
MVT NVT = Node->getSimpleValueType(0);
|
2006-01-06 20:36:21 +00:00
|
|
|
unsigned Opc, MOpc;
|
|
|
|
unsigned Opcode = Node->getOpcode();
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc dl(Node);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
|
2006-02-10 22:24:32 +00:00
|
|
|
|
2008-07-17 19:10:17 +00:00
|
|
|
if (Node->isMachineOpcode()) {
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
|
2013-09-22 08:21:56 +00:00
|
|
|
Node->setNodeId(-1);
|
2006-08-11 09:08:15 +00:00
|
|
|
return NULL; // Already selected.
|
2006-02-09 00:37:58 +00:00
|
|
|
}
|
2006-01-11 22:15:18 +00:00
|
|
|
|
2006-01-06 20:36:21 +00:00
|
|
|
switch (Opcode) {
|
2009-08-02 16:10:52 +00:00
|
|
|
default: break;
|
2012-06-26 19:47:59 +00:00
|
|
|
case ISD::INTRINSIC_W_CHAIN: {
|
|
|
|
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
|
|
|
|
switch (IntNo) {
|
|
|
|
default: break;
|
|
|
|
case Intrinsic::x86_avx2_gather_d_pd:
|
|
|
|
case Intrinsic::x86_avx2_gather_d_pd_256:
|
|
|
|
case Intrinsic::x86_avx2_gather_q_pd:
|
|
|
|
case Intrinsic::x86_avx2_gather_q_pd_256:
|
|
|
|
case Intrinsic::x86_avx2_gather_d_ps:
|
|
|
|
case Intrinsic::x86_avx2_gather_d_ps_256:
|
|
|
|
case Intrinsic::x86_avx2_gather_q_ps:
|
|
|
|
case Intrinsic::x86_avx2_gather_q_ps_256:
|
2012-06-29 00:54:20 +00:00
|
|
|
case Intrinsic::x86_avx2_gather_d_q:
|
|
|
|
case Intrinsic::x86_avx2_gather_d_q_256:
|
|
|
|
case Intrinsic::x86_avx2_gather_q_q:
|
|
|
|
case Intrinsic::x86_avx2_gather_q_q_256:
|
|
|
|
case Intrinsic::x86_avx2_gather_d_d:
|
|
|
|
case Intrinsic::x86_avx2_gather_d_d_256:
|
|
|
|
case Intrinsic::x86_avx2_gather_q_d:
|
2012-07-01 02:05:52 +00:00
|
|
|
case Intrinsic::x86_avx2_gather_q_d_256: {
|
2013-06-05 18:12:26 +00:00
|
|
|
if (!Subtarget->hasAVX2())
|
|
|
|
break;
|
2012-07-01 02:05:52 +00:00
|
|
|
unsigned Opc;
|
|
|
|
switch (IntNo) {
|
2012-07-01 02:55:34 +00:00
|
|
|
default: llvm_unreachable("Impossible intrinsic");
|
2012-07-01 02:05:52 +00:00
|
|
|
case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
|
|
|
|
case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
|
|
|
|
}
|
2012-07-01 02:17:08 +00:00
|
|
|
SDNode *RetVal = SelectGather(Node, Opc);
|
|
|
|
if (RetVal)
|
2012-07-12 06:52:41 +00:00
|
|
|
// We already called ReplaceUses inside SelectGather.
|
|
|
|
return NULL;
|
2012-07-01 02:18:18 +00:00
|
|
|
break;
|
2012-07-01 02:05:52 +00:00
|
|
|
}
|
2012-06-26 19:47:59 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2009-08-02 16:10:52 +00:00
|
|
|
case X86ISD::GlobalBaseReg:
|
|
|
|
return getGlobalBaseReg();
|
|
|
|
|
2012-07-01 02:55:34 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
case X86ISD::ATOMOR64_DAG:
|
|
|
|
case X86ISD::ATOMXOR64_DAG:
|
|
|
|
case X86ISD::ATOMADD64_DAG:
|
|
|
|
case X86ISD::ATOMSUB64_DAG:
|
|
|
|
case X86ISD::ATOMNAND64_DAG:
|
|
|
|
case X86ISD::ATOMAND64_DAG:
|
2012-09-25 18:08:13 +00:00
|
|
|
case X86ISD::ATOMMAX64_DAG:
|
|
|
|
case X86ISD::ATOMMIN64_DAG:
|
|
|
|
case X86ISD::ATOMUMAX64_DAG:
|
|
|
|
case X86ISD::ATOMUMIN64_DAG:
|
2012-07-01 02:55:34 +00:00
|
|
|
case X86ISD::ATOMSWAP64_DAG: {
|
|
|
|
unsigned Opc;
|
|
|
|
switch (Opcode) {
|
2012-08-11 17:44:14 +00:00
|
|
|
default: llvm_unreachable("Impossible opcode");
|
2012-07-01 02:55:34 +00:00
|
|
|
case X86ISD::ATOMOR64_DAG: Opc = X86::ATOMOR6432; break;
|
|
|
|
case X86ISD::ATOMXOR64_DAG: Opc = X86::ATOMXOR6432; break;
|
|
|
|
case X86ISD::ATOMADD64_DAG: Opc = X86::ATOMADD6432; break;
|
|
|
|
case X86ISD::ATOMSUB64_DAG: Opc = X86::ATOMSUB6432; break;
|
|
|
|
case X86ISD::ATOMNAND64_DAG: Opc = X86::ATOMNAND6432; break;
|
|
|
|
case X86ISD::ATOMAND64_DAG: Opc = X86::ATOMAND6432; break;
|
2012-09-25 18:08:13 +00:00
|
|
|
case X86ISD::ATOMMAX64_DAG: Opc = X86::ATOMMAX6432; break;
|
|
|
|
case X86ISD::ATOMMIN64_DAG: Opc = X86::ATOMMIN6432; break;
|
|
|
|
case X86ISD::ATOMUMAX64_DAG: Opc = X86::ATOMUMAX6432; break;
|
|
|
|
case X86ISD::ATOMUMIN64_DAG: Opc = X86::ATOMUMIN6432; break;
|
2012-07-01 02:55:34 +00:00
|
|
|
case X86ISD::ATOMSWAP64_DAG: Opc = X86::ATOMSWAP6432; break;
|
|
|
|
}
|
|
|
|
SDNode *RetVal = SelectAtomic64(Node, Opc);
|
|
|
|
if (RetVal)
|
|
|
|
return RetVal;
|
|
|
|
break;
|
|
|
|
}
|
2009-08-02 16:10:52 +00:00
|
|
|
|
2011-05-17 08:10:18 +00:00
|
|
|
case ISD::ATOMIC_LOAD_XOR:
|
|
|
|
case ISD::ATOMIC_LOAD_AND:
|
2012-09-19 19:36:58 +00:00
|
|
|
case ISD::ATOMIC_LOAD_OR:
|
|
|
|
case ISD::ATOMIC_LOAD_ADD: {
|
2011-05-17 08:10:18 +00:00
|
|
|
SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
|
2011-05-10 23:57:45 +00:00
|
|
|
if (RetVal)
|
|
|
|
return RetVal;
|
|
|
|
break;
|
|
|
|
}
|
X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039)
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
shlq $42, %rdi ## encoding: [0x48,0xc1,0xe7,0x2a]
movabsq $4398046511104, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
andq %rdi, %rax ## encoding: [0x48,0x21,0xf8]
ret ## encoding: [0xc3]
with this patch we can fold the immediate into the and:
andq $1, %rdi ## encoding: [0x48,0x83,0xe7,0x01]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
shlq $42, %rax ## encoding: [0x48,0xc1,0xe0,0x2a]
ret ## encoding: [0xc3]
It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 15:30:40 +00:00
|
|
|
case ISD::AND:
|
|
|
|
case ISD::OR:
|
|
|
|
case ISD::XOR: {
|
|
|
|
// For operations of the form (x << C1) op C2, check if we can use a smaller
|
|
|
|
// encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
|
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
|
|
|
|
|
|
|
if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
|
|
|
|
break;
|
|
|
|
|
|
|
|
// i8 is unshrinkable, i16 should be promoted to i32.
|
|
|
|
if (NVT != MVT::i32 && NVT != MVT::i64)
|
|
|
|
break;
|
|
|
|
|
|
|
|
ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
|
|
|
|
ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
|
|
|
|
if (!Cst || !ShlCst)
|
|
|
|
break;
|
|
|
|
|
|
|
|
int64_t Val = Cst->getSExtValue();
|
|
|
|
uint64_t ShlVal = ShlCst->getZExtValue();
|
|
|
|
|
|
|
|
// Make sure that we don't change the operation by removing bits.
|
|
|
|
// This only matters for OR and XOR, AND is unaffected.
|
2012-08-24 23:29:28 +00:00
|
|
|
uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
|
|
|
|
if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
|
X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039)
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
shlq $42, %rdi ## encoding: [0x48,0xc1,0xe7,0x2a]
movabsq $4398046511104, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
andq %rdi, %rax ## encoding: [0x48,0x21,0xf8]
ret ## encoding: [0xc3]
with this patch we can fold the immediate into the and:
andq $1, %rdi ## encoding: [0x48,0x83,0xe7,0x01]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
shlq $42, %rax ## encoding: [0x48,0xc1,0xe0,0x2a]
ret ## encoding: [0xc3]
It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 15:30:40 +00:00
|
|
|
break;
|
|
|
|
|
2012-08-11 17:44:14 +00:00
|
|
|
unsigned ShlOp, Op;
|
2013-08-15 05:57:07 +00:00
|
|
|
MVT CstVT = NVT;
|
X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039)
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
shlq $42, %rdi ## encoding: [0x48,0xc1,0xe7,0x2a]
movabsq $4398046511104, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
andq %rdi, %rax ## encoding: [0x48,0x21,0xf8]
ret ## encoding: [0xc3]
with this patch we can fold the immediate into the and:
andq $1, %rdi ## encoding: [0x48,0x83,0xe7,0x01]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
shlq $42, %rax ## encoding: [0x48,0xc1,0xe0,0x2a]
ret ## encoding: [0xc3]
It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 15:30:40 +00:00
|
|
|
|
|
|
|
// Check the minimum bitwidth for the new constant.
|
|
|
|
// TODO: AND32ri is the same as AND64ri32 with zext imm.
|
|
|
|
// TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
|
|
|
|
// TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
|
|
|
|
if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
|
|
|
|
CstVT = MVT::i8;
|
|
|
|
else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
|
|
|
|
CstVT = MVT::i32;
|
|
|
|
|
|
|
|
// Bail if there is no smaller encoding.
|
|
|
|
if (NVT == CstVT)
|
|
|
|
break;
|
|
|
|
|
2013-08-15 05:57:07 +00:00
|
|
|
switch (NVT.SimpleTy) {
|
X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039)
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
shlq $42, %rdi ## encoding: [0x48,0xc1,0xe7,0x2a]
movabsq $4398046511104, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
andq %rdi, %rax ## encoding: [0x48,0x21,0xf8]
ret ## encoding: [0xc3]
with this patch we can fold the immediate into the and:
andq $1, %rdi ## encoding: [0x48,0x83,0xe7,0x01]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
shlq $42, %rax ## encoding: [0x48,0xc1,0xe0,0x2a]
ret ## encoding: [0xc3]
It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 15:30:40 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
|
|
|
case MVT::i32:
|
|
|
|
assert(CstVT == MVT::i8);
|
|
|
|
ShlOp = X86::SHL32ri;
|
|
|
|
|
|
|
|
switch (Opcode) {
|
2012-08-11 17:44:14 +00:00
|
|
|
default: llvm_unreachable("Impossible opcode");
|
X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039)
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
shlq $42, %rdi ## encoding: [0x48,0xc1,0xe7,0x2a]
movabsq $4398046511104, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
andq %rdi, %rax ## encoding: [0x48,0x21,0xf8]
ret ## encoding: [0xc3]
with this patch we can fold the immediate into the and:
andq $1, %rdi ## encoding: [0x48,0x83,0xe7,0x01]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
shlq $42, %rax ## encoding: [0x48,0xc1,0xe0,0x2a]
ret ## encoding: [0xc3]
It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 15:30:40 +00:00
|
|
|
case ISD::AND: Op = X86::AND32ri8; break;
|
|
|
|
case ISD::OR: Op = X86::OR32ri8; break;
|
|
|
|
case ISD::XOR: Op = X86::XOR32ri8; break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
assert(CstVT == MVT::i8 || CstVT == MVT::i32);
|
|
|
|
ShlOp = X86::SHL64ri;
|
|
|
|
|
|
|
|
switch (Opcode) {
|
2012-08-11 17:44:14 +00:00
|
|
|
default: llvm_unreachable("Impossible opcode");
|
X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039)
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
shlq $42, %rdi ## encoding: [0x48,0xc1,0xe7,0x2a]
movabsq $4398046511104, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
andq %rdi, %rax ## encoding: [0x48,0x21,0xf8]
ret ## encoding: [0xc3]
with this patch we can fold the immediate into the and:
andq $1, %rdi ## encoding: [0x48,0x83,0xe7,0x01]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
shlq $42, %rax ## encoding: [0x48,0xc1,0xe0,0x2a]
ret ## encoding: [0xc3]
It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 15:30:40 +00:00
|
|
|
case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
|
|
|
|
case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
|
|
|
|
case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Emit the smaller op and the shift.
|
|
|
|
SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
|
|
|
|
SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
|
|
|
|
return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
|
|
|
|
getI8Imm(ShlVal));
|
|
|
|
}
|
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 07:30:36 +00:00
|
|
|
case X86ISD::UMUL: {
|
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2011-01-14 22:34:13 +00:00
|
|
|
unsigned LoReg;
|
2013-08-15 05:57:07 +00:00
|
|
|
switch (NVT.SimpleTy) {
|
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 07:30:36 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2011-01-14 22:34:13 +00:00
|
|
|
case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
|
|
|
|
case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
|
|
|
|
case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
|
|
|
|
case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
|
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 07:30:36 +00:00
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 07:30:36 +00:00
|
|
|
SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
|
|
|
|
N0, SDValue()).getValue(1);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 07:30:36 +00:00
|
|
|
SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
|
|
|
|
SDValue Ops[] = {N1, InFlag};
|
2013-04-19 22:22:57 +00:00
|
|
|
SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
|
2012-08-01 18:39:17 +00:00
|
|
|
|
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 07:30:36 +00:00
|
|
|
ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
|
|
|
|
ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
|
|
|
|
ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
|
|
|
|
return NULL;
|
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
case ISD::SMUL_LOHI:
|
|
|
|
case ISD::UMUL_LOHI: {
|
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
2006-01-06 20:36:21 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
bool isSigned = Opcode == ISD::SMUL_LOHI;
|
2012-09-26 08:22:37 +00:00
|
|
|
bool hasBMI2 = Subtarget->hasBMI2();
|
2009-08-07 21:33:25 +00:00
|
|
|
if (!isSigned) {
|
2013-08-15 05:57:07 +00:00
|
|
|
switch (NVT.SimpleTy) {
|
2009-07-14 16:55:14 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
|
|
|
|
case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
|
2012-09-26 08:22:37 +00:00
|
|
|
case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
|
|
|
|
MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
|
|
|
|
case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
|
|
|
|
MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
|
2006-01-06 20:36:21 +00:00
|
|
|
}
|
2009-08-07 21:33:25 +00:00
|
|
|
} else {
|
2013-08-15 05:57:07 +00:00
|
|
|
switch (NVT.SimpleTy) {
|
2009-08-02 16:10:52 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
|
|
|
|
case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
|
|
|
|
case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
|
|
|
|
case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
2009-08-07 21:33:25 +00:00
|
|
|
}
|
2006-01-06 23:19:29 +00:00
|
|
|
|
2012-09-26 08:22:37 +00:00
|
|
|
unsigned SrcReg, LoReg, HiReg;
|
|
|
|
switch (Opc) {
|
|
|
|
default: llvm_unreachable("Unknown MUL opcode!");
|
|
|
|
case X86::IMUL8r:
|
|
|
|
case X86::MUL8r:
|
|
|
|
SrcReg = LoReg = X86::AL; HiReg = X86::AH;
|
|
|
|
break;
|
|
|
|
case X86::IMUL16r:
|
|
|
|
case X86::MUL16r:
|
|
|
|
SrcReg = LoReg = X86::AX; HiReg = X86::DX;
|
|
|
|
break;
|
|
|
|
case X86::IMUL32r:
|
|
|
|
case X86::MUL32r:
|
|
|
|
SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
|
|
|
|
break;
|
|
|
|
case X86::IMUL64r:
|
|
|
|
case X86::MUL64r:
|
|
|
|
SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
|
|
|
|
break;
|
|
|
|
case X86::MULX32rr:
|
|
|
|
SrcReg = X86::EDX; LoReg = HiReg = 0;
|
|
|
|
break;
|
|
|
|
case X86::MULX64rr:
|
|
|
|
SrcReg = X86::RDX; LoReg = HiReg = 0;
|
|
|
|
break;
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
2006-01-06 20:36:21 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
|
2010-01-05 01:24:18 +00:00
|
|
|
bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
2009-08-07 21:33:25 +00:00
|
|
|
// Multiply is commmutative.
|
2009-08-02 16:10:52 +00:00
|
|
|
if (!foldedLoad) {
|
2010-01-05 01:24:18 +00:00
|
|
|
foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
2009-08-02 16:10:52 +00:00
|
|
|
if (foldedLoad)
|
|
|
|
std::swap(N0, N1);
|
|
|
|
}
|
|
|
|
|
2012-09-26 08:22:37 +00:00
|
|
|
SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
|
2012-05-23 05:44:51 +00:00
|
|
|
N0, SDValue()).getValue(1);
|
2012-09-26 08:22:37 +00:00
|
|
|
SDValue ResHi, ResLo;
|
2009-08-02 16:10:52 +00:00
|
|
|
|
|
|
|
if (foldedLoad) {
|
2012-09-26 08:22:37 +00:00
|
|
|
SDValue Chain;
|
2009-08-02 16:10:52 +00:00
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
|
|
|
|
InFlag };
|
2012-09-26 08:22:37 +00:00
|
|
|
if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
|
|
|
|
SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
|
2013-04-19 22:22:57 +00:00
|
|
|
SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
|
2012-09-26 08:22:37 +00:00
|
|
|
ResHi = SDValue(CNode, 0);
|
|
|
|
ResLo = SDValue(CNode, 1);
|
|
|
|
Chain = SDValue(CNode, 2);
|
|
|
|
InFlag = SDValue(CNode, 3);
|
|
|
|
} else {
|
|
|
|
SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
|
2013-04-19 22:22:57 +00:00
|
|
|
SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
|
2012-09-26 08:22:37 +00:00
|
|
|
Chain = SDValue(CNode, 0);
|
|
|
|
InFlag = SDValue(CNode, 1);
|
|
|
|
}
|
it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul. This one fell back
to the default implementation that did a hi/lo multiply and compared the
top. Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test. Now we compile:
void *func(long count) {
return new int[count];
}
into:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
seto %cl ## encoding: [0x0f,0x90,0xc1]
testb %cl, %cl ## encoding: [0x84,0xc9]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
instead of:
__Z4funcl: ## @_Z4funcl
movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
mulq %rcx ## encoding: [0x48,0xf7,0xe1]
testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2]
movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8]
jmp __Znam ## TAILCALL
Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-05 07:30:36 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
// Update the chain.
|
2012-09-26 08:22:37 +00:00
|
|
|
ReplaceUses(N1.getValue(1), Chain);
|
2009-08-02 16:10:52 +00:00
|
|
|
} else {
|
2012-09-26 08:22:37 +00:00
|
|
|
SDValue Ops[] = { N1, InFlag };
|
|
|
|
if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
|
|
|
|
SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
|
2013-04-19 22:22:57 +00:00
|
|
|
SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
|
2012-09-26 08:22:37 +00:00
|
|
|
ResHi = SDValue(CNode, 0);
|
|
|
|
ResLo = SDValue(CNode, 1);
|
|
|
|
InFlag = SDValue(CNode, 2);
|
|
|
|
} else {
|
|
|
|
SDVTList VTs = CurDAG->getVTList(MVT::Glue);
|
2013-04-19 22:22:57 +00:00
|
|
|
SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
|
2012-09-26 08:22:37 +00:00
|
|
|
InFlag = SDValue(CNode, 0);
|
|
|
|
}
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
|
|
|
|
2010-06-26 00:39:23 +00:00
|
|
|
// Prevent use of AH in a REX instruction by referencing AX instead.
|
|
|
|
if (HiReg == X86::AH && Subtarget->is64Bit() &&
|
|
|
|
!SDValue(Node, 1).use_empty()) {
|
|
|
|
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
|
|
X86::AX, MVT::i16, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
|
|
|
// Get the low part if needed. Don't use getCopyFromReg for aliasing
|
|
|
|
// registers.
|
|
|
|
if (!SDValue(Node, 0).use_empty())
|
|
|
|
ReplaceUses(SDValue(Node, 1),
|
|
|
|
CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
|
|
|
|
|
|
|
|
// Shift AX down 8 bits.
|
|
|
|
Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
|
|
|
|
Result,
|
|
|
|
CurDAG->getTargetConstant(8, MVT::i8)), 0);
|
|
|
|
// Then truncate it down to i8.
|
|
|
|
ReplaceUses(SDValue(Node, 1),
|
|
|
|
CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
|
|
|
|
}
|
2009-08-02 16:10:52 +00:00
|
|
|
// Copy the low half of the result, if it is needed.
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SDValue(Node, 0).use_empty()) {
|
2012-09-26 08:22:37 +00:00
|
|
|
if (ResLo.getNode() == 0) {
|
|
|
|
assert(LoReg && "Register for low half is not defined!");
|
|
|
|
ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
|
|
|
|
InFlag);
|
|
|
|
InFlag = ResLo.getValue(2);
|
|
|
|
}
|
|
|
|
ReplaceUses(SDValue(Node, 0), ResLo);
|
|
|
|
DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
|
|
|
// Copy the high half of the result, if it is needed.
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SDValue(Node, 1).use_empty()) {
|
2012-09-26 08:22:37 +00:00
|
|
|
if (ResHi.getNode() == 0) {
|
|
|
|
assert(HiReg && "Register for high half is not defined!");
|
|
|
|
ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
|
|
|
|
InFlag);
|
|
|
|
InFlag = ResHi.getValue(2);
|
|
|
|
}
|
|
|
|
ReplaceUses(SDValue(Node, 1), ResHi);
|
|
|
|
DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
case ISD::SDIVREM:
|
|
|
|
case ISD::UDIVREM: {
|
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
2006-01-06 23:19:29 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
bool isSigned = Opcode == ISD::SDIVREM;
|
2009-08-07 21:33:25 +00:00
|
|
|
if (!isSigned) {
|
2013-08-15 05:57:07 +00:00
|
|
|
switch (NVT.SimpleTy) {
|
2009-08-02 16:10:52 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
|
|
|
|
case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
|
|
|
|
case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
|
|
|
|
case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
2009-08-07 21:33:25 +00:00
|
|
|
} else {
|
2013-08-15 05:57:07 +00:00
|
|
|
switch (NVT.SimpleTy) {
|
2009-07-14 16:55:14 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
|
|
|
|
case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
|
|
|
|
case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
|
|
|
|
case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
2009-08-07 21:33:25 +00:00
|
|
|
}
|
2006-01-06 23:19:29 +00:00
|
|
|
|
2009-12-23 01:45:04 +00:00
|
|
|
unsigned LoReg, HiReg, ClrReg;
|
2013-05-30 13:19:42 +00:00
|
|
|
unsigned SExtOpcode;
|
2013-08-15 05:57:07 +00:00
|
|
|
switch (NVT.SimpleTy) {
|
2009-08-02 16:10:52 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8:
|
2009-12-23 01:45:04 +00:00
|
|
|
LoReg = X86::AL; ClrReg = HiReg = X86::AH;
|
2009-08-02 16:10:52 +00:00
|
|
|
SExtOpcode = X86::CBW;
|
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i16:
|
2009-08-02 16:10:52 +00:00
|
|
|
LoReg = X86::AX; HiReg = X86::DX;
|
2013-05-30 13:19:42 +00:00
|
|
|
ClrReg = X86::DX;
|
2009-08-02 16:10:52 +00:00
|
|
|
SExtOpcode = X86::CWD;
|
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i32:
|
2009-12-23 01:45:04 +00:00
|
|
|
LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
|
2009-08-02 16:10:52 +00:00
|
|
|
SExtOpcode = X86::CDQ;
|
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i64:
|
2009-12-23 01:45:04 +00:00
|
|
|
LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
|
2009-08-02 16:10:52 +00:00
|
|
|
SExtOpcode = X86::CQO;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
|
2010-01-05 01:24:18 +00:00
|
|
|
bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
2009-08-02 16:10:52 +00:00
|
|
|
bool signBitIsZero = CurDAG->SignBitIsZero(N0);
|
|
|
|
|
|
|
|
SDValue InFlag;
|
2009-08-11 20:47:22 +00:00
|
|
|
if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
|
2009-08-02 16:10:52 +00:00
|
|
|
// Special case for div8, just use a move with zero extension to AX to
|
|
|
|
// clear the upper 8 bits (AH).
|
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
|
2010-01-05 01:24:18 +00:00
|
|
|
if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
|
2009-08-02 16:10:52 +00:00
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
|
|
|
|
Move =
|
2011-05-20 19:04:40 +00:00
|
|
|
SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
|
2013-04-19 22:22:57 +00:00
|
|
|
MVT::Other, Ops), 0);
|
2009-08-02 16:10:52 +00:00
|
|
|
Chain = Move.getValue(1);
|
|
|
|
ReplaceUses(N0.getValue(1), Chain);
|
2006-11-17 22:10:14 +00:00
|
|
|
} else {
|
2009-08-02 16:10:52 +00:00
|
|
|
Move =
|
2011-05-20 19:04:40 +00:00
|
|
|
SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
|
2009-08-02 16:10:52 +00:00
|
|
|
Chain = CurDAG->getEntryNode();
|
|
|
|
}
|
2011-05-20 19:04:40 +00:00
|
|
|
Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
|
2009-08-02 16:10:52 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
} else {
|
|
|
|
InFlag =
|
|
|
|
CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
|
|
|
|
LoReg, N0, SDValue()).getValue(1);
|
|
|
|
if (isSigned && !signBitIsZero) {
|
|
|
|
// Sign extend the low part into the high part.
|
2006-11-17 22:10:14 +00:00
|
|
|
InFlag =
|
2010-12-21 02:38:05 +00:00
|
|
|
SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
|
2009-08-02 16:10:52 +00:00
|
|
|
} else {
|
|
|
|
// Zero out the high part, effectively zero extending the input.
|
2013-05-30 13:19:42 +00:00
|
|
|
SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
|
2013-08-15 05:57:07 +00:00
|
|
|
switch (NVT.SimpleTy) {
|
2013-05-30 13:19:42 +00:00
|
|
|
case MVT::i16:
|
|
|
|
ClrNode =
|
|
|
|
SDValue(CurDAG->getMachineNode(
|
|
|
|
TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
|
|
|
|
CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
|
|
|
|
0);
|
|
|
|
break;
|
|
|
|
case MVT::i32:
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
ClrNode =
|
|
|
|
SDValue(CurDAG->getMachineNode(
|
|
|
|
TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
|
|
|
|
CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
|
|
|
|
CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
|
|
|
|
0);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected division source");
|
|
|
|
}
|
|
|
|
|
2009-12-23 01:45:04 +00:00
|
|
|
InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
|
2009-08-02 16:10:52 +00:00
|
|
|
ClrNode, InFlag).getValue(1);
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
2006-01-06 23:19:29 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
if (foldedLoad) {
|
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
|
|
|
|
InFlag };
|
|
|
|
SDNode *CNode =
|
2013-04-19 22:22:57 +00:00
|
|
|
CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
|
2009-08-02 16:10:52 +00:00
|
|
|
InFlag = SDValue(CNode, 1);
|
|
|
|
// Update the chain.
|
|
|
|
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
|
|
|
|
} else {
|
|
|
|
InFlag =
|
2010-12-21 02:38:05 +00:00
|
|
|
SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
|
|
|
|
2010-06-26 00:39:23 +00:00
|
|
|
// Prevent use of AH in a REX instruction by referencing AX instead.
|
|
|
|
// Shift it down 8 bits.
|
2013-07-09 02:07:28 +00:00
|
|
|
//
|
|
|
|
// The current assumption of the register allocator is that isel
|
|
|
|
// won't generate explicit references to the GPR8_NOREX registers. If
|
|
|
|
// the allocator and/or the backend get enhanced to be more robust in
|
|
|
|
// that regard, this can be, and should be, removed.
|
2010-06-26 00:39:23 +00:00
|
|
|
if (HiReg == X86::AH && Subtarget->is64Bit() &&
|
|
|
|
!SDValue(Node, 1).use_empty()) {
|
|
|
|
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
|
|
X86::AX, MVT::i16, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
|
|
|
|
|
|
|
// If we also need AL (the quotient), get it by extracting a subreg from
|
|
|
|
// Result. The fast register allocator does not like multiple CopyFromReg
|
|
|
|
// nodes using aliasing registers.
|
|
|
|
if (!SDValue(Node, 0).use_empty())
|
|
|
|
ReplaceUses(SDValue(Node, 0),
|
|
|
|
CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
|
|
|
|
|
|
|
|
// Shift AX right by 8 bits instead of using AH.
|
|
|
|
Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
|
|
|
|
Result,
|
|
|
|
CurDAG->getTargetConstant(8, MVT::i8)),
|
|
|
|
0);
|
|
|
|
ReplaceUses(SDValue(Node, 1),
|
|
|
|
CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
|
|
|
|
}
|
2009-08-02 16:10:52 +00:00
|
|
|
// Copy the division (low) result, if it is needed.
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SDValue(Node, 0).use_empty()) {
|
2009-08-02 16:10:52 +00:00
|
|
|
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
|
|
LoReg, NVT, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
2010-01-05 01:24:18 +00:00
|
|
|
ReplaceUses(SDValue(Node, 0), Result);
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
|
|
|
// Copy the remainder (high) result, if it is needed.
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SDValue(Node, 1).use_empty()) {
|
2010-06-26 00:39:23 +00:00
|
|
|
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
|
|
HiReg, NVT, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
2010-01-05 01:24:18 +00:00
|
|
|
ReplaceUses(SDValue(Node, 1), Result);
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2012-08-08 00:51:41 +00:00
|
|
|
case X86ISD::CMP:
|
|
|
|
case X86ISD::SUB: {
|
|
|
|
// Sometimes a SUB is used to perform comparison.
|
|
|
|
if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
|
|
|
|
// This node is not a CMP.
|
|
|
|
break;
|
2009-08-19 18:16:17 +00:00
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
|
|
|
|
|
|
|
// Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
|
|
|
|
// use a smaller encoding.
|
2010-08-04 22:40:58 +00:00
|
|
|
if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
|
|
|
|
HasNoSignedComparisonUses(Node))
|
2010-04-28 08:30:49 +00:00
|
|
|
// Look past the truncate if CMP is the only use of it.
|
|
|
|
N0 = N0.getOperand(0);
|
2011-11-03 21:49:52 +00:00
|
|
|
if ((N0.getNode()->getOpcode() == ISD::AND ||
|
|
|
|
(N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
|
|
|
|
N0.getNode()->hasOneUse() &&
|
2009-08-19 18:16:17 +00:00
|
|
|
N0.getValueType() != MVT::i8 &&
|
|
|
|
X86::isZeroNode(N1)) {
|
|
|
|
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
|
|
|
|
if (!C) break;
|
|
|
|
|
|
|
|
// For example, convert "testl %eax, $8" to "testb %al, $8"
|
2009-10-09 20:35:19 +00:00
|
|
|
if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
|
|
|
|
(!(C->getZExtValue() & 0x80) ||
|
|
|
|
HasNoSignedComparisonUses(Node))) {
|
2009-08-19 18:16:17 +00:00
|
|
|
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
|
|
|
|
SDValue Reg = N0.getNode()->getOperand(0);
|
|
|
|
|
|
|
|
// On x86-32, only the ABCD registers have 8-bit subregisters.
|
|
|
|
if (!Subtarget->is64Bit()) {
|
2012-02-22 07:28:11 +00:00
|
|
|
const TargetRegisterClass *TRC;
|
2013-08-15 02:33:50 +00:00
|
|
|
switch (N0.getSimpleValueType().SimpleTy) {
|
2009-08-19 18:16:17 +00:00
|
|
|
case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
|
|
|
|
case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
|
|
|
|
default: llvm_unreachable("Unsupported TEST operand type!");
|
|
|
|
}
|
|
|
|
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
|
2009-09-25 18:54:59 +00:00
|
|
|
Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
|
|
|
|
Reg.getValueType(), Reg, RC), 0);
|
2009-08-19 18:16:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Extract the l-register.
|
2010-05-24 14:48:17 +00:00
|
|
|
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
|
2009-08-19 18:16:17 +00:00
|
|
|
MVT::i8, Reg);
|
|
|
|
|
|
|
|
// Emit a testb.
|
2012-09-28 18:53:24 +00:00
|
|
|
SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
|
|
|
|
Subreg, Imm);
|
|
|
|
// Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
|
|
|
|
// one, do not call ReplaceAllUsesWith.
|
|
|
|
ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
|
|
|
|
SDValue(NewNode, 0));
|
|
|
|
return NULL;
|
2009-08-19 18:16:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// For example, "testl %eax, $2048" to "testb %ah, $8".
|
2009-10-09 20:35:19 +00:00
|
|
|
if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
|
|
|
|
(!(C->getZExtValue() & 0x8000) ||
|
|
|
|
HasNoSignedComparisonUses(Node))) {
|
2009-08-19 18:16:17 +00:00
|
|
|
// Shift the immediate right by 8 bits.
|
|
|
|
SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
|
|
|
|
MVT::i8);
|
|
|
|
SDValue Reg = N0.getNode()->getOperand(0);
|
|
|
|
|
|
|
|
// Put the value in an ABCD register.
|
2012-02-22 07:28:11 +00:00
|
|
|
const TargetRegisterClass *TRC;
|
2013-08-15 02:33:50 +00:00
|
|
|
switch (N0.getSimpleValueType().SimpleTy) {
|
2009-08-19 18:16:17 +00:00
|
|
|
case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
|
|
|
|
case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
|
|
|
|
case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
|
|
|
|
default: llvm_unreachable("Unsupported TEST operand type!");
|
|
|
|
}
|
|
|
|
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
|
2009-09-25 18:54:59 +00:00
|
|
|
Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
|
|
|
|
Reg.getValueType(), Reg, RC), 0);
|
2009-08-19 18:16:17 +00:00
|
|
|
|
|
|
|
// Extract the h-register.
|
2010-05-24 14:48:17 +00:00
|
|
|
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
|
2009-08-19 18:16:17 +00:00
|
|
|
MVT::i8, Reg);
|
|
|
|
|
2011-10-08 18:28:28 +00:00
|
|
|
// Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
|
|
|
|
// target GR8_NOREX registers, so make sure the register class is
|
|
|
|
// forced.
|
2012-09-28 18:53:24 +00:00
|
|
|
SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
|
|
|
|
MVT::i32, Subreg, ShiftedImm);
|
|
|
|
// Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
|
|
|
|
// one, do not call ReplaceAllUsesWith.
|
|
|
|
ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
|
|
|
|
SDValue(NewNode, 0));
|
|
|
|
return NULL;
|
2009-08-19 18:16:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// For example, "testl %eax, $32776" to "testw %ax, $32776".
|
|
|
|
if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
|
2009-10-09 20:35:19 +00:00
|
|
|
N0.getValueType() != MVT::i16 &&
|
|
|
|
(!(C->getZExtValue() & 0x8000) ||
|
|
|
|
HasNoSignedComparisonUses(Node))) {
|
2009-08-19 18:16:17 +00:00
|
|
|
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
|
|
|
|
SDValue Reg = N0.getNode()->getOperand(0);
|
|
|
|
|
|
|
|
// Extract the 16-bit subregister.
|
2010-05-24 14:48:17 +00:00
|
|
|
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
|
2009-08-19 18:16:17 +00:00
|
|
|
MVT::i16, Reg);
|
|
|
|
|
|
|
|
// Emit a testw.
|
2012-09-28 18:53:24 +00:00
|
|
|
SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
|
|
|
|
Subreg, Imm);
|
|
|
|
// Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
|
|
|
|
// one, do not call ReplaceAllUsesWith.
|
|
|
|
ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
|
|
|
|
SDValue(NewNode, 0));
|
|
|
|
return NULL;
|
2009-08-19 18:16:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// For example, "testq %rax, $268468232" to "testl %eax, $268468232".
|
|
|
|
if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
|
2009-10-09 20:35:19 +00:00
|
|
|
N0.getValueType() == MVT::i64 &&
|
|
|
|
(!(C->getZExtValue() & 0x80000000) ||
|
|
|
|
HasNoSignedComparisonUses(Node))) {
|
2009-08-19 18:16:17 +00:00
|
|
|
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
|
|
|
|
SDValue Reg = N0.getNode()->getOperand(0);
|
|
|
|
|
|
|
|
// Extract the 32-bit subregister.
|
2010-05-24 14:48:17 +00:00
|
|
|
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
|
2009-08-19 18:16:17 +00:00
|
|
|
MVT::i32, Reg);
|
|
|
|
|
|
|
|
// Emit a testl.
|
2012-09-28 18:53:24 +00:00
|
|
|
SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
|
|
|
|
Subreg, Imm);
|
|
|
|
// Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
|
|
|
|
// one, do not call ReplaceAllUsesWith.
|
|
|
|
ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
|
|
|
|
SDValue(NewNode, 0));
|
|
|
|
return NULL;
|
2009-08-19 18:16:17 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2011-11-15 21:57:53 +00:00
|
|
|
case ISD::STORE: {
|
2012-03-29 05:45:48 +00:00
|
|
|
// Change a chain of {load; incr or dec; store} of the same value into
|
|
|
|
// a simple increment or decrement through memory of that value, if the
|
|
|
|
// uses of the modified value and its address are suitable.
|
2011-11-16 19:03:23 +00:00
|
|
|
// The DEC64m tablegen pattern is currently not able to match the case where
|
2012-08-01 18:39:17 +00:00
|
|
|
// the EFLAGS on the original DEC are used. (This also applies to
|
2012-03-29 05:45:48 +00:00
|
|
|
// {INC,DEC}X{64,32,16,8}.)
|
|
|
|
// We'll need to improve tablegen to allow flags to be transferred from a
|
2011-11-16 19:03:23 +00:00
|
|
|
// node in the pattern to the result node. probably with a new keyword
|
|
|
|
// for example, we have this
|
|
|
|
// def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
|
|
|
|
// [(store (add (loadi64 addr:$dst), -1), addr:$dst),
|
|
|
|
// (implicit EFLAGS)]>;
|
|
|
|
// but maybe need something like this
|
|
|
|
// def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
|
|
|
|
// [(store (add (loadi64 addr:$dst), -1), addr:$dst),
|
|
|
|
// (transferrable EFLAGS)]>;
|
2012-03-29 05:45:48 +00:00
|
|
|
|
2011-11-15 21:57:53 +00:00
|
|
|
StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
|
|
|
|
SDValue StoredVal = StoreNode->getOperand(1);
|
2012-03-29 05:45:48 +00:00
|
|
|
unsigned Opc = StoredVal->getOpcode();
|
2011-11-15 21:57:53 +00:00
|
|
|
|
2012-04-12 19:14:21 +00:00
|
|
|
LoadSDNode *LoadNode = 0;
|
|
|
|
SDValue InputChain;
|
|
|
|
if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
|
|
|
|
LoadNode, InputChain))
|
|
|
|
break;
|
2011-11-15 21:57:53 +00:00
|
|
|
|
|
|
|
SDValue Base, Scale, Index, Disp, Segment;
|
|
|
|
if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
|
|
|
|
Base, Scale, Index, Disp, Segment))
|
|
|
|
break;
|
|
|
|
|
|
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
|
|
|
|
MemOp[0] = StoreNode->getMemOperand();
|
|
|
|
MemOp[1] = LoadNode->getMemOperand();
|
|
|
|
const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
|
2012-08-01 18:39:17 +00:00
|
|
|
EVT LdVT = LoadNode->getMemoryVT();
|
2012-03-29 05:45:48 +00:00
|
|
|
unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
|
|
|
|
MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc(Node),
|
2013-04-19 22:22:57 +00:00
|
|
|
MVT::i32, MVT::Other, Ops);
|
2011-11-15 21:57:53 +00:00
|
|
|
Result->setMemRefs(MemOp, MemOp + 2);
|
|
|
|
|
|
|
|
ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
|
|
|
|
ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
|
|
|
|
|
|
|
|
return Result;
|
|
|
|
}
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|
|
|
|
|
2010-01-05 01:24:18 +00:00
|
|
|
SDNode *ResNode = SelectCode(Node);
|
2006-08-11 09:08:15 +00:00
|
|
|
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "=> ";
|
|
|
|
if (ResNode == NULL || ResNode == Node)
|
|
|
|
Node->dump(CurDAG);
|
|
|
|
else
|
|
|
|
ResNode->dump(CurDAG);
|
|
|
|
dbgs() << '\n');
|
2006-08-11 09:08:15 +00:00
|
|
|
|
|
|
|
return ResNode;
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|
|
|
|
|
2006-06-08 18:03:49 +00:00
|
|
|
bool X86DAGToDAGISel::
|
2008-07-27 21:46:04 +00:00
|
|
|
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
|
2008-08-23 02:25:05 +00:00
|
|
|
std::vector<SDValue> &OutOps) {
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue Op0, Op1, Op2, Op3, Op4;
|
2006-06-08 18:03:49 +00:00
|
|
|
switch (ConstraintCode) {
|
|
|
|
case 'o': // offsetable ??
|
|
|
|
case 'v': // not offsetable ??
|
|
|
|
default: return true;
|
|
|
|
case 'm': // memory
|
2010-09-21 22:07:31 +00:00
|
|
|
if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
|
2006-06-08 18:03:49 +00:00
|
|
|
return true;
|
|
|
|
break;
|
|
|
|
}
|
2012-08-01 18:39:17 +00:00
|
|
|
|
2006-08-26 01:05:16 +00:00
|
|
|
OutOps.push_back(Op0);
|
|
|
|
OutOps.push_back(Op1);
|
|
|
|
OutOps.push_back(Op2);
|
|
|
|
OutOps.push_back(Op3);
|
2009-04-08 21:14:34 +00:00
|
|
|
OutOps.push_back(Op4);
|
2006-06-08 18:03:49 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-08-01 18:39:17 +00:00
|
|
|
/// createX86ISelDag - This pass converts a legalized DAG into a
|
2005-11-16 01:54:32 +00:00
|
|
|
/// X86-specific DAG, ready for instruction scheduling.
|
|
|
|
///
|
2009-04-29 23:29:43 +00:00
|
|
|
FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
|
2012-03-27 07:21:54 +00:00
|
|
|
CodeGenOpt::Level OptLevel) {
|
2009-04-29 00:15:41 +00:00
|
|
|
return new X86DAGToDAGISel(TM, OptLevel);
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|