2010-07-21 22:26:11 +00:00
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//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the ARM-specific support for the FastISel class. Some
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// of the target-specific code is generated by tablegen in the file
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// ARMGenFastISel.inc, which is #included here.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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2010-08-19 00:37:05 +00:00
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#include "ARMBaseInstrInfo.h"
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2010-09-10 23:18:12 +00:00
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#include "ARMCallingConv.h"
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2010-07-21 22:26:11 +00:00
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#include "ARMTargetMachine.h"
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#include "ARMSubtarget.h"
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2010-10-01 23:24:42 +00:00
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#include "ARMConstantPoolValue.h"
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2011-07-20 23:34:39 +00:00
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#include "MCTargetDesc/ARMAddressingModes.h"
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2010-07-21 22:26:11 +00:00
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/Instructions.h"
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#include "llvm/IntrinsicInst.h"
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2010-09-14 23:03:37 +00:00
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#include "llvm/Module.h"
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2011-04-11 09:35:34 +00:00
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#include "llvm/Operator.h"
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2010-07-21 22:26:11 +00:00
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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2010-08-17 01:25:29 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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2010-07-21 22:26:11 +00:00
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2010-10-17 01:51:42 +00:00
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#include "llvm/CodeGen/MachineMemOperand.h"
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2010-07-21 22:26:11 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CallSite.h"
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2010-08-17 00:46:57 +00:00
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#include "llvm/Support/CommandLine.h"
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2010-07-21 22:26:11 +00:00
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/GetElementPtrTypeIterator.h"
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2012-10-08 16:38:25 +00:00
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#include "llvm/DataLayout.h"
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2010-08-17 01:25:29 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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2010-07-21 22:26:11 +00:00
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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2010-12-15 23:47:29 +00:00
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extern cl::opt<bool> EnableARMLongCalls;
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2010-07-21 22:26:11 +00:00
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namespace {
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2010-11-20 22:38:27 +00:00
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2010-11-19 22:30:02 +00:00
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// All possible address modes, plus some.
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typedef struct Address {
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enum {
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RegBase,
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FrameIndexBase
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} BaseType;
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2010-11-20 22:38:27 +00:00
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2010-11-19 22:30:02 +00:00
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union {
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unsigned Reg;
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int FI;
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} Base;
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2010-11-20 22:38:27 +00:00
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2010-11-19 22:30:02 +00:00
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int Offset;
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2010-11-20 22:38:27 +00:00
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2010-11-19 22:30:02 +00:00
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// Innocuous defaults for our address.
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Address()
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2011-05-16 22:24:07 +00:00
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: BaseType(RegBase), Offset(0) {
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2010-11-19 22:30:02 +00:00
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Base.Reg = 0;
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}
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} Address;
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2010-07-21 22:26:11 +00:00
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class ARMFastISel : public FastISel {
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const ARMSubtarget *Subtarget;
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2010-08-17 01:25:29 +00:00
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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2010-10-01 23:24:42 +00:00
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ARMFunctionInfo *AFI;
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2010-07-21 22:26:11 +00:00
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2010-09-29 22:24:45 +00:00
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// Convenience variables to avoid some queries.
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2011-11-08 21:12:00 +00:00
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bool isThumb2;
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2010-09-29 22:24:45 +00:00
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LLVMContext *Context;
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2010-09-02 01:39:14 +00:00
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2010-07-21 22:26:11 +00:00
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public:
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2012-08-03 04:06:28 +00:00
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explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo)
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: FastISel(funcInfo, libInfo),
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2010-08-17 01:25:29 +00:00
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TM(funcInfo.MF->getTarget()),
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TII(*TM.getInstrInfo()),
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TLI(*TM.getTargetLowering()) {
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2010-07-21 22:26:11 +00:00
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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2010-08-23 22:32:45 +00:00
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AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
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2011-11-08 21:12:00 +00:00
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isThumb2 = AFI->isThumbFunction();
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2010-09-29 22:24:45 +00:00
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Context = &funcInfo.Fn->getContext();
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2010-07-21 22:26:11 +00:00
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}
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2010-08-20 00:20:31 +00:00
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// Code from FastISel.cpp.
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2012-08-18 21:38:45 +00:00
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private:
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unsigned FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC);
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unsigned FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill);
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unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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unsigned Op2, bool Op2IsKill);
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unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm);
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unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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const ConstantFP *FPImm);
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unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm);
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unsigned FastEmitInst_i(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm);
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unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm1, uint64_t Imm2);
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unsigned FastEmitInst_extractsubreg(MVT RetVT,
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unsigned Op0, bool Op0IsKill,
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uint32_t Idx);
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2010-09-09 01:06:51 +00:00
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2010-08-20 00:20:31 +00:00
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// Backend specific FastISel code.
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2012-08-18 21:38:45 +00:00
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private:
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2010-07-21 22:26:11 +00:00
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virtual bool TargetSelectInstruction(const Instruction *I);
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2010-09-02 01:48:11 +00:00
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virtual unsigned TargetMaterializeConstant(const Constant *C);
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2010-09-30 20:49:44 +00:00
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virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
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2011-11-13 02:23:59 +00:00
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virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
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const LoadInst *LI);
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2012-08-18 21:38:45 +00:00
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private:
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2010-07-21 22:26:11 +00:00
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#include "ARMGenFastISel.inc"
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2010-09-09 01:06:51 +00:00
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2010-08-23 21:44:12 +00:00
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// Instruction selection routines.
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2010-09-10 23:10:30 +00:00
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private:
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2010-10-21 21:47:51 +00:00
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bool SelectLoad(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool SelectBranch(const Instruction *I);
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2012-02-07 23:56:08 +00:00
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bool SelectIndirectBr(const Instruction *I);
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2010-10-21 21:47:51 +00:00
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bool SelectCmp(const Instruction *I);
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bool SelectFPExt(const Instruction *I);
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bool SelectFPTrunc(const Instruction *I);
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2012-02-06 23:50:07 +00:00
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bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
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bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
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2012-02-03 21:14:11 +00:00
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bool SelectIToFP(const Instruction *I, bool isSigned);
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bool SelectFPToI(const Instruction *I, bool isSigned);
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2012-02-03 21:07:27 +00:00
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bool SelectDiv(const Instruction *I, bool isSigned);
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2012-02-03 21:23:45 +00:00
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bool SelectRem(const Instruction *I, bool isSigned);
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2011-11-11 23:31:03 +00:00
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bool SelectCall(const Instruction *I, const char *IntrMemName);
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bool SelectIntrinsicCall(const IntrinsicInst &I);
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2010-10-21 21:47:51 +00:00
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bool SelectSelect(const Instruction *I);
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2010-10-22 01:28:00 +00:00
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bool SelectRet(const Instruction *I);
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2011-11-02 00:18:48 +00:00
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bool SelectTrunc(const Instruction *I);
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bool SelectIntExt(const Instruction *I);
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2012-08-03 02:37:48 +00:00
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bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
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2010-07-21 22:26:11 +00:00
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2010-08-23 21:44:12 +00:00
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// Utility routines.
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2010-08-19 00:37:05 +00:00
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private:
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2011-07-18 04:54:35 +00:00
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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2011-11-02 18:08:25 +00:00
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bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
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bool isZExt);
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2011-12-14 17:26:05 +00:00
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
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unsigned Alignment = 0, bool isZExt = true,
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bool allocReg = true);
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2011-12-04 00:52:23 +00:00
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bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment = 0);
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2010-11-19 22:30:02 +00:00
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bool ARMComputeAddress(const Value *Obj, Address &Addr);
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2011-11-13 02:23:59 +00:00
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void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
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2011-11-14 23:04:09 +00:00
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bool ARMIsMemCpySmall(uint64_t Len);
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bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len);
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2011-11-02 17:20:24 +00:00
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unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
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2010-09-09 00:19:41 +00:00
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unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
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2010-09-28 22:47:54 +00:00
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unsigned ARMMaterializeInt(const Constant *C, EVT VT);
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2010-10-01 23:24:42 +00:00
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unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
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2010-09-09 20:49:25 +00:00
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unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
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2010-09-09 21:44:45 +00:00
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unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
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2012-06-12 19:25:13 +00:00
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unsigned ARMSelectCallOp(bool UseReg);
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2012-09-27 05:21:41 +00:00
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unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, EVT VT);
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2010-09-09 01:06:51 +00:00
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2010-09-10 23:18:12 +00:00
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// Call handling routines.
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private:
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2012-07-19 09:49:00 +00:00
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CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
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bool Return,
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bool isVarArg);
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2010-10-11 08:38:55 +00:00
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bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
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2010-09-29 23:11:09 +00:00
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SmallVectorImpl<unsigned> &ArgRegs,
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2010-11-03 11:35:31 +00:00
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SmallVectorImpl<MVT> &ArgVTs,
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2010-09-29 23:11:09 +00:00
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SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
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SmallVectorImpl<unsigned> &RegArgs,
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CallingConv::ID CC,
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2012-07-19 09:49:00 +00:00
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unsigned &NumBytes,
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bool isVarArg);
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2012-06-12 19:25:13 +00:00
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unsigned getLibcallReg(const Twine &Name);
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2010-11-03 11:35:31 +00:00
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bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
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2010-09-29 23:11:09 +00:00
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const Instruction *I, CallingConv::ID CC,
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2012-07-19 09:49:00 +00:00
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unsigned &NumBytes, bool isVarArg);
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2010-09-28 01:21:42 +00:00
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bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
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2010-09-10 23:18:12 +00:00
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// OptionalDef handling routines.
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private:
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2011-03-12 01:09:29 +00:00
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bool isARMNEONPred(const MachineInstr *MI);
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2010-08-19 00:37:05 +00:00
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bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
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const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
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2010-12-01 01:40:24 +00:00
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void AddLoadStoreOperands(EVT VT, Address &Addr,
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2011-05-28 20:34:49 +00:00
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const MachineInstrBuilder &MIB,
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2011-11-13 02:23:59 +00:00
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unsigned Flags, bool useAM3);
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2010-08-19 00:37:05 +00:00
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};
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2010-07-21 22:26:11 +00:00
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} // end anonymous namespace
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2010-09-10 23:18:12 +00:00
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#include "ARMGenCallingConv.inc"
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2010-07-21 22:26:11 +00:00
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2010-08-19 00:37:05 +00:00
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// DefinesOptionalPredicate - This is different from DefinesPredicate in that
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// we don't care about implicit defs here, just places we'll need to add a
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// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
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bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
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2011-12-07 07:15:52 +00:00
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if (!MI->hasOptionalDef())
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2010-08-19 00:37:05 +00:00
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return false;
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// Look to see if our OptionalDef is defining CPSR or CCR.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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2010-08-20 00:36:24 +00:00
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if (!MO.isReg() || !MO.isDef()) continue;
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if (MO.getReg() == ARM::CPSR)
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2010-08-19 00:37:05 +00:00
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*CPSR = true;
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}
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return true;
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}
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2011-03-12 01:09:29 +00:00
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bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
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2011-06-28 19:10:37 +00:00
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const MCInstrDesc &MCID = MI->getDesc();
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2011-04-29 00:03:10 +00:00
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2011-03-12 01:09:29 +00:00
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// If we're a thumb2 or not NEON function we were handled via isPredicable.
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2011-06-28 19:10:37 +00:00
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if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
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2011-03-12 01:09:29 +00:00
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AFI->isThumb2Function())
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return false;
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2011-04-29 00:03:10 +00:00
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2011-06-28 19:10:37 +00:00
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for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
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if (MCID.OpInfo[i].isPredicate())
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2011-03-12 01:09:29 +00:00
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return true;
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2011-04-29 00:03:10 +00:00
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2011-03-12 01:09:29 +00:00
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return false;
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}
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|
2010-08-19 00:37:05 +00:00
|
|
|
// If the machine is predicable go ahead and add the predicate operands, if
|
|
|
|
// it needs default CC operands add those.
|
2010-11-02 01:21:28 +00:00
|
|
|
// TODO: If we want to support thumb1 then we'll need to deal with optional
|
|
|
|
// CPSR defs that need to be added before the remaining operands. See s_cc_out
|
|
|
|
// for descriptions why.
|
2010-08-19 00:37:05 +00:00
|
|
|
const MachineInstrBuilder &
|
|
|
|
ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
|
|
|
|
MachineInstr *MI = &*MIB;
|
|
|
|
|
2011-03-12 01:09:29 +00:00
|
|
|
// Do we use a predicate? or...
|
|
|
|
// Are we NEON in ARM mode and have a predicate operand? If so, I know
|
|
|
|
// we're not predicable but add it anyways.
|
|
|
|
if (TII.isPredicable(MI) || isARMNEONPred(MI))
|
2010-08-19 00:37:05 +00:00
|
|
|
AddDefaultPred(MIB);
|
2011-04-29 00:03:10 +00:00
|
|
|
|
2012-09-27 10:14:43 +00:00
|
|
|
// Do we optionally set a predicate? Preds is size > 0 iff the predicate
|
2010-08-19 00:37:05 +00:00
|
|
|
// defines CPSR. All other OptionalDefines in ARM are the CCR register.
|
2010-08-19 15:35:27 +00:00
|
|
|
bool CPSR = false;
|
2010-08-19 00:37:05 +00:00
|
|
|
if (DefinesOptionalPredicate(MI, &CPSR)) {
|
|
|
|
if (CPSR)
|
|
|
|
AddDefaultT1CC(MIB);
|
|
|
|
else
|
|
|
|
AddDefaultCC(MIB);
|
|
|
|
}
|
|
|
|
return MIB;
|
|
|
|
}
|
|
|
|
|
2010-08-17 01:25:29 +00:00
|
|
|
unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass* RC) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
2010-08-17 01:25:29 +00:00
|
|
|
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
|
2010-08-17 01:25:29 +00:00
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0, bool Op0IsKill) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
2010-08-17 01:25:29 +00:00
|
|
|
|
2012-02-15 17:36:21 +00:00
|
|
|
if (II.getNumDefs() >= 1) {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill));
|
2012-02-15 17:36:21 +00:00
|
|
|
} else {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill));
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-08-17 01:25:29 +00:00
|
|
|
TII.get(TargetOpcode::COPY), ResultReg)
|
|
|
|
.addReg(II.ImplicitDefs[0]));
|
|
|
|
}
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0, bool Op0IsKill,
|
|
|
|
unsigned Op1, bool Op1IsKill) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
2010-08-17 01:25:29 +00:00
|
|
|
|
2012-02-15 17:36:21 +00:00
|
|
|
if (II.getNumDefs() >= 1) {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
|
|
|
.addReg(Op1, Op1IsKill * RegState::Kill));
|
2012-02-15 17:36:21 +00:00
|
|
|
} else {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
|
|
|
.addReg(Op1, Op1IsKill * RegState::Kill));
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-08-17 01:25:29 +00:00
|
|
|
TII.get(TargetOpcode::COPY), ResultReg)
|
|
|
|
.addReg(II.ImplicitDefs[0]));
|
|
|
|
}
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
2011-03-30 23:01:21 +00:00
|
|
|
unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0, bool Op0IsKill,
|
|
|
|
unsigned Op1, bool Op1IsKill,
|
|
|
|
unsigned Op2, bool Op2IsKill) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
2011-03-30 23:01:21 +00:00
|
|
|
|
2012-02-15 17:36:21 +00:00
|
|
|
if (II.getNumDefs() >= 1) {
|
2011-03-30 23:01:21 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
|
|
|
.addReg(Op1, Op1IsKill * RegState::Kill)
|
|
|
|
.addReg(Op2, Op2IsKill * RegState::Kill));
|
2012-02-15 17:36:21 +00:00
|
|
|
} else {
|
2011-03-30 23:01:21 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
|
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
|
|
|
.addReg(Op1, Op1IsKill * RegState::Kill)
|
|
|
|
.addReg(Op2, Op2IsKill * RegState::Kill));
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(TargetOpcode::COPY), ResultReg)
|
|
|
|
.addReg(II.ImplicitDefs[0]));
|
|
|
|
}
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
2010-08-17 01:25:29 +00:00
|
|
|
unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0, bool Op0IsKill,
|
|
|
|
uint64_t Imm) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
2010-08-17 01:25:29 +00:00
|
|
|
|
2012-02-15 17:36:21 +00:00
|
|
|
if (II.getNumDefs() >= 1) {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
|
|
|
.addImm(Imm));
|
2012-02-15 17:36:21 +00:00
|
|
|
} else {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
|
|
|
.addImm(Imm));
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-08-17 01:25:29 +00:00
|
|
|
TII.get(TargetOpcode::COPY), ResultReg)
|
|
|
|
.addReg(II.ImplicitDefs[0]));
|
|
|
|
}
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0, bool Op0IsKill,
|
|
|
|
const ConstantFP *FPImm) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
2010-08-17 01:25:29 +00:00
|
|
|
|
2012-02-15 17:36:21 +00:00
|
|
|
if (II.getNumDefs() >= 1) {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
|
|
|
.addFPImm(FPImm));
|
2012-02-15 17:36:21 +00:00
|
|
|
} else {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
|
|
|
.addFPImm(FPImm));
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-08-17 01:25:29 +00:00
|
|
|
TII.get(TargetOpcode::COPY), ResultReg)
|
|
|
|
.addReg(II.ImplicitDefs[0]));
|
|
|
|
}
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
unsigned Op0, bool Op0IsKill,
|
|
|
|
unsigned Op1, bool Op1IsKill,
|
|
|
|
uint64_t Imm) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
2010-08-17 01:25:29 +00:00
|
|
|
|
2012-02-15 17:36:21 +00:00
|
|
|
if (II.getNumDefs() >= 1) {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
|
|
|
.addReg(Op1, Op1IsKill * RegState::Kill)
|
|
|
|
.addImm(Imm));
|
2012-02-15 17:36:21 +00:00
|
|
|
} else {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addReg(Op0, Op0IsKill * RegState::Kill)
|
|
|
|
.addReg(Op1, Op1IsKill * RegState::Kill)
|
|
|
|
.addImm(Imm));
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-08-17 01:25:29 +00:00
|
|
|
TII.get(TargetOpcode::COPY), ResultReg)
|
|
|
|
.addReg(II.ImplicitDefs[0]));
|
|
|
|
}
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
uint64_t Imm) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2012-02-15 17:36:21 +00:00
|
|
|
if (II.getNumDefs() >= 1) {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addImm(Imm));
|
2012-02-15 17:36:21 +00:00
|
|
|
} else {
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
|
2010-08-17 01:25:29 +00:00
|
|
|
.addImm(Imm));
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-08-17 01:25:29 +00:00
|
|
|
TII.get(TargetOpcode::COPY), ResultReg)
|
|
|
|
.addReg(II.ImplicitDefs[0]));
|
|
|
|
}
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
2011-04-29 22:07:50 +00:00
|
|
|
unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
uint64_t Imm1, uint64_t Imm2) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &II = TII.get(MachineInstOpcode);
|
2011-06-08 23:55:35 +00:00
|
|
|
|
2012-02-15 17:36:21 +00:00
|
|
|
if (II.getNumDefs() >= 1) {
|
2011-04-29 22:07:50 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
|
|
|
|
.addImm(Imm1).addImm(Imm2));
|
2012-02-15 17:36:21 +00:00
|
|
|
} else {
|
2011-04-29 22:07:50 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
|
|
|
|
.addImm(Imm1).addImm(Imm2));
|
2011-06-08 23:55:35 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2011-04-29 22:07:50 +00:00
|
|
|
TII.get(TargetOpcode::COPY),
|
|
|
|
ResultReg)
|
|
|
|
.addReg(II.ImplicitDefs[0]));
|
|
|
|
}
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
2010-08-17 01:25:29 +00:00
|
|
|
unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
|
|
|
|
unsigned Op0, bool Op0IsKill,
|
|
|
|
uint32_t Idx) {
|
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
|
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
|
|
|
|
"Cannot yet extract from physregs");
|
2012-02-15 17:36:21 +00:00
|
|
|
|
2010-08-19 00:37:05 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
|
2012-02-15 17:36:21 +00:00
|
|
|
DL, TII.get(TargetOpcode::COPY), ResultReg)
|
|
|
|
.addReg(Op0, getKillRegState(Op0IsKill), Idx));
|
2010-08-17 01:25:29 +00:00
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
2010-09-10 00:34:35 +00:00
|
|
|
// TODO: Don't worry about 64-bit now, but when this is fixed remove the
|
|
|
|
// checks from the various callers.
|
2010-09-09 20:49:25 +00:00
|
|
|
unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
|
2010-11-03 12:17:33 +00:00
|
|
|
if (VT == MVT::f64) return 0;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-09 21:44:45 +00:00
|
|
|
unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2012-03-01 22:47:09 +00:00
|
|
|
TII.get(ARM::VMOVSR), MoveReg)
|
2010-09-09 21:44:45 +00:00
|
|
|
.addReg(SrcReg));
|
|
|
|
return MoveReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
|
2010-11-03 12:17:33 +00:00
|
|
|
if (VT == MVT::i64) return 0;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-09 20:49:25 +00:00
|
|
|
unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2012-03-01 22:47:09 +00:00
|
|
|
TII.get(ARM::VMOVRS), MoveReg)
|
2010-09-09 20:49:25 +00:00
|
|
|
.addReg(SrcReg));
|
|
|
|
return MoveReg;
|
|
|
|
}
|
|
|
|
|
2010-09-09 00:19:41 +00:00
|
|
|
// For double width floating point we need to materialize two constants
|
|
|
|
// (the high and the low) into integer registers then use a move to get
|
|
|
|
// the combined constant into an FP reg.
|
|
|
|
unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
|
|
|
|
const APFloat Val = CFP->getValueAPF();
|
2010-11-03 12:17:33 +00:00
|
|
|
bool is64bit = VT == MVT::f64;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-09-09 00:19:41 +00:00
|
|
|
// This checks to see if we can use VFP3 instructions to materialize
|
|
|
|
// a constant, otherwise we have to go through the constant pool.
|
|
|
|
if (TLI.isFPImmLegal(Val, VT)) {
|
2011-09-30 00:50:06 +00:00
|
|
|
int Imm;
|
|
|
|
unsigned Opc;
|
|
|
|
if (is64bit) {
|
|
|
|
Imm = ARM_AM::getFP64Imm(Val);
|
|
|
|
Opc = ARM::FCONSTD;
|
|
|
|
} else {
|
|
|
|
Imm = ARM_AM::getFP32Imm(Val);
|
|
|
|
Opc = ARM::FCONSTS;
|
|
|
|
}
|
2010-09-09 00:19:41 +00:00
|
|
|
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
|
|
|
|
DestReg)
|
2011-09-30 00:50:06 +00:00
|
|
|
.addImm(Imm));
|
2010-09-09 00:19:41 +00:00
|
|
|
return DestReg;
|
|
|
|
}
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-10 00:34:35 +00:00
|
|
|
// Require VFP2 for loading fp constants.
|
2010-09-09 23:50:00 +00:00
|
|
|
if (!Subtarget->hasVFP2()) return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-09 23:50:00 +00:00
|
|
|
// MachineConstantPool wants an explicit alignment.
|
|
|
|
unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
|
|
|
|
if (Align == 0) {
|
|
|
|
// TODO: Figure out if this is correct.
|
|
|
|
Align = TD.getTypeAllocSize(CFP->getType());
|
|
|
|
}
|
|
|
|
unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
|
|
|
|
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
|
|
|
|
unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-10 00:34:35 +00:00
|
|
|
// The extra reg is for addrmode5.
|
2010-09-28 00:35:09 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
|
|
|
|
DestReg)
|
|
|
|
.addConstantPoolIndex(Idx)
|
2010-09-09 23:50:00 +00:00
|
|
|
.addReg(0));
|
|
|
|
return DestReg;
|
2010-09-09 00:19:41 +00:00
|
|
|
}
|
2010-09-02 23:43:26 +00:00
|
|
|
|
2010-09-28 22:47:54 +00:00
|
|
|
unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2011-11-04 22:29:00 +00:00
|
|
|
if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
|
|
|
|
return false;
|
2010-11-03 20:21:17 +00:00
|
|
|
|
|
|
|
// If we can do this in a single instruction without a constant pool entry
|
|
|
|
// do so now.
|
|
|
|
const ConstantInt *CI = cast<ConstantInt>(C);
|
2011-11-04 23:09:49 +00:00
|
|
|
if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
|
2011-11-11 00:36:21 +00:00
|
|
|
unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
|
2010-11-03 20:21:17 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2011-11-04 22:29:00 +00:00
|
|
|
TII.get(Opc), ImmReg)
|
2011-11-05 20:16:15 +00:00
|
|
|
.addImm(CI->getZExtValue()));
|
2011-11-04 22:29:00 +00:00
|
|
|
return ImmReg;
|
2010-11-03 20:21:17 +00:00
|
|
|
}
|
|
|
|
|
2011-11-11 00:36:21 +00:00
|
|
|
// Use MVN to emit negative constants.
|
|
|
|
if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
|
|
|
|
unsigned Imm = (unsigned)~(CI->getSExtValue());
|
2011-11-11 06:27:41 +00:00
|
|
|
bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
|
2011-11-11 00:36:21 +00:00
|
|
|
(ARM_AM::getSOImmVal(Imm) != -1);
|
2011-11-11 06:27:41 +00:00
|
|
|
if (UseImm) {
|
2011-11-11 00:36:21 +00:00
|
|
|
unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
|
|
|
|
unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(Opc), ImmReg)
|
|
|
|
.addImm(Imm));
|
|
|
|
return ImmReg;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Load from constant pool. For now 32-bit only.
|
2011-11-04 22:29:00 +00:00
|
|
|
if (VT != MVT::i32)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
|
|
|
|
|
2010-09-02 23:43:26 +00:00
|
|
|
// MachineConstantPool wants an explicit alignment.
|
|
|
|
unsigned Align = TD.getPrefTypeAlignment(C->getType());
|
|
|
|
if (Align == 0) {
|
|
|
|
// TODO: Figure out if this is correct.
|
|
|
|
Align = TD.getTypeAllocSize(C->getType());
|
|
|
|
}
|
|
|
|
unsigned Idx = MCP.getConstantPoolIndex(C, Align);
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2011-11-08 21:12:00 +00:00
|
|
|
if (isThumb2)
|
2010-09-02 23:43:26 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-09-28 21:55:34 +00:00
|
|
|
TII.get(ARM::t2LDRpci), DestReg)
|
|
|
|
.addConstantPoolIndex(Idx));
|
2010-09-02 23:43:26 +00:00
|
|
|
else
|
2010-11-12 09:48:30 +00:00
|
|
|
// The extra immediate is for addrmode2.
|
2010-09-02 23:43:26 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-09-28 21:55:34 +00:00
|
|
|
TII.get(ARM::LDRcp), DestReg)
|
|
|
|
.addConstantPoolIndex(Idx)
|
2010-10-26 22:37:02 +00:00
|
|
|
.addImm(0));
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-09-02 23:43:26 +00:00
|
|
|
return DestReg;
|
2010-09-02 01:48:11 +00:00
|
|
|
}
|
|
|
|
|
2010-10-01 23:24:42 +00:00
|
|
|
unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
|
2010-10-02 00:32:44 +00:00
|
|
|
// For now 32-bit only.
|
2010-11-03 12:17:33 +00:00
|
|
|
if (VT != MVT::i32) return 0;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-10-02 00:32:44 +00:00
|
|
|
Reloc::Model RelocM = TM.getRelocationModel();
|
2012-08-29 02:41:21 +00:00
|
|
|
bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
|
2010-10-02 00:32:44 +00:00
|
|
|
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
|
2012-01-07 01:47:05 +00:00
|
|
|
|
|
|
|
// Use movw+movt when possible, it avoids constant pool entries.
|
2012-01-07 20:49:15 +00:00
|
|
|
// Darwin targets don't support movt with Reloc::Static, see
|
|
|
|
// ARMTargetLowering::LowerGlobalAddressDarwin. Other targets only support
|
|
|
|
// static movt relocations.
|
|
|
|
if (Subtarget->useMovt() &&
|
|
|
|
Subtarget->isTargetDarwin() == (RelocM != Reloc::Static)) {
|
2012-01-07 01:47:05 +00:00
|
|
|
unsigned Opc;
|
|
|
|
switch (RelocM) {
|
|
|
|
case Reloc::PIC_:
|
|
|
|
Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
|
|
|
|
break;
|
|
|
|
case Reloc::DynamicNoPIC:
|
|
|
|
Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
|
|
|
|
DestReg).addGlobalAddress(GV));
|
2010-10-02 00:32:44 +00:00
|
|
|
} else {
|
2012-01-07 01:47:05 +00:00
|
|
|
// MachineConstantPool wants an explicit alignment.
|
|
|
|
unsigned Align = TD.getPrefTypeAlignment(GV->getType());
|
|
|
|
if (Align == 0) {
|
|
|
|
// TODO: Figure out if this is correct.
|
|
|
|
Align = TD.getTypeAllocSize(GV->getType());
|
|
|
|
}
|
|
|
|
|
2012-09-27 05:21:41 +00:00
|
|
|
if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
|
|
|
|
return ARMLowerPICELF(GV, Align, VT);
|
|
|
|
|
2012-01-07 01:47:05 +00:00
|
|
|
// Grab index.
|
|
|
|
unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
|
|
|
|
(Subtarget->isThumb() ? 4 : 8);
|
|
|
|
unsigned Id = AFI->createPICLabelUId();
|
|
|
|
ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
|
|
|
|
ARMCP::CPValue,
|
|
|
|
PCAdj);
|
|
|
|
unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
|
|
|
|
|
|
|
|
// Load value.
|
|
|
|
MachineInstrBuilder MIB;
|
|
|
|
if (isThumb2) {
|
|
|
|
unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
|
|
|
|
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
|
|
|
|
.addConstantPoolIndex(Idx);
|
|
|
|
if (RelocM == Reloc::PIC_)
|
|
|
|
MIB.addImm(Id);
|
2012-08-29 02:41:21 +00:00
|
|
|
AddOptionalDefs(MIB);
|
2012-01-07 01:47:05 +00:00
|
|
|
} else {
|
|
|
|
// The extra immediate is for addrmode2.
|
|
|
|
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
|
|
|
|
DestReg)
|
|
|
|
.addConstantPoolIndex(Idx)
|
|
|
|
.addImm(0);
|
2012-08-29 02:41:21 +00:00
|
|
|
AddOptionalDefs(MIB);
|
|
|
|
|
|
|
|
if (RelocM == Reloc::PIC_) {
|
|
|
|
unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
|
|
|
|
unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
|
|
|
|
|
|
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
|
|
|
|
DL, TII.get(Opc), NewDestReg)
|
|
|
|
.addReg(DestReg)
|
|
|
|
.addImm(Id);
|
|
|
|
AddOptionalDefs(MIB);
|
|
|
|
return NewDestReg;
|
|
|
|
}
|
2012-01-07 01:47:05 +00:00
|
|
|
}
|
2010-10-02 00:32:44 +00:00
|
|
|
}
|
2011-06-03 01:13:19 +00:00
|
|
|
|
2012-08-29 02:41:21 +00:00
|
|
|
if (IsIndirect) {
|
2012-01-07 01:47:05 +00:00
|
|
|
MachineInstrBuilder MIB;
|
2011-06-03 01:13:19 +00:00
|
|
|
unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
|
2011-11-08 21:12:00 +00:00
|
|
|
if (isThumb2)
|
2011-09-13 20:30:37 +00:00
|
|
|
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(ARM::t2LDRi12), NewDestReg)
|
2011-06-03 01:13:19 +00:00
|
|
|
.addReg(DestReg)
|
|
|
|
.addImm(0);
|
|
|
|
else
|
|
|
|
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
|
|
|
|
NewDestReg)
|
|
|
|
.addReg(DestReg)
|
|
|
|
.addImm(0);
|
|
|
|
DestReg = NewDestReg;
|
|
|
|
AddOptionalDefs(MIB);
|
|
|
|
}
|
|
|
|
|
2010-10-02 00:32:44 +00:00
|
|
|
return DestReg;
|
2010-10-01 23:24:42 +00:00
|
|
|
}
|
|
|
|
|
2010-09-09 00:19:41 +00:00
|
|
|
unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
|
|
|
|
EVT VT = TLI.getValueType(C->getType(), true);
|
|
|
|
|
|
|
|
// Only handle simple types.
|
|
|
|
if (!VT.isSimple()) return 0;
|
|
|
|
|
|
|
|
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
|
|
|
|
return ARMMaterializeFP(CFP, VT);
|
2010-10-01 23:24:42 +00:00
|
|
|
else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
|
|
|
|
return ARMMaterializeGV(GV, VT);
|
|
|
|
else if (isa<ConstantInt>(C))
|
|
|
|
return ARMMaterializeInt(C, VT);
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-10-01 23:24:42 +00:00
|
|
|
return 0;
|
2010-09-09 00:19:41 +00:00
|
|
|
}
|
|
|
|
|
2011-11-17 21:46:13 +00:00
|
|
|
// TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
|
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
|
|
|
|
// Don't handle dynamic allocas.
|
|
|
|
if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT VT;
|
2012-05-11 16:41:38 +00:00
|
|
|
if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
DenseMap<const AllocaInst*, int>::iterator SI =
|
|
|
|
FuncInfo.StaticAllocaMap.find(AI);
|
|
|
|
|
|
|
|
// This will get lowered later into the correct offsets and registers
|
|
|
|
// via rewriteXFrameIndex.
|
|
|
|
if (SI != FuncInfo.StaticAllocaMap.end()) {
|
2012-02-22 05:59:10 +00:00
|
|
|
const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
|
2010-09-30 20:49:44 +00:00
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
|
2011-12-14 02:11:42 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-09-30 20:49:44 +00:00
|
|
|
TII.get(Opc), ResultReg)
|
|
|
|
.addFrameIndex(SI->second)
|
|
|
|
.addImm(0));
|
|
|
|
return ResultReg;
|
|
|
|
}
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-07-18 04:54:35 +00:00
|
|
|
bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
|
2010-11-03 11:35:31 +00:00
|
|
|
EVT evt = TLI.getValueType(Ty, true);
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-08-25 07:23:49 +00:00
|
|
|
// Only handle simple types.
|
2010-11-03 11:35:31 +00:00
|
|
|
if (evt == MVT::Other || !evt.isSimple()) return false;
|
|
|
|
VT = evt.getSimpleVT();
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-08-31 01:28:42 +00:00
|
|
|
// Handle all legal types, i.e. a register that will directly hold this
|
|
|
|
// value.
|
|
|
|
return TLI.isTypeLegal(VT);
|
2010-08-25 07:23:49 +00:00
|
|
|
}
|
|
|
|
|
2011-07-18 04:54:35 +00:00
|
|
|
bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
|
2010-09-01 18:01:32 +00:00
|
|
|
if (isTypeLegal(Ty, VT)) return true;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-09-01 18:01:32 +00:00
|
|
|
// If this is a type than can be sign or zero-extended to a basic operation
|
|
|
|
// go ahead and accept it now.
|
2011-11-13 02:23:59 +00:00
|
|
|
if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
|
2010-09-01 18:01:32 +00:00
|
|
|
return true;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-09-01 18:01:32 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-11-19 22:36:41 +00:00
|
|
|
// Computes the address to get to an object.
|
2010-11-19 22:30:02 +00:00
|
|
|
bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
|
2010-08-23 21:44:12 +00:00
|
|
|
// Some boilerplate from the X86 FastISel.
|
|
|
|
const User *U = NULL;
|
|
|
|
unsigned Opcode = Instruction::UserOp1;
|
2010-08-24 00:07:24 +00:00
|
|
|
if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
|
2010-11-19 22:37:58 +00:00
|
|
|
// Don't walk into other basic blocks unless the object is an alloca from
|
|
|
|
// another block, otherwise it may not have a virtual register assigned.
|
2010-11-15 21:11:06 +00:00
|
|
|
if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
|
|
|
|
FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
|
|
|
|
Opcode = I->getOpcode();
|
|
|
|
U = I;
|
|
|
|
}
|
2010-08-24 00:07:24 +00:00
|
|
|
} else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
|
2010-08-23 21:44:12 +00:00
|
|
|
Opcode = C->getOpcode();
|
|
|
|
U = C;
|
|
|
|
}
|
|
|
|
|
2011-07-18 04:54:35 +00:00
|
|
|
if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
|
2010-08-23 21:44:12 +00:00
|
|
|
if (Ty->getAddressSpace() > 255)
|
|
|
|
// Fast instruction selection doesn't support the special
|
|
|
|
// address spaces.
|
|
|
|
return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-08-23 21:44:12 +00:00
|
|
|
switch (Opcode) {
|
2010-09-09 01:06:51 +00:00
|
|
|
default:
|
2010-08-23 21:44:12 +00:00
|
|
|
break;
|
2010-10-12 00:43:21 +00:00
|
|
|
case Instruction::BitCast: {
|
|
|
|
// Look through bitcasts.
|
2010-11-19 22:30:02 +00:00
|
|
|
return ARMComputeAddress(U->getOperand(0), Addr);
|
2010-10-12 00:43:21 +00:00
|
|
|
}
|
|
|
|
case Instruction::IntToPtr: {
|
|
|
|
// Look past no-op inttoptrs.
|
|
|
|
if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
|
2010-11-19 22:30:02 +00:00
|
|
|
return ARMComputeAddress(U->getOperand(0), Addr);
|
2010-10-12 00:43:21 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case Instruction::PtrToInt: {
|
|
|
|
// Look past no-op ptrtoints.
|
|
|
|
if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
|
2010-11-19 22:30:02 +00:00
|
|
|
return ARMComputeAddress(U->getOperand(0), Addr);
|
2010-10-12 00:43:21 +00:00
|
|
|
break;
|
|
|
|
}
|
2010-10-14 09:29:41 +00:00
|
|
|
case Instruction::GetElementPtr: {
|
2010-11-19 22:39:56 +00:00
|
|
|
Address SavedAddr = Addr;
|
2010-11-19 22:30:02 +00:00
|
|
|
int TmpOffset = Addr.Offset;
|
2010-10-15 18:02:07 +00:00
|
|
|
|
2010-10-14 09:29:41 +00:00
|
|
|
// Iterate through the GEP folding the constants into offsets where
|
|
|
|
// we can.
|
|
|
|
gep_type_iterator GTI = gep_type_begin(U);
|
|
|
|
for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
|
|
|
|
i != e; ++i, ++GTI) {
|
|
|
|
const Value *Op = *i;
|
2011-07-18 04:54:35 +00:00
|
|
|
if (StructType *STy = dyn_cast<StructType>(*GTI)) {
|
2010-10-14 09:29:41 +00:00
|
|
|
const StructLayout *SL = TD.getStructLayout(STy);
|
|
|
|
unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
|
|
|
|
TmpOffset += SL->getElementOffset(Idx);
|
|
|
|
} else {
|
2010-10-15 18:02:07 +00:00
|
|
|
uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
|
2011-03-22 19:39:17 +00:00
|
|
|
for (;;) {
|
2010-10-15 18:02:07 +00:00
|
|
|
if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
|
|
|
|
// Constant-offset addressing.
|
|
|
|
TmpOffset += CI->getSExtValue() * S;
|
2011-03-22 19:39:17 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (isa<AddOperator>(Op) &&
|
|
|
|
(!isa<Instruction>(Op) ||
|
|
|
|
FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
|
|
|
|
== FuncInfo.MBB) &&
|
|
|
|
isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
|
2011-04-29 00:03:10 +00:00
|
|
|
// An add (in the same block) with a constant operand. Fold the
|
2011-03-22 19:39:17 +00:00
|
|
|
// constant.
|
2010-10-15 18:02:07 +00:00
|
|
|
ConstantInt *CI =
|
2011-03-22 19:39:17 +00:00
|
|
|
cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
|
2010-10-15 18:02:07 +00:00
|
|
|
TmpOffset += CI->getSExtValue() * S;
|
2011-03-22 19:39:17 +00:00
|
|
|
// Iterate on the other operand.
|
|
|
|
Op = cast<AddOperator>(Op)->getOperand(0);
|
|
|
|
continue;
|
2011-04-29 00:03:10 +00:00
|
|
|
}
|
2011-03-22 19:39:17 +00:00
|
|
|
// Unsupported
|
|
|
|
goto unsupported_gep;
|
|
|
|
}
|
2010-10-14 09:29:41 +00:00
|
|
|
}
|
|
|
|
}
|
2010-10-15 18:02:07 +00:00
|
|
|
|
|
|
|
// Try to grab the base operand now.
|
2010-11-19 22:30:02 +00:00
|
|
|
Addr.Offset = TmpOffset;
|
|
|
|
if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
|
2010-10-15 18:02:07 +00:00
|
|
|
|
|
|
|
// We failed, restore everything and try the other options.
|
2010-11-19 22:39:56 +00:00
|
|
|
Addr = SavedAddr;
|
2010-10-15 18:02:07 +00:00
|
|
|
|
2010-10-14 09:29:41 +00:00
|
|
|
unsupported_gep:
|
|
|
|
break;
|
|
|
|
}
|
2010-08-23 21:44:12 +00:00
|
|
|
case Instruction::Alloca: {
|
2010-10-12 05:39:06 +00:00
|
|
|
const AllocaInst *AI = cast<AllocaInst>(Obj);
|
2010-11-20 22:38:27 +00:00
|
|
|
DenseMap<const AllocaInst*, int>::iterator SI =
|
|
|
|
FuncInfo.StaticAllocaMap.find(AI);
|
|
|
|
if (SI != FuncInfo.StaticAllocaMap.end()) {
|
|
|
|
Addr.BaseType = Address::FrameIndexBase;
|
|
|
|
Addr.Base.FI = SI->second;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
2010-08-23 21:44:12 +00:00
|
|
|
}
|
|
|
|
}
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-08-24 00:07:24 +00:00
|
|
|
// Try to get this in a register if nothing else has worked.
|
2010-11-19 22:30:02 +00:00
|
|
|
if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
|
|
|
|
return Addr.Base.Reg != 0;
|
2010-10-14 09:29:41 +00:00
|
|
|
}
|
|
|
|
|
2011-11-13 02:23:59 +00:00
|
|
|
void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-10-21 19:40:30 +00:00
|
|
|
assert(VT.isSimple() && "Non-simple types are invalid here!");
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-10-21 19:40:30 +00:00
|
|
|
bool needsLowering = false;
|
|
|
|
switch (VT.getSimpleVT().SimpleTy) {
|
2012-02-07 02:50:20 +00:00
|
|
|
default: llvm_unreachable("Unhandled load/store type!");
|
2011-11-13 02:23:59 +00:00
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
2011-11-09 21:30:12 +00:00
|
|
|
case MVT::i16:
|
2011-11-13 02:23:59 +00:00
|
|
|
case MVT::i32:
|
2011-11-14 20:22:27 +00:00
|
|
|
if (!useAM3) {
|
2011-11-09 21:30:12 +00:00
|
|
|
// Integer loads/stores handle 12-bit offsets.
|
|
|
|
needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
|
2011-11-14 20:22:27 +00:00
|
|
|
// Handle negative offsets.
|
2011-11-14 22:34:48 +00:00
|
|
|
if (needsLowering && isThumb2)
|
|
|
|
needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
|
|
|
|
Addr.Offset > -256);
|
2011-11-14 20:22:27 +00:00
|
|
|
} else {
|
2011-11-13 04:25:02 +00:00
|
|
|
// ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
|
2011-11-14 04:09:28 +00:00
|
|
|
needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
|
2011-11-14 20:22:27 +00:00
|
|
|
}
|
2010-10-21 19:40:30 +00:00
|
|
|
break;
|
|
|
|
case MVT::f32:
|
|
|
|
case MVT::f64:
|
|
|
|
// Floating point operands handle 8-bit offsets.
|
2010-11-19 22:30:02 +00:00
|
|
|
needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
|
2010-10-21 19:40:30 +00:00
|
|
|
break;
|
|
|
|
}
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-11-20 22:38:27 +00:00
|
|
|
// If this is a stack pointer and the offset needs to be simplified then
|
|
|
|
// put the alloca address into a register, set the base type back to
|
|
|
|
// register and continue. This should almost never happen.
|
|
|
|
if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
|
2012-04-20 07:30:17 +00:00
|
|
|
const TargetRegisterClass *RC = isThumb2 ?
|
|
|
|
(const TargetRegisterClass*)&ARM::tGPRRegClass :
|
|
|
|
(const TargetRegisterClass*)&ARM::GPRRegClass;
|
2010-11-20 22:38:27 +00:00
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
|
2011-12-14 02:11:42 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-11-20 22:38:27 +00:00
|
|
|
TII.get(Opc), ResultReg)
|
|
|
|
.addFrameIndex(Addr.Base.FI)
|
|
|
|
.addImm(0));
|
|
|
|
Addr.Base.Reg = ResultReg;
|
|
|
|
Addr.BaseType = Address::RegBase;
|
|
|
|
}
|
|
|
|
|
2010-10-21 19:40:30 +00:00
|
|
|
// Since the offset is too large for the load/store instruction
|
2010-09-02 00:53:56 +00:00
|
|
|
// get the reg+offset into a register.
|
2010-10-21 19:40:30 +00:00
|
|
|
if (needsLowering) {
|
2011-04-29 21:22:56 +00:00
|
|
|
Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
|
|
|
|
/*Op0IsKill*/false, Addr.Offset, MVT::i32);
|
2010-11-19 22:30:02 +00:00
|
|
|
Addr.Offset = 0;
|
2010-09-02 00:53:56 +00:00
|
|
|
}
|
2010-08-23 21:44:12 +00:00
|
|
|
}
|
|
|
|
|
2010-12-01 01:40:24 +00:00
|
|
|
void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
|
2011-05-28 20:34:49 +00:00
|
|
|
const MachineInstrBuilder &MIB,
|
2011-11-13 02:23:59 +00:00
|
|
|
unsigned Flags, bool useAM3) {
|
2010-12-01 01:40:24 +00:00
|
|
|
// addrmode5 output depends on the selection dag addressing dividing the
|
|
|
|
// offset by 4 that it then later multiplies. Do this here as well.
|
|
|
|
if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
|
|
|
|
VT.getSimpleVT().SimpleTy == MVT::f64)
|
|
|
|
Addr.Offset /= 4;
|
2011-04-29 00:03:10 +00:00
|
|
|
|
2010-12-01 01:40:24 +00:00
|
|
|
// Frame base works a bit differently. Handle it separately.
|
|
|
|
if (Addr.BaseType == Address::FrameIndexBase) {
|
|
|
|
int FI = Addr.Base.FI;
|
|
|
|
int Offset = Addr.Offset;
|
|
|
|
MachineMemOperand *MMO =
|
|
|
|
FuncInfo.MF->getMachineMemOperand(
|
|
|
|
MachinePointerInfo::getFixedStack(FI, Offset),
|
2011-05-28 20:34:49 +00:00
|
|
|
Flags,
|
2010-12-01 01:40:24 +00:00
|
|
|
MFI.getObjectSize(FI),
|
|
|
|
MFI.getObjectAlignment(FI));
|
|
|
|
// Now add the rest of the operands.
|
|
|
|
MIB.addFrameIndex(FI);
|
|
|
|
|
2011-12-04 00:52:23 +00:00
|
|
|
// ARM halfword load/stores and signed byte loads need an additional
|
|
|
|
// operand.
|
2011-11-14 04:09:28 +00:00
|
|
|
if (useAM3) {
|
|
|
|
signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
|
|
|
|
MIB.addReg(0);
|
|
|
|
MIB.addImm(Imm);
|
|
|
|
} else {
|
|
|
|
MIB.addImm(Addr.Offset);
|
|
|
|
}
|
2010-12-01 01:40:24 +00:00
|
|
|
MIB.addMemOperand(MMO);
|
|
|
|
} else {
|
|
|
|
// Now add the rest of the operands.
|
|
|
|
MIB.addReg(Addr.Base.Reg);
|
2011-04-29 00:03:10 +00:00
|
|
|
|
2011-12-04 00:52:23 +00:00
|
|
|
// ARM halfword load/stores and signed byte loads need an additional
|
|
|
|
// operand.
|
2011-11-14 04:09:28 +00:00
|
|
|
if (useAM3) {
|
|
|
|
signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
|
|
|
|
MIB.addReg(0);
|
|
|
|
MIB.addImm(Imm);
|
|
|
|
} else {
|
|
|
|
MIB.addImm(Addr.Offset);
|
|
|
|
}
|
2010-12-01 01:40:24 +00:00
|
|
|
}
|
|
|
|
AddOptionalDefs(MIB);
|
|
|
|
}
|
|
|
|
|
2011-11-13 02:23:59 +00:00
|
|
|
bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
|
2011-12-13 19:22:14 +00:00
|
|
|
unsigned Alignment, bool isZExt, bool allocReg) {
|
2010-08-25 07:23:49 +00:00
|
|
|
assert(VT.isSimple() && "Non-simple types are invalid here!");
|
2010-08-31 01:28:42 +00:00
|
|
|
unsigned Opc;
|
2011-11-13 02:23:59 +00:00
|
|
|
bool useAM3 = false;
|
2011-12-13 19:22:14 +00:00
|
|
|
bool needVMOV = false;
|
2012-02-22 05:59:10 +00:00
|
|
|
const TargetRegisterClass *RC;
|
2010-08-25 07:23:49 +00:00
|
|
|
switch (VT.getSimpleVT().SimpleTy) {
|
2010-12-01 01:40:24 +00:00
|
|
|
// This is mostly going to be Neon/vector support.
|
|
|
|
default: return false;
|
2011-11-11 02:38:59 +00:00
|
|
|
case MVT::i1:
|
2010-09-01 18:01:32 +00:00
|
|
|
case MVT::i8:
|
2011-11-14 20:22:27 +00:00
|
|
|
if (isThumb2) {
|
|
|
|
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
|
|
|
|
Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
|
|
|
|
else
|
|
|
|
Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
|
2011-11-13 02:23:59 +00:00
|
|
|
} else {
|
2011-11-14 20:22:27 +00:00
|
|
|
if (isZExt) {
|
|
|
|
Opc = ARM::LDRBi12;
|
|
|
|
} else {
|
|
|
|
Opc = ARM::LDRSB;
|
|
|
|
useAM3 = true;
|
|
|
|
}
|
2011-11-13 02:23:59 +00:00
|
|
|
}
|
2012-04-20 07:30:17 +00:00
|
|
|
RC = &ARM::GPRRegClass;
|
2010-09-01 18:01:32 +00:00
|
|
|
break;
|
2011-11-09 21:30:12 +00:00
|
|
|
case MVT::i16:
|
2012-09-21 00:41:42 +00:00
|
|
|
if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
|
|
|
|
return false;
|
|
|
|
|
2011-11-14 20:22:27 +00:00
|
|
|
if (isThumb2) {
|
|
|
|
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
|
|
|
|
Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
|
|
|
|
else
|
|
|
|
Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
|
|
|
|
} else {
|
|
|
|
Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
|
|
|
|
useAM3 = true;
|
|
|
|
}
|
2012-04-20 07:30:17 +00:00
|
|
|
RC = &ARM::GPRRegClass;
|
2011-11-09 21:30:12 +00:00
|
|
|
break;
|
2010-08-31 01:28:42 +00:00
|
|
|
case MVT::i32:
|
2012-09-21 16:58:35 +00:00
|
|
|
if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
|
|
|
|
return false;
|
|
|
|
|
2011-11-14 20:22:27 +00:00
|
|
|
if (isThumb2) {
|
|
|
|
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
|
|
|
|
Opc = ARM::t2LDRi8;
|
|
|
|
else
|
|
|
|
Opc = ARM::t2LDRi12;
|
|
|
|
} else {
|
|
|
|
Opc = ARM::LDRi12;
|
|
|
|
}
|
2012-04-20 07:30:17 +00:00
|
|
|
RC = &ARM::GPRRegClass;
|
2010-08-31 01:28:42 +00:00
|
|
|
break;
|
2010-09-18 01:59:37 +00:00
|
|
|
case MVT::f32:
|
2011-12-14 17:55:03 +00:00
|
|
|
if (!Subtarget->hasVFP2()) return false;
|
2011-12-13 19:22:14 +00:00
|
|
|
// Unaligned loads need special handling. Floats require word-alignment.
|
|
|
|
if (Alignment && Alignment < 4) {
|
|
|
|
needVMOV = true;
|
|
|
|
VT = MVT::i32;
|
|
|
|
Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
|
2012-04-20 07:30:17 +00:00
|
|
|
RC = &ARM::GPRRegClass;
|
2011-12-13 19:22:14 +00:00
|
|
|
} else {
|
|
|
|
Opc = ARM::VLDRS;
|
|
|
|
RC = TLI.getRegClassFor(VT);
|
|
|
|
}
|
2010-09-18 01:59:37 +00:00
|
|
|
break;
|
|
|
|
case MVT::f64:
|
2011-12-14 17:55:03 +00:00
|
|
|
if (!Subtarget->hasVFP2()) return false;
|
2011-12-14 17:26:05 +00:00
|
|
|
// FIXME: Unaligned loads need special handling. Doublewords require
|
|
|
|
// word-alignment.
|
|
|
|
if (Alignment && Alignment < 4)
|
2011-12-13 19:22:14 +00:00
|
|
|
return false;
|
2011-12-14 17:26:05 +00:00
|
|
|
|
2010-09-18 01:59:37 +00:00
|
|
|
Opc = ARM::VLDRD;
|
2010-10-07 05:50:44 +00:00
|
|
|
RC = TLI.getRegClassFor(VT);
|
2010-09-18 01:59:37 +00:00
|
|
|
break;
|
2010-08-25 07:23:49 +00:00
|
|
|
}
|
2010-12-01 01:40:24 +00:00
|
|
|
// Simplify this down to something we can handle.
|
2011-11-13 02:23:59 +00:00
|
|
|
ARMSimplifyAddress(Addr, VT, useAM3);
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-12-01 01:40:24 +00:00
|
|
|
// Create the base instruction, then add the operands.
|
2011-11-13 02:23:59 +00:00
|
|
|
if (allocReg)
|
|
|
|
ResultReg = createResultReg(RC);
|
|
|
|
assert (ResultReg > 255 && "Expected an allocated virtual register.");
|
2010-12-01 01:40:24 +00:00
|
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(Opc), ResultReg);
|
2011-11-13 02:23:59 +00:00
|
|
|
AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
|
2011-12-13 19:22:14 +00:00
|
|
|
|
|
|
|
// If we had an unaligned load of a float we've converted it to an regular
|
|
|
|
// load. Now we must move from the GRP to the FP register.
|
|
|
|
if (needVMOV) {
|
|
|
|
unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(ARM::VMOVSR), MoveReg)
|
|
|
|
.addReg(ResultReg));
|
|
|
|
ResultReg = MoveReg;
|
|
|
|
}
|
2010-08-31 01:28:42 +00:00
|
|
|
return true;
|
2010-08-25 07:23:49 +00:00
|
|
|
}
|
|
|
|
|
2010-09-27 06:02:23 +00:00
|
|
|
bool ARMFastISel::SelectLoad(const Instruction *I) {
|
2011-09-02 22:33:24 +00:00
|
|
|
// Atomic loads need special handling.
|
|
|
|
if (cast<LoadInst>(I)->isAtomic())
|
|
|
|
return false;
|
|
|
|
|
2010-09-10 00:34:35 +00:00
|
|
|
// Verify we have a legal type before going any further.
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT VT;
|
2010-09-10 00:34:35 +00:00
|
|
|
if (!isLoadTypeLegal(I->getType(), VT))
|
|
|
|
return false;
|
|
|
|
|
2010-12-01 01:40:24 +00:00
|
|
|
// See if we can handle this address.
|
2010-11-19 22:30:02 +00:00
|
|
|
Address Addr;
|
2010-12-01 01:40:24 +00:00
|
|
|
if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
|
2010-09-10 00:34:35 +00:00
|
|
|
|
|
|
|
unsigned ResultReg;
|
2011-12-13 19:22:14 +00:00
|
|
|
if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
|
|
|
|
return false;
|
2010-09-10 00:34:35 +00:00
|
|
|
UpdateValueMap(I, ResultReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-12-04 00:52:23 +00:00
|
|
|
bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
|
|
|
|
unsigned Alignment) {
|
2010-09-02 00:53:56 +00:00
|
|
|
unsigned StrOpc;
|
2011-11-13 02:23:59 +00:00
|
|
|
bool useAM3 = false;
|
2010-09-02 00:53:56 +00:00
|
|
|
switch (VT.getSimpleVT().SimpleTy) {
|
2010-12-01 01:40:24 +00:00
|
|
|
// This is mostly going to be Neon/vector support.
|
2010-09-02 00:53:56 +00:00
|
|
|
default: return false;
|
2010-11-02 23:59:09 +00:00
|
|
|
case MVT::i1: {
|
2012-04-20 07:30:17 +00:00
|
|
|
unsigned Res = createResultReg(isThumb2 ?
|
|
|
|
(const TargetRegisterClass*)&ARM::tGPRRegClass :
|
|
|
|
(const TargetRegisterClass*)&ARM::GPRRegClass);
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
|
2010-11-02 23:59:09 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(Opc), Res)
|
|
|
|
.addReg(SrcReg).addImm(1));
|
|
|
|
SrcReg = Res;
|
|
|
|
} // Fallthrough here.
|
2010-10-15 18:02:07 +00:00
|
|
|
case MVT::i8:
|
2011-11-14 20:22:27 +00:00
|
|
|
if (isThumb2) {
|
|
|
|
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
|
|
|
|
StrOpc = ARM::t2STRBi8;
|
|
|
|
else
|
|
|
|
StrOpc = ARM::t2STRBi12;
|
|
|
|
} else {
|
|
|
|
StrOpc = ARM::STRBi12;
|
|
|
|
}
|
2010-10-12 05:39:06 +00:00
|
|
|
break;
|
|
|
|
case MVT::i16:
|
2012-09-21 00:41:42 +00:00
|
|
|
if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
|
|
|
|
return false;
|
|
|
|
|
2011-11-14 20:22:27 +00:00
|
|
|
if (isThumb2) {
|
|
|
|
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
|
|
|
|
StrOpc = ARM::t2STRHi8;
|
|
|
|
else
|
|
|
|
StrOpc = ARM::t2STRHi12;
|
|
|
|
} else {
|
|
|
|
StrOpc = ARM::STRH;
|
|
|
|
useAM3 = true;
|
|
|
|
}
|
2010-10-12 05:39:06 +00:00
|
|
|
break;
|
2010-10-16 01:10:35 +00:00
|
|
|
case MVT::i32:
|
2012-09-21 16:58:35 +00:00
|
|
|
if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
|
|
|
|
return false;
|
|
|
|
|
2011-11-14 20:22:27 +00:00
|
|
|
if (isThumb2) {
|
|
|
|
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
|
|
|
|
StrOpc = ARM::t2STRi8;
|
|
|
|
else
|
|
|
|
StrOpc = ARM::t2STRi12;
|
|
|
|
} else {
|
|
|
|
StrOpc = ARM::STRi12;
|
|
|
|
}
|
2010-10-16 01:10:35 +00:00
|
|
|
break;
|
2010-09-02 23:43:26 +00:00
|
|
|
case MVT::f32:
|
|
|
|
if (!Subtarget->hasVFP2()) return false;
|
2011-12-06 01:44:17 +00:00
|
|
|
// Unaligned stores need special handling. Floats require word-alignment.
|
2011-12-03 02:21:57 +00:00
|
|
|
if (Alignment && Alignment < 4) {
|
|
|
|
unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(ARM::VMOVRS), MoveReg)
|
|
|
|
.addReg(SrcReg));
|
|
|
|
SrcReg = MoveReg;
|
|
|
|
VT = MVT::i32;
|
|
|
|
StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
|
2011-12-14 17:32:02 +00:00
|
|
|
} else {
|
|
|
|
StrOpc = ARM::VSTRS;
|
2011-12-03 02:21:57 +00:00
|
|
|
}
|
2010-09-02 23:43:26 +00:00
|
|
|
break;
|
|
|
|
case MVT::f64:
|
|
|
|
if (!Subtarget->hasVFP2()) return false;
|
2011-12-06 01:44:17 +00:00
|
|
|
// FIXME: Unaligned stores need special handling. Doublewords require
|
|
|
|
// word-alignment.
|
2011-12-14 17:26:05 +00:00
|
|
|
if (Alignment && Alignment < 4)
|
2011-12-03 02:21:57 +00:00
|
|
|
return false;
|
2011-12-14 17:26:05 +00:00
|
|
|
|
2010-09-02 23:43:26 +00:00
|
|
|
StrOpc = ARM::VSTRD;
|
|
|
|
break;
|
2010-09-02 00:53:56 +00:00
|
|
|
}
|
2010-12-01 01:40:24 +00:00
|
|
|
// Simplify this down to something we can handle.
|
2011-11-13 02:23:59 +00:00
|
|
|
ARMSimplifyAddress(Addr, VT, useAM3);
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-12-01 01:40:24 +00:00
|
|
|
// Create the base instruction, then add the operands.
|
|
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(StrOpc))
|
2011-11-17 01:16:53 +00:00
|
|
|
.addReg(SrcReg);
|
2011-11-13 02:23:59 +00:00
|
|
|
AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
|
2010-09-02 00:53:56 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-09-27 06:02:23 +00:00
|
|
|
bool ARMFastISel::SelectStore(const Instruction *I) {
|
2010-09-02 00:53:56 +00:00
|
|
|
Value *Op0 = I->getOperand(0);
|
|
|
|
unsigned SrcReg = 0;
|
|
|
|
|
2011-09-02 22:33:24 +00:00
|
|
|
// Atomic stores need special handling.
|
|
|
|
if (cast<StoreInst>(I)->isAtomic())
|
|
|
|
return false;
|
|
|
|
|
2010-12-01 01:40:24 +00:00
|
|
|
// Verify we have a legal type before going any further.
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT VT;
|
2010-09-02 00:53:56 +00:00
|
|
|
if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
|
|
|
|
return false;
|
|
|
|
|
2010-09-02 01:48:11 +00:00
|
|
|
// Get the value to be stored into a register.
|
|
|
|
SrcReg = getRegForValue(Op0);
|
2010-12-01 01:40:24 +00:00
|
|
|
if (SrcReg == 0) return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-12-01 01:40:24 +00:00
|
|
|
// See if we can handle this address.
|
2010-11-19 22:30:02 +00:00
|
|
|
Address Addr;
|
|
|
|
if (!ARMComputeAddress(I->getOperand(1), Addr))
|
2010-09-01 22:16:27 +00:00
|
|
|
return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2011-12-03 02:21:57 +00:00
|
|
|
if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
|
|
|
|
return false;
|
2010-09-17 22:28:18 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
|
|
|
|
switch (Pred) {
|
|
|
|
// Needs two compares...
|
|
|
|
case CmpInst::FCMP_ONE:
|
2010-10-11 08:38:55 +00:00
|
|
|
case CmpInst::FCMP_UEQ:
|
2010-09-17 22:28:18 +00:00
|
|
|
default:
|
2010-11-02 01:24:49 +00:00
|
|
|
// AL is our "false" for now. The other two need more compares.
|
2010-09-17 22:28:18 +00:00
|
|
|
return ARMCC::AL;
|
|
|
|
case CmpInst::ICMP_EQ:
|
|
|
|
case CmpInst::FCMP_OEQ:
|
|
|
|
return ARMCC::EQ;
|
|
|
|
case CmpInst::ICMP_SGT:
|
|
|
|
case CmpInst::FCMP_OGT:
|
|
|
|
return ARMCC::GT;
|
|
|
|
case CmpInst::ICMP_SGE:
|
|
|
|
case CmpInst::FCMP_OGE:
|
|
|
|
return ARMCC::GE;
|
|
|
|
case CmpInst::ICMP_UGT:
|
|
|
|
case CmpInst::FCMP_UGT:
|
|
|
|
return ARMCC::HI;
|
|
|
|
case CmpInst::FCMP_OLT:
|
|
|
|
return ARMCC::MI;
|
|
|
|
case CmpInst::ICMP_ULE:
|
|
|
|
case CmpInst::FCMP_OLE:
|
|
|
|
return ARMCC::LS;
|
|
|
|
case CmpInst::FCMP_ORD:
|
|
|
|
return ARMCC::VC;
|
|
|
|
case CmpInst::FCMP_UNO:
|
|
|
|
return ARMCC::VS;
|
|
|
|
case CmpInst::FCMP_UGE:
|
|
|
|
return ARMCC::PL;
|
|
|
|
case CmpInst::ICMP_SLT:
|
|
|
|
case CmpInst::FCMP_ULT:
|
2010-10-11 08:38:55 +00:00
|
|
|
return ARMCC::LT;
|
2010-09-17 22:28:18 +00:00
|
|
|
case CmpInst::ICMP_SLE:
|
|
|
|
case CmpInst::FCMP_ULE:
|
|
|
|
return ARMCC::LE;
|
|
|
|
case CmpInst::FCMP_UNE:
|
|
|
|
case CmpInst::ICMP_NE:
|
|
|
|
return ARMCC::NE;
|
|
|
|
case CmpInst::ICMP_UGE:
|
|
|
|
return ARMCC::HS;
|
|
|
|
case CmpInst::ICMP_ULT:
|
|
|
|
return ARMCC::LO;
|
|
|
|
}
|
2010-09-01 22:16:27 +00:00
|
|
|
}
|
|
|
|
|
2010-09-27 06:02:23 +00:00
|
|
|
bool ARMFastISel::SelectBranch(const Instruction *I) {
|
2010-09-03 00:35:47 +00:00
|
|
|
const BranchInst *BI = cast<BranchInst>(I);
|
|
|
|
MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
|
|
|
|
MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-09-03 00:35:47 +00:00
|
|
|
// Simple branch support.
|
2010-11-09 19:22:26 +00:00
|
|
|
|
2010-10-29 21:08:19 +00:00
|
|
|
// If we can, avoid recomputing the compare - redoing it could lead to wonky
|
|
|
|
// behavior.
|
|
|
|
if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
|
2011-10-26 23:17:28 +00:00
|
|
|
if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
|
2010-10-29 21:08:19 +00:00
|
|
|
|
|
|
|
// Get the compare predicate.
|
2011-04-29 21:56:31 +00:00
|
|
|
// Try to take advantage of fallthrough opportunities.
|
|
|
|
CmpInst::Predicate Predicate = CI->getPredicate();
|
|
|
|
if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
|
|
|
|
std::swap(TBB, FBB);
|
|
|
|
Predicate = CmpInst::getInversePredicate(Predicate);
|
|
|
|
}
|
|
|
|
|
|
|
|
ARMCC::CondCodes ARMPred = getComparePred(Predicate);
|
2010-10-29 21:08:19 +00:00
|
|
|
|
|
|
|
// We may not handle every CC for now.
|
|
|
|
if (ARMPred == ARMCC::AL) return false;
|
|
|
|
|
2011-10-26 23:17:28 +00:00
|
|
|
// Emit the compare.
|
2011-11-02 18:08:25 +00:00
|
|
|
if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
|
2011-10-26 23:17:28 +00:00
|
|
|
return false;
|
2010-11-09 19:22:26 +00:00
|
|
|
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
|
2010-10-29 21:08:19 +00:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
|
|
|
|
.addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
|
2011-04-29 20:02:39 +00:00
|
|
|
FastEmitBranch(FBB, DL);
|
|
|
|
FuncInfo.MBB->addSuccessor(TBB);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
} else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
|
|
|
|
MVT SourceVT;
|
|
|
|
if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
|
2011-05-25 23:49:02 +00:00
|
|
|
(isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
|
2011-04-29 20:02:39 +00:00
|
|
|
unsigned OpReg = getRegForValue(TI->getOperand(0));
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(TstOpc))
|
|
|
|
.addReg(OpReg).addImm(1));
|
|
|
|
|
|
|
|
unsigned CCMode = ARMCC::NE;
|
|
|
|
if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
|
|
|
|
std::swap(TBB, FBB);
|
|
|
|
CCMode = ARMCC::EQ;
|
|
|
|
}
|
|
|
|
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
|
2011-04-29 20:02:39 +00:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
|
|
|
|
.addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
|
|
|
|
|
2010-10-29 21:08:19 +00:00
|
|
|
FastEmitBranch(FBB, DL);
|
|
|
|
FuncInfo.MBB->addSuccessor(TBB);
|
|
|
|
return true;
|
|
|
|
}
|
2011-10-27 00:21:16 +00:00
|
|
|
} else if (const ConstantInt *CI =
|
|
|
|
dyn_cast<ConstantInt>(BI->getCondition())) {
|
|
|
|
uint64_t Imm = CI->getZExtValue();
|
|
|
|
MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
|
|
|
|
FastEmitBranch(Target, DL);
|
|
|
|
return true;
|
2010-10-29 21:08:19 +00:00
|
|
|
}
|
2010-11-09 19:22:26 +00:00
|
|
|
|
2010-10-29 21:08:19 +00:00
|
|
|
unsigned CmpReg = getRegForValue(BI->getCondition());
|
|
|
|
if (CmpReg == 0) return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2011-04-16 03:31:26 +00:00
|
|
|
// We've been divorced from our compare! Our block was split, and
|
|
|
|
// now our compare lives in a predecessor block. We musn't
|
|
|
|
// re-compare here, as the children of the compare aren't guaranteed
|
|
|
|
// live across the block boundary (we *could* check for this).
|
|
|
|
// Regardless, the compare has been done in the predecessor block,
|
|
|
|
// and it left a value for us in a virtual register. Ergo, we test
|
|
|
|
// the one-bit value left in the virtual register.
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
|
2011-04-16 03:31:26 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
|
|
|
|
.addReg(CmpReg).addImm(1));
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2011-04-28 16:52:09 +00:00
|
|
|
unsigned CCMode = ARMCC::NE;
|
|
|
|
if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
|
|
|
|
std::swap(TBB, FBB);
|
|
|
|
CCMode = ARMCC::EQ;
|
|
|
|
}
|
|
|
|
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
|
2010-09-03 00:35:47 +00:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
|
2011-04-28 16:52:09 +00:00
|
|
|
.addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
|
2010-09-03 00:35:47 +00:00
|
|
|
FastEmitBranch(FBB, DL);
|
|
|
|
FuncInfo.MBB->addSuccessor(TBB);
|
2010-10-11 08:38:55 +00:00
|
|
|
return true;
|
2010-09-03 00:35:47 +00:00
|
|
|
}
|
|
|
|
|
2012-02-07 23:56:08 +00:00
|
|
|
bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
|
|
|
|
unsigned AddrReg = getRegForValue(I->getOperand(0));
|
|
|
|
if (AddrReg == 0) return false;
|
|
|
|
|
|
|
|
unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
|
|
|
|
.addReg(AddrReg));
|
2012-10-22 23:30:04 +00:00
|
|
|
|
|
|
|
const IndirectBrInst *IB = cast<IndirectBrInst>(I);
|
|
|
|
for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
|
|
|
|
FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
|
|
|
|
|
2012-06-14 06:08:19 +00:00
|
|
|
return true;
|
2012-02-07 23:56:08 +00:00
|
|
|
}
|
|
|
|
|
2011-11-02 18:08:25 +00:00
|
|
|
bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
|
|
|
|
bool isZExt) {
|
2011-10-26 23:25:44 +00:00
|
|
|
Type *Ty = Src1Value->getType();
|
2011-11-02 18:08:25 +00:00
|
|
|
EVT SrcVT = TLI.getValueType(Ty, true);
|
|
|
|
if (!SrcVT.isSimple()) return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2011-10-26 23:25:44 +00:00
|
|
|
bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
|
|
|
|
if (isFloat && !Subtarget->hasVFP2())
|
2010-09-08 23:13:45 +00:00
|
|
|
return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2011-11-09 03:22:02 +00:00
|
|
|
// Check to see if the 2nd operand is a constant that we can encode directly
|
|
|
|
// in the compare.
|
2011-11-11 06:27:41 +00:00
|
|
|
int Imm = 0;
|
|
|
|
bool UseImm = false;
|
2011-11-09 03:22:02 +00:00
|
|
|
bool isNegativeImm = false;
|
2011-11-16 00:32:20 +00:00
|
|
|
// FIXME: At -O0 we don't have anything that canonicalizes operand order.
|
|
|
|
// Thus, Src1Value may be a ConstantInt, but we're missing it.
|
2011-11-09 03:22:02 +00:00
|
|
|
if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
|
|
|
|
if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
|
|
|
|
SrcVT == MVT::i1) {
|
|
|
|
const APInt &CIVal = ConstInt->getValue();
|
2011-11-11 06:27:41 +00:00
|
|
|
Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
|
2012-03-15 22:54:20 +00:00
|
|
|
// For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
|
|
|
|
// then a cmn, because there is no way to represent 2147483648 as a
|
|
|
|
// signed 32-bit int.
|
|
|
|
if (Imm < 0 && Imm != (int)0x80000000) {
|
|
|
|
isNegativeImm = true;
|
|
|
|
Imm = -Imm;
|
2011-11-10 01:30:39 +00:00
|
|
|
}
|
2012-03-15 22:54:20 +00:00
|
|
|
UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
|
|
|
|
(ARM_AM::getSOImmVal(Imm) != -1);
|
2011-11-09 03:22:02 +00:00
|
|
|
}
|
|
|
|
} else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
|
|
|
|
if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
|
|
|
|
if (ConstFP->isZero() && !ConstFP->isNegative())
|
2011-11-11 06:27:41 +00:00
|
|
|
UseImm = true;
|
2011-11-09 03:22:02 +00:00
|
|
|
}
|
|
|
|
|
2010-09-08 23:13:45 +00:00
|
|
|
unsigned CmpOpc;
|
2011-11-09 03:22:02 +00:00
|
|
|
bool isICmp = true;
|
2011-11-02 18:08:25 +00:00
|
|
|
bool needsExt = false;
|
|
|
|
switch (SrcVT.getSimpleVT().SimpleTy) {
|
2010-09-08 23:13:45 +00:00
|
|
|
default: return false;
|
|
|
|
// TODO: Verify compares.
|
|
|
|
case MVT::f32:
|
2011-11-09 03:22:02 +00:00
|
|
|
isICmp = false;
|
2011-11-11 06:27:41 +00:00
|
|
|
CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
|
2010-09-08 23:13:45 +00:00
|
|
|
break;
|
|
|
|
case MVT::f64:
|
2011-11-09 03:22:02 +00:00
|
|
|
isICmp = false;
|
2011-11-11 06:27:41 +00:00
|
|
|
CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
|
2010-09-08 23:13:45 +00:00
|
|
|
break;
|
2011-11-02 18:08:25 +00:00
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
needsExt = true;
|
|
|
|
// Intentional fall-through.
|
2010-09-08 23:13:45 +00:00
|
|
|
case MVT::i32:
|
2011-11-09 03:22:02 +00:00
|
|
|
if (isThumb2) {
|
2011-11-11 06:27:41 +00:00
|
|
|
if (!UseImm)
|
2011-11-09 03:22:02 +00:00
|
|
|
CmpOpc = ARM::t2CMPrr;
|
|
|
|
else
|
2012-06-11 08:07:26 +00:00
|
|
|
CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
|
2011-11-09 03:22:02 +00:00
|
|
|
} else {
|
2011-11-11 06:27:41 +00:00
|
|
|
if (!UseImm)
|
2011-11-09 03:22:02 +00:00
|
|
|
CmpOpc = ARM::CMPrr;
|
|
|
|
else
|
2012-06-11 08:07:26 +00:00
|
|
|
CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
|
2011-11-09 03:22:02 +00:00
|
|
|
}
|
2010-09-08 23:13:45 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-11-02 18:08:25 +00:00
|
|
|
unsigned SrcReg1 = getRegForValue(Src1Value);
|
|
|
|
if (SrcReg1 == 0) return false;
|
|
|
|
|
2011-11-28 10:31:27 +00:00
|
|
|
unsigned SrcReg2 = 0;
|
2011-11-11 06:27:41 +00:00
|
|
|
if (!UseImm) {
|
2011-11-09 03:22:02 +00:00
|
|
|
SrcReg2 = getRegForValue(Src2Value);
|
|
|
|
if (SrcReg2 == 0) return false;
|
|
|
|
}
|
2011-11-02 18:08:25 +00:00
|
|
|
|
|
|
|
// We have i1, i8, or i16, we need to either zero extend or sign extend.
|
|
|
|
if (needsExt) {
|
2012-02-16 22:45:33 +00:00
|
|
|
SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
|
|
|
|
if (SrcReg1 == 0) return false;
|
2011-11-11 06:27:41 +00:00
|
|
|
if (!UseImm) {
|
2012-02-16 22:45:33 +00:00
|
|
|
SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
|
|
|
|
if (SrcReg2 == 0) return false;
|
2011-11-09 03:22:02 +00:00
|
|
|
}
|
2011-11-02 18:08:25 +00:00
|
|
|
}
|
2011-10-26 22:47:55 +00:00
|
|
|
|
2011-11-11 06:27:41 +00:00
|
|
|
if (!UseImm) {
|
2011-11-09 03:22:02 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(CmpOpc))
|
|
|
|
.addReg(SrcReg1).addReg(SrcReg2));
|
|
|
|
} else {
|
|
|
|
MachineInstrBuilder MIB;
|
|
|
|
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
|
|
|
|
.addReg(SrcReg1);
|
|
|
|
|
|
|
|
// Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
|
|
|
|
if (isICmp)
|
2011-11-11 06:27:41 +00:00
|
|
|
MIB.addImm(Imm);
|
2011-11-09 03:22:02 +00:00
|
|
|
AddOptionalDefs(MIB);
|
|
|
|
}
|
2011-10-26 23:25:44 +00:00
|
|
|
|
|
|
|
// For floating point we need to move the result to a comparison register
|
|
|
|
// that we can then use for branches.
|
|
|
|
if (Ty->isFloatTy() || Ty->isDoubleTy())
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(ARM::FMSTAT)));
|
2011-10-26 22:47:55 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMFastISel::SelectCmp(const Instruction *I) {
|
|
|
|
const CmpInst *CI = cast<CmpInst>(I);
|
|
|
|
|
2010-09-29 01:14:47 +00:00
|
|
|
// Get the compare predicate.
|
|
|
|
ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-29 01:14:47 +00:00
|
|
|
// We may not handle every CC for now.
|
|
|
|
if (ARMPred == ARMCC::AL) return false;
|
|
|
|
|
2011-10-26 22:47:55 +00:00
|
|
|
// Emit the compare.
|
2011-11-02 18:08:25 +00:00
|
|
|
if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
|
2011-10-26 22:47:55 +00:00
|
|
|
return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-09-29 01:14:47 +00:00
|
|
|
// Now set a register based on the comparison. Explicitly set the predicates
|
|
|
|
// here.
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
|
2012-04-20 07:30:17 +00:00
|
|
|
const TargetRegisterClass *RC = isThumb2 ?
|
|
|
|
(const TargetRegisterClass*)&ARM::rGPRRegClass :
|
|
|
|
(const TargetRegisterClass*)&ARM::GPRRegClass;
|
2010-10-07 05:39:19 +00:00
|
|
|
unsigned DestReg = createResultReg(RC);
|
2011-10-26 23:25:44 +00:00
|
|
|
Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
|
2010-09-29 01:14:47 +00:00
|
|
|
unsigned ZeroReg = TargetMaterializeConstant(Zero);
|
2012-03-07 20:59:26 +00:00
|
|
|
// ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
|
2010-09-29 01:14:47 +00:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
|
|
|
|
.addReg(ZeroReg).addImm(1)
|
2012-03-07 20:59:26 +00:00
|
|
|
.addImm(ARMPred).addReg(ARM::CPSR);
|
2010-09-29 01:14:47 +00:00
|
|
|
|
2010-09-17 22:28:18 +00:00
|
|
|
UpdateValueMap(I, DestReg);
|
2010-09-08 23:13:45 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-09-27 06:02:23 +00:00
|
|
|
bool ARMFastISel::SelectFPExt(const Instruction *I) {
|
2010-09-09 00:26:48 +00:00
|
|
|
// Make sure we have VFP and that we're extending float to double.
|
|
|
|
if (!Subtarget->hasVFP2()) return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-09-09 00:26:48 +00:00
|
|
|
Value *V = I->getOperand(0);
|
|
|
|
if (!I->getType()->isDoubleTy() ||
|
|
|
|
!V->getType()->isFloatTy()) return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-09-09 00:26:48 +00:00
|
|
|
unsigned Op = getRegForValue(V);
|
|
|
|
if (Op == 0) return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2012-04-20 07:30:17 +00:00
|
|
|
unsigned Result = createResultReg(&ARM::DPRRegClass);
|
2010-09-09 20:26:31 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-09-09 20:36:19 +00:00
|
|
|
TII.get(ARM::VCVTDS), Result)
|
2010-09-09 20:26:31 +00:00
|
|
|
.addReg(Op));
|
|
|
|
UpdateValueMap(I, Result);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-09-27 06:02:23 +00:00
|
|
|
bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
|
2010-09-09 20:26:31 +00:00
|
|
|
// Make sure we have VFP and that we're truncating double to float.
|
|
|
|
if (!Subtarget->hasVFP2()) return false;
|
|
|
|
|
|
|
|
Value *V = I->getOperand(0);
|
2010-10-05 23:13:24 +00:00
|
|
|
if (!(I->getType()->isFloatTy() &&
|
|
|
|
V->getType()->isDoubleTy())) return false;
|
2010-09-09 20:26:31 +00:00
|
|
|
|
|
|
|
unsigned Op = getRegForValue(V);
|
|
|
|
if (Op == 0) return false;
|
|
|
|
|
2012-04-20 07:30:17 +00:00
|
|
|
unsigned Result = createResultReg(&ARM::SPRRegClass);
|
2010-09-09 01:06:51 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
2010-09-09 20:36:19 +00:00
|
|
|
TII.get(ARM::VCVTSD), Result)
|
2010-09-09 00:26:48 +00:00
|
|
|
.addReg(Op));
|
|
|
|
UpdateValueMap(I, Result);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-02-03 21:14:11 +00:00
|
|
|
bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
|
2010-09-09 18:54:59 +00:00
|
|
|
// Make sure we have VFP.
|
|
|
|
if (!Subtarget->hasVFP2()) return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT DstVT;
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *Ty = I->getType();
|
2010-09-09 21:44:45 +00:00
|
|
|
if (!isTypeLegal(Ty, DstVT))
|
2010-09-09 18:54:59 +00:00
|
|
|
return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2011-11-03 02:04:59 +00:00
|
|
|
Value *Src = I->getOperand(0);
|
|
|
|
EVT SrcVT = TLI.getValueType(Src->getType(), true);
|
|
|
|
if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
|
2011-05-25 19:09:45 +00:00
|
|
|
return false;
|
|
|
|
|
2011-11-03 02:04:59 +00:00
|
|
|
unsigned SrcReg = getRegForValue(Src);
|
|
|
|
if (SrcReg == 0) return false;
|
|
|
|
|
|
|
|
// Handle sign-extension.
|
|
|
|
if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
|
|
|
|
EVT DestVT = MVT::i32;
|
2012-02-16 22:45:33 +00:00
|
|
|
SrcReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT,
|
2012-02-03 21:14:11 +00:00
|
|
|
/*isZExt*/!isSigned);
|
2012-02-16 22:45:33 +00:00
|
|
|
if (SrcReg == 0) return false;
|
2011-11-03 02:04:59 +00:00
|
|
|
}
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-10 00:34:35 +00:00
|
|
|
// The conversion routine works on fp-reg to fp-reg and the operand above
|
|
|
|
// was an integer, move it to the fp registers if possible.
|
2011-11-03 02:04:59 +00:00
|
|
|
unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
|
2010-09-09 21:44:45 +00:00
|
|
|
if (FP == 0) return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-09 18:54:59 +00:00
|
|
|
unsigned Opc;
|
2012-02-03 21:14:11 +00:00
|
|
|
if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
|
|
|
|
else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
|
2011-08-31 23:49:05 +00:00
|
|
|
else return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-09 21:44:45 +00:00
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
|
2010-09-09 18:54:59 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
|
|
|
|
ResultReg)
|
2010-09-09 21:44:45 +00:00
|
|
|
.addReg(FP));
|
2010-09-09 20:26:31 +00:00
|
|
|
UpdateValueMap(I, ResultReg);
|
2010-09-09 18:54:59 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-02-03 21:14:11 +00:00
|
|
|
bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
|
2010-09-09 18:54:59 +00:00
|
|
|
// Make sure we have VFP.
|
|
|
|
if (!Subtarget->hasVFP2()) return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT DstVT;
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *RetTy = I->getType();
|
2010-09-10 00:35:09 +00:00
|
|
|
if (!isTypeLegal(RetTy, DstVT))
|
2010-09-09 18:54:59 +00:00
|
|
|
return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-09 18:54:59 +00:00
|
|
|
unsigned Op = getRegForValue(I->getOperand(0));
|
|
|
|
if (Op == 0) return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-09 18:54:59 +00:00
|
|
|
unsigned Opc;
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *OpTy = I->getOperand(0)->getType();
|
2012-02-03 21:14:11 +00:00
|
|
|
if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
|
|
|
|
else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
|
2011-08-31 23:49:05 +00:00
|
|
|
else return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2012-02-03 20:27:51 +00:00
|
|
|
// f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
|
2010-10-05 23:13:24 +00:00
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
|
2010-09-09 18:54:59 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
|
|
|
|
ResultReg)
|
|
|
|
.addReg(Op));
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-09 21:44:45 +00:00
|
|
|
// This result needs to be in an integer register, but the conversion only
|
|
|
|
// takes place in fp-regs.
|
2010-09-10 00:34:35 +00:00
|
|
|
unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
|
2010-09-09 21:44:45 +00:00
|
|
|
if (IntReg == 0) return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-09 21:44:45 +00:00
|
|
|
UpdateValueMap(I, IntReg);
|
2010-09-09 18:54:59 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-10-11 08:27:59 +00:00
|
|
|
bool ARMFastISel::SelectSelect(const Instruction *I) {
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT VT;
|
|
|
|
if (!isTypeLegal(I->getType(), VT))
|
2010-10-11 08:27:59 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Things need to be register sized for register moves.
|
2010-11-03 11:35:31 +00:00
|
|
|
if (VT != MVT::i32) return false;
|
2010-10-11 08:27:59 +00:00
|
|
|
const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
|
|
|
|
|
|
|
|
unsigned CondReg = getRegForValue(I->getOperand(0));
|
|
|
|
if (CondReg == 0) return false;
|
|
|
|
unsigned Op1Reg = getRegForValue(I->getOperand(1));
|
|
|
|
if (Op1Reg == 0) return false;
|
|
|
|
|
2011-11-11 06:20:39 +00:00
|
|
|
// Check to see if we can use an immediate in the conditional move.
|
|
|
|
int Imm = 0;
|
|
|
|
bool UseImm = false;
|
|
|
|
bool isNegativeImm = false;
|
|
|
|
if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
|
|
|
|
assert (VT == MVT::i32 && "Expecting an i32.");
|
|
|
|
Imm = (int)ConstInt->getValue().getZExtValue();
|
|
|
|
if (Imm < 0) {
|
|
|
|
isNegativeImm = true;
|
|
|
|
Imm = ~Imm;
|
|
|
|
}
|
|
|
|
UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
|
|
|
|
(ARM_AM::getSOImmVal(Imm) != -1);
|
|
|
|
}
|
|
|
|
|
2011-11-28 10:31:27 +00:00
|
|
|
unsigned Op2Reg = 0;
|
2011-11-11 06:20:39 +00:00
|
|
|
if (!UseImm) {
|
|
|
|
Op2Reg = getRegForValue(I->getOperand(2));
|
|
|
|
if (Op2Reg == 0) return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
|
2010-10-11 08:27:59 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
|
2011-11-11 06:20:39 +00:00
|
|
|
.addReg(CondReg).addImm(0));
|
|
|
|
|
|
|
|
unsigned MovCCOpc;
|
|
|
|
if (!UseImm) {
|
|
|
|
MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
|
|
|
|
} else {
|
|
|
|
if (!isNegativeImm) {
|
|
|
|
MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
|
|
|
|
} else {
|
|
|
|
MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
|
|
|
|
}
|
|
|
|
}
|
2010-10-11 08:27:59 +00:00
|
|
|
unsigned ResultReg = createResultReg(RC);
|
2011-11-11 06:20:39 +00:00
|
|
|
if (!UseImm)
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
|
|
|
|
.addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
|
|
|
|
else
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
|
|
|
|
.addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
|
2010-10-11 08:27:59 +00:00
|
|
|
UpdateValueMap(I, ResultReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-02-03 21:07:27 +00:00
|
|
|
bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT VT;
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *Ty = I->getType();
|
2010-09-30 22:34:19 +00:00
|
|
|
if (!isTypeLegal(Ty, VT))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// If we have integer div support we should have selected this automagically.
|
|
|
|
// In case we have a real miss go ahead and return false and we'll pick
|
|
|
|
// it up later.
|
2010-10-11 08:38:55 +00:00
|
|
|
if (Subtarget->hasDivide()) return false;
|
|
|
|
|
2010-09-30 22:34:19 +00:00
|
|
|
// Otherwise emit a libcall.
|
|
|
|
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
|
2010-10-11 08:31:54 +00:00
|
|
|
if (VT == MVT::i8)
|
2012-02-03 21:07:27 +00:00
|
|
|
LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
|
2010-10-11 08:31:54 +00:00
|
|
|
else if (VT == MVT::i16)
|
2012-02-03 21:07:27 +00:00
|
|
|
LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
|
2010-09-30 22:34:19 +00:00
|
|
|
else if (VT == MVT::i32)
|
2012-02-03 21:07:27 +00:00
|
|
|
LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
|
2010-09-30 22:34:19 +00:00
|
|
|
else if (VT == MVT::i64)
|
2012-02-03 21:07:27 +00:00
|
|
|
LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
|
2010-09-30 22:34:19 +00:00
|
|
|
else if (VT == MVT::i128)
|
2012-02-03 21:07:27 +00:00
|
|
|
LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
|
2010-09-30 22:34:19 +00:00
|
|
|
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-30 22:34:19 +00:00
|
|
|
return ARMEmitLibcall(I, LC);
|
|
|
|
}
|
|
|
|
|
2012-02-03 21:23:45 +00:00
|
|
|
bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT VT;
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *Ty = I->getType();
|
2010-10-11 08:37:26 +00:00
|
|
|
if (!isTypeLegal(Ty, VT))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
|
|
|
|
if (VT == MVT::i8)
|
2012-02-03 21:23:45 +00:00
|
|
|
LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
|
2010-10-11 08:37:26 +00:00
|
|
|
else if (VT == MVT::i16)
|
2012-02-03 21:23:45 +00:00
|
|
|
LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
|
2010-10-11 08:37:26 +00:00
|
|
|
else if (VT == MVT::i32)
|
2012-02-03 21:23:45 +00:00
|
|
|
LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
|
2010-10-11 08:37:26 +00:00
|
|
|
else if (VT == MVT::i64)
|
2012-02-03 21:23:45 +00:00
|
|
|
LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
|
2010-10-11 08:37:26 +00:00
|
|
|
else if (VT == MVT::i128)
|
2012-02-03 21:23:45 +00:00
|
|
|
LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
|
2010-10-11 08:40:05 +00:00
|
|
|
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
|
2010-10-15 18:02:07 +00:00
|
|
|
|
2010-10-11 08:37:26 +00:00
|
|
|
return ARMEmitLibcall(I, LC);
|
|
|
|
}
|
|
|
|
|
2012-02-06 23:50:07 +00:00
|
|
|
bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
|
|
|
|
EVT DestVT = TLI.getValueType(I->getType(), true);
|
|
|
|
|
|
|
|
// We can get here in the case when we have a binary operation on a non-legal
|
|
|
|
// type and the target independent selector doesn't know how to handle it.
|
|
|
|
if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
|
|
|
|
return false;
|
2012-06-14 06:08:19 +00:00
|
|
|
|
2012-02-08 02:29:21 +00:00
|
|
|
unsigned Opc;
|
|
|
|
switch (ISDOpcode) {
|
|
|
|
default: return false;
|
|
|
|
case ISD::ADD:
|
|
|
|
Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
|
|
|
|
break;
|
|
|
|
case ISD::OR:
|
|
|
|
Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
|
|
|
|
break;
|
2012-02-08 02:45:44 +00:00
|
|
|
case ISD::SUB:
|
|
|
|
Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
|
|
|
|
break;
|
2012-02-08 02:29:21 +00:00
|
|
|
}
|
|
|
|
|
2012-02-06 23:50:07 +00:00
|
|
|
unsigned SrcReg1 = getRegForValue(I->getOperand(0));
|
|
|
|
if (SrcReg1 == 0) return false;
|
|
|
|
|
|
|
|
// TODO: Often the 2nd operand is an immediate, which can be encoded directly
|
|
|
|
// in the instruction, rather then materializing the value in a register.
|
|
|
|
unsigned SrcReg2 = getRegForValue(I->getOperand(1));
|
|
|
|
if (SrcReg2 == 0) return false;
|
|
|
|
|
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(Opc), ResultReg)
|
|
|
|
.addReg(SrcReg1).addReg(SrcReg2));
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
|
2010-09-09 01:02:03 +00:00
|
|
|
EVT VT = TLI.getValueType(I->getType(), true);
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-09-09 00:53:57 +00:00
|
|
|
// We can get here in the case when we want to use NEON for our fp
|
|
|
|
// operations, but can't figure out how to. Just use the vfp instructions
|
|
|
|
// if we have them.
|
|
|
|
// FIXME: It'd be nice to use NEON instructions.
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *Ty = I->getType();
|
2010-09-09 01:02:03 +00:00
|
|
|
bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
|
|
|
|
if (isFloat && !Subtarget->hasVFP2())
|
|
|
|
return false;
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-09-09 00:53:57 +00:00
|
|
|
unsigned Opc;
|
2010-11-03 12:17:33 +00:00
|
|
|
bool is64bit = VT == MVT::f64 || VT == MVT::i64;
|
2010-09-09 00:53:57 +00:00
|
|
|
switch (ISDOpcode) {
|
|
|
|
default: return false;
|
|
|
|
case ISD::FADD:
|
2010-09-09 01:02:03 +00:00
|
|
|
Opc = is64bit ? ARM::VADDD : ARM::VADDS;
|
2010-09-09 00:53:57 +00:00
|
|
|
break;
|
|
|
|
case ISD::FSUB:
|
2010-09-09 01:02:03 +00:00
|
|
|
Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
|
2010-09-09 00:53:57 +00:00
|
|
|
break;
|
|
|
|
case ISD::FMUL:
|
2010-09-09 01:02:03 +00:00
|
|
|
Opc = is64bit ? ARM::VMULD : ARM::VMULS;
|
2010-09-09 00:53:57 +00:00
|
|
|
break;
|
|
|
|
}
|
2011-11-16 18:39:44 +00:00
|
|
|
unsigned Op1 = getRegForValue(I->getOperand(0));
|
|
|
|
if (Op1 == 0) return false;
|
|
|
|
|
|
|
|
unsigned Op2 = getRegForValue(I->getOperand(1));
|
|
|
|
if (Op2 == 0) return false;
|
|
|
|
|
2010-09-09 01:02:03 +00:00
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
|
2010-09-09 00:53:57 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(Opc), ResultReg)
|
|
|
|
.addReg(Op1).addReg(Op2));
|
2010-09-09 20:26:31 +00:00
|
|
|
UpdateValueMap(I, ResultReg);
|
2010-09-09 00:53:57 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-09-10 23:18:12 +00:00
|
|
|
// Call Handling Code
|
|
|
|
|
2012-07-19 09:49:00 +00:00
|
|
|
// This is largely taken directly from CCAssignFnForNode
|
2010-09-10 23:18:12 +00:00
|
|
|
// TODO: We may not support all of this.
|
2012-07-19 09:49:00 +00:00
|
|
|
CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
|
|
|
|
bool Return,
|
|
|
|
bool isVarArg) {
|
2010-09-10 23:18:12 +00:00
|
|
|
switch (CC) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unsupported calling convention");
|
|
|
|
case CallingConv::Fast:
|
2012-08-16 05:15:53 +00:00
|
|
|
if (Subtarget->hasVFP2() && !isVarArg) {
|
|
|
|
if (!Subtarget->isAAPCS_ABI())
|
|
|
|
return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
|
|
|
|
// For AAPCS ABI targets, just use VFP variant of the calling convention.
|
|
|
|
return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
|
|
|
|
}
|
2010-10-22 18:57:05 +00:00
|
|
|
// Fallthrough
|
|
|
|
case CallingConv::C:
|
2010-09-10 23:18:12 +00:00
|
|
|
// Use target triple & subtarget features to do actual dispatch.
|
|
|
|
if (Subtarget->isAAPCS_ABI()) {
|
|
|
|
if (Subtarget->hasVFP2() &&
|
2012-07-19 09:49:00 +00:00
|
|
|
TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
|
2010-09-10 23:18:12 +00:00
|
|
|
return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
|
|
|
|
else
|
|
|
|
return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
|
|
|
|
} else
|
|
|
|
return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
|
|
|
|
case CallingConv::ARM_AAPCS_VFP:
|
2012-07-19 09:49:00 +00:00
|
|
|
if (!isVarArg)
|
|
|
|
return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
|
|
|
|
// Fall through to soft float variant, variadic functions don't
|
|
|
|
// use hard floating point ABI.
|
2010-09-10 23:18:12 +00:00
|
|
|
case CallingConv::ARM_AAPCS:
|
|
|
|
return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
|
|
|
|
case CallingConv::ARM_APCS:
|
|
|
|
return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
|
2012-08-03 00:05:53 +00:00
|
|
|
case CallingConv::GHC:
|
|
|
|
if (Return)
|
|
|
|
llvm_unreachable("Can't return in GHC call convention");
|
|
|
|
else
|
|
|
|
return CC_ARM_APCS_GHC;
|
2010-09-10 23:18:12 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-29 23:11:09 +00:00
|
|
|
bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
|
|
|
|
SmallVectorImpl<unsigned> &ArgRegs,
|
2010-11-03 11:35:31 +00:00
|
|
|
SmallVectorImpl<MVT> &ArgVTs,
|
2010-09-29 23:11:09 +00:00
|
|
|
SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
|
|
|
|
SmallVectorImpl<unsigned> &RegArgs,
|
|
|
|
CallingConv::ID CC,
|
2012-07-19 09:49:00 +00:00
|
|
|
unsigned &NumBytes,
|
|
|
|
bool isVarArg) {
|
2010-09-29 23:11:09 +00:00
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
2012-07-19 09:49:00 +00:00
|
|
|
CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
|
|
|
|
CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
|
|
|
|
CCAssignFnForCall(CC, false, isVarArg));
|
2010-09-29 23:11:09 +00:00
|
|
|
|
2012-03-16 23:11:07 +00:00
|
|
|
// Check that we can handle all of the arguments. If we can't, then bail out
|
|
|
|
// now before we add code to the MBB.
|
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
|
|
CCValAssign &VA = ArgLocs[i];
|
|
|
|
MVT ArgVT = ArgVTs[VA.getValNo()];
|
|
|
|
|
|
|
|
// We don't handle NEON/vector parameters yet.
|
|
|
|
if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Now copy/store arg to correct locations.
|
|
|
|
if (VA.isRegLoc() && !VA.needsCustom()) {
|
|
|
|
continue;
|
|
|
|
} else if (VA.needsCustom()) {
|
|
|
|
// TODO: We need custom lowering for vector (v2f64) args.
|
|
|
|
if (VA.getLocVT() != MVT::f64 ||
|
|
|
|
// TODO: Only handle register args for now.
|
|
|
|
!VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
switch (static_cast<EVT>(ArgVT).getSimpleVT().SimpleTy) {
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
case MVT::i32:
|
|
|
|
break;
|
|
|
|
case MVT::f32:
|
|
|
|
if (!Subtarget->hasVFP2())
|
|
|
|
return false;
|
|
|
|
break;
|
|
|
|
case MVT::f64:
|
|
|
|
if (!Subtarget->hasVFP2())
|
|
|
|
return false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// At the point, we are able to handle the call's arguments in fast isel.
|
|
|
|
|
2010-09-29 23:11:09 +00:00
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
|
|
|
NumBytes = CCInfo.getNextStackOffset();
|
|
|
|
|
|
|
|
// Issue CALLSEQ_START
|
2011-06-28 21:14:33 +00:00
|
|
|
unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
|
2010-10-11 21:20:02 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(AdjStackDown))
|
|
|
|
.addImm(NumBytes));
|
2010-09-29 23:11:09 +00:00
|
|
|
|
|
|
|
// Process the args.
|
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
|
|
CCValAssign &VA = ArgLocs[i];
|
|
|
|
unsigned Arg = ArgRegs[VA.getValNo()];
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT ArgVT = ArgVTs[VA.getValNo()];
|
2010-09-29 23:11:09 +00:00
|
|
|
|
2012-03-16 23:11:07 +00:00
|
|
|
assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
|
|
|
|
"We don't handle NEON/vector parameters yet.");
|
2010-10-23 09:37:17 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
// Handle arg promotion, etc.
|
2010-09-29 23:11:09 +00:00
|
|
|
switch (VA.getLocInfo()) {
|
|
|
|
case CCValAssign::Full: break;
|
2010-10-18 02:17:53 +00:00
|
|
|
case CCValAssign::SExt: {
|
2011-12-02 20:25:18 +00:00
|
|
|
MVT DestVT = VA.getLocVT();
|
2012-02-14 22:29:48 +00:00
|
|
|
Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
|
|
|
|
assert (Arg != 0 && "Failed to emit a sext");
|
2011-12-02 20:25:18 +00:00
|
|
|
ArgVT = DestVT;
|
2010-10-18 02:17:53 +00:00
|
|
|
break;
|
|
|
|
}
|
2011-11-05 20:16:15 +00:00
|
|
|
case CCValAssign::AExt:
|
|
|
|
// Intentional fall-through. Handle AExt and ZExt.
|
2010-10-18 02:17:53 +00:00
|
|
|
case CCValAssign::ZExt: {
|
2011-12-02 20:25:18 +00:00
|
|
|
MVT DestVT = VA.getLocVT();
|
2012-02-14 22:29:48 +00:00
|
|
|
Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
|
|
|
|
assert (Arg != 0 && "Failed to emit a sext");
|
2011-12-02 20:25:18 +00:00
|
|
|
ArgVT = DestVT;
|
2010-10-18 02:17:53 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case CCValAssign::BCvt: {
|
2010-11-23 03:31:01 +00:00
|
|
|
unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
|
2010-11-03 11:35:31 +00:00
|
|
|
/*TODO: Kill=*/false);
|
2010-10-18 02:17:53 +00:00
|
|
|
assert(BC != 0 && "Failed to emit a bitcast!");
|
|
|
|
Arg = BC;
|
|
|
|
ArgVT = VA.getLocVT();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: llvm_unreachable("Unknown arg promotion!");
|
2010-09-29 23:11:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Now copy/store arg to correct locations.
|
2010-10-11 21:20:02 +00:00
|
|
|
if (VA.isRegLoc() && !VA.needsCustom()) {
|
2010-09-29 23:11:09 +00:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
|
2010-09-30 20:49:44 +00:00
|
|
|
VA.getLocReg())
|
2011-11-05 20:16:15 +00:00
|
|
|
.addReg(Arg);
|
2010-09-29 23:11:09 +00:00
|
|
|
RegArgs.push_back(VA.getLocReg());
|
2010-10-21 00:01:47 +00:00
|
|
|
} else if (VA.needsCustom()) {
|
|
|
|
// TODO: We need custom lowering for vector (v2f64) args.
|
2012-03-16 23:11:07 +00:00
|
|
|
assert(VA.getLocVT() == MVT::f64 &&
|
|
|
|
"Custom lowering for v2f64 args not available");
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-10-21 00:01:47 +00:00
|
|
|
CCValAssign &NextVA = ArgLocs[++i];
|
|
|
|
|
2012-03-16 23:11:07 +00:00
|
|
|
assert(VA.isRegLoc() && NextVA.isRegLoc() &&
|
|
|
|
"We only handle register args!");
|
2010-10-21 00:01:47 +00:00
|
|
|
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(ARM::VMOVRRD), VA.getLocReg())
|
|
|
|
.addReg(NextVA.getLocReg(), RegState::Define)
|
|
|
|
.addReg(Arg));
|
|
|
|
RegArgs.push_back(VA.getLocReg());
|
|
|
|
RegArgs.push_back(NextVA.getLocReg());
|
2010-09-29 23:11:09 +00:00
|
|
|
} else {
|
2010-10-21 20:09:54 +00:00
|
|
|
assert(VA.isMemLoc());
|
|
|
|
// Need to store on the stack.
|
2010-11-19 22:30:02 +00:00
|
|
|
Address Addr;
|
|
|
|
Addr.BaseType = Address::RegBase;
|
|
|
|
Addr.Base.Reg = ARM::SP;
|
|
|
|
Addr.Offset = VA.getLocMemOffset();
|
2010-10-21 20:09:54 +00:00
|
|
|
|
2012-03-16 23:11:07 +00:00
|
|
|
bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
|
|
|
|
assert(EmitRet && "Could not emit a store for argument!");
|
2010-09-29 23:11:09 +00:00
|
|
|
}
|
|
|
|
}
|
2012-03-16 23:11:07 +00:00
|
|
|
|
2010-09-29 23:11:09 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-11-03 11:35:31 +00:00
|
|
|
bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
|
2010-09-29 23:11:09 +00:00
|
|
|
const Instruction *I, CallingConv::ID CC,
|
2012-07-19 09:49:00 +00:00
|
|
|
unsigned &NumBytes, bool isVarArg) {
|
2010-09-29 23:11:09 +00:00
|
|
|
// Issue CALLSEQ_END
|
2011-06-28 21:14:33 +00:00
|
|
|
unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
|
2010-10-11 21:20:02 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(AdjStackUp))
|
|
|
|
.addImm(NumBytes).addImm(0));
|
2010-09-29 23:11:09 +00:00
|
|
|
|
|
|
|
// Now the return value.
|
2010-11-03 11:35:31 +00:00
|
|
|
if (RetVT != MVT::isVoid) {
|
2010-09-29 23:11:09 +00:00
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2012-07-19 09:49:00 +00:00
|
|
|
CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
|
|
|
|
CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
|
2010-09-29 23:11:09 +00:00
|
|
|
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
2010-11-03 11:35:31 +00:00
|
|
|
if (RVLocs.size() == 2 && RetVT == MVT::f64) {
|
2010-10-01 00:00:11 +00:00
|
|
|
// For this move we copy into two registers and then move into the
|
|
|
|
// double fp reg we want.
|
|
|
|
EVT DestVT = RVLocs[0].getValVT();
|
2012-02-22 05:59:10 +00:00
|
|
|
const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
|
2010-10-01 00:00:11 +00:00
|
|
|
unsigned ResultReg = createResultReg(DstRC);
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(ARM::VMOVDRR), ResultReg)
|
2010-10-20 08:02:24 +00:00
|
|
|
.addReg(RVLocs[0].getLocReg())
|
|
|
|
.addReg(RVLocs[1].getLocReg()));
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-10-20 08:02:24 +00:00
|
|
|
UsedRegs.push_back(RVLocs[0].getLocReg());
|
|
|
|
UsedRegs.push_back(RVLocs[1].getLocReg());
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-10-11 08:38:55 +00:00
|
|
|
// Finally update the result.
|
2010-10-01 00:00:11 +00:00
|
|
|
UpdateValueMap(I, ResultReg);
|
2012-05-11 18:51:55 +00:00
|
|
|
} else {
|
|
|
|
assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
|
2010-10-01 00:00:11 +00:00
|
|
|
EVT CopyVT = RVLocs[0].getValVT();
|
2011-11-08 00:03:32 +00:00
|
|
|
|
|
|
|
// Special handling for extended integers.
|
|
|
|
if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
|
|
|
|
CopyVT = MVT::i32;
|
|
|
|
|
2012-02-22 05:59:10 +00:00
|
|
|
const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
|
2010-09-29 23:11:09 +00:00
|
|
|
|
2010-10-01 00:00:11 +00:00
|
|
|
unsigned ResultReg = createResultReg(DstRC);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
|
|
|
|
ResultReg).addReg(RVLocs[0].getLocReg());
|
|
|
|
UsedRegs.push_back(RVLocs[0].getLocReg());
|
2010-09-29 23:11:09 +00:00
|
|
|
|
2010-10-11 08:38:55 +00:00
|
|
|
// Finally update the result.
|
2010-10-01 00:00:11 +00:00
|
|
|
UpdateValueMap(I, ResultReg);
|
|
|
|
}
|
2010-09-29 23:11:09 +00:00
|
|
|
}
|
|
|
|
|
2010-10-11 08:38:55 +00:00
|
|
|
return true;
|
2010-09-29 23:11:09 +00:00
|
|
|
}
|
|
|
|
|
2010-10-22 01:28:00 +00:00
|
|
|
bool ARMFastISel::SelectRet(const Instruction *I) {
|
|
|
|
const ReturnInst *Ret = cast<ReturnInst>(I);
|
|
|
|
const Function &F = *I->getParent()->getParent();
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-10-22 01:28:00 +00:00
|
|
|
if (!FuncInfo.CanLowerReturn)
|
|
|
|
return false;
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-10-22 01:28:00 +00:00
|
|
|
CallingConv::ID CC = F.getCallingConv();
|
|
|
|
if (Ret->getNumOperands() > 0) {
|
|
|
|
SmallVector<ISD::OutputArg, 4> Outs;
|
|
|
|
GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
|
|
|
|
Outs, TLI);
|
|
|
|
|
|
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
|
|
SmallVector<CCValAssign, 16> ValLocs;
|
2011-09-13 20:30:37 +00:00
|
|
|
CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
|
2012-07-19 09:49:00 +00:00
|
|
|
CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
|
|
|
|
F.isVarArg()));
|
2010-10-22 01:28:00 +00:00
|
|
|
|
|
|
|
const Value *RV = Ret->getOperand(0);
|
|
|
|
unsigned Reg = getRegForValue(RV);
|
|
|
|
if (Reg == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Only handle a single return value for now.
|
|
|
|
if (ValLocs.size() != 1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
CCValAssign &VA = ValLocs[0];
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-10-22 01:28:00 +00:00
|
|
|
// Don't bother handling odd stuff for now.
|
|
|
|
if (VA.getLocInfo() != CCValAssign::Full)
|
|
|
|
return false;
|
|
|
|
// Only handle register returns for now.
|
|
|
|
if (!VA.isRegLoc())
|
|
|
|
return false;
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2010-10-22 01:28:00 +00:00
|
|
|
unsigned SrcReg = Reg + VA.getValNo();
|
2011-11-04 00:50:21 +00:00
|
|
|
EVT RVVT = TLI.getValueType(RV->getType());
|
|
|
|
EVT DestVT = VA.getValVT();
|
|
|
|
// Special handling for extended integers.
|
|
|
|
if (RVVT != DestVT) {
|
|
|
|
if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
assert(DestVT == MVT::i32 && "ARM should always ext to i32");
|
|
|
|
|
2012-02-17 01:21:28 +00:00
|
|
|
// Perform extension if flagged as either zext or sext. Otherwise, do
|
|
|
|
// nothing.
|
|
|
|
if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
|
|
|
|
SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
|
|
|
|
if (SrcReg == 0) return false;
|
|
|
|
}
|
2011-11-04 00:50:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Make the copy.
|
2010-10-22 01:28:00 +00:00
|
|
|
unsigned DstReg = VA.getLocReg();
|
|
|
|
const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
|
|
|
|
// Avoid a cross-class copy. This is very unlikely.
|
|
|
|
if (!SrcRC->contains(DstReg))
|
|
|
|
return false;
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
|
|
|
|
DstReg).addReg(SrcReg);
|
|
|
|
|
|
|
|
// Mark the register as live out of the function.
|
|
|
|
MRI.addLiveOut(VA.getLocReg());
|
|
|
|
}
|
2010-10-27 21:39:08 +00:00
|
|
|
|
2011-11-08 21:12:00 +00:00
|
|
|
unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
|
2010-10-22 01:28:00 +00:00
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(RetOpc)));
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-06-12 19:25:13 +00:00
|
|
|
unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
|
|
|
|
if (UseReg)
|
|
|
|
return isThumb2 ? ARM::tBLXr : ARM::BLX;
|
|
|
|
else
|
|
|
|
return isThumb2 ? ARM::tBL : ARM::BL;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
|
|
|
|
GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
|
|
|
|
GlobalValue::ExternalLinkage, 0, Name);
|
|
|
|
return ARMMaterializeGV(GV, TLI.getValueType(GV->getType()));
|
2011-02-22 01:37:10 +00:00
|
|
|
}
|
|
|
|
|
2010-09-14 23:03:37 +00:00
|
|
|
// A quick function that will emit a call for a named libcall in F with the
|
|
|
|
// vector of passed arguments for the Instruction in I. We can assume that we
|
2010-10-11 08:38:55 +00:00
|
|
|
// can emit a call for any libcall we can produce. This is an abridged version
|
|
|
|
// of the full call infrastructure since we won't need to worry about things
|
2010-09-14 23:03:37 +00:00
|
|
|
// like computed function pointers or strange arguments at call sites.
|
|
|
|
// TODO: Try to unify this and the normal call bits for ARM, then try to unify
|
|
|
|
// with X86.
|
2010-09-28 01:21:42 +00:00
|
|
|
bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
|
|
|
|
CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-14 23:03:37 +00:00
|
|
|
// Handle *simple* calls for now.
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *RetTy = I->getType();
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT RetVT;
|
2010-09-14 23:03:37 +00:00
|
|
|
if (RetTy->isVoidTy())
|
|
|
|
RetVT = MVT::isVoid;
|
|
|
|
else if (!isTypeLegal(RetTy, RetVT))
|
|
|
|
return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2012-05-11 18:51:55 +00:00
|
|
|
// Can't handle non-double multi-reg retvals.
|
2012-06-14 06:08:19 +00:00
|
|
|
if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
|
2012-05-11 18:51:55 +00:00
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
|
|
CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
|
2012-07-19 09:49:00 +00:00
|
|
|
CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
|
2012-05-11 18:51:55 +00:00
|
|
|
if (RVLocs.size() >= 2 && RetVT != MVT::f64)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-09-29 23:11:09 +00:00
|
|
|
// Set up the argument vectors.
|
2010-09-14 23:03:37 +00:00
|
|
|
SmallVector<Value*, 8> Args;
|
|
|
|
SmallVector<unsigned, 8> ArgRegs;
|
2010-11-03 11:35:31 +00:00
|
|
|
SmallVector<MVT, 8> ArgVTs;
|
2010-09-14 23:03:37 +00:00
|
|
|
SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
|
|
|
|
Args.reserve(I->getNumOperands());
|
|
|
|
ArgRegs.reserve(I->getNumOperands());
|
|
|
|
ArgVTs.reserve(I->getNumOperands());
|
|
|
|
ArgFlags.reserve(I->getNumOperands());
|
2010-09-28 01:21:42 +00:00
|
|
|
for (unsigned i = 0; i < I->getNumOperands(); ++i) {
|
2010-09-14 23:03:37 +00:00
|
|
|
Value *Op = I->getOperand(i);
|
|
|
|
unsigned Arg = getRegForValue(Op);
|
|
|
|
if (Arg == 0) return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *ArgTy = Op->getType();
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT ArgVT;
|
2010-09-14 23:03:37 +00:00
|
|
|
if (!isTypeLegal(ArgTy, ArgVT)) return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-14 23:03:37 +00:00
|
|
|
ISD::ArgFlagsTy Flags;
|
|
|
|
unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
|
|
|
|
Flags.setOrigAlign(OriginalAlignment);
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-14 23:03:37 +00:00
|
|
|
Args.push_back(Op);
|
|
|
|
ArgRegs.push_back(Arg);
|
|
|
|
ArgVTs.push_back(ArgVT);
|
|
|
|
ArgFlags.push_back(Flags);
|
|
|
|
}
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-29 23:11:09 +00:00
|
|
|
// Handle the arguments now that we've gotten them.
|
2010-09-14 23:03:37 +00:00
|
|
|
SmallVector<unsigned, 4> RegArgs;
|
2010-09-29 23:11:09 +00:00
|
|
|
unsigned NumBytes;
|
2012-07-19 09:49:00 +00:00
|
|
|
if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
|
|
|
|
RegArgs, CC, NumBytes, false))
|
2010-09-29 23:11:09 +00:00
|
|
|
return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2012-06-12 19:25:13 +00:00
|
|
|
unsigned CalleeReg = 0;
|
|
|
|
if (EnableARMLongCalls) {
|
|
|
|
CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
|
|
|
|
if (CalleeReg == 0) return false;
|
|
|
|
}
|
|
|
|
|
2012-04-06 00:04:58 +00:00
|
|
|
// Issue the call.
|
2012-06-12 19:25:13 +00:00
|
|
|
unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
|
|
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
|
|
|
|
DL, TII.get(CallOpc));
|
2012-08-24 20:52:46 +00:00
|
|
|
// BL / BLX don't take a predicate, but tBL / tBLX do.
|
|
|
|
if (isThumb2)
|
2012-06-12 19:25:13 +00:00
|
|
|
AddDefaultPred(MIB);
|
2012-08-24 20:52:46 +00:00
|
|
|
if (EnableARMLongCalls)
|
|
|
|
MIB.addReg(CalleeReg);
|
|
|
|
else
|
|
|
|
MIB.addExternalSymbol(TLI.getLibcallName(Call));
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-14 23:03:37 +00:00
|
|
|
// Add implicit physical register uses to the call.
|
|
|
|
for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
|
2012-08-24 20:52:46 +00:00
|
|
|
MIB.addReg(RegArgs[i], RegState::Implicit);
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2012-02-24 01:19:29 +00:00
|
|
|
// Add a register mask with the call-preserved registers.
|
|
|
|
// Proper defs for return values will be added by setPhysRegsDeadExcept().
|
|
|
|
MIB.addRegMask(TRI.getCallPreservedMask(CC));
|
|
|
|
|
2010-09-29 23:11:09 +00:00
|
|
|
// Finish off the call including any return values.
|
2010-10-11 08:38:55 +00:00
|
|
|
SmallVector<unsigned, 4> UsedRegs;
|
2012-07-19 09:49:00 +00:00
|
|
|
if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-14 23:03:37 +00:00
|
|
|
// Set all unused physreg defs as dead.
|
|
|
|
static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-14 23:03:37 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-11-11 23:31:03 +00:00
|
|
|
bool ARMFastISel::SelectCall(const Instruction *I,
|
|
|
|
const char *IntrMemName = 0) {
|
2010-09-30 20:49:44 +00:00
|
|
|
const CallInst *CI = cast<CallInst>(I);
|
|
|
|
const Value *Callee = CI->getCalledValue();
|
|
|
|
|
2011-11-11 23:31:03 +00:00
|
|
|
// Can't handle inline asm.
|
|
|
|
if (isa<InlineAsm>(Callee)) return false;
|
2010-09-30 20:49:44 +00:00
|
|
|
|
|
|
|
// Check the calling convention.
|
|
|
|
ImmutableCallSite CS(CI);
|
|
|
|
CallingConv::ID CC = CS.getCallingConv();
|
2010-10-18 06:49:12 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
// TODO: Avoid some calling conventions?
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2011-07-18 04:54:35 +00:00
|
|
|
PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
|
|
|
|
FunctionType *FTy = cast<FunctionType>(PT->getElementType());
|
2012-07-19 09:49:00 +00:00
|
|
|
bool isVarArg = FTy->isVarArg();
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
// Handle *simple* calls for now.
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *RetTy = I->getType();
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT RetVT;
|
2010-09-30 20:49:44 +00:00
|
|
|
if (RetTy->isVoidTy())
|
|
|
|
RetVT = MVT::isVoid;
|
2011-11-08 00:03:32 +00:00
|
|
|
else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
|
|
|
|
RetVT != MVT::i8 && RetVT != MVT::i1)
|
2010-09-30 20:49:44 +00:00
|
|
|
return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2012-05-11 18:51:55 +00:00
|
|
|
// Can't handle non-double multi-reg retvals.
|
|
|
|
if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
|
|
|
|
RetVT != MVT::i16 && RetVT != MVT::i32) {
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2012-07-19 09:49:00 +00:00
|
|
|
CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
|
|
|
|
CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
|
2012-05-11 18:51:55 +00:00
|
|
|
if (RVLocs.size() >= 2 && RetVT != MVT::f64)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
// Set up the argument vectors.
|
|
|
|
SmallVector<Value*, 8> Args;
|
|
|
|
SmallVector<unsigned, 8> ArgRegs;
|
2010-11-03 11:35:31 +00:00
|
|
|
SmallVector<MVT, 8> ArgVTs;
|
2010-09-30 20:49:44 +00:00
|
|
|
SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
|
2012-02-15 00:23:55 +00:00
|
|
|
unsigned arg_size = CS.arg_size();
|
|
|
|
Args.reserve(arg_size);
|
|
|
|
ArgRegs.reserve(arg_size);
|
|
|
|
ArgVTs.reserve(arg_size);
|
|
|
|
ArgFlags.reserve(arg_size);
|
2010-09-30 20:49:44 +00:00
|
|
|
for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
|
|
|
|
i != e; ++i) {
|
2011-11-11 23:31:03 +00:00
|
|
|
// If we're lowering a memory intrinsic instead of a regular call, skip the
|
|
|
|
// last two arguments, which shouldn't be passed to the underlying function.
|
|
|
|
if (IntrMemName && e-i <= 2)
|
|
|
|
break;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
ISD::ArgFlagsTy Flags;
|
|
|
|
unsigned AttrInd = i - CS.arg_begin() + 1;
|
2012-10-09 21:38:14 +00:00
|
|
|
if (CS.paramHasAttr(AttrInd, Attributes::SExt))
|
2010-09-30 20:49:44 +00:00
|
|
|
Flags.setSExt();
|
2012-10-09 21:38:14 +00:00
|
|
|
if (CS.paramHasAttr(AttrInd, Attributes::ZExt))
|
2010-09-30 20:49:44 +00:00
|
|
|
Flags.setZExt();
|
|
|
|
|
2011-11-04 00:58:10 +00:00
|
|
|
// FIXME: Only handle *easy* calls for now.
|
2012-10-09 21:38:14 +00:00
|
|
|
if (CS.paramHasAttr(AttrInd, Attributes::InReg) ||
|
|
|
|
CS.paramHasAttr(AttrInd, Attributes::StructRet) ||
|
|
|
|
CS.paramHasAttr(AttrInd, Attributes::Nest) ||
|
|
|
|
CS.paramHasAttr(AttrInd, Attributes::ByVal))
|
2010-09-30 20:49:44 +00:00
|
|
|
return false;
|
|
|
|
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *ArgTy = (*i)->getType();
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT ArgVT;
|
2011-11-05 20:16:15 +00:00
|
|
|
if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
|
|
|
|
ArgVT != MVT::i1)
|
2010-09-30 20:49:44 +00:00
|
|
|
return false;
|
2011-11-18 01:17:34 +00:00
|
|
|
|
|
|
|
unsigned Arg = getRegForValue(*i);
|
|
|
|
if (Arg == 0)
|
|
|
|
return false;
|
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
|
|
|
|
Flags.setOrigAlign(OriginalAlignment);
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
Args.push_back(*i);
|
|
|
|
ArgRegs.push_back(Arg);
|
|
|
|
ArgVTs.push_back(ArgVT);
|
|
|
|
ArgFlags.push_back(Flags);
|
|
|
|
}
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
// Handle the arguments now that we've gotten them.
|
|
|
|
SmallVector<unsigned, 4> RegArgs;
|
|
|
|
unsigned NumBytes;
|
2012-07-19 09:49:00 +00:00
|
|
|
if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
|
|
|
|
RegArgs, CC, NumBytes, isVarArg))
|
2010-09-30 20:49:44 +00:00
|
|
|
return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2012-06-12 19:25:13 +00:00
|
|
|
bool UseReg = false;
|
2012-05-23 18:38:57 +00:00
|
|
|
const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
|
2012-06-12 19:25:13 +00:00
|
|
|
if (!GV || EnableARMLongCalls) UseReg = true;
|
|
|
|
|
2012-05-23 18:38:57 +00:00
|
|
|
unsigned CalleeReg = 0;
|
2012-06-12 19:25:13 +00:00
|
|
|
if (UseReg) {
|
|
|
|
if (IntrMemName)
|
|
|
|
CalleeReg = getLibcallReg(IntrMemName);
|
|
|
|
else
|
|
|
|
CalleeReg = getRegForValue(Callee);
|
2012-05-23 18:38:57 +00:00
|
|
|
|
|
|
|
if (CalleeReg == 0) return false;
|
|
|
|
}
|
|
|
|
|
2012-06-12 19:25:13 +00:00
|
|
|
// Issue the call.
|
|
|
|
unsigned CallOpc = ARMSelectCallOp(UseReg);
|
|
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
|
|
|
|
DL, TII.get(CallOpc));
|
|
|
|
|
2012-08-24 20:52:46 +00:00
|
|
|
// ARM calls don't take a predicate, but tBL / tBLX do.
|
|
|
|
if(isThumb2)
|
2012-06-12 19:25:13 +00:00
|
|
|
AddDefaultPred(MIB);
|
2012-08-24 20:52:46 +00:00
|
|
|
if (UseReg)
|
|
|
|
MIB.addReg(CalleeReg);
|
|
|
|
else if (!IntrMemName)
|
|
|
|
MIB.addGlobalAddress(GV, 0, 0);
|
|
|
|
else
|
|
|
|
MIB.addExternalSymbol(IntrMemName, 0);
|
2012-06-14 06:08:19 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
// Add implicit physical register uses to the call.
|
|
|
|
for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
|
2012-08-24 20:52:46 +00:00
|
|
|
MIB.addReg(RegArgs[i], RegState::Implicit);
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2012-02-24 01:19:29 +00:00
|
|
|
// Add a register mask with the call-preserved registers.
|
|
|
|
// Proper defs for return values will be added by setPhysRegsDeadExcept().
|
|
|
|
MIB.addRegMask(TRI.getCallPreservedMask(CC));
|
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
// Finish off the call including any return values.
|
2010-10-11 08:38:55 +00:00
|
|
|
SmallVector<unsigned, 4> UsedRegs;
|
2012-07-19 09:49:00 +00:00
|
|
|
if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
|
|
|
|
return false;
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
// Set all unused physreg defs as dead.
|
|
|
|
static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
|
2010-10-11 08:38:55 +00:00
|
|
|
|
2010-09-30 20:49:44 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-11-14 23:04:09 +00:00
|
|
|
bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
|
2011-11-14 22:46:17 +00:00
|
|
|
return Len <= 16;
|
|
|
|
}
|
|
|
|
|
2012-04-06 23:43:50 +00:00
|
|
|
bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
|
|
|
|
uint64_t Len) {
|
2011-11-14 22:46:17 +00:00
|
|
|
// Make sure we don't bloat code by inlining very large memcpy's.
|
2011-11-14 23:04:09 +00:00
|
|
|
if (!ARMIsMemCpySmall(Len))
|
2011-11-14 22:46:17 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// We don't care about alignment here since we just emit integer accesses.
|
|
|
|
while (Len) {
|
|
|
|
MVT VT;
|
|
|
|
if (Len >= 4)
|
|
|
|
VT = MVT::i32;
|
|
|
|
else if (Len >= 2)
|
|
|
|
VT = MVT::i16;
|
|
|
|
else {
|
|
|
|
assert(Len == 1);
|
|
|
|
VT = MVT::i8;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool RV;
|
|
|
|
unsigned ResultReg;
|
|
|
|
RV = ARMEmitLoad(VT, ResultReg, Src);
|
2012-01-11 20:55:27 +00:00
|
|
|
assert (RV == true && "Should be able to handle this load.");
|
2011-11-14 22:46:17 +00:00
|
|
|
RV = ARMEmitStore(VT, ResultReg, Dest);
|
2012-01-11 20:55:27 +00:00
|
|
|
assert (RV == true && "Should be able to handle this store.");
|
2012-02-05 14:20:11 +00:00
|
|
|
(void)RV;
|
2011-11-14 22:46:17 +00:00
|
|
|
|
|
|
|
unsigned Size = VT.getSizeInBits()/8;
|
|
|
|
Len -= Size;
|
|
|
|
Dest.Offset += Size;
|
|
|
|
Src.Offset += Size;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-11-11 23:31:03 +00:00
|
|
|
bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
|
|
|
|
// FIXME: Handle more intrinsics.
|
|
|
|
switch (I.getIntrinsicID()) {
|
|
|
|
default: return false;
|
2012-05-30 17:23:22 +00:00
|
|
|
case Intrinsic::frameaddress: {
|
|
|
|
MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
|
|
|
|
MFI->setFrameAddressIsTaken(true);
|
|
|
|
|
|
|
|
unsigned LdrOpc;
|
|
|
|
const TargetRegisterClass *RC;
|
|
|
|
if (isThumb2) {
|
|
|
|
LdrOpc = ARM::t2LDRi12;
|
|
|
|
RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
|
|
|
|
} else {
|
|
|
|
LdrOpc = ARM::LDRi12;
|
|
|
|
RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
|
|
|
|
}
|
|
|
|
|
|
|
|
const ARMBaseRegisterInfo *RegInfo =
|
|
|
|
static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
|
|
|
|
unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
|
|
|
|
unsigned SrcReg = FramePtr;
|
|
|
|
|
|
|
|
// Recursively load frame address
|
|
|
|
// ldr r0 [fp]
|
|
|
|
// ldr r0 [r0]
|
|
|
|
// ldr r0 [r0]
|
|
|
|
// ...
|
|
|
|
unsigned DestReg;
|
|
|
|
unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
|
|
|
|
while (Depth--) {
|
|
|
|
DestReg = createResultReg(RC);
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(LdrOpc), DestReg)
|
|
|
|
.addReg(SrcReg).addImm(0));
|
|
|
|
SrcReg = DestReg;
|
|
|
|
}
|
2012-06-01 21:12:31 +00:00
|
|
|
UpdateValueMap(&I, SrcReg);
|
2012-05-30 17:23:22 +00:00
|
|
|
return true;
|
|
|
|
}
|
2011-11-11 23:31:03 +00:00
|
|
|
case Intrinsic::memcpy:
|
|
|
|
case Intrinsic::memmove: {
|
|
|
|
const MemTransferInst &MTI = cast<MemTransferInst>(I);
|
|
|
|
// Don't handle volatile.
|
|
|
|
if (MTI.isVolatile())
|
|
|
|
return false;
|
2011-11-14 22:46:17 +00:00
|
|
|
|
|
|
|
// Disable inlining for memmove before calls to ComputeAddress. Otherwise,
|
|
|
|
// we would emit dead code because we don't currently handle memmoves.
|
|
|
|
bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
|
|
|
|
if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
|
2011-11-14 23:04:09 +00:00
|
|
|
// Small memcpy's are common enough that we want to do them without a call
|
|
|
|
// if possible.
|
2011-11-14 22:46:17 +00:00
|
|
|
uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
|
2011-11-14 23:04:09 +00:00
|
|
|
if (ARMIsMemCpySmall(Len)) {
|
2011-11-14 22:46:17 +00:00
|
|
|
Address Dest, Src;
|
|
|
|
if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
|
|
|
|
!ARMComputeAddress(MTI.getRawSource(), Src))
|
|
|
|
return false;
|
2011-11-14 23:04:09 +00:00
|
|
|
if (ARMTryEmitSmallMemCpy(Dest, Src, Len))
|
2011-11-14 22:46:17 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
2012-06-14 06:08:19 +00:00
|
|
|
|
2011-11-11 23:31:03 +00:00
|
|
|
if (!MTI.getLength()->getType()->isIntegerTy(32))
|
|
|
|
return false;
|
2012-06-14 06:08:19 +00:00
|
|
|
|
2011-11-11 23:31:03 +00:00
|
|
|
if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
|
|
|
|
return SelectCall(&I, IntrMemName);
|
|
|
|
}
|
|
|
|
case Intrinsic::memset: {
|
|
|
|
const MemSetInst &MSI = cast<MemSetInst>(I);
|
|
|
|
// Don't handle volatile.
|
|
|
|
if (MSI.isVolatile())
|
|
|
|
return false;
|
2012-06-14 06:08:19 +00:00
|
|
|
|
2011-11-11 23:31:03 +00:00
|
|
|
if (!MSI.getLength()->getType()->isIntegerTy(32))
|
|
|
|
return false;
|
2012-06-14 06:08:19 +00:00
|
|
|
|
2011-11-11 23:31:03 +00:00
|
|
|
if (MSI.getDestAddressSpace() > 255)
|
|
|
|
return false;
|
2012-06-14 06:08:19 +00:00
|
|
|
|
2011-11-11 23:31:03 +00:00
|
|
|
return SelectCall(&I, "memset");
|
|
|
|
}
|
2012-05-11 21:33:49 +00:00
|
|
|
case Intrinsic::trap: {
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::TRAP));
|
|
|
|
return true;
|
|
|
|
}
|
2011-11-11 23:31:03 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-02 00:18:48 +00:00
|
|
|
bool ARMFastISel::SelectTrunc(const Instruction *I) {
|
2012-06-14 06:08:19 +00:00
|
|
|
// The high bits for a type smaller than the register size are assumed to be
|
2011-11-02 00:18:48 +00:00
|
|
|
// undefined.
|
|
|
|
Value *Op = I->getOperand(0);
|
|
|
|
|
|
|
|
EVT SrcVT, DestVT;
|
|
|
|
SrcVT = TLI.getValueType(Op->getType(), true);
|
|
|
|
DestVT = TLI.getValueType(I->getType(), true);
|
|
|
|
|
|
|
|
if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
|
|
|
|
return false;
|
|
|
|
if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned SrcReg = getRegForValue(Op);
|
|
|
|
if (!SrcReg) return false;
|
|
|
|
|
|
|
|
// Because the high bits are undefined, a truncate doesn't generate
|
|
|
|
// any code.
|
|
|
|
UpdateValueMap(I, SrcReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-11-02 17:20:24 +00:00
|
|
|
unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
|
|
|
|
bool isZExt) {
|
2011-05-25 23:49:02 +00:00
|
|
|
if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
|
2011-11-02 17:20:24 +00:00
|
|
|
return 0;
|
2011-05-25 23:49:02 +00:00
|
|
|
|
|
|
|
unsigned Opc;
|
|
|
|
bool isBoolZext = false;
|
2011-11-02 17:20:24 +00:00
|
|
|
if (!SrcVT.isSimple()) return 0;
|
2011-05-25 23:49:02 +00:00
|
|
|
switch (SrcVT.getSimpleVT().SimpleTy) {
|
2011-11-02 17:20:24 +00:00
|
|
|
default: return 0;
|
2011-05-25 23:49:02 +00:00
|
|
|
case MVT::i16:
|
2011-11-02 17:20:24 +00:00
|
|
|
if (!Subtarget->hasV6Ops()) return 0;
|
|
|
|
if (isZExt)
|
2011-11-08 21:12:00 +00:00
|
|
|
Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
|
2011-05-25 23:49:02 +00:00
|
|
|
else
|
2011-11-08 21:12:00 +00:00
|
|
|
Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
|
2011-05-25 23:49:02 +00:00
|
|
|
break;
|
|
|
|
case MVT::i8:
|
2011-11-02 17:20:24 +00:00
|
|
|
if (!Subtarget->hasV6Ops()) return 0;
|
|
|
|
if (isZExt)
|
2011-11-08 21:12:00 +00:00
|
|
|
Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
|
2011-05-25 23:49:02 +00:00
|
|
|
else
|
2011-11-08 21:12:00 +00:00
|
|
|
Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
|
2011-05-25 23:49:02 +00:00
|
|
|
break;
|
|
|
|
case MVT::i1:
|
2011-11-02 17:20:24 +00:00
|
|
|
if (isZExt) {
|
2011-11-08 21:12:00 +00:00
|
|
|
Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
|
2011-05-25 23:49:02 +00:00
|
|
|
isBoolZext = true;
|
|
|
|
break;
|
|
|
|
}
|
2011-11-02 17:20:24 +00:00
|
|
|
return 0;
|
2011-05-25 23:49:02 +00:00
|
|
|
}
|
|
|
|
|
2011-11-02 17:20:24 +00:00
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
|
2011-05-25 23:49:02 +00:00
|
|
|
MachineInstrBuilder MIB;
|
2011-11-02 17:20:24 +00:00
|
|
|
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
|
2011-05-25 23:49:02 +00:00
|
|
|
.addReg(SrcReg);
|
|
|
|
if (isBoolZext)
|
|
|
|
MIB.addImm(1);
|
2011-07-27 16:47:19 +00:00
|
|
|
else
|
|
|
|
MIB.addImm(0);
|
2011-05-25 23:49:02 +00:00
|
|
|
AddOptionalDefs(MIB);
|
2011-11-02 17:20:24 +00:00
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMFastISel::SelectIntExt(const Instruction *I) {
|
|
|
|
// On ARM, in general, integer casts don't involve legal types; this code
|
|
|
|
// handles promotable integers.
|
|
|
|
Type *DestTy = I->getType();
|
|
|
|
Value *Src = I->getOperand(0);
|
|
|
|
Type *SrcTy = Src->getType();
|
|
|
|
|
|
|
|
EVT SrcVT, DestVT;
|
|
|
|
SrcVT = TLI.getValueType(SrcTy, true);
|
|
|
|
DestVT = TLI.getValueType(DestTy, true);
|
|
|
|
|
|
|
|
bool isZExt = isa<ZExtInst>(I);
|
|
|
|
unsigned SrcReg = getRegForValue(Src);
|
|
|
|
if (!SrcReg) return false;
|
|
|
|
|
|
|
|
unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
|
|
|
|
if (ResultReg == 0) return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
2011-05-25 23:49:02 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-08-03 02:37:48 +00:00
|
|
|
bool ARMFastISel::SelectShift(const Instruction *I,
|
|
|
|
ARM_AM::ShiftOpc ShiftTy) {
|
|
|
|
// We handle thumb2 mode by target independent selector
|
|
|
|
// or SelectionDAG ISel.
|
|
|
|
if (isThumb2)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Only handle i32 now.
|
|
|
|
EVT DestVT = TLI.getValueType(I->getType(), true);
|
|
|
|
if (DestVT != MVT::i32)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned Opc = ARM::MOVsr;
|
|
|
|
unsigned ShiftImm;
|
|
|
|
Value *Src2Value = I->getOperand(1);
|
|
|
|
if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
|
|
|
|
ShiftImm = CI->getZExtValue();
|
|
|
|
|
|
|
|
// Fall back to selection DAG isel if the shift amount
|
|
|
|
// is zero or greater than the width of the value type.
|
|
|
|
if (ShiftImm == 0 || ShiftImm >=32)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
Opc = ARM::MOVsi;
|
|
|
|
}
|
|
|
|
|
|
|
|
Value *Src1Value = I->getOperand(0);
|
|
|
|
unsigned Reg1 = getRegForValue(Src1Value);
|
|
|
|
if (Reg1 == 0) return false;
|
|
|
|
|
2012-09-06 11:13:55 +00:00
|
|
|
unsigned Reg2 = 0;
|
2012-08-03 02:37:48 +00:00
|
|
|
if (Opc == ARM::MOVsr) {
|
|
|
|
Reg2 = getRegForValue(Src2Value);
|
|
|
|
if (Reg2 == 0) return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
|
|
|
|
if(ResultReg == 0) return false;
|
|
|
|
|
|
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(Opc), ResultReg)
|
|
|
|
.addReg(Reg1);
|
|
|
|
|
|
|
|
if (Opc == ARM::MOVsi)
|
|
|
|
MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
|
|
|
|
else if (Opc == ARM::MOVsr) {
|
|
|
|
MIB.addReg(Reg2);
|
|
|
|
MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
|
|
|
|
}
|
|
|
|
|
|
|
|
AddOptionalDefs(MIB);
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-09-02 23:43:26 +00:00
|
|
|
// TODO: SoftFP support.
|
2010-07-21 22:26:11 +00:00
|
|
|
bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
|
2010-09-09 01:06:51 +00:00
|
|
|
|
2010-07-21 22:26:11 +00:00
|
|
|
switch (I->getOpcode()) {
|
2010-08-23 21:44:12 +00:00
|
|
|
case Instruction::Load:
|
2010-09-27 06:02:23 +00:00
|
|
|
return SelectLoad(I);
|
2010-09-01 22:16:27 +00:00
|
|
|
case Instruction::Store:
|
2010-09-27 06:02:23 +00:00
|
|
|
return SelectStore(I);
|
2010-09-03 00:35:47 +00:00
|
|
|
case Instruction::Br:
|
2010-09-27 06:02:23 +00:00
|
|
|
return SelectBranch(I);
|
2012-02-07 23:56:08 +00:00
|
|
|
case Instruction::IndirectBr:
|
|
|
|
return SelectIndirectBr(I);
|
2010-09-08 23:13:45 +00:00
|
|
|
case Instruction::ICmp:
|
|
|
|
case Instruction::FCmp:
|
2010-09-27 06:02:23 +00:00
|
|
|
return SelectCmp(I);
|
2010-09-09 00:26:48 +00:00
|
|
|
case Instruction::FPExt:
|
2010-09-27 06:02:23 +00:00
|
|
|
return SelectFPExt(I);
|
2010-09-09 20:26:31 +00:00
|
|
|
case Instruction::FPTrunc:
|
2010-09-27 06:02:23 +00:00
|
|
|
return SelectFPTrunc(I);
|
2010-09-09 18:54:59 +00:00
|
|
|
case Instruction::SIToFP:
|
2012-02-03 21:14:11 +00:00
|
|
|
return SelectIToFP(I, /*isSigned*/ true);
|
2012-02-03 19:42:52 +00:00
|
|
|
case Instruction::UIToFP:
|
2012-02-03 21:14:11 +00:00
|
|
|
return SelectIToFP(I, /*isSigned*/ false);
|
2010-09-09 18:54:59 +00:00
|
|
|
case Instruction::FPToSI:
|
2012-02-03 21:14:11 +00:00
|
|
|
return SelectFPToI(I, /*isSigned*/ true);
|
2012-02-03 20:27:51 +00:00
|
|
|
case Instruction::FPToUI:
|
2012-02-03 21:14:11 +00:00
|
|
|
return SelectFPToI(I, /*isSigned*/ false);
|
2012-02-06 23:50:07 +00:00
|
|
|
case Instruction::Add:
|
|
|
|
return SelectBinaryIntOp(I, ISD::ADD);
|
2012-02-08 02:29:21 +00:00
|
|
|
case Instruction::Or:
|
|
|
|
return SelectBinaryIntOp(I, ISD::OR);
|
2012-02-08 02:45:44 +00:00
|
|
|
case Instruction::Sub:
|
|
|
|
return SelectBinaryIntOp(I, ISD::SUB);
|
2010-09-09 00:53:57 +00:00
|
|
|
case Instruction::FAdd:
|
2012-02-06 23:50:07 +00:00
|
|
|
return SelectBinaryFPOp(I, ISD::FADD);
|
2010-09-09 00:53:57 +00:00
|
|
|
case Instruction::FSub:
|
2012-02-06 23:50:07 +00:00
|
|
|
return SelectBinaryFPOp(I, ISD::FSUB);
|
2010-09-09 00:53:57 +00:00
|
|
|
case Instruction::FMul:
|
2012-02-06 23:50:07 +00:00
|
|
|
return SelectBinaryFPOp(I, ISD::FMUL);
|
2010-09-14 23:03:37 +00:00
|
|
|
case Instruction::SDiv:
|
2012-02-03 21:07:27 +00:00
|
|
|
return SelectDiv(I, /*isSigned*/ true);
|
|
|
|
case Instruction::UDiv:
|
|
|
|
return SelectDiv(I, /*isSigned*/ false);
|
2010-10-11 08:37:26 +00:00
|
|
|
case Instruction::SRem:
|
2012-02-03 21:23:45 +00:00
|
|
|
return SelectRem(I, /*isSigned*/ true);
|
|
|
|
case Instruction::URem:
|
|
|
|
return SelectRem(I, /*isSigned*/ false);
|
2010-09-30 20:49:44 +00:00
|
|
|
case Instruction::Call:
|
2011-11-11 23:31:03 +00:00
|
|
|
if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
|
|
|
|
return SelectIntrinsicCall(*II);
|
2010-09-30 20:49:44 +00:00
|
|
|
return SelectCall(I);
|
2010-10-11 08:27:59 +00:00
|
|
|
case Instruction::Select:
|
|
|
|
return SelectSelect(I);
|
2010-10-22 01:28:00 +00:00
|
|
|
case Instruction::Ret:
|
|
|
|
return SelectRet(I);
|
2011-05-25 23:49:02 +00:00
|
|
|
case Instruction::Trunc:
|
2011-11-02 00:18:48 +00:00
|
|
|
return SelectTrunc(I);
|
2011-05-25 23:49:02 +00:00
|
|
|
case Instruction::ZExt:
|
|
|
|
case Instruction::SExt:
|
2011-11-02 00:18:48 +00:00
|
|
|
return SelectIntExt(I);
|
2012-08-03 02:37:48 +00:00
|
|
|
case Instruction::Shl:
|
|
|
|
return SelectShift(I, ARM_AM::lsl);
|
|
|
|
case Instruction::LShr:
|
|
|
|
return SelectShift(I, ARM_AM::lsr);
|
|
|
|
case Instruction::AShr:
|
|
|
|
return SelectShift(I, ARM_AM::asr);
|
2010-07-21 22:26:11 +00:00
|
|
|
default: break;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2011-11-13 02:23:59 +00:00
|
|
|
/// TryToFoldLoad - The specified machine instr operand is a vreg, and that
|
|
|
|
/// vreg is being provided by the specified load instruction. If possible,
|
|
|
|
/// try to fold the load as an operand to the instruction, returning true if
|
|
|
|
/// successful.
|
|
|
|
bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
|
|
|
|
const LoadInst *LI) {
|
|
|
|
// Verify we have a legal type before going any further.
|
|
|
|
MVT VT;
|
|
|
|
if (!isLoadTypeLegal(LI->getType(), VT))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Combine load followed by zero- or sign-extend.
|
|
|
|
// ldrb r1, [r0] ldrb r1, [r0]
|
|
|
|
// uxtb r2, r1 =>
|
|
|
|
// mov r3, r2 mov r3, r1
|
|
|
|
bool isZExt = true;
|
|
|
|
switch(MI->getOpcode()) {
|
|
|
|
default: return false;
|
|
|
|
case ARM::SXTH:
|
|
|
|
case ARM::t2SXTH:
|
|
|
|
isZExt = false;
|
|
|
|
case ARM::UXTH:
|
|
|
|
case ARM::t2UXTH:
|
|
|
|
if (VT != MVT::i16)
|
|
|
|
return false;
|
|
|
|
break;
|
|
|
|
case ARM::SXTB:
|
|
|
|
case ARM::t2SXTB:
|
|
|
|
isZExt = false;
|
|
|
|
case ARM::UXTB:
|
|
|
|
case ARM::t2UXTB:
|
|
|
|
if (VT != MVT::i8)
|
|
|
|
return false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// See if we can handle this address.
|
|
|
|
Address Addr;
|
|
|
|
if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
|
2012-06-14 06:08:19 +00:00
|
|
|
|
2011-11-13 02:23:59 +00:00
|
|
|
unsigned ResultReg = MI->getOperand(0).getReg();
|
2011-12-13 19:22:14 +00:00
|
|
|
if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
|
2011-11-13 02:23:59 +00:00
|
|
|
return false;
|
|
|
|
MI->eraseFromParent();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-09-27 05:21:41 +00:00
|
|
|
unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
|
|
|
|
unsigned Align, EVT VT) {
|
|
|
|
bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
|
|
|
|
ARMConstantPoolConstant *CPV =
|
|
|
|
ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
|
|
|
|
unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
|
|
|
|
|
|
|
|
unsigned Opc;
|
|
|
|
unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
|
|
|
|
// Load value.
|
|
|
|
if (isThumb2) {
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(ARM::t2LDRpci), DestReg1)
|
|
|
|
.addConstantPoolIndex(Idx));
|
|
|
|
Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
|
|
|
|
} else {
|
|
|
|
// The extra immediate is for addrmode2.
|
|
|
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
|
|
|
|
DL, TII.get(ARM::LDRcp), DestReg1)
|
|
|
|
.addConstantPoolIndex(Idx).addImm(0));
|
|
|
|
Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
|
|
|
|
if (GlobalBaseReg == 0) {
|
|
|
|
GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
|
|
|
|
AFI->setGlobalBaseReg(GlobalBaseReg);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
|
|
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
|
|
|
|
DL, TII.get(Opc), DestReg2)
|
|
|
|
.addReg(DestReg1)
|
|
|
|
.addReg(GlobalBaseReg);
|
|
|
|
if (!UseGOTOFF)
|
|
|
|
MIB.addImm(0);
|
|
|
|
AddOptionalDefs(MIB);
|
|
|
|
|
|
|
|
return DestReg2;
|
|
|
|
}
|
|
|
|
|
2010-07-21 22:26:11 +00:00
|
|
|
namespace llvm {
|
2012-08-03 04:06:28 +00:00
|
|
|
FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
|
|
|
|
const TargetLibraryInfo *libInfo) {
|
2011-12-20 18:26:50 +00:00
|
|
|
// Completely untested on non-iOS.
|
2010-10-11 20:05:22 +00:00
|
|
|
const TargetMachine &TM = funcInfo.MF->getTarget();
|
2010-11-09 19:22:26 +00:00
|
|
|
|
2010-11-02 01:21:28 +00:00
|
|
|
// Darwin and thumb1 only for now.
|
2010-10-11 20:05:22 +00:00
|
|
|
const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
|
2012-05-11 19:40:25 +00:00
|
|
|
if (Subtarget->isTargetIOS() && !Subtarget->isThumb1Only())
|
2012-08-03 04:06:28 +00:00
|
|
|
return new ARMFastISel(funcInfo, libInfo);
|
2010-07-26 18:32:55 +00:00
|
|
|
return 0;
|
2010-07-21 22:26:11 +00:00
|
|
|
}
|
|
|
|
}
|