Commit Graph

14573 Commits

Author SHA1 Message Date
Nadav Rotem
ee0ce15ce1 Make the indirect branch optimization deterministic. No functionality change.
Patch by Daniel Reynaud.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166501 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23 21:05:33 +00:00
Richard Smith
c1f7ae15bb Per the C++ standard, we need to include the definition of llvm::Calculate in
every TU where it's implicitly instantiated, even if there's an implicit
instantiation for the same types available in another TU.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23 06:19:46 +00:00
Jakob Stoklund Olesen
56acf63e35 Don't crash when the Assignments vector is empty.
Reported by Vincent Lejeune using an out-of-tree target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166398 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-21 19:05:03 +00:00
Benjamin Kramer
63a4c24616 Symbol hygiene: Make sure declarations and definitions match, make helper functions static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166376 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-20 12:53:26 +00:00
Shuxin Yang
cfc6cb0c61 1. Remove noreturn attribute from __builtin_debugtrap().
(The change at Clang side was committed in r166345)

2. Cosmetic change in order to conform to coding standards. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166350 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19 23:00:20 +00:00
Nadav Rotem
a04a4a79ea revert r166264 because the LTO build is still failing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19 21:28:43 +00:00
Shuxin Yang
970755e519 This patch is to fix radar://8426430. It is about llvm support of __builtin_debugtrap()
which is supposed to consistently raise SIGTRAP across all systems. In contrast,
__builtin_trap() behave differently on different systems. e.g. it raises SIGTRAP on ARM, and
SIGILL on X86. The purpose of __builtin_debugtrap() is to consistently provide "trap"
functionality, in the mean time preserve the compatibility with on gcc on __builtin_trap().

  The X86 backend is already able to handle debugtrap(). This patch is to:
  1) make front-end recognize "__builtin_debugtrap()" (emboddied in the one-line change to Clang).
  2) In DAG legalization phase, by default, "debugtrap" will be replaced with "trap", which
     make the __builtin_debugtrap() "available" to all existing ports without the hassle of
     changing their code.
  3) If trap-function is specified (via -trap-func=xyz to llc), both __builtin_debugtrap() and
     __builtin_trap() will be expanded into the function call of the specified trap function.
    This behavior may need change in the future.

  The provided testing-case is to make sure 2) and 3) are working for ARM port, and we
already have a testing case for x86. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19 20:11:16 +00:00
Nadav Rotem
725f1d1280 recommit the patch that makes LSR and LowerInvoke use the TargetTransform interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166264 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19 04:27:49 +00:00
Michael Liao
9aecdb51c7 Simplify condition checking as CONCAT assume all inputs of the same type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166260 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19 03:17:00 +00:00
Sebastian Pop
83ba06afa8 Clear unknown mem ops when merging stack slots (pr14090)
When merging stack slots, if StackColoring::remapInstructions gets a
value back from GetUnderlyingObject that it does not know about or is
not itself a stack slot, clear the memory operand in case it aliases
the merged slot. This prevents the introduction of incorrect aliasing
information.

Author:    Matthew Curtis <mcurtis@codeaurora.org>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166216 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18 19:53:48 +00:00
Sebastian Pop
bf0683f0f7 Change MachineFrameInfo::StackObject::Alloca from Value* to AllocaInst*
This more accurately reflects what is actually being stored in the
field.

No functionality change intended.

Author:    Matthew Curtis <mcurtis@codeaurora.org>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166215 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18 19:53:45 +00:00
Nadav Rotem
1c5bf3f429 In SimplifySelectOps we pulled two loads through a select node despite the fact that one was dependent on the other.
rdar://12513091



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18 18:06:48 +00:00
Bob Wilson
3b9a911efc Temporarily revert the TargetTransform changes.
The TargetTransform changes are breaking LTO bootstraps of clang.  I am
working with Nadav to figure out the problem, but I am reverting it for now
to get our buildbots working.

This reverts svn commits: 165665 165669 165670 165786 165787 165997
and I have also reverted clang svn 165741

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18 05:43:52 +00:00
Michael Liao
07edaf3801 Revert part of r166049 back and enable test case in r166125.
- Folding (trunc (concat ... X )) to (concat ... (trunc X) ...) is valid
  when '...' are all 'undef's.
- r166125 relies on this transformation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166155 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17 23:45:54 +00:00
Michael Liao
4031e9018b Revert r166049
- In general, it's unsafe for this transformation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166135 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17 22:41:15 +00:00
Michael Liao
13429e224c Teach DAG combine to fold (extract_subvec (concat v1, ..) i) to v_i
- If the extracted vector has the same type of all vectored being concatenated
  together, it should be simplified directly into v_i, where i is the index of
  the element being extracted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166125 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17 20:48:33 +00:00
Jakob Stoklund Olesen
4b1aa961fd Switch MRI::UsedPhysRegs to a register unit bit vector.
This is a more compact, less redundant representation, and it avoids
scanning long lists of aliases for ARM D-registers, for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17 20:26:33 +00:00
Evan Cheng
d4f759696d Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't use
any scheduling heuristics nor does it build up any scheduling data structure
that other heuristics use. It essentially linearize by doing a DFA walk but
it does handle glues correctly.

IMPORTANT: it probably can't handle all the physical register dependencies so
it's not suitable for x86. It also doesn't deal with dbg_value nodes right now
so it's definitely is still WIP.

rdar://12474515


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17 19:39:36 +00:00
Jakob Stoklund Olesen
9aa6e0a134 Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed().
All callers of these functions really want the isPhysRegOrOverlapUsed()
functionality which also checks aliases. For historical reasons, targets
without register aliases were calling isPhysRegUsed() instead.

Change isPhysRegUsed() to also check aliases, and switch all
isPhysRegOrOverlapUsed() callers to isPhysRegUsed().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17 18:44:18 +00:00
Andrew Trick
fdd6fa89b9 misched: Better handling of invalid latencies in the machine model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17 17:27:10 +00:00
Jakob Stoklund Olesen
d7ea7d5cd7 Use a SparseSet instead of a BitVector for UsedInInstr in RAFast.
This is just as fast, and it makes it possible to avoid leaking the
UsedPhysRegs BitVector implementation through
MachineRegisterInfo::addPhysRegsUsed().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17 01:37:59 +00:00
Jakob Stoklund Olesen
320db3f805 Avoid rematerializing a redef immediately after the old def.
PR14098 contains an example where we would rematerialize a MOV8ri
immediately after the original instruction:

  %vreg7:sub_8bit<def> = MOV8ri 9; GR32_ABCD:%vreg7
  %vreg22:sub_8bit<def> = MOV8ri 9; GR32_ABCD:%vreg7

Besides being pointless, it is also wrong since the original instruction
only redefines part of the register, and the value read by the new
instruction is wrong.

The problem was the LiveRangeEdit::allUsesAvailableAt() didn't
special-case OrigIdx == UseIdx and found the wrong SSA value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166068 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 22:51:58 +00:00
Jakob Stoklund Olesen
cdcdfd2cab Revert r166046 "Switch back to the old coalescer for now to fix the 32 bit bit"
A fix for PR14098, including the test case is in the next commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 22:51:55 +00:00
Michael Liao
272ea03239 Teach DAG combine to fold (trunc (fptoXi x)) to (fptoXi x)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 19:38:35 +00:00
Rafael Espindola
6f7cccd2e2 Switch back to the old coalescer for now to fix the 32 bit bit
llvm+clang+compiler-rt bootstrap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166046 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 19:34:06 +00:00
Stepan Dyatkovskiy
b52ba9f8a8 Issue:
Stack is formed improperly for long structures passed as byval arguments for
EABI mode.

If we took AAPCS reference, we can found the next statements:

A: "If the argument requires double-word alignment (8-byte), the NCRN (Next
Core Register Number) is rounded up to the next even register number." (5.5
Parameter Passing, Stage C, C.3).

B: "The alignment of an aggregate shall be the alignment of its most-aligned
component." (4.3 Composite Types, 4.3.1 Aggregates).

So if we have structure with doubles (9 double fields) and 3 Core unused
registers (r1, r2, r3): caller should use r2 and r3 registers only.
Currently r1,r2,r3 set is used, but it is invalid.

Callee VA routine should also use r2 and r3 regs only. All is ok here. This
behaviour is guessed by rounding up SP address with ADD+BFC operations.

Fix:
Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and
8 byte alignment, we waste odd registers then.

P.S.:
I also improved LDRB_POST_IMM regression test. Since ldrb instruction will
not generated by current regression test after this patch. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166018 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 07:16:47 +00:00
Andrew Trick
27c28cef11 misched: Added handleMove support for updating all kill flags, not just for allocatable regs.
This is a medium term workaround until we have a more robust solution
in the form of a register liveness utility for postRA passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 00:22:51 +00:00
Jakob Stoklund Olesen
feab72c20a Remove unused BitVectors from getAllocatableSet().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 00:05:06 +00:00
Jakob Stoklund Olesen
14d1dd95c7 Remove RegisterClassInfo::isReserved() and isAllocatable().
Clients can use the equivalent functions in MRI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 22:41:03 +00:00
Jakob Stoklund Olesen
790047620a Remove LIS::isAllocatable() and isReserved() helpers.
All callers can simply use the corresponding MRI functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165985 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 22:14:34 +00:00
Jakob Stoklund Olesen
fb9ebbf236 Switch most getReservedRegs() clients to the MRI equivalent.
Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 21:57:41 +00:00
Jakob Stoklund Olesen
e4f273908b Freeze the reserved registers as soon as isel is complete.
Also provide an MRI::getReservedRegs() function to access the frozen
register set, and isReserved() and isAllocatable() methods to test
individual registers.

The various implementations of TRI::getReservedRegs() are quite
complicated, and many passes need to look at the reserved register set.
This patch makes it possible for these passes to use the cached copy in
MRI, avoiding a lot of malloc traffic and repeated calculations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 21:33:06 +00:00
Bill Wendling
702cc91aa1 Move the Attributes::Builder outside of the Attributes class and into its own class named AttrBuilder. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 20:35:56 +00:00
Rafael Espindola
10ad98bbbb Make sure we iterate over newly created instructions. Fixes pr13625. Testcase to
follow in one sec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 18:21:07 +00:00
Andrew Trick
1e94e98b0e misched: ILP scheduler for experimental heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165950 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 18:02:27 +00:00
Micah Villmow
2c39b15073 Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165941 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 16:24:29 +00:00
Bill Wendling
3756e70af6 Remove the bitwise XOR operator from the Attributes class. Replace it with the equivalent from the builder class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165893 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 06:56:13 +00:00
Jakob Stoklund Olesen
d86296a4ae Drop <def,dead> flags when merging into an unused lane.
The new coalescer can merge a dead def into an unused lane of an
otherwise live vector register.

Clear the <dead> flag when that happens since the flag refers to the
full virtual register which is still live after the partial dead def.

This fixes PR14079.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-13 17:26:47 +00:00
Jakob Stoklund Olesen
af89690760 Allow for loops in LiveIntervals::pruneValue().
It is possible that the live range of the value being pruned loops back
into the kill MBB where the search started. When that happens, make sure
that the beginning of KillMBB is also pruned.

Instead of starting a DFS at KillMBB and skipping the root of the
search, start a DFS at each KillMBB successor, and allow the search to
loop back to KillMBB.

This fixes PR14078.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165872 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-13 16:15:31 +00:00
Jakob Stoklund Olesen
ad5e969ba9 Use a transposed algorithm for handleMove().
Completely update one interval at a time instead of collecting live
range fragments to be updated. This avoids building data structures,
except for a single SmallPtrSet of updated intervals.

Also share code between handleMove() and handleMoveIntoBundle().

Add support for moving dead defs across other live values in the
interval. The MI scheduler can do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12 21:31:57 +00:00
Jakob Stoklund Olesen
795f951c6d Fix coalescing with IMPLICIT_DEF values.
PHIElimination inserts IMPLICIT_DEF instructions to guarantee that all
PHI predecessors have a live-out value. These IMPLICIT_DEF values are
not considered to be real interference when coalescing virtual
registers:

  %vreg1 = IMPLICIT_DEF
  %vreg2 = MOV32r0

When joining %vreg1 and %vreg2, the IMPLICIT_DEF instruction and its
value number should simply be erased since the %vreg2 value number now
provides a live-out value for the PHI predecesor block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12 18:03:04 +00:00
Ulrich Weigand
7bbb9c7b4a Fix big-endian codegen bug in DAGTypeLegalizer::ExpandRes_BITCAST
On PowerPC, a bitcast of <16 x i8> to i128 may run through a code
path in ExpandRes_BITCAST that attempts to do an intermediate
bitcast to a <4 x i32> vector, and then construct the Hi and Lo parts
of the resulting i128 by pairing up two of those i32 vector elements
each.  The code already recognizes that on a big-endian system, the
first two vector elements form the Hi part, and the final two vector
elements form the Lo part (vice-versa from the little-endian situation).

However, we also need to take endianness into account when forming each
of those separate pairs:  on a big-endian system, vector element 0 is
the *high* part of the pair making up the Hi part of the result, and
vector element 1 is the low part of the pair.  The code currently always
uses vector element 0 as the low part and vector element 1 as the high
part, as is appropriate for little-endian platforms only.

This patch fixes this by swapping the vector elements as they are
paired up as appropriate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12 15:42:58 +00:00
Evan Cheng
d36696c4e0 Legalizer optimize a pair of div / mod to a call to divrem libcall if they are
not legal. However, it should use a div instruction + mul + sub if divide is
legal. The rem legalization code was missing a check and incorrectly uses a
divrem libcall even when div is legal.

rdar://12481395


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12 01:15:47 +00:00
Sean Silva
ed84062812 Remove unnecessary classof()'s
isa<> et al. automatically infer when the cast is an upcast (including a
self-cast), so these are no longer necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11 23:30:49 +00:00
Micah Villmow
fb384d61c7 Revert 165732 for further review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11 21:27:41 +00:00
Micah Villmow
f3840d2c16 Add in the first iteration of support for llvm/clang/lldb to allow variable per address space pointer sizes to be optimized correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11 17:21:41 +00:00
Jakob Stoklund Olesen
ebba49395c Pass an explicit operand number to addLiveIns.
Not all instructions define a virtual register in their first operand.
Specifically, INLINEASM has a different format.

<rdar://problem/12472811>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11 16:46:07 +00:00
Michael Liao
be9262b8c7 Follow the same routine to add target float expansion hook
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165707 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11 07:22:01 +00:00
Andrew Trick
4903c15b7d misched: Handle "transient" non-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11 05:37:06 +00:00
Nadav Rotem
e3d0e86919 Add a new interface to allow IR-level passes to access codegen-specific information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 22:04:55 +00:00
Micah Villmow
d6458a0aa1 Add in support for expansion of all of the comparison operations to the absolute minimum required set. This allows a backend to expand any arbitrary set of comparisons as long as a minimum set is supported.
The minimum set of required instructions is ISD::AND, ISD::OR, ISD::SETO(or ISD::SETOEQ) and ISD::SETUO(or ISD::SETUNE). Everything is expanded into one of two patterns:
Pattern 1: (LHS CC1 RHS) Opc (LHS CC2 RHS)
Pattern 2: (LHS CC1 LHS) Opc (RHS CC2 RHS)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 20:50:51 +00:00
Michael Liao
9d796db3e7 Add alternative support for FP_ROUND from v2f32 to v2f64
- Due to the current matching vector elements constraints in ISD::FP_EXTEND,
  rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening
  to convert it into a target-specific X86ISD::VFPEXT to work around this
  constraints. This patch also reverts a previous attempt to fix this issue by
  recovering the scalarized ISD::FP_EXTEND pattern and thus significantly
  reduces the overhead of supporting non-power-2 vector FP extend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 16:32:15 +00:00
Stepan Dyatkovskiy
661afe75e8 Issue description:
SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack
objects and byval parameters. So loading byval parameters from stack may be
inserted *before* it will be stored, since these operations are treated as
independent.

Fix:
Currently ARMTargetLowering::LowerFormalArguments saves byval registers with
FixedStack MachinePointerInfo. To fix the problem we need to store byval
registers with MachinePointerInfo referenced to first the "byval" parameter.

Also commit adds two new fields to the InputArg structure: Function's argument
index and InputArg's part offset in bytes relative to the start position of
Function's argument. E.g.: If function's argument is 128 bit width and it was
splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index,
but different offset values. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 11:37:36 +00:00
Bill Wendling
7d2f2496c1 Remove the final bits of Attributes being declared in the Attribute
namespace. Use the attribute's enum value instead. No functionality change
intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 07:36:45 +00:00
Lang Hames
8a8cf9617c My earlier "fix" for PBQP (see r165201) was incorrect. The real issue was that
checkRegMaskInterference only initializes the bitmask on the first interference.

This fixes PR14027 and (re)fixes PR13945.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 06:39:48 +00:00
Andrew Trick
82d46aec62 misched: fall-back to a target hook for instr bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165606 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 05:43:18 +00:00
Andrew Trick
412cd2f813 misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 05:43:09 +00:00
Andrew Trick
c0dfffa448 misched: Add computeInstrLatency to TargetSchedModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 23:44:32 +00:00
Andrew Trick
42bb106118 misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165564 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 23:44:26 +00:00
Andrew Trick
714973e459 misched: Remove LoopDependencies heuristic.
This wasn't contributing anything significant to postRA heuristics except compile time (by my measurements) and will be replaced by a more general heuristic for cross-region dependencies within the scheduler itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165563 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 23:44:23 +00:00
Bill Wendling
3e2d76c946 Use the attribute enums to query if a parameter has an attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 21:38:14 +00:00
Micah Villmow
7d66146868 Add in the first step of the multiple pointer support. This adds in support to the data layout for specifying a per address space pointer size.
The next step is to update the optimizers to allow them to optimize the different address spaces with this information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165505 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 16:06:12 +00:00
Bill Wendling
6765834754 Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 07:45:08 +00:00
Eric Christopher
2d65efed53 Fix up comment to be more clear.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165463 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 23:53:45 +00:00
Nadav Rotem
ad6aedc7d9 Refactor the AddrMode class out of TLI to its own header file.
This class is used by LSR and a number of places in the codegen.
This is the first step in de-coupling LSR from TLI, and creating
a new interface in between them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165455 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 23:06:34 +00:00
Jakob Stoklund Olesen
6be75ae196 Don't crash on extra evil irreducible control flow.
When the CFG contains a loop with multiple entry blocks, the traces
computed by MachineTraceMetrics don't always have the same nice
properties. Loop back-edges are normally excluded from traces, but
MachineLoopInfo doesn't recognize loops with multiple entry blocks, so
those back-edges may be included.

Avoid asserting when that happens by adding an isEarlierInSameTrace()
function that accurately determines if a dominating block is part of the
same trace AND is above the currrent block in the trace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165434 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 22:06:44 +00:00
Eric Christopher
c56e3f0cdd Fixup comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165427 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 20:48:54 +00:00
Eric Christopher
02c1a64efe Fixup comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165426 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 20:48:49 +00:00
Andrew Trick
39817f9d39 misched: remove the unused getSpecialAddressLatency hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165418 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 18:54:00 +00:00
Andrew Trick
a98f600a64 misched: remove forceUnitLatencies. Defaults are handled by the default SchedModel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 18:53:57 +00:00
Andrew Trick
30c6ec2199 misched: avoid scheduling an instruction twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165416 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 18:53:53 +00:00
Micah Villmow
3574eca1b0 Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 16:38:25 +00:00
Craig Topper
87802d52e1 Remove unused MachineInstr constructors that don't take a DebugLoc argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-07 23:03:22 +00:00
Craig Topper
14ce91cc27 Fix indentation. Remove 'else' after return. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165381 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-07 20:31:05 +00:00
Benjamin Kramer
a4b5050cf5 Remove unused but set variable flagged by GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05 20:08:45 +00:00
Benjamin Kramer
ebd7eabca4 Simplify code, don't or a bool with an uint64_t.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05 18:19:44 +00:00
Nadav Rotem
ea2c50c041 When merging connsecutive stores, use vectors to store the constant zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165267 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 22:35:15 +00:00
Eric Christopher
0313ced016 Update this a bit more to represent how the prologue should work:
a) frame setup instructions define the prologue
b) we shouldn't change our location mid-stream

Add a test to make sure that the stack adjustment stays within
the prologue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 20:46:14 +00:00
Jakob Stoklund Olesen
e6521b57cc Get MCSchedModel directly from the subtarget.
Not all targets have itineraries, but the subtarget always has an
MCSchedModel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165236 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 17:30:43 +00:00
Jakob Stoklund Olesen
f43fe1d163 Switch MachineTraceMetrics to the new TargetSchedModel interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165235 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 17:30:40 +00:00
Lang Hames
442c59f0a2 Fix reg mask slot test, and preserve LiveIntervals and VirtRegMap in the PBQP
allocator. Fixes PR13945.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165201 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 04:50:53 +00:00
Andrew Trick
72fd0a9448 Enable -schedmodel, but prefer itineraries until we have more benchmark data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 00:24:34 +00:00
Bill Wendling
4c230b3338 Update to use the predicate methods to query if an attribute exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165163 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 21:17:09 +00:00
Nadav Rotem
2e7d38192d Fix a cycle in the DAG. In this code we replace multiple loads with a single load and
multiple stores with a single load. We create the wide loads and stores (and their chains)
before we remove the scalar loads and stores and fix the DAG chain. We attempted to merge
loads with a different chain. When that happened, the assumption that it is safe to RAUW
broke and a cycle was introduced.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 19:30:31 +00:00
Nadav Rotem
c653de6c0f A DAGCombine optimization for mergeing consecutive stores to memory. The optimization
is not profitable in many cases because modern processors perform multiple stores
in parallel and merging stores prior to merging requires extra work. We handle two main cases:

1. Store of multiple consecutive constants:
  q->a = 3;
  q->4 = 5;
In this case we store a single legal wide integer.

2. Store of multiple consecutive loads:
  int a = p->a;
  int b = p->b;
  q->a = a;
  q->b = b;
In this case we load/store either ilegal vector registers or legal wide integer registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165125 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 16:11:15 +00:00
Silviu Baranga
541a858f1a Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to not propagate through implicit defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165102 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 08:29:36 +00:00
Eric Christopher
76ad43c6e1 Revert 165051-165049 while looking into the foreach.m failure in
more detail.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 08:10:01 +00:00
Jakob Stoklund Olesen
0d141f867d The early if conversion pass is ready to be used as an opt-in.
Enable the pass by default for targets that request it, and change the
-enable-early-ifcvt to the opposite -disable-early-ifcvt.

There are still some x86 regressions when enabling early if-conversion
because of the missing machine models. Disable the pass for x86 until
machine models are added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 00:51:32 +00:00
Eric Christopher
394820b8e1 Revert "Don't use a debug location for frame setup instructions in the"
This reverts 165055 and 165052 temporarily while I look at debugger
failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02 23:43:11 +00:00
Jakob Stoklund Olesen
6c0c6d613a Remove the old coalescer algorithm.
The new algorithm has been enabled by default for almost a week now and
seems to be stable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02 22:45:03 +00:00
Jakob Stoklund Olesen
d4919a988d Handle reserved registers more accurately in handleMove().
Reserved register live ranges look like a set of dead defs - any uses of
reserved registers are ignored.

Instead of skipping the updating of reserved register operands entirely,
just ignore the use operands and treat the def operands normally.

No test case, handleMove() is not commonly used yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02 22:08:36 +00:00
Jakob Stoklund Olesen
27cb347d0e Make sure the whole live range is covered when values are pruned twice.
JoinVals::pruneValues() calls LIS->pruneValue() to avoid conflicts when
overlapping two different values. This produces a set of live range end
points that are used to reconstruct the live range (with SSA update)
after joining the two registers.

When a value is pruned twice, the set of end points was insufficient:

  v1 = DEF
  v1 = REPLACE1
  v1 = REPLACE2
  KILL v1

The end point at KILL would only reconstruct the live range from
REPLACE2 to KILL, leaving the range REPLACE1-REPLACE2 dead.

Add REPLACE2 as an end point in this case so the full live range is
reconstructed.

This fixes PR13999.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165056 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02 21:46:39 +00:00
Eric Christopher
55c86c67ee 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165054 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02 21:44:12 +00:00
Eric Christopher
9fd304672c Don't use a debug location for frame setup instructions in the
prologue. Also skip frame setup instructions when looking for the
first location.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165052 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02 21:17:00 +00:00
Eric Christopher
96bd4418b2 Remove the SavePoint infrastructure from fast isel, replace
with just an insert point from the MachineBasicBlock and let
the location be updated as we access it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02 21:16:50 +00:00
Duncan Sands
48da0be8b5 Fix PR13991: legalizing an overflowing multiplication operation is harder than
the add/sub case since in the case of multiplication you also have to check that
the operation in the larger type did not overflow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165017 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02 15:03:49 +00:00
Jakub Staszak
554c6762e8 Use dyn_cast instead of isa and cast.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164924 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-30 21:24:57 +00:00
Nadav Rotem
73fab91f2c Revert r164910 because it causes failures to several phase2 builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164911 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-30 07:17:56 +00:00
Nadav Rotem
e5f163a3b9 A DAGCombine optimization for merging consecutive stores. This optimization is not profitable in many cases
because moden processos can store multiple values in parallel, and preparing the consecutive store requires
some work.  We only handle these cases:

1. Consecutive stores where the values and consecutive loads. For example:
 int a = p->a;
 int b = p->b;
 q->a = a;
 q->b = b;

2. Consecutive stores where the values are constants. Foe example:
 q->a = 4;
 q->b = 5;



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-30 06:24:14 +00:00
Duncan Sands
454627252b Speculatively revert commit 164885 (nadav) in the hope of ressurecting a pile of
buildbots.  Original commit message:

A DAGCombine optimization for merging consecutive stores. This optimization is not profitable in many cases
because moden processos can store multiple values in parallel, and preparing the consecutive store requires
some work.  We only handle these cases:

1. Consecutive stores where the values and consecutive loads. For example:
  int a = p->a;
  int b = p->b;
  q->a = a;
  q->b = b;

2. Consecutive stores where the values are constants. Foe example:
  q->a = 4;
  q->b = 5;



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164890 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29 10:25:35 +00:00
Craig Topper
0eb5dadf65 Tidy up to match coding standards. Remove 'else' after 'return' and moving operators to end of preceding line. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164887 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29 07:18:53 +00:00
Craig Topper
32b7343a96 Replace a couple if/elses around similar calls with conditional operators on the varying arguments. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164886 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29 06:54:22 +00:00
Nadav Rotem
72f7b0811e A DAGCombine optimization for merging consecutive stores. This optimization is not profitable in many cases
because moden processos can store multiple values in parallel, and preparing the consecutive store requires
some work.  We only handle these cases:

1. Consecutive stores where the values and consecutive loads. For example:
  int a = p->a;
  int b = p->b;
  q->a = a;
  q->b = b;

2. Consecutive stores where the values are constants. Foe example:
  q->a = 4;
  q->b = 5;



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164885 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29 06:33:25 +00:00
Jakob Stoklund Olesen
83ef63efce Remove <def,read-undef> flags from partial redefinitions.
The new coalescer can turn a full virtual register definition into a
partial redef by merging another value into an unused vector lane.

Make sure to clear the <read-undef> flag on such defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 23:31:32 +00:00
Jakob Stoklund Olesen
5cf178f281 Enable the new coalescer algorithm by default.
The new coalescer is better at merging values into unused vector lanes,
improving NEON code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 21:06:02 +00:00
Jakob Stoklund Olesen
657720bc6e Don't dereference begin() on an empty vector.
The fix is obvious and the only test case I have is horrible, so I am
not including it. The problem shows up when self-hosting clang on i386
with -new-coalescer enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164793 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 21:05:59 +00:00
Jakob Stoklund Olesen
ddc26d8936 Avoid dereferencing a NULL pointer.
Fixes PR13943.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 16:34:19 +00:00
Sylvestre Ledru
94c22716d6 Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 10:14:43 +00:00
Sylvestre Ledru
7e2c793a2b Fix a typo 'iff' => 'if'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 09:59:43 +00:00
Bill Wendling
2c18906118 Remove the `hasFnAttr' method from Function.
The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26 21:48:26 +00:00
Craig Topper
4bb51cc83b Rename virtual table anchors from Anchor() to anchor() for consistency with the rest of the tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164666 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26 06:36:36 +00:00
Bill Wendling
f18eb5887f Generate an error message instead of asserting or segfaulting when we have a
scalar-to-vector conversion that we cannot handle. For instance, when an invalid
constraint is used in an inline asm statement.
<rdar://problem/12284092>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164662 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26 06:16:18 +00:00
Bill Wendling
1293130f4f Generate an error message instead of asserting or segfaulting when we have a
scalar-to-vector conversion that we cannot handle. For instance, when an invalid
constraint is used in an inline asm statement.
<rdar://problem/12284092>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26 04:04:19 +00:00
Sebastian Pop
1a37d7e807 TargetLowering interface to set/get minimum block entries for jump tables.
Provide interface in TargetLowering to set or get the minimum number of basic
blocks whereby jump tables are generated for switch statements rather than an
if sequence.

    getMinimumJumpTableEntries() defaults to 4.
    setMinimumJumpTableEntries() allows target configuration.

    This patch changes the default for the Hexagon architecture to 5
    as it improves performance on some benchmarks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25 20:35:36 +00:00
Jim Grosbach
e9525d8624 Mark jump tables in code sections with DataRegion directives.
Even out-of-line jump tables can be in the code section, so mark them
as data-regions for those targets which support the directives.

rdar://12362871&12362974

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24 23:06:27 +00:00
Eric Christopher
7b451cf356 Have the DbgVariable "isArtificial" and "isObjectPointer" not
care about it being an argument variable so that we can decide
that captured block and lambda vars that don't happen to
be arguments could be an argument pointer.

Add the object pointer for one case onto the subprogram die.

rdar://12001329

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164419 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21 22:18:52 +00:00
Evan Cheng
bb36a43872 Fix a significant recent(?) regression. StackSlotColoring no longer did anything
because LiveStackAnalysis was not preserved by VirtRegWriter. This caused
big stack usage regression in some cases.

rdar://12340383


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21 20:04:28 +00:00
Bill Wendling
ef99fe8efa Make the 'get*AlignmentFromAttr' functions into member functions within the Attributes class. Now with fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164370 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21 15:26:31 +00:00
Jakob Stoklund Olesen
e6e2d8cd90 Ignore PHI-defs for -new-coalescer interference checks.
A PHI can't create interference on its own. If two live ranges interfere
at a PHI, they must also interfere when leaving one of the PHI
predecessors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20 23:08:42 +00:00
Jakob Stoklund Olesen
2df8ac84ae Extend -new-coalescer SSA update to handle mapped values as well.
The old-fashioned many-to-one value mapping doesn't always work when
merging vector lanes. A value can map to multiple different values, and
it can even be necessary to insert new PHIs.

When a value number is defined by a copy from a value number that
required SSa update, include the live range of the copied value number
in the SSA update as well. It is not necessarily a copy of the original
value number any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164329 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20 23:08:39 +00:00
Eric Christopher
d57ae39a88 Only emit DW_AT_object_pointer if this is a definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164326 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20 22:51:57 +00:00
Bill Wendling
4aa189909a Revert r164308 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20 16:59:57 +00:00
Bill Wendling
f2e89e00b4 Make the 'get*AlignmentFromAttr' functions into member functions within the Attributes class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164308 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20 16:27:05 +00:00
Nadav Rotem
6dfabb6cc7 Fix 80-col violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20 08:53:31 +00:00
Bill Wendling
e603fe4664 Convert some attribute existence queries over to use the predicate methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164268 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 23:54:18 +00:00
Bill Wendling
e853d2e250 Add predicates for queries on whether an attribute exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164264 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 23:35:21 +00:00
Jakob Stoklund Olesen
d40d4c34f7 Resolve conflicts involving dead vector lanes for -new-coalescer.
A common coalescing conflict in vector code is lane insertion:

  %dst = FOO
  %src = BAR
  %dst:ssub0 = COPY %src

The live range of %src interferes with the ssub0 lane of %dst, but that
lane is never read after %src would have clobbered it. That makes it
safe to merge the live ranges and eliminate the COPY:

  %dst = FOO
  %dst:ssub0 = BAR

This patch teaches the new coalescer to resolve conflicts where dead
vector lanes would be clobbered, at least as long as the clobbered
vector lanes don't escape the basic block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 21:29:18 +00:00
Andrew Trick
d8f39afb47 comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 22:57:42 +00:00
Andrew Trick
3918cade8f TargetSchedule: cleanup computeOperandLatency logic & diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 18:20:02 +00:00
Andrew Trick
781ab4777f misched: Make ScheduleDAGInstrs use the TargetSchedule interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 18:20:00 +00:00
Roman Divacky
536a88ad5b When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend
store this and use it to not emit long nops when the CPU is geode which
doesnt support them.

Fixes PR11212.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 16:08:49 +00:00
Andrew Trick
34301ceca8 TargetSchedModel API. Implement latency lookup, disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164098 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 04:03:34 +00:00
Craig Topper
c2945e44d5 Mark unimplemented copy constructors and copy assignment operators as LLVM_DELETED_FUNCTION.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 02:01:41 +00:00
Evan Cheng
fe257cc8af Fix some funky indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164087 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 01:34:40 +00:00
Jakob Stoklund Olesen
87f7864c6d Merge into undefined lanes under -new-coalescer.
Add LIS::pruneValue() and extendToIndices(). These two functions are
used by the register coalescer when merging two live ranges requires
more than a trivial value mapping as supported by LiveInterval::join().

The pruneValue() function can remove the part of a value number that is
going to conflict in join(). Afterwards, extendToIndices can restore the
live range, using any new dominating value numbers and updating the SSA
form.

Use this complex value mapping to support merging a register into a
vector lane that has a conflicting value, but the clobbered lane is
undef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164074 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 23:03:25 +00:00
Jakob Stoklund Olesen
98279e8d65 Stop adding <imp-def> operands when expanding REG_SEQUENCE.
These extra operands are not needed by register allocators using
VirtRegRewriter, and RAFast don't need them any longer.

By omitting the <imp-def> operands, it becomes possible for the new
register coalescer to track which lanes are valid and which are undef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 23:03:21 +00:00
Andrew Trick
e1b5328717 Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 23:00:42 +00:00
Andrew Trick
12886db4a7 TargetSchedModel API. Implement latency lookup, disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164065 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:19:08 +00:00
Michael Ilseman
8dcc99496d Increase the static sizes of some SmallSets. finalizeBundle() is very frequently called for some backends, and growing into an std::set is overkill for these numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 18:31:15 +00:00
Michael Ilseman
2b94302433 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 18:25:23 +00:00
Michael Liao
bb73002247 Fix PR13859
- Preserve the original NOutVT during casting from vector to integer by
  extracting vector elements.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164042 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 18:05:20 +00:00
Tom Stellard
a52c3acc14 Add a MachinePostDominator pass
This is used in the AMDIL and R600 backends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 14:08:37 +00:00
Nadav Rotem
a26cadc58d Disable the protection from escaped allocas in an attempt to find violating passes. This may break the buildbots. I plan to revert it in a few hours.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164024 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 10:21:55 +00:00
Craig Topper
1d2b45f167 Fix bad comment. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-16 16:48:25 +00:00
Jakob Stoklund Olesen
c722ae7a2b Add alternative coalescing algorithm under a flag.
The live range of an SSA value forms a sub-tree of the dominator tree.
That means the live ranges of two values overlap if and only if the def
of one value lies within the live range of the other.

This can be used to simplify the interference checking a bit: Visit each
def in the two registers about to be joined. Check for interference
against the value that is live in the other register at the def point
only. It is not necessary to scan the set of overlapping live ranges,
this interference check can be done while computing the value mapping
required for the final live range join.

The new algorithm is prepared to handle more complicated conflict
resolution - We can allow overlapping live ranges with different values
as long as the differing lanes are undef or unused in the other
register.

The implementation in this patch doesn't do that yet, it creates code
that is nearly identical to the old algorithm's, except:

- The new stripCopies() function sees through multiple copies while
  the old RegistersDefinedFromSameValue() only can handle one.

- There are a few rare cases where the new algorithm can erase an
  IMPLICIT_DEF instuction that RegistersDefinedFromSameValue() couldn't
  handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-16 02:15:36 +00:00
Craig Topper
86a1c32e67 Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 17:09:36 +00:00
Jakob Stoklund Olesen
ab9baf7ff4 Don't depend on kill flags in removeCopyByCommutingDef().
Kill flags are removed more and more aggressively during the register
allocation passes, it is better to get information from LiveIntervals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 16:32:11 +00:00
Andrew Trick
99ab6c6035 TargetSchedModel interface. To be implemented...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163934 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 20:26:46 +00:00
Andrew Trick
d039b383e7 misched: add a hook for custom DAG postprocessing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 17:22:42 +00:00
Duncan Sands
74b4762234 Remove silly dead store. Patch by Ettl Martin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 09:00:11 +00:00
Eric Christopher
ffaf69b8b1 Fix both the test for zero and what we do if we have a zero for
umulo legalization.

Fixes PR13839

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163856 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 23:24:02 +00:00
Eric Christopher
331f64cd0d Reformat, remove a couple unused variables and move some variables
closer to where they're needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 23:23:58 +00:00
Michael Liao
092122f124 Enhance type legalization on bitcast from vector to integer
- Find a legal vector type before casting and extracting element from it.
- As the new vector type may have more than 2 elements, build the final
  hi/lo pair by BFS pairing them from bottom to top.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 19:58:21 +00:00
Nadav Rotem
18e2c29094 Rename the flag which protects from escaped allocas, which may come from bugs in user code or in the compiler. Also, dont assert if the protection is not enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 15:46:30 +00:00
Nadav Rotem
91a7e0184a Fix a dagcombine optimization. The optimization attempts to optimize a bitcast of fneg to integers
by xoring the high-bit. This fails if the source operand is a vector because we need to negate
each of the elements in the vector.

Fix rdar://12281066 PR13813.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 14:54:28 +00:00
Nadav Rotem
faf31d01db Fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163801 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 14:51:00 +00:00
Nadav Rotem
0cd19b9301 Stack Coloring: We have code that checks that all of the uses of allocas
are within the lifetime zone. Sometime legitimate usages of allocas are
hoisted outside of the lifetime zone. For example, GEPS may calculate the
address of a member of an allocated struct. This commit makes sure that
we only check (abort regions or assert) for instructions that read and write
memory using stack frames directly. Notice that by allowing legitimate
usages outside the lifetime zone we also stop checking for instructions
which use derivatives of allocas. We will catch less bugs in user code
and in the compiler itself.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163791 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 12:38:37 +00:00
Eric Christopher
e521278f00 Recommit, with fixes:
Add some support for dealing with an object pointer on arguments.

    Part of rdar://9797999

which now supports adding the object pointer attribute to the
subprogram as it should.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 23:36:19 +00:00
Michael Liao
6c7ccaa3fd Fix PR11985
- BlockAddress has no support of BA + offset form and there is no way to
  propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
  simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
  support BA + offset addressing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 21:43:09 +00:00
Owen Anderson
045ca86bb3 Remove an overly-aggressive assertion. The code following this assertion already knows how to handle the case where DstRC was NULL, so it's not actually protecting us from anything, and this pattern can come up when using unknown_class operands in the SelectionDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163736 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 20:09:19 +00:00
Jakob Stoklund Olesen
01b50ca5b3 Delete dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 20:04:17 +00:00
Eric Christopher
fd1cd57221 Revert "Add some support for dealing with an object pointer on arguments."
This should be done on the subprogram, not the variable itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 18:42:31 +00:00
Dmitri Gribenko
67c8978617 Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 16:59:47 +00:00
Kristof Beyls
789efbad2a Fix constant folding through bitcasts by no longer relying on undefined behaviour (converting NaN values between float and double).
SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget);
should not be used when Val is not a simple constant (as the comment in
SelectionDAG.h indicates). This patch avoids using this function
when folding an unknown constant through a bitcast, where it cannot be
guaranteed that Val will be a simple constant.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 11:25:02 +00:00
Nadav Rotem
d76f6eadc8 Add a flag to disable the code that looks for allocas which escaped the lifetime regions. This is useful for debugging. No testcase because without this check we fail on assertions when finding escaped allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163702 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 11:06:26 +00:00
James Molloy
c4f70d437d Add a function computeRegisterLiveness() to MachineBasicBlock. This uses analyzePhysReg() from r163694 to heuristically try and determine the liveness state of a physical register upon arrival at a particular instruction in a block.
The search for liveness is clipped to a specific number of instructions around the target MachineInstr, in order to avoid degenerating into an O(N^2) algorithm. It tries to use various clues about how instructions around (both before and after) a given MachineInstr use that register, to determine its state at the MachineInstr.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163695 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 10:18:23 +00:00
James Molloy
b17cf29784 Add an analyzePhysReg() function to MachineOperandIteratorBase that analyses an instruction's use of a physical register, analogous to analyzeVirtReg.
Rename RegInfo to VirtRegInfo so as not to be confused with the new PhysRegInfo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 10:03:31 +00:00
Nadav Rotem
dba5de5246 Enable stack-coloring, in hope that the recent fixes will enable correct dragonegg self-hosting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 07:58:35 +00:00
Lang Hames
6d742cc61e Make findLastUseBefore handle reg-unit liveness.
findLastUseBefore was previous considering virtreg liveness only, leading to
incorrect live intervals for reg units when instrs with physreg operands were
moved up.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 06:56:16 +00:00
Nadav Rotem
0a16da4457 Stack coloring: remove lifetime intervals which contain escaped allocas.
The input program may contain intructions which are not inside lifetime
markers. This can happen due to a bug in the compiler or due to a bug in
user code (for example, returning a reference to a local variable).
This commit adds checks that all of the instructions in the function and
invalidates lifetime ranges which do not contain all of the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163678 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 04:57:37 +00:00
Eric Christopher
2c57a334d7 Add some support for dealing with an object pointer on arguments.
Part of rdar://9797999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 00:26:55 +00:00
Manman Ren
b720be6a50 Release build: guard dump functions with
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"

No functional change. Update r163339.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 22:23:19 +00:00
Chad Rosier
a7b159ccdd [ms-inline asm] Split the parsing of IR asm strings into GCC and MS variants.
Add support in the EmitMSInlineAsmStr() function for handling integer consts.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163645 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 19:09:56 +00:00
Nadav Rotem
1eba4a7a28 Dragonegg selfhost exposed additional cases where alloca usage moved outside of lifetime markers. Disabling the pass for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 15:40:27 +00:00
Nadav Rotem
50bdea299c Enable stack coloring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163617 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 13:48:35 +00:00
Nadav Rotem
8754bbbe67 Stack Coloring: Dont crash on dbg values which use stack frames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 12:34:27 +00:00
Craig Topper
dd201ff1dc Teach DAG combiner to constant fold FABS of a BUILD_VECTOR of ConstantFPs. Factor similar code out of FNEG DAG combiner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 01:45:21 +00:00
Andrew Trick
78e5efe1b2 Reorganize MachineScheduler interfaces and publish them in the header.
The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.

For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 00:39:15 +00:00
Eric Christopher
09e4750919 Revert r160148 it seems to cause more problems than it should
right now. We'll fix PR13303 a different way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 23:34:06 +00:00
Eric Christopher
4984e01fd5 80-col fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 23:34:03 +00:00
Eric Christopher
edf8bc8c88 80-col fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 23:34:00 +00:00
Eric Christopher
5c38de99f1 No reason to construct this twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 23:33:57 +00:00
Chad Rosier
24f5fddbdf [ms-inline asm] Properly emit the asm directives when the AsmPrinterVariant
and InlineAsmVariant don't match.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 21:36:05 +00:00
Dmitri Gribenko
2de0572cae Remove redundant semicolons which are null statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 21:26:47 +00:00
Nadav Rotem
8631a90f46 Disable stack coloring because it makes dragonegg fail bootstrapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 21:17:58 +00:00
Chad Rosier
3b132fab0b [ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() function
and update the printOperand() function accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 21:10:49 +00:00
Nadav Rotem
b6d52a5b4a Enable stack coloring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163539 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 20:15:49 +00:00
Nadav Rotem
6165dba25f Stack Coloring: Handle the case where END markers come before BEGIN markers properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163530 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 18:51:09 +00:00
Michael Ilseman
10def396cb Fold multiply by 0 or 1 when in UnsafeFPMath mode in SelectionDAG::getNode().
This folding happens as early as possible for performance reasons, and to make sure it isn't foiled by other transforms (e.g. forming FMAs).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 17:00:37 +00:00
Michael Ilseman
06b9690463 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 16:56:31 +00:00
James Molloy
8cd08bf4ac Fix an assertion failure when optimising a shufflevector incorrectly into concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163511 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 14:01:21 +00:00
Nadav Rotem
ff1b63172d Minor cleanup. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 13:20:00 +00:00
Nadav Rotem
9438d1e351 Stack Coloring: Debug prints to print the slot number and not the array index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163509 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 13:17:58 +00:00
Nadav Rotem
a7de8a61df Stack Coloring: When searching for disjoint regions, do not compare intervals twice or to theirself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163508 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 12:47:38 +00:00
Nadav Rotem
e47feeb823 Stack Coloring: Add support for multiple regions of the same slot, within a single basic block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163507 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 12:39:35 +00:00
Nadav Rotem
8cc1494905 Fix a typo in the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163496 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 08:51:46 +00:00
Nadav Rotem
0aa52ee04e Add an assertion that the frame index is indeed inside the declared lifetime region.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163495 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 08:44:15 +00:00
Nadav Rotem
9a2ae00c85 Teach the DAGBuilder about lifetime markers which are generated from PHINodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 08:43:23 +00:00
Craig Topper
956342b210 Teach DAG combiner to constant fold fneg of a BUILD_VECTOR of constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163483 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-09 22:58:45 +00:00
Benjamin Kramer
11b4505899 LiveVariables: Compute a set of defs and kills to speed up updating LV during critical edge splitting.
Previously we checked if the register is def'd in a block via the def/use list a
nd walked the list of kills to check if the register is killed in a block. Both
of these checks can be made much cheaper by walking the block first and
recording all defs and kills.

This reduces the compile time of the test case from PR13651 from 40s to 15s at
-O2. The compile time is still dominated by LV updating but now the main culprit
is SparseBitVector's slowness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163478 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-09 11:56:14 +00:00
Benjamin Kramer
a9e37c5eaf Fix alignment of .comm and .lcomm on mingw32.
For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't
use the same setting for both. Fix this by reintroducing the LCOMM enum.
I verified this against mingw's gcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 21:08:01 +00:00
Chad Rosier
26c5d5f0a9 Fix indent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163416 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 20:23:29 +00:00
Chad Rosier
c53ade2889 Update function names to conform to guidelines. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163401 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 18:16:38 +00:00
Benjamin Kramer
39646d96e7 MC: Overhaul handling of .lcomm
- Darwin lied about not supporting .lcomm and turned it into zerofill in the
  asm parser. Push the zerofill-conversion down into macho-specific code.
- This makes the tri-state LCOMMType enum superfluous, there are no targets
  without .lcomm.
- Do proper error reporting when trying to use .lcomm with alignment on a target
  that doesn't support it.
- .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2.
- Fixes PR13755 (.lcomm crashes on ELF).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 17:25:13 +00:00
Michael Liao
1fdaee9995 Stop emitting lifetime region info when stack coloring is not enabled in O0
- this should fix PR13780



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163370 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 05:13:00 +00:00
Manman Ren
77e300e8f0 Release build: guard dump functions with "ifndef NDEBUG"
No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 19:06:06 +00:00
Jakob Stoklund Olesen
45c5c57179 Allow overlaps between virtreg and physreg live ranges.
The RegisterCoalescer understands overlapping live ranges where one
register is defined as a copy of the other. With this change, register
allocators using LiveRegMatrix can do the same, at least for copies
between physical and virtual registers.

When a physreg is defined by a copy from a virtreg, allow those live
ranges to overlap:

  %CL<def> = COPY %vreg11:sub_8bit; GR32_ABCD:%vreg11
  %vreg13<def,tied1> = SAR32rCL %vreg13<tied0>, %CL<imp-use,kill>

We can assign %vreg11 to %ECX, overlapping the live range of %CL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 18:15:23 +00:00
Jakob Stoklund Olesen
e617ccb80d Handle overlapping regunit intervals in LiveIntervals::addKillFlags().
We will soon allow virtual register live ranges to overlap regunit live
ranges when the physreg is defined as a copy of the virtreg:

  %EAX = COPY %vreg5
  FOO %vreg5
  BAR %EAX<kill>

There is no real interference since %vreg5 and %EAX have the same value
where they overlap.

This patch prevents addKillFlags from adding virtreg kill flags to FOO
where the assigned physreg is overlapping the virtual register live
range.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163335 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 18:15:18 +00:00
Jakob Stoklund Olesen
f9dff0e0e4 Clear kill flags while computing live ranges.
Kill flags are difficult to maintain, and liveness queries are better
handled by live intervals.

Kill flags are reinserted after register allocation by addKillFlags().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 18:15:15 +00:00
Roman Divacky
5177b3a8c4 Dont cast away const needlessly. Found by gcc48 -Wcast-qual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 15:42:13 +00:00
Nadav Rotem
79cb162e5d Disable stack coloring by default in order to resolve the i386 failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 14:27:06 +00:00
Nadav Rotem
e757640df0 Fix a few old-GCC warnings. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 11:13:55 +00:00
Nadav Rotem
c05d30601c Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 09:17:37 +00:00
Chad Rosier
366df7945f [ms-inline asm] Use the asm dialect from the MI to set the parser dialect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163273 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 23:57:37 +00:00
Chad Rosier
2f1d815479 Cleanup a few magic numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163263 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 22:40:13 +00:00
Roman Divacky
5932429765 Stop casting away const qualifier needlessly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 22:26:57 +00:00
Chad Rosier
77fffa6fdd [ms-inline asm] We only need one bit to represent the AsmDialect in the
MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 22:17:43 +00:00
Roman Divacky
2943e37804 Constify this properly. Found by gcc48 -Wcast-qual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 22:15:49 +00:00
Roman Divacky
141e99745a Constify SDNodeIterator an stop its only non-const user being cast stripped
of its constness. Found by gcc48 -Wcast-qual.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163254 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 22:03:34 +00:00
Chad Rosier
576cd11ab8 [ms-inline asm] Propagate the asm dialect into the MachineInstr representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 21:00:58 +00:00
Roman Divacky
15d0c81b24 Remove unused typedefs gcc4.8 warns about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 17:55:46 +00:00
Silviu Baranga
3d5e161fe4 Fixed the DAG combiner to better handle the folding of AND nodes for vector types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 08:57:21 +00:00
Logan Chien
ec90cc8b0f Reorder the comments of EmitExceptionTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 06:28:26 +00:00
Craig Topper
f6dc792df1 Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163192 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 05:48:09 +00:00
Jakob Stoklund Olesen
f363ebdb03 Search the whole instruction for tied operands.
Implicit uses can be dynamically tied to defs. This will soon be used
for predicated instructions on ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 22:59:30 +00:00
Jakob Stoklund Olesen
4f1a56ce3c Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 18:44:43 +00:00
Jakob Stoklund Olesen
99c416c9f7 Actually use the MachineOperand field for isRegTiedToDefOperand().
The MachineOperand::TiedTo field was maintained, but not used.

This patch enables it in isRegTiedToDefOperand() and
isRegTiedToUseOperand() which are the actual functions use by the
register allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 18:43:25 +00:00
Jakob Stoklund Olesen
daddf07497 Move tie checks into MachineVerifier::visitMachineOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 18:38:28 +00:00
Jakob Stoklund Olesen
9c13067276 Allow tied uses and defs in different orders.
After much agonizing, use a full 4 bits of precious MachineOperand space
to encode this. This uses existing padding, and doesn't grow
MachineOperand beyond its current 32 bytes.

This allows tied defs among the first 15 operands on a normal
instruction, just like the current MCInstrDesc constraint encoding.
Inline assembly needs to be able to tie more than the first 15 operands,
and gets special treatment.

Tied uses can appear beyond 15 operands, as long as they are tied to a
def that's in range.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163151 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 18:36:28 +00:00
Preston Gurd
2e2efd9600 Generic Bypass Slow Div
- CodeGenPrepare pass for identifying div/rem ops
- Backend specifies the type mapping using addBypassSlowDivType
- Enabled only for Intel Atom with O2 32-bit -> 8-bit
- Replace IDIV with instructions which test its value and use DIVB if the value
is positive and less than 256.
- In the case when the quotient and remainder of a divide are used a DIV
and a REM instruction will be present in the IR. In the non-Atom case
they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
using the quotient and remainder from the first IDIV. However,
due to this optimization CSE is not able to eliminate redundant
IDIV instructions because they are located in different basic blocks.
This is overcome by calculating both the quotient (DIV) and remainder (REM)
in each basic block that is inserted by the optimization and reusing the result
values when a subsequent DIV or REM instruction uses the same operands.
- Test cases check for the presents of the optimization when calculating
either the quotient, remainder,  or both.

Patch by Tyler Nowicki!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 18:22:17 +00:00
Benjamin Kramer
f68b87f5fc IRBuilderify the SjlLjEHPrepare pass.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163115 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03 12:27:43 +00:00
Lang Hames
7b23d08385 When updating live range endpoints, make sure to preserve the early clobber bit.
Fixs PR13719.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03 06:31:45 +00:00
Nadav Rotem
ee77da6b28 Fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-02 12:21:50 +00:00
Nadav Rotem
f55ef64544 Generate better select code by allowing the target to use scalar select, and not sign-extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-02 08:20:07 +00:00
Pete Cooper
d906017c1a Only legalise a VSELECT in to bitwise operations if the vector mask bool is zeros or all ones. A vector bool with just ones isn't suitable for masking with.
No test case unfortunately as i couldn't find a target which fit all
the conditions needed to hit this code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01 22:27:48 +00:00
Pete Cooper
0fc44aba18 Revert "Take account of boolean vector contents when promoting a build vector from i1 to some other type. rdar://problem/12210060"
This reverts commit 5dd9e214fb.

Thanks to Duncan for explaining how this should have been done.

Conflicts:

	test/CodeGen/X86/vec_select.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01 17:37:55 +00:00
Logan Chien
e2ac552421 Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01 12:11:41 +00:00
Owen Anderson
58d5729540 Teach DAG combine a number of tricks to simplify FMA expressions in fast-math mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01 06:04:27 +00:00
Michael Liao
b79bff50bd Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01 04:09:16 +00:00
Jakob Stoklund Olesen
94083149fd Add MachineInstr::tieOperands, remove setIsTied().
Manage tied operands entirely internally to MachineInstr. This makes it
possible to change the representation of tied operands, as I will do
shortly.

The constraint that tied uses and defs must be in the same order was too
restrictive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163021 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31 20:50:53 +00:00
Craig Topper
89b2ff0b5c Use CloneMachineInstr to make a new MI in commuteInstruction to make the code tolerant of instructions with more than two input operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31 16:30:05 +00:00
Jakob Stoklund Olesen
908c0c01f6 Don't enforce ordered inline asm operands.
I was too optimistic, inline asm can have tied operands that don't
follow the def order.

Fixes PR13742.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162998 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31 15:34:59 +00:00
Pete Cooper
5dd9e214fb Take account of boolean vector contents when promoting a build vector from i1 to some other type. rdar://problem/12210060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 23:58:52 +00:00
Owen Anderson
43da6c7f13 Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by constants. This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 23:35:16 +00:00
Nadav Rotem
e757f00446 Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target
because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR
to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2).

rdar://12201387



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 19:17:29 +00:00
Jakob Stoklund Olesen
e941df5e35 Don't use MCInstrDesc flags for implicit operands.
When a MachineInstr is constructed, its implicit operands are added
first, then the explicit operands are inserted before the implicits.

MCInstrDesc has oprand flags like early clobber and operand ties that
apply to the explicit operands.

Don't look at those flags when the implicit operands are first added in
the explicit operands's positions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 14:39:06 +00:00
Craig Topper
6b1e1d8b3d Add FMA to switch statement in VectorLegalizer::LegalizeOp so that it can be expanded when it isn't legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162894 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 07:34:22 +00:00
Craig Topper
3b9dfc9bf7 Add support for FMA to WidenVectorResult.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162893 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 07:13:41 +00:00
Jakob Stoklund Olesen
492d76b02e Verify the order of tied operands in inline asm.
When there are multiple tied use-def pairs on an inline asm instruction,
the tied uses must appear in the same order as the defs.

It is possible to write an LLVM IR inline asm instruction that breaks
this constraint, but there is no reason for a front end to emit the
operands out of order.

The gnu inline asm syntax specifies tied operands as a single read/write
constraint "+r", so ouf of order operands are not possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 23:52:52 +00:00
Jakob Stoklund Olesen
66390805ad Set the isTied flags when building INLINEASM MachineInstrs.
For normal instructions, isTied() is set automatically by addOperand(),
based on MCInstrDesc, but inline asm has tied operands outside the
descriptor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 22:02:00 +00:00
Jakob Stoklund Olesen
f036f7a1e7 Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().
Ordered memory operations are more constrained than volatile loads and
stores because they must be ordered with respect to all other memory
operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 21:19:21 +00:00
Jakob Stoklund Olesen
0d75858395 Don't move normal loads across volatile/atomic loads.
It is technically allowed to move a normal load across a volatile load,
but probably not a good idea.

It is not allowed to move a load across an atomic load with
Ordering > Monotonic, and we model those with MOVolatile as well.

I recently removed the mayStore flag from atomic load instructions, so
they don't need a pseudo-opcode. This patch makes up for the difference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162857 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 20:48:45 +00:00
Jakob Stoklund Olesen
90a4f78d3b Verify the consistency of inline asm operands.
The operands on an INLINEASM machine instruction are divided into groups
headed by immediate flag operands. Verify this structure.

Extract verifyTiedOperands(), and only call it for non-inlineasm
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162849 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 18:11:05 +00:00
Eric Christopher
17dd9a992a Clean this up slightly, doesn't really fall through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 17:59:32 +00:00
Jakob Stoklund Olesen
ca71c5debe Verify the tied operand flags.
WHen running with -verify-machineinstrs, check that tied operands come
in matching use/def pairs, and that they are consistent with MCInstrDesc
when it applies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:38:03 +00:00
Jakob Stoklund Olesen
699ac04951 Maintain a vaild isTied bit as operands are added and removed.
The isTied bit is set automatically when a tied use is added and
MCInstrDesc indicates a tied operand. The tie is broken when one of the
tied operands is removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 00:37:58 +00:00
Jakob Stoklund Olesen
4ba6916a98 Add a MachineOperand::isTied() flag.
While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.

Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.

The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.

Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.

Adding a predicate to:

  %vreg0<def> = ADD %vreg1, %vreg2

Will look like:

  %vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>

The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.

This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 18:34:41 +00:00
Jakob Stoklund Olesen
190e342cbc Don't allow TargetFlags on MO_Register MachineOperands.
Register operands are manipulated by a lot of target-independent code,
and it is not always possible to preserve target flags. That means it is
not safe to use target flags on register operands.

None of the targets in the tree are using register operand target flags.
External targets should be using immediate operands to annotate
instructions with operand modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 18:05:48 +00:00
Jakob Stoklund Olesen
36d29bc723 Remove extra MayLoad/MayStore flags from atomic_load/store.
These extra flags are not required to properly order the atomic
load/store instructions. SelectionDAGBuilder chains atomics as if they
were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on
the memory operands of all atomic operations.

The volatile bit is enough to order atomic loads and stores during and
after SelectionDAG.

This means we set mayLoad on atomic_load, mayStore on atomic_store, and
mayLoad+mayStore on the remaining atomic read-modify-write operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 03:11:32 +00:00
Akira Hatanaka
1d522388bf Fix bug 13532.
In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without
using any f64 operations if f64 is not a legal type.

Patch by Stefan Kristiansson. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 02:12:42 +00:00
Richard Smith
1144af3c9b Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 23:29:28 +00:00
Jakob Stoklund Olesen
baa74e4b35 Avoid including explicit uses when counting SDNode imp-uses.
It is legal to have a register node as an explicit operand, it shouldn't
be counted as an implicit use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 20:52:42 +00:00
Manman Ren
1a710fdde1 BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle
the case of multiple edges from one block to another.

A simple example is a switch statement with multiple values to the same
destination. The definition of an edge is modified from a pair of blocks to
a pair of PredBlock and an index into the successors.

Also set the weight correctly when building SelectionDAG from LLVM IR,
especially when converting a Switch.
IntegersSubsetMapping is updated to calculate the weight for each cluster.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162572 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 18:14:27 +00:00
Eric Christopher
873cf0a0d7 Use DW_FORM_flag_present to save space in debug information if we're
not in darwin gdb compat mode.

Fixes rdar://10975088

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 01:14:27 +00:00
Eric Christopher
cbbd5b1d86 Remove the DW_AT_MIPS_linkage name attribute when we don't need it
output (we're emitting a specification already and the information
isn't changing) and we're not in old gdb compat mode.

Saves 1% on the debug information for a build of llvm.

Fixes rdar://11043421

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162493 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 22:52:55 +00:00
Eric Christopher
20f47ab768 Turn these two options in to trinary state so that they can be
turned on and off separate from the platform if you're on darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 22:36:40 +00:00
Eric Christopher
c1610fa3c4 Add a flag to DwarfDebug to allow it to communicate whether or not
we're using the darwin old gdb compat mode for emitting dwarf.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 22:36:36 +00:00
Eric Christopher
9d9f5a5855 Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162438 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 07:32:06 +00:00
Eric Christopher
9eb1a94c20 Only emit the __debug_inlined section if we're trying to be compatible
with older gdbs on darwin.

rdar://10975874

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162436 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 07:32:02 +00:00
Eric Christopher
360f0062bc Emit pubtypes only when going for darwin gdb compatibility.
rdar://10393214

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162434 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 07:10:56 +00:00
Eric Christopher
10cb744f19 Add an option for darwin gdb compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162432 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 07:10:46 +00:00
Andrew Trick
ffd2526fa4 Simplify the computeOperandLatency API.
The logic for recomputing latency based on a ScheduleDAG edge was
shady. This bypasses the problem by requiring the client to provide
operand indices. This ensures consistent use of the machine model's
API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 00:39:43 +00:00
David Blaikie
986d76d7b3 Tidy up a few more uses of MF.getFunction()->getName().
Based on CR feedback from r162301 and Craig Topper's refactoring in r162347
here are a few other places that could use the same API (& in one instance drop
a Function.h dependency).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162367 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 17:18:53 +00:00
Benjamin Kramer
05d96f98cb Reduce duplicated hash map lookups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162362 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 15:37:57 +00:00
Stepan Dyatkovskiy
fdeb9fe5e0 Rejected 169195. As Duncan commented, bitcasting to proper type is wrong approach. We need to insert some valid TRANCATE node here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162354 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 09:33:55 +00:00
Craig Topper
96601ca332 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 06:07:19 +00:00
Richard Smith
cb1f68d7c8 Initialize SelectionDAGBuilder's Context in 'init', not in its constructor. The
SelectionDAG's 'init' has not been called when the SelectionDAGBuilder is
constructed (in SelectionDAGISel's constructor), so this was previously always
initialized with 0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162333 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 00:42:39 +00:00
David Blaikie
79c78de378 Remove unnecessary cast that was also unnecessarily casting away constness.
Even looking at the revision history I couldn't quite piece together why this
cast was ever written in the first place, but I assume it was because of some
change in the inheritance, perhaps this function was reimplemented in a
derived type & this caller was meant to get the base version (& it wasn't
virtual)?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-21 18:54:23 +00:00
Chad Rosier
35907e9862 Add support for the --param ssp-buffer-size= driver option.
PR9673

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-21 16:15:24 +00:00
Jakob Stoklund Olesen
990ca5517f Fix a quadratic algorithm in MachineBranchProbabilityInfo.
The getSumForBlock function was quadratic in the number of successors
because getSuccWeight would perform a linear search for an already known
iterator.

This patch was originally committed as r161460, but reverted again
because of assertion failures. Now that duplicate Machine CFG edges have
been eliminated, this works properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-20 22:01:38 +00:00
Jakob Stoklund Olesen
e7fdef420d Don't add CFG edges for redundant conditional branches.
IR that hasn't been through SimplifyCFG can look like this:

  br i1 %b, label %r, label %r

Make sure we don't create duplicate Machine CFG edges in this case.

Fix the machine code verifier to accept conditional branches with a
single CFG edge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-20 21:39:52 +00:00
Jakob Stoklund Olesen
228e3f5fac Add a verification pass after ExpandISelPseudos.
This pass often has weird CFG hacks and hand-written MI building code
that can go wrong in many ways.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-20 20:52:08 +00:00
Jakob Stoklund Olesen
b254c6d77a Add CFG checks to MachineVerifier.
Verify that the predecessor and successor lists are consistent and free
of duplicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162223 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-20 20:52:06 +00:00
Stepan Dyatkovskiy
08da177c35 Fixed DAGCombiner bug (found and localized by James Malloy):
The DAGCombiner tries to optimise a BUILD_VECTOR by checking if it
consists purely of get_vector_elts from one or two source vectors. If
so, it either makes a concat_vectors node or a shufflevector node.

However, it doesn't check the element type width of the underlying
vector, so if you have this sequence:

Node0: v4i16 = ...
Node1: i32 = extract_vector_elt Node0
Node2: i32 = extract_vector_elt Node0
Node3: v16i8 = BUILD_VECTOR Node1, Node2, ...

It will attempt to:

Node0:    v4i16 = ...
NewNode1: v16i8 = concat_vectors Node0, ...

Where this is actually invalid because the element width is completely
different. This causes an assertion failure on DAG legalization stage.

Fix:
If output item type of BUILD_VECTOR differs from input item type.
Make concat_vectors based on input element type and then bitcast it to the output vector type. So the case described above will transformed to:
Node0:    v4i16 = ...
NewNode1: v8i16 = concat_vectors Node0, ...
NewNode2: v16i8 = bitcast NewNode1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-20 07:57:06 +00:00
Eli Friedman
fd45fa1503 Make atomic load and store of pointers work. Tighten verification of atomic operations
so other unexpected operations don't slip through.  Based on patch by Logan Chien.
PR11786/PR13186.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162146 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 23:24:29 +00:00
Bill Wendling
a67eda76c0 Implement stack protectors for structures with character arrays in them.
<rdar://problem/10545247>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 20:59:56 +00:00
Bill Wendling
32811bef95 Change the linker_private_weak_def_auto' linkage to linkonce_odr_auto_hide' to
make it more consistent with its intended semantics.

The `linker_private_weak_def_auto' linkage type was meant to automatically hide
globals which never had their addresses taken. It has nothing to do with the
`linker_private' linkage type, which outputs the symbols with a `l' (ell) prefix
among other things.

The intended semantic is more like the `linkonce_odr' linkage type.

Change the name of the linkage type to `linkonce_odr_auto_hide'. And therefore
changing the semantics so that it produces the correct output for the linker.

Note: The old linkage name `linker_private_weak_def_auto' will still parse but
is not a synonym for `linkonce_odr_auto_hide'. This should be removed in 4.0.
<rdar://problem/11754934>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 18:33:14 +00:00
Benjamin Kramer
b97cebdfcc TargetLowering: Use the large shift amount during legalize types. The legalizer may call us with an overly large type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 15:54:21 +00:00
Jakob Stoklund Olesen
cabc0699ea Use standard pattern for iterate+erase.
Increment the MBB iterator at the top of the loop to properly handle the
current (and previous) instructions getting erased.

This fixes PR13625.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 14:38:59 +00:00
Jakob Stoklund Olesen
f2c64ef519 Add an MCID::Select flag and TII hooks for optimizing selects.
Select instructions pick one of two virtual registers based on a
condition, like x86 cmov. On targets like ARM that support predication,
selects can sometimes be eliminated by predicating the instruction
defining one of the operands.

Teach PeepholeOptimizer to recognize select instructions, and ask the
target to optimize them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16 23:11:47 +00:00
Richard Smith
11a4fa4523 Fix undefined behavior: don't perform array indexing through a potentially null
pointer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161919 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15 01:39:31 +00:00
Richard Smith
bb57febe3c Fix undefined behavior: binding null pointer to reference. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161853 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14 05:31:26 +00:00
Eric Christopher
443c9ed768 Grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14 05:13:29 +00:00
Owen Anderson
7c626d3097 Add a roundToIntegral method to APFloat, which can be parameterized over various rounding modes. Use this to implement SelectionDAG constant folding of FFLOOR, FCEIL, and FTRUNC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13 23:32:49 +00:00
Jakob Stoklund Olesen
03e593efc6 Transfer weights in transferSuccessorsAndUpdatePHIs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161805 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13 23:13:25 +00:00
Jakob Stoklund Olesen
cb6889b23d Print out MachineBasicBlock successor weights when available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161804 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13 23:13:23 +00:00
Jakob Stoklund Olesen
43600e95ec Remove the TII::scheduleTwoAddrSource() hook.
It never does anything when running 'make check', and it get's in the
way of updating live intervals in 2-addr.

The hook was originally added to help form IT blocks in Thumb2 code
before register allocation, but the pass ordering has changed since
then, and we run if-conversion after register allocation now.

When the MI scheduler is enabled, there will be no less than two
schedulers between 2-addr and Thumb2ITBlockPass, so this hook is
unlikely to help anything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13 21:52:57 +00:00
Bill Wendling
6d86f3cdfc Whitespace cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161788 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13 21:20:43 +00:00
Jakob Stoklund Olesen
786556c268 Count triangles and diamonds in early if-conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161783 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13 21:03:27 +00:00
Jakob Stoklund Olesen
5f6d36335b Delete dead typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13 21:03:25 +00:00
Jakob Stoklund Olesen
bc70ff3cb9 Handle extra Tail predecessors in if-conversion.
It is still possible to if-convert if the tail block has extra
predecessors, but the tail phis must be rewritten instead of being
removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161781 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13 20:49:04 +00:00
Benjamin Kramer
5fa2d458af MachineCSE: Hoist isConstantPhysReg out of the loop, it checks for overlaps already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 20:42:59 +00:00
Benjamin Kramer
cfc0ad6e48 PR13578: Teach MachineCSE that instructions that use a constant register can be CSE'd safely.
This is common e.g. when doing rip-relative addressing on x86_64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 19:05:13 +00:00
Jakob Stoklund Olesen
eb74c08192 Add a proper if-conversion cost model.
Detect when there is not enough available ILP, so if-conversion can't
speculate instructions for free.

Compute the lengthening of the critical path when inserting a select
instruction that depends on the condition as well as both sides of the
if.

Reject conversions that would stretch the critical path by more than
half a mispredict penalty.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161713 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 22:27:31 +00:00
Jakob Stoklund Olesen
a35bf506f4 Give MachineTraceMetrics its own debug tag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 22:27:29 +00:00
Jakob Stoklund Olesen
5413b68b1f Add more trace query functions.
Trace::getResourceLength() computes the number of cycles required to
execute the trace when ignoring data dependencies. The number can be
compared to the critical path to estimate the trace ILP.

Trace::getPHIDepth() computes the data dependency depth of a PHI in a
trace successor that isn't necessarily part of the trace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 22:27:27 +00:00
Jakob Stoklund Olesen
870da6de2c Add getTPred() and getFPred() functions.
They identify the PHI predecessors in both diamonds and triangles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 20:19:17 +00:00
Jakob Stoklund Olesen
8828c4ccd4 Include loop-carried dependencies when computing instr heights.
When a trace ends with a back-edge, include PHIs in the loop header in
the height computations. This makes the critical path through a loop
more accurate by including the latencies of the last instructions in the
loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161688 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 20:11:38 +00:00
Jakob Stoklund Olesen
15121ca0d1 Update edge weights correctly in replaceSuccessor().
When replacing Old with New, it can happen that New is already a
successor. Add the old and new edge weights instead of creating a
duplicate edge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 03:23:27 +00:00
Jakob Stoklund Olesen
c7908037d8 Reapply r161633-161634 "Partition use lists so defs always come before uses.""
No changes to these patches, MRI needed to be notified when changing
uses into defs and vice versa.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 00:21:30 +00:00
Jakob Stoklund Olesen
d6397eba23 Also update MRI use lists when changing a use to a def and vice versa.
This was the cause of the buildbot failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161643 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 00:21:26 +00:00
Jakob Stoklund Olesen
1134aae4e7 Revert r161633-161634 "Partition use lists so defs always come before uses."
These commits broke a number of buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161640 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 23:31:36 +00:00
Jakob Stoklund Olesen
81a6995243 Partition use lists so defs always come before uses.
This makes it possible to speed up def_iterator by stopping at the first
use. This makes def_empty() and getUniqueVRegDef() much faster when
there are many uses.

In a +Asserts build, LiveVariables is 100x faster in one case because
getVRegDef() has an assertion that would scan to the end of a
def_iterator chain.

Spill weight calculation is significantly faster (300x in one case)
because isTriviallyReMaterializable() calls MRI->isConstantPhysReg(%RIP)
which calls def_empty(%RIP).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 22:49:46 +00:00
Jakob Stoklund Olesen
46f4c35372 Don't use pointer-pointers for the register use lists.
Use a more conventional doubly linked list where the Prev pointers form
a cycle. This means it is no longer necessary to adjust the Prev
pointers when reallocating the VRegInfo array.

The test changes are required because the register allocation hint is
using the use-list order to break ties.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161633 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 22:49:42 +00:00
Jakob Stoklund Olesen
ff2b99afc8 Move use list management into MachineRegisterInfo.
Register MachineOperands are kept in linked lists accessible via MRI's
reg_iterator interfaces. The linked list management was handled partly
by MachineOperand methods, partly by MRI methods.

Move all of the list management into MRI, delete
MO::AddRegOperandToRegInfo() and MO::RemoveRegOperandFromRegInfo().

Be more explicit about handling the cases where an MRI pointer isn't
available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 22:49:37 +00:00
Jakob Stoklund Olesen
988069e229 Fix a future TwoAddressInstructionPass crash.
No test case, the crash only happens when the default use list order is
changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161627 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 22:08:26 +00:00
Nadav Rotem
0b66bd9b07 Fix the legalization of ExtLoad on ARM. ExpandUnalignedLoad did not properly
handle the cases where the memory value type was illegal. 
PR 13111. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161565 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 01:56:44 +00:00
Jakob Stoklund Olesen
4e6966266a Don't use getNextOperandForReg() in RAFast.
That particular optimization was probably premature anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 23:44:01 +00:00
Jakob Stoklund Olesen
e723007ee6 Deal with irreducible control flow when building traces.
We filter out MachineLoop back-edges during the trace-building PO
traversals, but it is possible to have CFG cycles that aren't natural
loops, and MachineLoopInfo doesn't include such cycles.

Use a standard visited set to detect such CFG cycles, and completely
ignore them when picking traces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 22:12:01 +00:00
Jakob Stoklund Olesen
d6cf5f4224 Heed -stress-early-ifcvt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 18:24:23 +00:00
Jakob Stoklund Olesen
0fac6aa076 Get the MispredictPenalty from MCSchedModel.
Thanks, Andy!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161507 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 18:19:58 +00:00
Andrew Trick
3c417554ca Minor cleanup of defaultDefLatency API
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 02:44:11 +00:00
Jakob Stoklund Olesen
913ff09a9a Revert "Fix a quadratic algorithm in MachineBranchProbabilityInfo."
It caused an assertion failure when compiling consumer-typeset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161463 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 01:10:31 +00:00
Manman Ren
39ad568c62 X86: enable CSE between CMP and SUB
We perform the following:
1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering.
2> Modify MachineCSE to correctly handle implicit defs.
3> Convert SUB back to CMP if possible at peephole.

Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled
by peephole now.

rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161462 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 00:51:41 +00:00
Jakob Stoklund Olesen
5e63d43e48 Fix a quadratic algorithm in MachineBranchProbabilityInfo.
The getSumForBlock function was quadratic in the number of successors
because getSuccWeight would perform a linear search for an already known
iterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 00:20:37 +00:00
Jakob Stoklund Olesen
8c5c0733cd Skip tied operand pairs that already have the same register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 22:47:06 +00:00
Jakob Stoklund Olesen
74500bdba3 Add SelectionDAG::getTargetIndex.
This adds support for TargetIndex operands during isel. The meaning of
these (index, offset, flags) operands is entirely defined by the target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161453 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 22:37:05 +00:00
Bill Wendling
1299422ee1 For non-Darwin platforms, we want to generate stack protectors only for
character arrays. This is in line with what GCC does.
<rdar://problem/10529227>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161446 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 20:59:05 +00:00
Jakob Stoklund Olesen
0b40d09ff6 Add a new kind of MachineOperand: MO_TargetIndex.
A target index operand looks a lot like a constant pool reference, but
it is completely target-defined. It contains the 8-bit TargetFlags, a
32-bit index, and a 64-bit offset. It is preserved by all code generator
passes.

TargetIndex operands can be used to carry target-specific information in
cases where immediate operands won't suffice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161441 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 18:56:39 +00:00
Jakob Stoklund Olesen
7a8f311ece Fix a couple of typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 18:32:57 +00:00
Jakob Stoklund Olesen
84ef6ba443 Add trace accessor methods, implement primitive if-conversion heuristic.
Compare the critical paths of the two traces through an if-conversion
candidate. If the difference is larger than the branch brediction
penalty, reject the if-conversion. If would never pay.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161433 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 18:02:19 +00:00
Chandler Carruth
e6450dc2af Add a much more conservative strategy for aligning branch targets.
Previously, MBP essentially aligned every branch target it could. This
bloats code quite a bit, especially non-looping code which has no real
reason to prefer aligned branch targets so heavily.

As Andy said in review, it's still a bit odd to do this without a real
cost model, but this at least has much more plausible heuristics.

Fixes PR13265.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161409 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 09:45:24 +00:00
Manman Ren
ba86b13ad9 MachineCSE: Update the heuristics for isProfitableToCSE.
If the result of a common subexpression is used at all uses of the candidate
expression, CSE should not increase the live range of the common subexpression.

rdar://11393714 and rdar://11819721


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 06:16:46 +00:00
Jakob Stoklund Olesen
cf1823dc25 Delete a dead variable.
TwoAddressInstructionPass doesn't remat any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161285 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04 00:04:03 +00:00
Jakob Stoklund Olesen
ae52faddeb TwoAddressInstructionPass refactoring: Extract another method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 23:57:58 +00:00
Bob Wilson
53624a2df5 Refactor and check "onlyReadsMemory" before optimizing builtins.
This patch is mostly just refactoring a bunch of copy-and-pasted code, but
it also adds a check that the call instructions are readnone or readonly.
That check was already present for sin, cos, sqrt, log2, and exp2 calls, but
it was missing for the rest of the builtins being handled in this code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161282 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 23:29:17 +00:00
Jakob Stoklund Olesen
6ac8066ae4 TwoAddressInstructionPass refactoring: Extract a method.
No functional change intended, except replacing a DenseMap with a
SmallDenseMap which should behave identically.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161281 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 23:25:45 +00:00
Jakob Stoklund Olesen
5bfdedf6ab Begin adding support for updating LiveIntervals in TwoAddressInstructionPass.
This is far from complete, and only changes behavior when the
-early-live-intervals flag is passed to llc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161273 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 22:58:34 +00:00
Jakob Stoklund Olesen
dcc4436cdd Add an experimental -early-live-intervals option.
This option runs LiveIntervals before TwoAddressInstructionPass which
will eventually learn to exploit and update the analysis.

Eventually, LiveIntervals will run before PHIElimination, and we can get
rid of LiveVariables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 22:12:54 +00:00
Jakob Stoklund Olesen
e744ac49f4 Delete merged physreg copies in joinReservedPhysReg().
Previously, the identity copy would survive through register allocation
before it was removed by the rewriter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 22:12:51 +00:00
Bob Wilson
982dc84762 Try to reduce the compile time impact of r161232.
The previous change caused fast isel to not attempt handling any calls to
builtin functions.  That included things like "printf" and caused some
noticable regressions in compile time.  I wanted to avoid having fast isel
keep a separate list of functions that had to be kept in sync with what the
code in SelectionDAGBuilder.cpp was handling.  I've resolved that here by
moving the list into TargetLibraryInfo.  This is somewhat redundant in
SelectionDAGBuilder but it will ensure that we keep things consistent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161263 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 21:26:24 +00:00
Bob Wilson
772af92cb1 Fix memcmp code-gen to honor -fno-builtin.
I noticed that SelectionDAGBuilder::visitCall was missing a check for memcmp
in TargetLibraryInfo, so that it would use custom code for memcmp calls even
with -fno-builtin.  I also had to add a new -disable-simplify-libcalls option
to llc so that I could write a test for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161262 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 21:26:18 +00:00
Jakob Stoklund Olesen
b2beac2b96 Completely eliminate VNInfo flags.
The 'unused' state of a value number can be represented as an invalid
def SlotIndex. This also exposed code that shouldn't have been looking
at unused value VNInfos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 20:59:32 +00:00
Jakob Stoklund Olesen
1599a64277 Fix a couple of loops that were processing unused value numbers.
Unused VNInfos should be left alone. Their def SlotIndex doesn't point
to anything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 20:59:29 +00:00
Matt Beaumont-Gay
a5b51f5694 Silence unused variable warning in -asserts build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 20:54:11 +00:00
Jakob Stoklund Olesen
bf60aa9db5 Eliminate the VNInfo::hasPHIKill() flag.
The only real user of the flag was removeCopyByCommutingDef(), and it
has been switched to LiveIntervals::hasPHIKill().

All the code changed by this patch was only concerned with computing and
propagating the flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 20:19:44 +00:00
Jakob Stoklund Olesen
0ab7103e06 Make the hasPHIKills flag a computed property.
The VNInfo::HAS_PHI_KILL is only half supported. We precompute it in
LiveIntervalAnalysis, but it isn't properly updated by live range
splitting and functions like shrinkToUses().

It is only used in one place: RegisterCoalescer::removeCopyByCommutingDef().

This patch changes that function to use a new LiveIntervals::hasPHIKill()
function that computes the flag for a given value number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161254 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 20:10:24 +00:00
Jakob Stoklund Olesen
3cd9f572ed Delete dead function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161242 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 15:21:21 +00:00
Jakob Stoklund Olesen
bc8d827b2b Don't delete dead code in TwoAddressInstructionPass.
This functionality was added before we started running
DeadMachineInstructionElim on all targets. It serves no purpose now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161241 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 15:11:57 +00:00
Bob Wilson
d49edb7ab0 Fall back to selection DAG isel for calls to builtin functions.
Fast isel doesn't currently have support for translating builtin function
calls to target instructions.  For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization.  Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel.  <rdar://problem/12008746>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 04:06:28 +00:00