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Author SHA1 Message Date
Bill Wendling
4e68054b20 More closely follow libgcc, which has code after the `ret' instruction to 
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141859 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 08:24:19 +00:00
Bill Wendling
1203fe7fc8 Revert r141854 because it was causing failures: 
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 07:48:07 +00:00
Bill Wendling
82222c20be Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141856 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 07:42:32 +00:00
Craig Topper
8ab1d1e900 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 07:09:14 +00:00
Jakob Stoklund Olesen
dee83c90bb Also inflate register classes around inline asm. 
Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.

This fixes PR11078.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141836 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 23:37:40 +00:00
Bill Wendling
f6fb7ed53c We need to verify that the machine instruction we're using as a replacement for 
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141830 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 23:03:40 +00:00
Lang Hames
68df750a4f Removed colons from some target datalayout strings in test, since they don't match the required format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141825 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 22:24:17 +00:00
Kevin Enderby
acbaecd4c8 Finish supporting cpp #file/line comments in assembler for error messages. So 
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141814 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 21:38:39 +00:00
Jim Grosbach
c66e7afcf2 Thumb2 assembly parsing and encoding for LDC/STC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 20:54:17 +00:00
Jim Grosbach
9f45754750 ARM encoding tests for STC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141787 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 17:36:13 +00:00
Jim Grosbach
9b8f2a0b36 ARM parsing and encoding for the <option> form of LDC/STC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 17:34:41 +00:00
Jakob Stoklund Olesen
1c062c24ab Fix -widen-vmovs liveness issues. 
When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 00:06:23 +00:00
Bob Wilson
b75e5d96dd Make this test more specific. There are 3 stats that matched "machine-licm". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141741 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 23:34:31 +00:00
Eric Christopher
6618a241f7 Add a new wrapper node for a DILexicalBlock that encapsulates it and a 
file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.

This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.

Part of rdar://10246360

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141729 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 22:59:11 +00:00
Jim Grosbach
2bd0118472 ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. 
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:55:36 +00:00
Bill Wendling
e575499d83 Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:40:47 +00:00
Cameron Zwarich
c055a8782e Fix PR11106 by correcting a typo that has been in the code for over a year. This 
would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:26:40 +00:00
Jim Grosbach
fbab2206cf Update test for r141704. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141705 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 20:18:50 +00:00
Devang Patel
2e35047947 Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 18:09:58 +00:00
Nadav Rotem
6fe4e51547 Add support for legalization of vector SHL/SRA/SRL instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141667 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 14:36:35 +00:00
Nick Lewycky
b1b8f5f7cd Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take 
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:58:11 +00:00
Craig Topper
a6f386b4cd Test case for X86 LZCNT instruction selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141652 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:47:01 +00:00
Craig Topper
37f2167f15 Add X86 LZCNT instruction. Including instruction selection support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:44:02 +00:00
Cameron Zwarich
66b20c4db6 Add a test for PR10565. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:10:37 +00:00
Cameron Zwarich
446d95224b Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's 
lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141646 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:10:30 +00:00
Bill Wendling
3606f75f35 Test simplification that Ana Pazos noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 04:43:15 +00:00
Craig Topper
29480fd798 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 04:34:23 +00:00
Nick Lewycky
7aabcb1fc0 Also create a shndx even if there are no symbols. This lets us test 
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 03:54:50 +00:00
NAKAMURA Takumi
b1044b042f test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak win32 hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 03:41:03 +00:00
Andrew Trick
204494149b Move replaceCongruentIVs into SCEVExapander and bias toward "expanded" 
IVs.

Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141633 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 02:28:51 +00:00
Akira Hatanaka
b58078be33 Test cases for 64-bit load and store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141631 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 01:52:31 +00:00
Lang Hames
eafc8192d1 Added a testcase for r141599, rdar://problem/10063881. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141628 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 01:32:10 +00:00
Bill Wendling
26e8ca34fe Add testcase for PR11107. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:26:57 +00:00
Devang Patel
db7334dbc5 Revert r141569 and r141576. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 23:18:02 +00:00
Bill Wendling
ef2c86f876 Reapply r141365 now that PR11107 is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:59:55 +00:00
Eli Friedman
dca62d53b7 Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:28:47 +00:00
Nick Lewycky
023bb15bea Add support for dumping section headers to llvm-objdump. This uses the same 
flags as binutils objdump but the output is different, not just in format but
also showing different sections. Compare its results against readelf, not
objdump.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 21:21:34 +00:00
Devang Patel
6b50bc9d88 If loop header is also loop exiting block then it may not be safe to hoist instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 20:32:03 +00:00
Nadav Rotem
a7934dd8e4 Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:31:45 +00:00
Devang Patel
9ac743a4ee Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:09:20 +00:00
Benjamin Kramer
a86a58695d X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:34:56 +00:00
Jakob Stoklund Olesen
a0ed0c0fcd Insert dummy ED table entries for pseudo-instructions. 
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:30:16 +00:00
Bill Wendling
eba564ceac Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:27:30 +00:00
Benjamin Kramer
5d53ff54c0 XFAIL tblgen tests on leak checkers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141533 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 13:09:59 +00:00
Bill Wendling
8129d21396 When getting the number of bits necessary for addressing mode 
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 07:24:23 +00:00
Craig Topper
da394041c4 Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen
ed74482704 Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. 
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141499 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 18:28:28 +00:00
Jakob Stoklund Olesen
a55f6575ae Add missing test case for r141410. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141498 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 18:06:54 +00:00
Andrew Trick
861a410cb6 Unit test for LSR phi reuse in r141442. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141472 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 02:34:51 +00:00
Michael J. Spencer
27781b78e1 llvm-objdump: Add relocation and archive support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 00:18:30 +00:00
Jim Grosbach
051fee0312 Enable ARM mode VDUP(scalar) tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141447 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:57:03 +00:00
Jim Grosbach
460a90540b ARM NEON assembly parsing and encoding for VDUP(scalar). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:56:00 +00:00
David Greene
a1b1b79be1 Remove Multidefs 
Multidefs are a bit unwieldy and incomplete.  Remove them in favor of
another mechanism, probably for loops.

Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 18:25:05 +00:00
Evan Cheng
7c1780c5fe High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141371 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 17:21:44 +00:00
Bob Wilson
6d2f9cec71 Reenable tail calls for iOS 5.0 and later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 17:17:49 +00:00
Bob Wilson
2fef4573df Reenable use of divmod compiler_rt functions for iOS 5.0 and later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 16:59:21 +00:00
Anton Korobeynikov
244455e6d6 Peephole optimization for ABS on ARM. 
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 16:15:08 +00:00
Duncan Sands
3f329cb781 Teach GVN to also propagate switch cases. For example, in this code 
switch (n) {
    case 27:
      do_something(x);
    ...
  }
the call do_something(x) will be replaced with do_something(27).  In
gcc-as-one-big-file this results in the removal of about 500 lines of
bitcode (about 0.02%), so has about 1/10 of the effect of propagating
branch conditions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141360 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 08:29:06 +00:00
Craig Topper
75fe5f3bab Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 07:02:24 +00:00
Craig Topper
1b526a98e3 Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 05:53:50 +00:00
Craig Topper
25f6dfd108 Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 05:35:38 +00:00
Jim Grosbach
bee5d2fac8 Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 22:04:05 +00:00
Jim Grosbach
7abb795635 Fix and clean up tests. Un-XFAIL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 21:32:50 +00:00
Jim Grosbach
d6f85098e1 Fix and clean up tests. Un-XFAIL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 21:28:30 +00:00
David Greene
2f0722c105 Make Test More Thorough 
Check that all ADD patters are processed.

Add a SUB test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141314 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 21:20:44 +00:00
Peter Collingbourne
5d5c0624d0 s/tblgen/llvm-tblgen/g in a few missed places, including the tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 13:39:59 +00:00
Torok Edwin
624c5edcd4 ocaml bindings: add llvm_ipo based on IPO.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 12:12:27 +00:00
Torok Edwin
0e68e90175 add more tests for the OCaml bindings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 12:12:12 +00:00
Craig Topper
7ea16b01fa Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 06:44:41 +00:00
Cameron Zwarich
d78ebe1e12 Remove a check from ARM shifted operand isel helper methods, which were blocking 
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 23:38:50 +00:00
David Greene
fd56d75396 Update Test for Multidefs 
Update the MultiPat.td test to create some defs via multidefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 22:42:48 +00:00
David Greene
e5d5cdf2e9 Add a Multidef Test 
Add a simple test for multidefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 22:42:47 +00:00
Eli Friedman
792860883e PR11061: Make simplifylibcalls fold strcmp("", x) correctly. 
While I'm here, fix the related issue with strncmp, add some actual tests for strcmp and strncmp, and start using StringRef::compare for constant folding instead of using strcmp/strncmp so that the optimized IR isn't dependent on the host's implementation of strcmp.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141227 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 22:27:16 +00:00
Jim Grosbach
e2999b4899 Revert 141203. InstCombine is looping on unit tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141209 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 20:44:29 +00:00
Rafael Espindola
11f1a8335e Check for the returns_twice attribute in callsFunctionThatReturnsTwice. This 
fixes PR11038, but there are still some cleanups to be done.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141204 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 20:05:13 +00:00
Jim Grosbach
30c1ff234d Update InstCombine worklist after instruction transform is complete. 
When updating the worklist for InstCombine, the Add/AddUsersToWorklist
functions may access the instruction(s) being added, for debug output for
example. If the instructions aren't yet added to the basic block, this
can result in a crash. Finish the instruction transformation before
adjusting the worklist instead.

rdar://10238555


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 20:05:00 +00:00
Dan Gohman
da5836572d Make this test less sensitive to codegen optimizations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141195 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 18:13:08 +00:00
Owen Anderson
2dbb46a0a0 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 17:16:40 +00:00
Duncan Sands
02b5e72ac6 GVN does simple propagation of conditions: when it sees a conditional 
branch "br i1 %x, label %if_true, label %if_false" then it replaces
"%x" with "true" in places only reachable via the %if_true arm, and
with "false" in places only reachable via the %if_false arm.  Except
that actually it doesn't: if value numbering shows that %y is equal
to %x then, yes, %y will be turned into true/false in this way, but
any occurrences of %x itself are not transformed.  Fix this.  What's
more, it's often the case that %x is an equality comparison such as
"%x = icmp eq %A, 0", in which case every occurrence of %A that is
only reachable via the %if_true arm can be replaced with 0.  Implement
this and a few other variations on this theme.  This reduces the number
of lines of LLVM IR in "GCC as one big file" by 0.2%.  It has a bigger
impact on Ada code, typically reducing the number of lines of bitcode
by around 0.4% by removing repeated compiler generated checks.  Passes
the LLVM nightly testsuite and the Ada ACATS testsuite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 14:28:49 +00:00
Duncan Sands
452c58f4c4 Generalize GVN's conditional propagation logic slightly: 
it's OK for the false/true destination to have multiple
predecessors as long as the extra ones are dominated by
the branch destination.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 14:17:01 +00:00
Andrew Trick
0c388583fb Missing test case for r141164. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141166 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 06:23:32 +00:00
Owen Anderson
2fec6c5ff1 Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 23:26:17 +00:00
Jim Grosbach
0ebefdf834 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 21:43:51 +00:00
Jim Grosbach
fdf6bb41a4 Un-XFAIL file. Comment out individual failing instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 21:16:42 +00:00
Jim Grosbach
20f8eb2fc1 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141115 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 20:52:57 +00:00
Jim Grosbach
e5c933848a Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 20:50:05 +00:00
Jim Grosbach
dc6c93531d Un-XFAIL file. Fix incorrect CHECK line. General format cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 20:46:49 +00:00
Jim Grosbach
100902c6da Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 20:42:35 +00:00
Jim Grosbach
0c0cf47ed5 Un-XFAIL file. Fix incorrect CHECK line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 20:42:09 +00:00
Jim Grosbach
62ea269b9a Un-XFAIL the file. Disable only the individual tests that aren't working yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 20:34:11 +00:00
David Greene
764b29e1c8 Test Operand Arguments 
Add a test to do list manipulation and pass the result as arguments.
This tests the new list element operator resolve code and provides an
example of using list manipulation to do instruction pattern
substitution.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 18:55:40 +00:00
Jim Grosbach
a02dfe7a6b Un-XFAIL the file. Disable only the individual tests that aren't working yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 18:43:15 +00:00
Jim Grosbach
36db6fbe57 Tidy up. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 17:49:45 +00:00
David Dean
8a567f1fb9 Fix PR9833/PR11054 (patch provided by Patrik Hägglund) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141092 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 16:26:41 +00:00
Craig Topper
6744a17dcf Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 06:30:42 +00:00
Andrew Trick
f143b79b78 LSR should avoid redundant edge splitting. 
This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 03:50:44 +00:00
Andrew Trick
d974ea22a5 Unit test for r140919, loop unroll heuristics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141049 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 00:07:02 +00:00
Jim Grosbach
3207e6c6b7 Tidy up. These tests are covered in the .s file tests now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:40:13 +00:00
Jim Grosbach
9d39036f62 ARM assembly parsing and encoding for VMOV immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:38:36 +00:00
Jim Grosbach
68259145d9 ARM parsing/encoding for VCMP/VCMPE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 22:30:24 +00:00
Akira Hatanaka
bbb47b320d Move CHECK after entry label. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141030 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:24:30 +00:00
Akira Hatanaka
43e43f7d8b Add support for 64-bit logical NOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:23:18 +00:00
Akira Hatanaka
2d57088ff0 Add support for 64-bit count leading ones and zeros instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:16:50 +00:00
Jim Grosbach
5cd5ac6ad4 ARM assembly parsing and encoding for VMRS/FMSTAT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:12:43 +00:00
Akira Hatanaka
dda4a07cd8 Add support for 64-bit divide instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:06:13 +00:00
Jim Grosbach
f8bf43ec99 Update test for 141010. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:58:08 +00:00
Akira Hatanaka
04d3762ff1 Add support for 64-bit integer multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:01:11 +00:00
Jim Grosbach
c82c101147 Tidy up a bit. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141010 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 17:59:31 +00:00
Craig Topper
581fe82c84 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 17:28:23 +00:00
Rafael Espindola
25456ef74c Add the returns_twice attribute to LLVM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141001 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 14:45:37 +00:00
Craig Topper
04c5be9f12 Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 08:14:29 +00:00
Craig Topper
04b0b34b3a Test updates that were supposed to go with r140993. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 07:53:59 +00:00
Nick Lewycky
1cbae18cf6 Reapply r140979 with fix! We never did get a testcase, but careful review of the 
logic by David Meyer revealed this bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140992 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 07:10:45 +00:00
Torok Edwin
48488a64fa attempt to fix ocaml bindings: landing pads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140991 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 06:41:46 +00:00
Nick Lewycky
4fcc80a486 Revert r140979 due to reports of bootstrap failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 05:14:59 +00:00
Nick Lewycky
8fde4f5842 Add one more case we compute a max trip count. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140979 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 01:03:57 +00:00
Craig Topper
82f131a017 Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 21:08:12 +00:00
Craig Topper
146c6d77f0 Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 16:56:09 +00:00
Nick Lewycky
11357d4f40 Add a new icmp+select optz'n. Also shows off the load(cst) folding added in 
r140966.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 10:37:37 +00:00
Craig Topper
846a2dcada Fix disassembling of INVEPT and INVVPID to take operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 21:20:14 +00:00
Craig Topper
e1b4a1a07e Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 19:54:56 +00:00
Bill Wendling
0676d2a04c Filecheck-ize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140904 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 23:40:29 +00:00
Bill Wendling
127f410c3a Add new line at end of file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 23:21:11 +00:00
Bill Wendling
e09b2a0d49 When inferring the pointer alignment, if the global doesn't have an initializer 
and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.

For instance, in file A.c:

   struct S s;

In file B.c:
   struct {
     // something long
   };
   extern S s;

   void foo() {
     struct S p = s;
     // ...
   }

this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 23:19:55 +00:00
David Greene
90b6e346ee Test More Complicated Lists 
Test of indexing lists of lists of lists works.  This also exercises
some operators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 20:59:52 +00:00
David Greene
f6c8cbba4e Test VarListElementInit:: resolveListElementReference 
Add a TableGen test to check if indexing lists of lists works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140883 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 20:59:51 +00:00
Akira Hatanaka
5773fd52ef Remove unnecessary checking of register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140872 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 19:18:24 +00:00
Akira Hatanaka
c7bafe9241 Add definitions of Mips64 rotate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 18:51:46 +00:00
Jim Grosbach
cbf676b3ba float comparison to double 'zero' constant can just be a float 'zero.' 
InstCombine was incorrectly considering the conversion of the constant
zero to be unsafe.

We want to transform:
define float @bar(float %x) nounwind readnone optsize ssp {
  %conv = fpext float %x to double
  %cmp = fcmp olt double %conv, 0.000000e+00
  %conv1 = zext i1 %cmp to i32
  %conv2 = sitofp i32 %conv1 to float
  ret float %conv2
}

Into:
define float @bar(float %x) nounwind readnone optsize ssp {
  %cmp = fcmp olt float %x, 0.000000e+00   ; <---- This
  %conv1 = zext i1 %cmp to i32
  %conv2 = sitofp i32 %conv1 to float
  ret float %conv2
}


rdar://10215914


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140869 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 18:45:50 +00:00
Jim Grosbach
6f09fcf5da ARM Darwin default relocation model is PIC. 
This matches clang, so default options in llc and friends are now closer to
clang's defaults.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 17:41:35 +00:00
Akira Hatanaka
d80c13bfed Check values of immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140860 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 17:19:21 +00:00
Duncan Sands
5bc93e782e Add forgotten tests that the cleanup flag is cleared if there 
is a catch-all landingpad clause.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140858 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 17:00:34 +00:00
Duncan Sands
0ad7b6e773 Inlining often produces landingpad instructions with repeated 
catch or repeated filter clauses.  Teach instcombine a bunch
of tricks for simplifying landingpad clauses.  Currently the
code only recognizes the GNU C++ and Ada personality functions,
but that doesn't stop it doing a bunch of "generic" transforms
which are hopefully fine for any real-world personality function.
If these "generic" transforms turn out not to be generic, they
can always be conditioned on the personality function.  Probably
someone should add the ObjC++ personality function.  I didn't as
I don't know anything about it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 13:12:16 +00:00
Akira Hatanaka
25a7d94e81 Mips64 shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140841 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 03:18:46 +00:00
Akira Hatanaka
f549ab7853 Mips64 arithmetic and logical instructions with one source register and 
immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140839 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 02:08:54 +00:00
Akira Hatanaka
a3defb07a0 Fill delay slot with useful instructions. Modified from Sparc's version of delay 
slot filler.

Patch by Reed Kotler at Mips Technologies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140825 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 23:52:13 +00:00
Dan Gohman
27e0666725 When eliminating unnecessary retain+autorelease on return values, 
handle the case where the retain is in a different basic block.
rdar://10210274.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140815 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 22:27:34 +00:00
Dan Gohman
597fece886 Don't eliminate objc_retainBlock calls on stack objects if the 
objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140814 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 22:25:23 +00:00
Akira Hatanaka
c0be26909f Mips64 arithmetic and logical instructions with two source registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140806 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 20:37:56 +00:00
Andrew Trick
0c01bc385a LSR: rewrite inner loops only. 
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140762 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 01:33:38 +00:00
Andrew Trick
03b08764d2 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140761 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 01:31:48 +00:00
Justin Holewinski
d57c1bc0b6 PTX: Add new patterns for bitconvert and any_extend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140753 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 01:13:12 +00:00
Evan Cheng
9b88d2d782 Tighten a ARM dag combine condition to avoid an identity transformation, which 
ends up introducing a cycle in the DAG.

rdar://10196296


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 23:16:31 +00:00
Eli Friedman
7d3e2b78c7 PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 21:00:25 +00:00
Justin Holewinski
d8e4ed2686 PTX: MC-ize the PTX back-end (patch 1 of N) 
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140697 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 14:32:04 +00:00
James Molloy
acad68da50 Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 14:21:38 +00:00
Andrew Trick
52164eaddc Test case for r140670: indvars should hoist sext. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140671 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 02:13:32 +00:00
Eli Friedman
e6fadced87 PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140666 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 00:34:27 +00:00
Jakob Stoklund Olesen
df4b35e3dd Remove X86-dependent stuff from SSEDomainFix. 
This also enables domain swizzling for AVX code which required a few
trivial test changes.

The pass will be moved to lib/CodeGen shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140659 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 23:50:46 +00:00
Jim Grosbach
25ddc2bf7e ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. 
Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799


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 2011-09-27 22:18:54 +00:00
NAKAMURA Takumi
5bac1146d9 test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 21:54:50 +00:00
Benjamin Kramer
a9390a4d5f Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit. 
If someone prefers %tmp42 to %42, run instnamer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 20:39:19 +00:00
Michael J. Spencer
9142ae2cf8 Add binary archive support to llvm-nm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140627 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 19:37:18 +00:00
Michael J. Spencer
98d0416fbf Unbreak tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140622 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 19:06:37 +00:00
Justin Holewinski
13e0c805a2 PTX: Add support for sitofp in backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140593 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 01:04:47 +00:00
Bill Wendling
d5520987d1 Split the landing pad basic block with the correct function. Also merge the 
split landingpad instructions into a PHI node.
PR11016


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 00:59:31 +00:00
Eli Friedman
139e6699c4 Last batch of test conversions to new atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 00:17:29 +00:00
Eli Friedman
184944acdf Convert a bunch more tests over to the new atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 23:15:09 +00:00
Owen Anderson
21733e8f80 Fix an incorrect decoder test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 23:08:34 +00:00
Owen Anderson
256e10f964 Remove incorrect testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140572 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 22:13:55 +00:00
Eli Friedman
47d3ee559a Convert more tests to new atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:36:10 +00:00
Eli Friedman
de412c391b Convert more tests over to the new atomic instructions. 
I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output.

The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:30:17 +00:00
Eli Friedman
ad2d46d0a5 Convert more tests over to the new atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 20:27:49 +00:00
Eli Friedman
236b71fc75 Upgrade a couple more tests to the new atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 20:15:56 +00:00
Eli Friedman
46cb5afdcd Enhance alias analysis for atomic instructions a bit. Upgrade a couple alias-analysis tests to the new atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 20:15:28 +00:00
Eli Friedman
28f7690e2d Fix this test so it doesn't fail on Mac. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 19:13:47 +00:00
Justin Holewinski
63602ed876 PTX: Fix detection of stack load/store vs. global load/store, as well as fix the 
printing of local offsets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140547 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 18:57:22 +00:00
James Molloy
439780eeae Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140539 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 17:40:42 +00:00
Justin Holewinski
6272c5d874 PTX: Add .align tests to stack object test file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 16:20:38 +00:00
Justin Holewinski
58788503b8 PTX: Fix some lingering issues with stack allocation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140535 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 16:20:34 +00:00
Justin Holewinski
c1d8fbd41a PTX: Unify handling of loads/stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140533 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 16:20:28 +00:00
David Meyer
6b97870746 Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 06:44:27 +00:00
David Meyer
8f418b11d2 PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 06:13:20 +00:00
Craig Topper
100d86ada5 Fix VEX decoding in i386 mode. Fixes PR11008. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 05:12:43 +00:00
Jakob Stoklund Olesen
51f0c76419 Only run MF.verify() with EXPENSIVE_CHECKS=1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140441 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-24 01:11:19 +00:00
Jakob Stoklund Olesen
5adc07ebe8 Verify that terminators follow non-terminators. 
This exposes a -segmented-stacks bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140429 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:45:39 +00:00
Eli Friedman
bde81d5be9 PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140428 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:41:57 +00:00
Owen Anderson
4d2a00147d Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:25:02 +00:00
Jakob Stoklund Olesen
11ebe3d7c1 Also match negative offsets for addrmode3 and addrmode5. 
Math is hard, and isScaledConstantInRange() always returned false for
negative constants.  It was doing unsigned division of negative numbers
before casting back to signed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140425 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:10:33 +00:00
Owen Anderson
1f24002ed4 Fix incorrect disassembly test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140423 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:05:54 +00:00
Owen Anderson
0781c1f700 Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:26:40 +00:00
Owen Anderson
31d485ec9a Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:07:25 +00:00
Justin Holewinski
75d809599b PTX: Handle function call return values 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140386 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 16:48:41 +00:00
Justin Holewinski
e953a64cb5 PTX: Start fixing function calls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 14:31:12 +00:00
Craig Topper
4da632e6e0 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 06:57:25 +00:00
Eli Friedman
7666c7e4d2 PR10989: Don't print .hidden on Windows. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 00:13:02 +00:00
Eli Friedman
a6176adc8a PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140355 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 23:41:28 +00:00
Dan Gohman
7b316c9327 Fix SimplifySelectCC to add newly created nodes to the DAGCombiner 
worklist, as it may be possible to perform further optimization on them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140349 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 23:01:29 +00:00
Duncan Sands
17470bee5f Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from 
floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 20:15:48 +00:00
Eli Friedman
d102a03b36 PR10987: add a missed safety check to isSafePHIToSpeculate in scalarrepl. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140327 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 18:56:30 +00:00
Justin Holewinski
4ddde0cba9 PTX: fixup test cases for register changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140311 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 16:45:51 +00:00
Craig Topper
adf01b3f18 Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-22 07:01:50 +00:00
Owen Anderson
6126870193 Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:53:44 +00:00
Owen Anderson
e136872970 Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:44:46 +00:00
Devang Patel
1dd4e56d55 Do not unnecessarily use AT_specification DIE because it does not add any value. 
Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140282 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:41:11 +00:00
Akira Hatanaka
4d77ae61f1 Remove +. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:43:48 +00:00
Akira Hatanaka
0b4a61548f Re-enable some of the disabled tests. Use FileCheck instead of grep to check 
output.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140263 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:36:30 +00:00
Nadav Rotem
d7e0ceaa59 add another testcase for pr10902 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140257 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:13:40 +00:00
Nadav Rotem
1147248e6f [VECTOR-SELECT] Address one of the bugs in pr10902. 
Vector SetCC result types need to be type-legalized.
This code worked before because scalar result types are known to be legal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140249 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 14:34:38 +00:00
Eric Christopher
eeef9e8180 Remove llvm-gcc and various compiler handling from llvm. It's not needed 
here anymore and has been migrated to the test-suite project.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140216 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 23:58:15 +00:00
Bill Wendling
4d1d86bac9 This test is completely invalid with the modern EH model. Delete. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140213 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 23:52:09 +00:00
Eli Friedman
79782fc864 Make sure IPSCCP never marks a tracked call as overdefined in SCCPSolver::ResolvedUndefsIn. If we do, we can end up in a situation where a function is resolved to return a constant, but the caller is marked overdefined, which confuses the code later. 
<rdar://problem/9956541> (again).



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 2011-09-20 23:28:51 +00:00
Bruno Cardoso Lopes
e97190fdf8 Add a DAGCombine for subvector extracts to remove useless chains of 
subvector inserts and extracts. Initial patch by Rackover, Zvi with
some tweak done by me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140204 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 23:19:33 +00:00
Bruno Cardoso Lopes
f4b841d4e2 Revert r140097, working on a better approach 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 23:19:29 +00:00
Bill Wendling
e3039de722 Update this test to the new EH model. 
Though I think it may be obsolete with the loop extract changes. And I couldn't
get the old version of LLVM to compile so that I could reduce this testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140197 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 22:29:43 +00:00
Bruno Cardoso Lopes
448d986858 The wrong relocation was being emitted for several SSSE3 instructions. 
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 21:39:21 +00:00
Evan Cheng
0d18174f0f Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 21:38:18 +00:00
Bill Wendling
9914f4a1f2 Update to new EH model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 20:21:16 +00:00
Owen Anderson
9d1a3dea15 Port over more Thumb2 encoding tests to decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 17:44:48 +00:00
NAKAMURA Takumi
6aaf0561ae test/CodeGen/X86/avx-minmax.ll: Unbreak Win32. 
On Windows x64, 128-bit arguments are not passed by reg but by indirect. eg.

maxpd:
        vmovapd (%rcx), %xmm0
        vmaxpd  (%rdx), %xmm0, %xmm0

FIXME: I don't care YMM on x64 for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140143 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 14:11:35 +00:00
Craig Topper
3699261d3f Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140140 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 07:38:59 +00:00
Andrew Trick
4815d56bb2 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 03:17:40 +00:00
Jim Grosbach
50172e77bc Nuke obsolete test file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140127 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 01:03:51 +00:00
Jim Grosbach
ac9c2aa8e1 Thumb2 assembly parsing and encoding for WFE/WFI/YIELD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:48:56 +00:00
Jim Grosbach
50f1c37123 Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:46:54 +00:00
Jim Grosbach
400b624e02 Thumb2 assembly parsing and encoding for USUB8/USUB16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140120 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:31:57 +00:00
Jim Grosbach
6053cd956f Thumb2 assembly parsing and encoding for USAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:30:45 +00:00
Jim Grosbach
653419fff0 Thumb2 assembly parsing and encoding for USAT16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140118 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:28:25 +00:00
Jim Grosbach
a7e5b01fe1 Thumb2 assembly parsing and encoding for USAT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:27:36 +00:00
Jim Grosbach
ae13ba7740 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:24:37 +00:00
Jim Grosbach
ad7d744456 Thumb2 assembly parsing and encoding for UQSAD8/USADA8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:23:51 +00:00
Jim Grosbach
73e019eb12 Thumb2 assembly parsing and encoding for UQSUB16/UQSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140112 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:20:44 +00:00
Jim Grosbach
ab3bf97fe0 Thumb2 assembly parsing and encoding for UQASX/UQSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:18:52 +00:00
Jim Grosbach
d7e2785ea8 Thumb2 assembly parsing and encoding for UQADD16/UQADD8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:15:03 +00:00
Bruno Cardoso Lopes
278cbfb3f5 Attempt to fix -mtriple=i686-{cygwin|mingw|win32} regressions. Nakamura, 
if this doesn't work, please provide more details.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:08:12 +00:00
Bill Wendling
9ead2c0609 Update to the new EH syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:50:34 +00:00
Bill Wendling
0b9a90932d Dramatically reduce this testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140101 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:47:06 +00:00
Bruno Cardoso Lopes
d91c6e058b Fix PR10949. Fix the encoding of VMOVPQIto64rr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:36:59 +00:00
Bruno Cardoso Lopes
97136c922e Based on the small opt Zvi's patch was trying to achieve, eliminate 
128-bit undef subvector insertion into a 256-bit vector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140097 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:36:50 +00:00
Jim Grosbach
9c6712721c Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:34:18 +00:00
Jim Grosbach
d5d0e81a4b Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:31:02 +00:00
Bill Wendling
a846585050 Revert r140083 and r140084 until buildbots can be fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140094 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:30:41 +00:00
Eric Christopher
f11750633d Remove llvmc and assorted build machinery for it. 
The problems that llvmc solved have largely been subsumed with the
tasks that the clang driver can accomplish, but llvmc lacks flexibility
and depends too heavily on the EOL'd llvm-gcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140093 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:22:41 +00:00
Jim Grosbach
9546de68aa Thumb2 assembly parsing and encoding for UHSUB16/UHSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140089 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:15:36 +00:00
Jim Grosbach
6729c48b94 Thumb2 assembly parsing and encoding for UHASX/UHSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:13:25 +00:00
Jim Grosbach
2c1ef5bac8 Thumb2 assembly parsing and encoding for UHADD16/UHADD8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140087 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:08:24 +00:00
Jim Grosbach
6451cbf79f Thumb2 assembly parsing and encoding for UBFX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140086 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:06:38 +00:00
Jim Grosbach
4032eaf98c Thumb2 assembly parsing and encoding for UASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140085 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:05:22 +00:00
Bill Wendling
39b4166d85 Update test to remove the 'unwind' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140084 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:01:11 +00:00
Jim Grosbach
11f23c1a72 Fix copy/past-o. Gotta remember that 'modify' step... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:53:00 +00:00
Jim Grosbach
661daa481e Thumb2 assembly parsing and encoding for UADD16/UADD8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:52:27 +00:00
Jim Grosbach
aa70695ef0 Thumb2 assembly parsing and encoding for TST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140080 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:46:06 +00:00
Jim Grosbach
7f739bee26 Thumb2 assembly parsing and encoding for TBB/TBH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:21:13 +00:00
Bill Wendling
463158fdb8 Replace uses of unwind with unreachable for the same effect. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140077 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:16:15 +00:00
Bill Wendling
803c9d33be Replace more uses of 'unwind' in the tests with calls to landingpad and 
resume. Note that some of these tests were basically dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140076 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:11:35 +00:00
Eli Friedman
17569fe05b Some additional tests for Thumb atomic load and store (which I somehow forgot to commit earlier). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:02:33 +00:00
Eli Friedman
c6b8ba8673 Fix an infinite loop where a transform in InstCombiner::visitAnd claims a construct is changed when it is not. (See included testcase.) 
Patch by Xiaoyi Guo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140072 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 21:58:15 +00:00
Jim Grosbach
1494c496e2 Thumb2 assembly parsing and encoding for TEQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 21:41:21 +00:00
Bruno Cardoso Lopes
97dc60b759 Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix 
PR10955 and PR10948.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 21:29:24 +00:00
Bill Wendling
f2d15db05b This testcase is dead. It doesn't inline even if I add the 'alwaysinline' 
attribute to the @foo function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140067 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 21:14:33 +00:00
Jim Grosbach
30b8b970e3 Remove FIXME. TBB/TBH are Thumb mode only instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140048 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 20:30:29 +00:00
Jim Grosbach
326efe5891 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 20:29:33 +00:00
Eli Friedman
c3d3598425 Fix a typo in the bitcode reader in the handling of atomic stores. Reported by David Meyer on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140040 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 19:41:28 +00:00
Owen Anderson
ecd1c55790 Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 18:07:10 +00:00
Jim Grosbach
8a8d28b039 Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 17:56:37 +00:00
Andrew Trick
24f48ece52 [indvars] Fix PR10946: SCEV cannot handle Vector IVs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 17:54:39 +00:00
Jim Grosbach
9883acd2a6 Thumb2 assembly parsing and encoding for SVC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 17:40:35 +00:00
Jim Grosbach
7649b0b8c7 Thumb2 assembly parsing and encoding for SUB(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 17:37:48 +00:00
Stepan Dyatkovskiy
76034c5f54 Added regression test for bug #10869. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 07:48:08 +00:00
Nadav Rotem
354efd88db setOperationAction should be done on the return value of the type, not the operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140001 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-18 14:57:03 +00:00
Nadav Rotem
91e43fd17a When promoting integer vectors we often create ext-loads. This patch adds a 
dag-combine optimization to implement the ext-load efficiently (using shuffles).

For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-18 10:39:32 +00:00
Benjamin Kramer
5778fef314 Apply Duncan's test fix from r139986 to the avx version of that test too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139992 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-18 00:41:38 +00:00
Duncan Sands
6bcd2196e5 Synthesize x86 max/min instructions also for vectors (i.e. produce 
maxps and maxpd).  This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it.  Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-17 16:49:39 +00:00
Owen Anderson
be290af0d8 Add a testcase for another corner-case decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139970 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 23:15:29 +00:00
Jim Grosbach
f67e8554bf Thumb2 assembly parsing and encoding for SUB(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:58:42 +00:00
Owen Anderson
89db0f690c Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:29:48 +00:00
Jim Grosbach
47313df81c Thumb2 assembly parsing and encoding for STRT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:27:12 +00:00
Jim Grosbach
18ceae2a70 Thumb2 assembly parsing and encoding for LDRHT/STRHT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139962 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:26:01 +00:00
Jim Grosbach
4a1d200c2f Thumb2 assembly parsing and encoding for STREX/STREXB/STREXH/STREXD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139961 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:22:07 +00:00
Jim Grosbach
e45451eea9 Thumb2 assembly parsing and encoding for STRD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139960 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:19:38 +00:00
Jim Grosbach
75d7428275 Simplify comment. There's no Thumb LDRD(register) encoding. That's ARM only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139959 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:18:42 +00:00
Owen Anderson
8a28bdcbcc Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:17:02 +00:00
Jim Grosbach
e041af7e0e Thumb2 assembly parsing and encoding for STRBT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139957 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:15:51 +00:00
Jim Grosbach
c71ed786c3 Thumb2 assembly parsing and encoding for STRH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139956 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:12:19 +00:00
Jim Grosbach
59c5076094 Remove test of undocumented format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139955 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:09:58 +00:00
Jim Grosbach
76ca6d9bcd Thumb2 assembly parsing and encoding for STRB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:09:19 +00:00
Jim Grosbach
2e7a94137b Shuffle a few more thumb2 tests to match the comment headings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139952 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:01:18 +00:00
Jim Grosbach
5320b40d9e Thumb2 tests for STR(literal), STR(register) and STR pre/post indexed immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139951 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:59:13 +00:00
Jim Grosbach
0bb7c6e8d6 Shuffle a few tests around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139950 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:57:10 +00:00
Owen Anderson
705b48ff86 Fix disassembly of Thumb2 LDRSH with a #-0 offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:08:33 +00:00
Jim Grosbach
642caea2c6 Thumb2 assembly parsing and encoding for STR(immediate). 
Add aliases for STRB/STRH while there. Tests forthcoming for those.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139942 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:06:12 +00:00
Jim Grosbach
36343d85cd Thumb2 assembly parsing and encoding for STMDB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139940 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 20:58:38 +00:00
Jim Grosbach
8213c96655 Thumb2 assembly parsing and encoding for STMIA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 20:50:13 +00:00
Jim Grosbach
3335029b1f Thumb2 assembly parsing and encoding for SSUB16/SSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139931 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:52:36 +00:00
Jim Grosbach
50bd470d85 Thumb2 assembly parsing and encoding for SSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:37:10 +00:00
Jim Grosbach
9f4ddb3efa Thumb2 assembly parsing and encoding for SSAT16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:33:22 +00:00
Jim Grosbach
b105b997a4 Thumb2 assembly parsing and encoding for SSAT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139926 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:32:30 +00:00
Jim Grosbach
05ec8f7ac9 Thumb2 assembly parsing and encoding for SRS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:25:22 +00:00
Jim Grosbach
dea8412784 Thumb2 assembly parsing and encoding for SMMUSD/SMUSDX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139923 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:08:48 +00:00
Jim Grosbach
41ca75bed0 Thumb2 assembly parsing and encoding for SMMULWB/SMULWT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:07:18 +00:00
Jim Grosbach
3443ed525a Thumb2 assembly parsing and encoding for SMMULL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:05:48 +00:00
Jim Grosbach
3c4c879695 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:03:00 +00:00
Jim Grosbach
d727148c21 Thumb2 assembly parsing and encoding for SMULBB/SMULBT/SMULTB/SMULTT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139918 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:02:36 +00:00
Jim Grosbach
c9592cbad5 Thumb2 assembly parsing and encoding for SMMUAD'dib. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139917 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 17:58:21 +00:00
Jim Grosbach
f3578a8497 Thumb2 assembly parsing and encoding for SMMUL/SMMULR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139916 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 17:56:06 +00:00
Owen Anderson
a610d619ce Port over more Thumb2 assembly tests to disassembly tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139915 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 17:56:04 +00:00
Owen Anderson
1070278efa Port over more Thumb2 assembly tests to disassembly tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139912 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 17:22:48 +00:00
Jim Grosbach
cb574bb71e Thumb2 assembly parsing and encoding for SMMLS/SMMLSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139911 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 17:16:55 +00:00
Jim Grosbach
3b61d23297 Thumb2 assembly parsing and encoding for SMMLA/SMMLAR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 17:15:18 +00:00
Jim Grosbach
7ff2472b82 Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139909 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 17:10:44 +00:00