6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-23 01:30:19 +00:00
Code Issues Projects Releases Wiki Activity
50,883 Commits 39 Branches 0 Tags 277 MiB
65a3788694
Commit Graph

7746 Commits

Author SHA1 Message Date
Anton Korobeynikov
f4ef8c9045 Add testcases for reg-mem arithemtics added recently 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78214 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 17:04:32 +00:00
Anton Korobeynikov
9e155d61da Convert bswap test to filecheck, add more test entries & convert stuff to filecheck 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78212 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:50:53 +00:00
Dan Gohman
22f7d57dde Fix a bug in the PIC16 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78211 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:46:43 +00:00
Dan Gohman
c61954b57c Change these tests to use function attributes rather than special llc 
command-line options.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78204 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:37:27 +00:00
Chris Lattner
299a8141e3 checking in broken testcases is not such a good idea. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78201 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 16:04:18 +00:00
Sanjiv Gupta
96a0a02119 Quite a few tests crashed in llc after 78142. This is just one of them. I hope to add a few more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78198 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 15:52:14 +00:00
Evan Cheng
6248fa4529 Disable stack coloring with register for now. It's not able to set kill markers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78179 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 07:26:17 +00:00
Evan Cheng
9cd1632814 Another nasty coalescer bug (is there another kind): 
After coalescing reg1027's def and kill are both at the same point:
 %reg1027,0.000000e+00 = [56,814:0)  0@70-(814)

bb5:
60   %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
68   %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
76   t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
84   %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
96   t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>

Do not remove the kill marker on t2LDRi12.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78178 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 07:05:41 +00:00
Dan Gohman
40a0b2c305 Revert changes accidentally committed along with r78163. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78165 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 05:38:13 +00:00
Dan Gohman
c3c9c486e4 Teach X86FastISel how to handle CCValAssign::BCvt, which is used for 
MMX arguments. This fixes PR4684.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78163 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 05:33:42 +00:00
Andreas Bolka
831f6f6d2a ZIV tester for LDA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78157 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 04:26:05 +00:00
Andreas Bolka
7cf85030f4 Fix LDA testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78153 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 04:03:29 +00:00
Evan Cheng
6ade93bbdc Turn some insert_subreg, extract_subreg, subreg_to_reg into implicit_defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78151 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 03:53:14 +00:00
Evan Cheng
b018a1e5a7 One more. Transfer kill of the larger register when lowering an EXTRACT_SUBREG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78145 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 02:25:11 +00:00
Evan Cheng
a72dfb522d One more place where subreg lowering forgot to transfer undefness. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78144 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 01:57:22 +00:00
Dan Gohman
98ca4f2a32 Major calling convention code refactoring. 
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 01:29:28 +00:00
Evan Cheng
518ad1a880 If the insert_subreg source is <undef>, insert an implicit_def instead of a copy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78141 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 01:29:24 +00:00
Evan Cheng
35d6c41fde Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 23:47:55 +00:00
Evan Cheng
57035994f7 Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78113 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 22:22:58 +00:00
Bob Wilson
42cdcb9a86 Convert more Neon tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78111 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 22:01:41 +00:00
Bob Wilson
ad5312ad70 Convert a few Neon tests to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78108 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 21:33:22 +00:00
Jakob Stoklund Olesen
323e7d32ab Clean up the handling of two-address operands in RegScavenger. 
This fixes PR4528.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78107 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 21:30:30 +00:00
Evan Cheng
9e7a312391 Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 21:12:13 +00:00
David Goodwin
53e4471adc Add NEON single-precision FP support for fabs and fneg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 20:39:05 +00:00
Jakob Stoklund Olesen
ded2e3b0d0 LowerSubregsInstructionPass::LowerExtract should not extend the live range of registers. 
When LowerExtract eliminates an EXTRACT_SUBREG with a kill flag, it moves the
kill flag to the place where the sub-register is killed. This can accidentally
overlap with the use of a sibling sub-register, and we have trouble.

In the test case we have this code:

Live Ins: %R0 %R1 %R2
	%R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
	%R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0]
	%R1L<def> = EXTRACT_SUBREG %R1<kill>, 1
	%R0L<def> = EXTRACT_SUBREG %R0<kill>, 1
	%R0H<def> = ADD16 %R2H<kill>, %R2L<kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def>

subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
subreg: eliminated!
subreg: killed here: %R0H<def> = ADD16 %R2H, %R2L, %R2<imp-use,kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def>

The kill flag on %R2 is moved to the last instruction, and the live range overlaps with the definition of %R2H:

*** Bad machine code: Redefining a live physical register ***
- function:    f
- basic block:  0x18358c0 (#0)
- instruction: %R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0]
Register R2H was defined but already live.

The fix is to replace EXTRACT_SUBREG with IMPLICIT_DEF instead of eliminating
it completely:

subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1
subreg: replace by: %R2L<def> = IMPLICIT_DEF %R2<kill>

Note that these IMPLICIT_DEF instructions survive to the asm output. It is
necessary to fix the stack-color-with-reg test case because of that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78093 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 20:01:11 +00:00
Evan Cheng
3425df44b5 In thumb mode, r7 is used as frame register. This fixes pr4681. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78086 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 18:46:17 +00:00
David Goodwin
b84f3d427c Match common pattern for FNMAC. Add NEON SP support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78085 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 18:44:29 +00:00
David Goodwin
831b500ec1 Improve tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78083 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 18:11:59 +00:00
David Goodwin
42a83f2d15 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 17:53:06 +00:00
Evan Cheng
7d35249e89 Fix PR4528. This scavenger assertion is too strict. The two-address value is 
killed by another operand.

There is probably a better fix. Either 1) scavenger can look at other operands, or
2) livevariables can be smarter about kill markers. Patches welcome.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78072 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 16:52:44 +00:00
Chris Lattner
ec409759e9 enhance codegen to put 16-bit character strings into the 
__TEXT,__ustring section on darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78068 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 16:27:13 +00:00
Chris Lattner
1850e5add1 Add support emiting for 2/4 byte mergable strings to the ".rodata.str*" 
section on ELF targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78066 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 16:13:09 +00:00
Devang Patel
d5ac40457b Use separate ValueList for metadata. 
This fixes PR4666.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78056 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 06:00:18 +00:00
Devang Patel
912538beca Revert recent bitcode writer patches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78053 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 05:01:35 +00:00
Bill Wendling
27d703b30f llvm-gcc checks the static asm variable is valid in ValidateRegisterVariable. Make this work for PPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78051 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 04:48:31 +00:00
Bill Wendling
2822e174f6 Fixed now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 03:46:54 +00:00
Rafael Espindola
c4f8861af3 Add test for PR4678 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78040 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 03:44:37 +00:00
Bill Wendling
d9a05eb97e XFAIL for the moment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78038 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 03:40:47 +00:00
Devang Patel
d701aa7bed Constants and Metadata share ValueList. This means they must be emitted interleaved (using appropriate BLOCK_IDs) otherwise ValuePtrs index gets out of sync. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78033 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 02:26:56 +00:00
Evan Cheng
fa2ea1a8cf Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 01:41:15 +00:00
Dan Gohman
8bb9c92892 Add -disable-output. Thanks Bill! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78009 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 22:24:22 +00:00
Dan Gohman
43ee5f7c08 Add a new Constant::getIntegerValue helper function, and convert a 
few places in InstCombine to use it, to fix problems handling pointer
types. This fixes the recent llvm-gcc bootstrap error.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78005 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 22:07:33 +00:00
Bob Wilson
a6d658620f Lower CONCAT_VECTOR during legalization instead of matching it during isel. 
Add a testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 20:36:38 +00:00
Jakob Stoklund Olesen
980daea857 Fix Bug 4657: register scavenger asserts with subreg lowering 
When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG
instriction because it is an identity copy, make sure that the same registers
are alive before and after the elimination.

When the super-register is marked <undef> this requires inserting an
IMPLICIT_DEF instruction to make sure the super register is live.

Fix a related bug where a kill flag on the inserted sub-register was not transferred properly.

Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77989 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 20:08:18 +00:00
Evan Cheng
eed0ff147c Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77967 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 08:41:59 +00:00
Anton Korobeynikov
cf6b739d3d Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77962 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 08:12:53 +00:00
Rafael Espindola
8d632c1e98 Use movd instead of movq 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77956 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 05:21:05 +00:00
Daniel Dunbar
3c2d4bf97f Pass target triple string in to TargetMachine constructor. 
This is not just a matter of passing in the target triple from the module;
currently backends are making decisions based on the build and host
architecture. The goal is to migrate to making these decisions based off of the
triple (in conjunction with the feature string). Thus most clients pass in the
target triple, or the host triple if that is empty.

This has one important change in the way behavior of the JIT and llc.

For the JIT, it was previously selecting the Target based on the host
(naturally), but it was setting the target machine features based on the triple
from the module. Now it is setting the target machine features based on the
triple of the host.

For LLC, -march was previously only used to select the target, the target
machine features were initialized from the module's triple (which may have been
empty). Now the target triple is taken from the module, or the host's triple is
used if that is empty. Then the triple is adjusted to match -march.

The take away is that -march for llc is now used in conjunction with the host
triple to initialize the subtarget. If users want more deterministic behavior
from llc, they should use -mtriple, or set the triple in the input module.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77946 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 04:03:51 +00:00
Rafael Espindola
def390a30a Use movq to move 64 bits in and out of mmx registers. 
Fixes PR4669



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 02:45:34 +00:00
Evan Cheng
a8e8984ee4 Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77939 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 02:38:06 +00:00
Andreas Bolka
c20a6fd8ce Expand LDA testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77926 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 23:28:14 +00:00
Richard Osborne
d558ea5e0a Add extra SEXT pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77920 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 22:45:24 +00:00
Jakob Stoklund Olesen
1391cc19d0 Remove unneeded intrinsics from Blackfin backend. 
__builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end.

__builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load.

We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77917 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 21:49:05 +00:00
Jakob Stoklund Olesen
b36eb9df20 Fix issue in regscavenger when scavenging a callee-saved register that has not been spilled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77912 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 20:29:41 +00:00
Jakob Stoklund Olesen
ece4818516 Never add a kill flag to a constrained physical register in a two-addr instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77906 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 19:13:03 +00:00
Jakob Stoklund Olesen
0e6a4efdd4 Scavenger asserts. 
Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier.
Allow redefinition of a sub-register of a live register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77904 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 18:28:41 +00:00
Jakob Stoklund Olesen
6b30f5c867 Add some basic blackfin intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77903 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 18:28:11 +00:00
Jakob Stoklund Olesen
63cc527fbc Inline assembly support for Blackfin. 
We use the same constraints as GCC, including those that are slightly insane for inline assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77899 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 17:39:17 +00:00
Jakob Stoklund Olesen
d950941e13 Analog Devices Blackfin back-end. 
Generate code for the Blackfin family of DSPs from Analog Devices:

  http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html
  
We aim to be compatible with the exsisting GNU toolchain found at:

  http://blackfin.uclinux.org/gf/project/toolchain
  
The back-end is experimental.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 17:32:10 +00:00
Evan Cheng
b9bcdd9ca4 Test both darwin and linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77852 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 02:54:34 +00:00
Chris Lattner
f9f1adbcbb switch to filecheck format 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77841 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 00:32:26 +00:00
Chris Lattner
c19ee610f6 fix a problem Eli noticed where we would compile the attached ptrtoint 
to:

.quad X

even on a 32-bit system, where X is not 64-bits.  There isn't much that
we can do here, so we just print:

.quad	((X) & 4294967295)

instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77818 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 22:25:12 +00:00
Dan Gohman
5f9b69f345 Add nounwind to this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77792 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 19:11:04 +00:00
Eli Friedman
f67e84edef Hack to make this test work on platforms which aren't Macs. Fixing this 
myself because I'm getting tired of seeing the red buildbots, which have 
been red since 5:30PM PDT last night.

Proposed supplement to developer policy: committers should make sure to 
be around to watch for buildbot failures after committing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77785 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 16:37:18 +00:00
Evan Cheng
25f7cfc3cc Workaround a couple of Darwin assembler bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 06:13:52 +00:00
Daniel Dunbar
54f9759404 Avoid a problem with ulimit on Solaris & friends, patch by Edward O'Callaghan! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 03:37:54 +00:00
Evan Cheng
13f8b36205 Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 01:43:45 +00:00
Daniel Dunbar
a6b3c5db2e llvm-mc: More quoted identifier support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77761 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 00:48:30 +00:00
Evan Cheng
b620724e61 Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 00:16:10 +00:00
Daniel Dunbar
35ee93b791 llvm-mc: Add -triple, and fix some typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77750 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 23:13:12 +00:00
Daniel Dunbar
ad4555c549 llvm-mc: Fix .s output to quote section & symbol names when necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77749 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 23:04:32 +00:00
Daniel Dunbar
c09e411102 llvm-mc: A few more parsing / match tweaks. 
- Operands which are just a label should be parsed as immediates, not memory
   operands (from the assembler perspective).

 - Match a few more flavors of immediates.

 - Distinguish match functions for memory operands which don't take a segment
   register.

 - We match the .s for "hello world" now!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77745 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 22:22:54 +00:00
David Greene
bef8768bd0 Simplify operand padding by keying off tabs in the asm stream. If 
padding is disabled, tabs get replaced by spaces except in the case of
the first operand, where the tab is output to line up the operands after
the mnemonics.

Add some better comments and eliminate redundant code.

Fix some testcases to not assume tabs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77740 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 21:57:10 +00:00
Daniel Dunbar
76c4d7696c llvm-mc: Support quoted identifiers. 
- Uses MCAsmToken::getIdentifier which returns the (sub)string representing the
   meaningfull contents a string or identifier token.

 - Directives aren't done yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77739 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 21:55:09 +00:00
Daniel Dunbar
022e2a84a8 llvm-mc/X86: Sketch match functions for immediates and memory operands. 
Also, change scale value to always be 1 when unspecified to machine MachineInst
encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 20:53:16 +00:00
Eli Friedman
d21e55abce PR4662: Fix a crash introduced by the recent LLVMContext changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77716 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 19:36:47 +00:00
Chris Lattner
a87dea4f8c switch off of 'Section' onto MCSection. We're not properly using 
MCSection subclasses yet, but this is a step in the right direction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:48:30 +00:00
Evan Cheng
ff6ab17619 Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:35:56 +00:00
Chris Lattner
82987bfe9b fix PR4650: we only track sizes for certain objects, so only put something 
into the mergable section if it is one of our special cases.  This could
obviously be improved, but this is the minimal fix and restores us to the
previous behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77679 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 16:17:13 +00:00
Daniel Dunbar
b6804e9126 Add this test back, the check pattern was too strict. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77662 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 03:11:49 +00:00
Daniel Dunbar
527695dd66 Remove this test while I figure out why it is failing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77659 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 02:46:36 +00:00
Daniel Dunbar
a027d222e1 llvm-mc: Match a few X86 instructions. 
- This is "experimental" code, I am feeling my way around and working out the
   best way to do things (and learning tblgen in the process). Comments welcome,
   but keep in mind this stuff will change radically.

 - This is enough to match "subb" and friends, but not much else. The next step is to
   automatically generate the matchers for individual operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77657 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 02:32:59 +00:00
Evan Cheng
ee42fd309e When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 23:29:25 +00:00
Devang Patel
b3f7c61d9c Do not use abbrev while writing NamedMDNode name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77637 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 23:06:35 +00:00
David Goodwin
8f65253236 Darwin assembler now recognizes "orn", so remove workaround. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 21:51:41 +00:00
David Goodwin
7c92f3ac99 Darwin assembler now supports "rrx", so remove workaround. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 21:38:40 +00:00
David Goodwin
d8c95b5ac2 Cleanup and include code selection for some frame index cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 18:56:48 +00:00
Evan Cheng
37b7387da9 Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77582 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 08:33:02 +00:00
Dan Gohman
a4714e025d Add a new register class to describe operands that can't be SP, 
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77565 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 01:56:29 +00:00
Evan Cheng
8770f747a9 tbb / tbh instructions only branch forward, not backwards. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77522 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 23:20:20 +00:00
Evan Cheng
d600522608 Add VFP3 D registers to the DPR register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77521 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 23:03:41 +00:00
Devang Patel
aa99314251 Read and write NamedMDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 22:34:41 +00:00
Daniel Dunbar
473955f439 Fix PR4645 which was fallout from the fix for PR4641. 
- Call RAUW to delete all instructions (this is a patch from Nick Lewycky).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77512 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 22:00:43 +00:00
Evan Cheng
b7d3ed05d9 xfail for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77478 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 17:40:28 +00:00
Bob Wilson
b7d0c90c44 Change Neon VLDn intrinsics to return multiple values instead of really 
wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 16:39:22 +00:00
Nick Lewycky
02a0d0eb24 Just discard the output, no need to turn it back into text. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77439 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 06:14:52 +00:00
Chris Lattner
45ce89ba08 don't dump .bc file to stdout, and simplify this to a trivial testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77436 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 05:32:07 +00:00
Chris Lattner
b8f396bdbb fix PR4584 with a trivial patch now that the pieces are in place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77434 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 05:20:33 +00:00
Nick Lewycky
0efa921736 Bulk erasing instructions without RAUWing them is unsafe. Instead, break them 
into a new BB that has no predecessors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77433 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 05:17:50 +00:00
Evan Cheng
5657c01949 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 02:18:14 +00:00
Eric Christopher
c841fe5fd1 Add a couple more tests for the ptest intrinsics to make sure we're 
grabbing them all correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77413 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 00:51:15 +00:00
Eric Christopher
71c6753d03 Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower 
to ptest instruction plus setcc. Revamp ptest instruction. Add test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 00:28:05 +00:00
Andreas Bolka
7b43f5cdd1 Slightly reformat LDA tests to ease grepping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77398 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 23:40:40 +00:00
Evan Cheng
e7c329bf4b In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:53:24 +00:00
David Goodwin
6340632d3b Remove support for ORN to workaround <rdar://problem/7096522>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:51:25 +00:00
David Goodwin
5743854f47 Add workaround for <rdar://problem/7098328>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77340 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 18:15:38 +00:00
Chris Lattner
3e23d42dee fix testcase for previous patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77338 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 18:04:18 +00:00
Chris Lattner
bf15e433b9 Fix PR4639, a ELF-TLS regression from some of my refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77336 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 17:57:51 +00:00
David Goodwin
3583df7676 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77329 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 17:06:49 +00:00
Evan Cheng
bae20a6353 tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77305 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 07:38:35 +00:00
Evan Cheng
6495f63945 - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 05:48:47 +00:00
Dan Gohman
d6aa02de10 Teach instcombine to respect and preserve inbounds. Add inbounds 
to a few tests where it is required for the expected transformation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77290 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 01:40:03 +00:00
David Goodwin
1f0962756d ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77275 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 23:34:12 +00:00
Daniel Dunbar
f9507ffa5b llvm-mc: Implement .abort fully in the front end 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77272 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 23:20:52 +00:00
Dan Gohman
dd8004dc73 Add a new keyword 'inbounds' for use with getelementptr. See the 
LangRef.html changes for details.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77259 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 21:53:46 +00:00
David Goodwin
af0d08d55c Add ".w" suffix for wide thumb-2 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77199 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 16:31:55 +00:00
Sanjiv Gupta
c3ee7960d9 Test case to check that separate section is created for a global variable specified with section attribute. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77195 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 16:20:41 +00:00
Dan Gohman
59858cf792 Change the assembly syntax for nsw, nuw, and exact, putting them 
after their associated opcodes rather than before. This makes them
a little easier to read.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77194 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 16:11:46 +00:00
Chris Lattner
a759135168 update testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77192 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 15:52:58 +00:00
Chris Lattner
abb477f663 put normal data into .data instead of .data.rel on elf systems. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77116 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 03:06:11 +00:00
Chris Lattner
30c4a3b9a8 finish simplifying DarwinTargetAsmInfo::SelectSectionForGlobal 
for now.  Make the section switching directives more consistent
by not including \n and including \t for them all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77107 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 01:24:18 +00:00
Chris Lattner
e3577da6d9 simplify DarwinTargetAsmInfo::SelectSectionForGlobal a bit 
and make it more aggressive, we now put:

const int G2 __attribute__((weak)) = 42;

into the text (readonly) segment like gcc, previously we put
it into the data (readwrite) segment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77104 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 00:51:36 +00:00
Bob Wilson
8bb9e48752 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 00:39:34 +00:00
Chris Lattner
10cf6a6a4b add the most expedient hack to fix PR4619, along with a testcase. 
Thanks to Rafael for the great example.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77083 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 17:57:37 +00:00
Dan Gohman
19378d622e When attempting to sign-extend an addrec by interpreting 
the step value as unsigned, the start value and the addrec
itself still need to be treated as signed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77078 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 16:03:30 +00:00
Chris Lattner
6dc82863a6 remove this test. It is currently failing because we now emit the string 
on darwin with ".cstring" instead of ".section  __TEXT,__cstring".  They
are the same and the former is better.  Remove this because this is no longer
magic pixie dust in the frontend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77055 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 07:31:51 +00:00
Dan Gohman
eb490a7aa3 Teach ScalarEvolution to make use of no-overflow flags when 
analyzing add recurrences.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77034 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 01:22:26 +00:00
Evan Cheng
b140f4907c I've lost my mind. PR4572 has not been fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77031 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 01:11:46 +00:00
Evan Cheng
66ac53165e Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:33:29 +00:00
Evan Cheng
b2fa93dc1c Remove a duplicated test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77020 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:24:40 +00:00
Evan Cheng
caca2b659f Forgot this test earlier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77007 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 22:42:45 +00:00
Evan Cheng
0bc116192d Fix these tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 22:42:22 +00:00
Eli Friedman
4e9bac3769 Fix assert assembling zero-argument constant GEP. 
There's still a strict-aliasing violation here, but I don't feel like 
dealing with that right now...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77005 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 21:56:17 +00:00
Eric Christopher
a1a491c094 Move insertps tests to sse41 combo test file, convert to filecheck 
format and add an extract/insert test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76994 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 19:24:26 +00:00
Evan Cheng
f631a68cf8 Convert a test to FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76954 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 06:01:46 +00:00
Chris Lattner
013e6b6309 Remove SectionKind::Small*. This was only used on mips, and is apparently 
a sad mistake that is regretted. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76935 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 03:11:51 +00:00
Richard Osborne
e23e0976c7 Add tests for handling of globals and tls on the XCore. These currently fail 
but pass when run against r76652.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76923 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:38:20 +00:00
Dan Gohman
d2cb3d2c32 Remove the IA-64 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76920 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:30:09 +00:00
Evan Cheng
eee839dd3c Thumb2 does not allow the use of "pc" register as part of the load / store address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76909 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 23:09:51 +00:00
Evan Cheng
d3d9d66dd2 Fix up ARM constant island pass for Thumb2. 
Also fixed up code to fully use the SoImm field for ADR on ARM mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76890 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 18:27:47 +00:00
Andreas Bolka
0dcde10f5e FileCheck'ize and expand LDA testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76880 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 15:56:53 +00:00
Chris Lattner
3cd526136a testcase for PR4590 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76868 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 06:07:59 +00:00
Chris Lattner
7b45fc51aa merge vector-casts-0.ll into vector-casts.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76864 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 05:33:39 +00:00
Chris Lattner
f98d253bc5 Make some existing optimizations that would only trigger on scalars 
also apply to vectors.  This allows us to compile this:

#include <emmintrin.h>
__m128i a(__m128 a, __m128 b) { return a==a & b==b; }
__m128i b(__m128 a, __m128 b) { return a!=a | b!=b; }

to:

_a:
	cmpordps	%xmm1, %xmm0
	ret
_b:
	cmpunordps	%xmm1, %xmm0
	ret

with clang instead of to a ton of horrible code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76863 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 05:32:17 +00:00
Chris Lattner
e5f6bfffe7 convert a test to filecheck format. This fixes an endemic problem 
with negative tests: this test wasn't checking what it thought it was
because it was grepping .bc, not .ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76861 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 05:27:48 +00:00
Chris Lattner
e6dab05b03 rename test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76860 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 05:25:12 +00:00
Chris Lattner
d58fb250bb merge one more sse41 test into sse41.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76853 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:49:39 +00:00
Chris Lattner
052876957c merge another sse41 test into sse41.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76852 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:43:48 +00:00
Chris Lattner
ca6883b007 merge sse41-pmovx.ll into sse41.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:39:09 +00:00
Chris Lattner
5fe2b03779 change a test to run in filecheck style. Rename it to be a general 
dumping ground of various SSE4.1 tests, since filecheck can reasonably
handle them all in one file.  Generalize it to check x86-64 stuff as
well since it has a different ABI (a convenient way to test both the 
reg and mem forms of these instructions).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76848 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 04:33:02 +00:00
Eric Christopher
1e5cdea9d7 Support insertps via the intrinsic and add a couple of simple 
testcases to make sure it's being generated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 02:22:41 +00:00
Eric Christopher
3091719b90 Add test for pinsrd and pinsrb instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76840 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 01:58:04 +00:00
Devang Patel
104cf9e02b Derive MDNode from MetadataBase instead of Constant. Emit MDNodes into METADATA_BLOCK in bitcode file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76834 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 01:07:34 +00:00
Dan Gohman
608ad24ac3 Revert r75663 (and r76805), as it is causing regressions on powerpc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76823 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 00:09:46 +00:00
Dan Gohman
41d0b9d952 x86 isel tweak: use lea (%reg,%reg) instead of lea (,%reg,2). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76817 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 23:26:55 +00:00
Dan Gohman
08d012eba4 Rename the new unsigned and signed keywords to nuw and nsw, 
which stand for no-unsigned-wrap and no-signed-wrap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76810 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:44:56 +00:00
Dan Gohman
1c88efff02 Add -march=ppc32 lines so that this test doesn't ever default to ppc64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76805 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:08:31 +00:00
Evan Cheng
eadf04992a Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:03:29 +00:00
Dan Gohman
784025039f Make the grep line in this test more specific, to avoid 
unintended matches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76802 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:02:42 +00:00
Evan Cheng
1e0c1588b1 Ignore undef uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76799 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 21:51:42 +00:00
Devang Patel
6dba7669e0 Remove empty test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76763 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 18:09:11 +00:00
Devang Patel
e54abc90fe Introduce MetadataBase, a base class for MDString and MDNode. 
Derive MDString directly from MetadataBase. 
Introduce new bitcode block to hold metadata.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76759 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 17:43:22 +00:00
Duncan Sands
ed4b2dc313 Revert commit 76707, it was breaking the llvm-gcc build 
on linux platforms.  The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76733 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 10:35:05 +00:00
Chris Lattner
828f704c10 set the ELF "small" flag on objects that end up in .rodata.cst4 consistently, 
updating a mips testcase to expect it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76707 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 00:41:56 +00:00
Dan Gohman
0f4b285a5b Replace the original ad-hoc code for determining whether (v pred w) implies 
(x pred y) with more thorough code that does more complete canonicalization
before resorting to range checks. This helps it find more cases where
the canonicalized expressions match.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76671 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 23:03:19 +00:00
Evan Cheng
47b1e2afd0 Remove a big test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76669 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 22:52:04 +00:00
Bob Wilson
b2f8806fdf Fix ocaml tests for 64-bit MacOS systems. LLVM is currently built 
as 32-bit code by default, and if gcc defaults to 64-bit code then ocamlc
requires a -cc "gcc -arch i386" option.  We were hardcoding -cc g++
and throwing away any other compiler options that were determined when
ocamlc was configured and built.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76658 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 21:56:46 +00:00
Evan Cheng
3ecadc816d Do not select tSXTB / tSXTH in thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 18:15:26 +00:00
Chris Lattner
74625023a8 convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76591 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 17:36:24 +00:00
Chris Lattner
99bd8bf8a2 add a testcase for the pic16 section handling stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76579 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 16:48:20 +00:00
Evan Cheng
5d885023fe Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76558 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 09:15:00 +00:00
Chris Lattner
634d61b135 remove a very large testcase for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76537 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 06:28:36 +00:00
Evan Cheng
d101a72d79 Fix a dagga combiner bug: avoid creating illegal constant. 
Is this really a winning transformation?
fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or                                                                              
                              (srl (and x, (shl -1, c1)), (sub c1, c2))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76535 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 05:40:15 +00:00
Dan Gohman
126b56659c Add a testcase for PR2831. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76527 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 01:02:18 +00:00
Dan Gohman
19211b47cc Add a testcase for PR4569, which is now fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 00:50:52 +00:00
Evan Cheng
af9e7a7c20 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76520 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 00:31:12 +00:00
Evan Cheng
c95be59371 Cross RC coalescing is now on by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 00:22:59 +00:00
Dan Gohman
746f3b1a9b The upper argument of ConstantRange is exclusive, not inclusive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76492 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 22:34:18 +00:00
David Greene
76081c4ef7 Re-apply 75490, 75806 and 76177 with fixes and tests. Efficiency comes 
next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76486 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 22:02:59 +00:00
Evan Cheng
87faa1fc67 Forgot this test earlier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76485 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 21:46:42 +00:00
Dan Gohman
1224c38698 Assembly and Bitcode support for unsigned/signed overflow flags and 
exact sdiv flags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76475 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 21:19:07 +00:00
Evan Cheng
33d0474bf5 Use TII->findCommutedOpIndices to find the commute operands (rather than guessing). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76472 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 21:16:08 +00:00
Kevin Enderby
5026ae4514 Removed the DumpSymbolsandMacros and LoadSymbolsandMacros MCStreamer API as 
the parsing of the .dump and .load should be done in the assembly parser and
not have any need for an MCStreamer API.  Changed the code for now so these
just produce an error saying these specific directives are not yet implemented
since they are likely no longer used and may never need to be implemented.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76462 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 20:25:37 +00:00
Evan Cheng
753480ad20 Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76458 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 19:47:55 +00:00
Dan Gohman
f241174421 Revert the addition of hasNoPointerOverflow to GEPOperator. 
Getelementptrs that are defined to wrap are virtually useless to
optimization, and getelementptrs that are undefined on any kind
of overflow are too restrictive -- it's difficult to ensure that
all intermediate addresses are within bounds. I'm going to take
a different approach.

Remove a few optimizations that depended on this flag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76437 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 17:43:30 +00:00
Evan Cheng
6aadc4d4dd xfail for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76423 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 15:33:09 +00:00
Chris Lattner
401e10c4fb implement a new magic global "llvm.compiler.used" which is like llvm.used, but 
doesn't cause ".no_dead_strip" to be emitted on darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76399 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 06:14:25 +00:00
Evan Cheng
ba8dc03935 Restore AsmWriterEmitter.cpp back to 74742. The recent changes broke Thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76398 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 06:10:07 +00:00
Daniel Dunbar
cc171839ad This test should be run with -m32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76382 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-19 22:44:03 +00:00
Jakob Stoklund Olesen
45d34fe358 Fix http://llvm.org/bugs/show_bug.cgi?id=4583 
Inline asm instructions may have additional <imp-def,kill> register operands.
These operands are not marked with a flag like the normal asm operands, so we
must not assert that there is a flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76373 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-19 19:09:59 +00:00
Eli Friedman
2451a64687 Canonicalize bitcasts between types like <1 x i64> and i64 to 
insertelement/extractelement.

I'm not entirely sure this is precisely what we want to do: should we 
prefer bitcast(insertelement) or insertelement(bitcast)?  Similarly. should we 
prefer extractelement(bitcast) or bitcast(extractelement)?



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76345 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 23:06:53 +00:00
Eli Friedman
76e7ba893f Back out 76300; apparently the preference is to canonicalize the other 
way (bitcast -> insert/extractelement).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76325 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 19:04:16 +00:00
Eli Friedman
8be17397c0 Add combine: X sdiv (1 << Y) -> X udiv (1 << Y) when X doesn't have the 
sign bit set.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76304 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 09:53:21 +00:00
Eli Friedman
fc21f8ff14 Canonicalize insert/extractelement from single-element vectors into 
bitcasts.

It would also be possible to canonicalize the other way; does anyone 
have a preference?



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76300 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 09:07:47 +00:00
Eli Friedman
62bb413435 Fix simplifylibcalls memset recognition to work on 64-bit platforms 
where int is 32 bits.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76293 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 08:34:51 +00:00
Evan Cheng
438d9900c0 Catch more coalescing opportunities. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76282 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 04:52:23 +00:00
Evan Cheng
5248468473 Enable cross register class coalescing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76281 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-18 02:10:10 +00:00
Evan Cheng
59959cd966 Fix pr4552. Stack slot coloring with register must take care not to generate illegal ams. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76258 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 22:42:51 +00:00
Daniel Dunbar
b4b53e5c13 llvm-mc: Add -triple, and start fetching the target asm printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76257 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 22:38:58 +00:00
Evan Cheng
47e9fab158 Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76248 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 22:13:25 +00:00
Chris Lattner
a9af7e626c rename test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76197 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 18:05:55 +00:00
Duncan Sands
cbc6da628a Testcase for PR4214. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76174 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 11:44:20 +00:00
Eli Friedman
a64eb92fe3 Make promotion in operation legalization for SETCC work correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76153 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-17 05:16:04 +00:00
Anton Korobeynikov
b8e9ac834a Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 23:26:06 +00:00
Dale Johannesen
423ccfe51d Assume an inline asm might be a call, so we get 
stack alignment right when it is.  This is not
ideal but conservatively correct.  Adjust a test
to compensate for changed stack offset value.
gcc.apple/asm-block-57.c



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76120 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 22:34:45 +00:00
David Greene
3ac1ab835c Emit line numbers in asm comments when available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76117 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 22:24:20 +00:00
Jakob Stoklund Olesen
57e599a46b Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands. 
The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 20:58:34 +00:00
Evan Cheng
5f15992b77 Changed my mind. We now allow remat of instructions whose defs have subreg indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76100 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 20:15:00 +00:00
Chris Lattner
dfce360306 this should be xfailed on darwin. Darwin doesn't use the libstdc++ in the llvm-gcc distro, it uses the system version. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76095 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 18:45:51 +00:00
Evan Cheng
2b48ab947c With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76094 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 18:44:05 +00:00
Dan Gohman
850f791abc Fill in some holes in ScalarEvolution's loop iteration condition 
analysis. This allows indvars to emit a simpler loop trip count
expression.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76085 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 17:34:36 +00:00
Anton Korobeynikov
ebfe2b2722 Make xfail proper 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76065 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:53:47 +00:00
Anton Korobeynikov
c975180624 Temporary disable 16 bit bswap 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76063 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:35:57 +00:00
Anton Korobeynikov
6ff3f2c710 Add bswap patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76061 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:34:52 +00:00
Anton Korobeynikov
54681eca69 Fix logic inversion for RI-mode address selection 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76052 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:31:14 +00:00
Anton Korobeynikov
9419a0d13d Unbreak the test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76051 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:30:49 +00:00
Anton Korobeynikov
bb8a04806d Expand 32-bit bitconverts via memory 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76050 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:30:29 +00:00
Anton Korobeynikov
f2fd8ea1c9 Fix incomin arg stack frame offset in case we need to generate stack frame 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76049 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:29:57 +00:00
Anton Korobeynikov
5dd38de2c2 Revert the commit, it just hides the real bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76045 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:28:26 +00:00
Anton Korobeynikov
75eef89ddb Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76035 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:24:41 +00:00
Anton Korobeynikov
8bd0db7615 Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:18:17 +00:00
Anton Korobeynikov
6fe326c713 Implement 'large' PIC model 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:16:05 +00:00
Anton Korobeynikov
48e8b3cc58 Implement shifts properly (hopefilly - finally!) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76005 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:15:24 +00:00
Anton Korobeynikov
0a42d2b437 Properly handle divides. As a bonus - implement memory versions of them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:14:33 +00:00
Anton Korobeynikov
014d4639d8 32 bit shifts have only 12 bit displacements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76000 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:13:24 +00:00
Anton Korobeynikov
1ed1e3ecd4 Consolidate reg-imm / reg-reg-imm address mode selection logic in one place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:10:17 +00:00
Anton Korobeynikov
720e3b00b8 Add support for 12 bit displacements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:09:35 +00:00
Anton Korobeynikov
980d5503c3 Emit proper lowering of load from arg stack slot 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:08:42 +00:00
Anton Korobeynikov
c772c4408e Implement dynamic allocas 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75985 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:08:15 +00:00
Anton Korobeynikov
c16cdc5de7 Add jump tables 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75984 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:07:50 +00:00
Anton Korobeynikov
759205d1ac Add rotates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75981 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:49 +00:00
Anton Korobeynikov
cfca8b1f62 Add patterns for integer negate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:27 +00:00
Anton Korobeynikov
8c993e1632 Provide proper patterns for and with imm instructions. Tune the tests accordingly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75979 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:06:00 +00:00
Anton Korobeynikov
25af73303f Add 32 bit and reg-imm and disable invalid patterns for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75978 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:05:32 +00:00
Anton Korobeynikov
747052c1a5 Add z9 and z10 target processors. Mark z10-only instructions as such. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75977 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 14:05:00 +00:00
Anton Korobeynikov
22836d1b31 Proper lower 'small' results 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75962 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:58:24 +00:00
Anton Korobeynikov
eb68f1c661 Completel forgot about unconditional branches 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75961 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:52 +00:00
Anton Korobeynikov
bad769f11a Lower addresses of globals 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75960 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:27 +00:00
Anton Korobeynikov
ed1a6d4cad Test (incomplete) for easy muls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75959 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:57:03 +00:00
Anton Korobeynikov
8d1837d9be Provide "wide" muls and divs/rems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75958 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:56:42 +00:00
Anton Korobeynikov
ecf22d5bdc Tests for cmp / br_cc / select_cc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75949 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:53:15 +00:00
Anton Korobeynikov
ef5decab53 Emit callee-saved regs spills / restores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75943 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:51:12 +00:00
Anton Korobeynikov
ba249e41f3 Some preliminary call lowering 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75941 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:50:21 +00:00
Anton Korobeynikov
3c98c616c5 Prologue / epilogue emission 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75940 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:49:49 +00:00
Anton Korobeynikov
51f613fb2b Add simple frame index elimination 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75939 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:49:25 +00:00
Anton Korobeynikov
81c0325cdf Provide proper test :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75938 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:48:59 +00:00
Anton Korobeynikov
711d5b68e0 Add address computation stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75935 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:59 +00:00
Anton Korobeynikov
c8301d17a8 Add mem-imm stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75933 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:47:14 +00:00
Anton Korobeynikov
961bb6f430 Add stores and truncstores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75931 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:45:00 +00:00
Anton Korobeynikov
dc28955b3f Add patterns for various extloads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 13:44:30 +00:00