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1228 Commits

Author SHA1 Message Date
Eric Christopher
05f9e4e8bd Match case for invalid constant error messages and add a new 
test for invalid hexadecimals.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129326 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 00:18:03 +00:00
Johnny Chen
e77f72d7d2 A8.6.16 B 
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 00:14:49 +00:00
Eric Christopher
164254d77c Test for invalid constant expr addition - bad octal constant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 00:03:38 +00:00
Johnny Chen
de16508955 Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 23:33:30 +00:00
Rafael Espindola
a61842bf6e Implement cfi_rel_offset 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:49:50 +00:00
Rafael Espindola
787d41aaa0 Add test for previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129304 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:41:34 +00:00
Johnny Chen
35563fee7b Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:14:35 +00:00
Johnny Chen
e679d3331b Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 
invalid instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:34:12 +00:00
Chris Lattner
15f8951799 fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately, 
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 19:41:05 +00:00
Benjamin Kramer
c18214a6e0 Don't store Twine temporaries, it's not safe. 
And don't append the name over and over again in the loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129210 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 11:26:27 +00:00
Johnny Chen
c636074afc Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. 
PR9650
rdar://problem/9257565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 19:41:22 +00:00
Johnny Chen
40de2b3f15 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 19:18:07 +00:00
Johnny Chen
084b5df5ae MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it. 
Add tests for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 17:29:58 +00:00
Johnny Chen
97fdff1d3f Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 00:29:09 +00:00
Rafael Espindola
9974b8b3cb Update tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 23:51:25 +00:00
Johnny Chen
3cf3059b11 Add a VEXT test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 22:04:01 +00:00
Rafael Espindola
ce8463f1fb Add support for .skip. 
Patch by Roman Divacky.
Fixes PR9361.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 20:26:23 +00:00
Johnny Chen
22dc4d9f59 Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:28:58 +00:00
Johnny Chen
8dbda0b51b Add sanity checking for invalid register encodings for saturating instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:02:08 +00:00
Johnny Chen
4d4e25740b Add some more comments about checkings of invalid register numbers. 
And two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 18:33:19 +00:00
Johnny Chen
f16f4e09ec Sanity check MSRi for invalid mask values and reject it as invalid. 
rdar://problem/9246844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 01:37:34 +00:00
Johnny Chen
8424a60fc9 The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values 
for USAD8 and USADA8.

rdar://problem/9247060


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 01:05:52 +00:00
Johnny Chen
2455268cdd Should also check SMLAD for invalid register values. 
rdar://problem/9246650


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 00:50:25 +00:00
Johnny Chen
d8b4c4d74f A8.6.393 
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 22:14:48 +00:00
Johnny Chen
4d81c9a6ba A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 20:49:02 +00:00
Johnny Chen
a9611549fe Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. 
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 18:27:46 +00:00
Johnny Chen
6a1220eeca Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. 
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 01:18:32 +00:00
Johnny Chen
2c868d1eef Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register 
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 23:28:00 +00:00
Johnny Chen
c3281c10c9 A7.3 register encoding 
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 22:57:07 +00:00
Johnny Chen
5438d76416 ARM disassembler was erroneously accepting an invalid RSC instruction. 
Added checks for regs which should not be 15.

rdar://problem/9237734


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 22:18:07 +00:00
Johnny Chen
c584e317e9 ARM disassembler was erroneously accepting an invalid LSL instruction. 
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 21:49:44 +00:00
Johnny Chen
2c2130bc64 The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. 
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 20:32:23 +00:00
Johnny Chen
bbc65bbb90 ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 19:42:11 +00:00
Johnny Chen
5dc0c50372 LDRD now prints out two dst registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128909 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 18:53:14 +00:00
Johnny Chen
12bb2958c4 Constants with multiple encodings (ARM): 
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:

    <byte> is the numeric value of abcdefgh, in the range 0-255
    <rot> is twice the numeric value of rotation, an even number in the range 0-30.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 18:02:46 +00:00
Johnny Chen
b26d8d7c49 Check for invalid register encodings for UMAAL and friends where: 
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
    if dHi == dLo then UNPREDICTABLE;

rdar://problem/9230202


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 17:43:10 +00:00
Johnny Chen
157536b1fb Fix SRS/SRSW encoding bits. 
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS

Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 00:16:18 +00:00
Johnny Chen
2d66cec9dd Fix incorrect alignment for NEON VST2b32_UPD. 
rdar://problem/9225433


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 20:35:31 +00:00
Bruno Cardoso Lopes
ac79e4c82f - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT 
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 17:18:19 +00:00
Joerg Sonnenberger
4a8ac8de1d Add support for the VIA PadLock instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 16:58:13 +00:00
Johnny Chen
04187ecd57 Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset; 
instead of the second operand in addrmode_imm12.

rdar://problem/9225289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 02:24:54 +00:00
Johnny Chen
103bf951a4 Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. 
rdar://problem/9224276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 23:30:25 +00:00
Johnny Chen
6da3fe68c6 MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE. 
rdar://problem/9224120


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 23:15:50 +00:00
Johnny Chen
857b1939da Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that 
all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 22:32:51 +00:00
Johnny Chen
ec30f6f5e5 Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction 
as invalid.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 20:21:38 +00:00
Johnny Chen
5307da994a Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). 
rdar://problem/9219356


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 18:26:38 +00:00
Bruno Cardoso Lopes
ae0855401b Apply again changes to support ARM memory asm parsing. I removed 
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 23:26:08 +00:00
Johnny Chen
0c630b5f38 Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which 
amounts to an UNDEFINED instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128668 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 20:54:30 +00:00
Johnny Chen
a52d7da1d8 Fix single word and unsigned byte data transfer instruction encodings so that 
Inst{4} = 0.

rdar://problem/9213022


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 19:28:35 +00:00
Johnny Chen
8901e6ff3d Add BLXi to the instruction table for disassembly purpose. 
A8.6.23 BLX (immediate)

rdar://problem/9212921


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 17:53:50 +00:00
Daniel Dunbar
48a36158ec Remove stray empty test file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 17:01:56 +00:00
Bruno Cardoso Lopes
b41aaab5a1 Revert r128632 again, until I figure out what break the tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 15:54:36 +00:00
Bruno Cardoso Lopes
bcd3a9cd84 Reapply r128585 without generating a lib depedency cycle. An updated log: 
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay
e4345c9977 Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" 
This revision introduced a dependency cycle, as nlewycky mentioned by email.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 00:39:16 +00:00
Bruno Cardoso Lopes
40829ed6f5 - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and 
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 23:32:32 +00:00
Johnny Chen
caee968481 Add a test case for thumb stc2 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 01:02:06 +00:00
Kevin Enderby
b715ce35d7 Adding a test for "-inf" as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128495 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 21:54:10 +00:00
Johnny Chen
e077157e54 Add a test case for MSRi. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 21:52:02 +00:00
Kevin Enderby
360d8d7a02 Added support symbolic floating point constants in the MC assembler for Infinity 
and Nans with the same strings as GAS supports.  rdar://8673024


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 21:11:52 +00:00
Johnny Chen
5726005e4f Add a thumb test file for printf (iOS 4.3). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128487 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 21:09:30 +00:00
Johnny Chen
9eda569a74 A8.6.188 STC, STC2 
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.

rdar://problem/9200661


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 19:49:38 +00:00
Johnny Chen
4381dd1f21 Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 19:10:06 +00:00
Johnny Chen
288a4284bb Add and modify some tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128476 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 19:08:52 +00:00
Owen Anderson
848b0c39b1 Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 16:45:53 +00:00
Daniel Dunbar
c6cf43d258 MC: Add support for disabling "temporary label" behavior. Useful for debugging 
on Darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128430 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-28 22:49:15 +00:00
Johnny Chen
d560a80925 Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases. 
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128417 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-28 18:41:58 +00:00
Johnny Chen
eca915fb52 Fixed the t2PLD and friends disassembly and add two test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-26 01:32:48 +00:00
Johnny Chen
cf0fe4650f Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 23:02:58 +00:00
Johnny Chen
65c0a59869 Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128305 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 22:43:28 +00:00
Johnny Chen
a2755b9829 Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID. 
Also add some test cases.

rdar://problem/9189829


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 22:19:07 +00:00
Johnny Chen
abeea57639 DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases. 
rdar://problem/9182892


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 19:35:37 +00:00
Johnny Chen
b66a097612 A8.6.226 TBB, TBH: 
Add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 18:40:21 +00:00
Johnny Chen
ceceabd4b1 Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to 
t2LDREX/t2STREX instructions.  Add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 18:29:49 +00:00
Daniel Dunbar
8b2b43c41d MC: Improve some diagnostics on uses of '.' pseudo-symbol. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128289 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 17:47:17 +00:00
Johnny Chen
6c3891067b Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that. 
rdar://problem/9184053


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 17:31:16 +00:00
Johnny Chen
f14d5cf33a Also need to handle invalid imod values for CPS2p. 
rdar://problem/9186136


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 17:03:12 +00:00
Johnny Chen
a7078c4f27 Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), 
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 01:09:48 +00:00
Johnny Chen
ef74e9ab40 delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 00:17:42 +00:00
Johnny Chen
8c13335c9a The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since 
the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 23:42:31 +00:00
Johnny Chen
1090d7711b The ARM disassembler was confused with the 16-bit tSTMIA instruction. 
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 23:21:14 +00:00
Johnny Chen
c39b6271be Handle the added VBICiv*i* NEON instructions, too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 22:04:39 +00:00
Johnny Chen
9091bf25d9 T2 Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:36:56 +00:00
Benjamin Kramer
83ccbff84f Plug a leak in the arm disassembler and put the tests back. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
505f3cd296 Add asm parsing support w/ testcases for strex/ldrex family of instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:04:58 +00:00
Johnny Chen
02af767dca Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'. 
These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 20:56:23 +00:00
Johnny Chen
e6d69e7dbe ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. 
Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 20:42:48 +00:00
Johnny Chen
b4ac342ea0 The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the 
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 18:40:38 +00:00
Johnny Chen
ce1868b21c Add comments to the handling of opcode CPS3p to reject invalid instruction encoding, 
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 17:04:22 +00:00
Johnny Chen
3d793962be Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 01:40:42 +00:00
Johnny Chen
571f290376 STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). 
We now tag them as IndexModePost.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 01:07:26 +00:00
Johnny Chen
2abc9d2444 The r128103 fix to cope with the removal of addressing modes from the MC instructions 
were incomplete.  The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 00:28:38 +00:00
Johnny Chen
8d668a8605 Add disassembly test cases for: 
A8.6.292 VCMPE


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128120 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-22 23:08:56 +00:00
Johnny Chen
27c6baeca2 LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). 
We now tag them as IndexModePost.

This fixed http://llvm.org/bugs/show_bug.cgi?id=9530.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-22 22:28:49 +00:00
Johnny Chen
83cf2ffdcd Add one more test case for VFP Load/Store Multiple (vpop). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-22 20:21:08 +00:00
Johnny Chen
758df29741 A8.6.399 VSTM: 
VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions.  Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.

Also add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-22 20:00:10 +00:00
Rafael Espindola
7c18fa87a4 Write the section table and the section data in the same order that 
gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127972 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-20 18:44:20 +00:00
Johnny Chen
94dad03a96 Fixed an assert by the ARM disassembler for LDRD_PRE/POST. 
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand.  Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-19 01:16:20 +00:00
Owen Anderson
0082830cb2 Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-18 22:50:18 +00:00
Joerg Sonnenberger
96622aa063 Support explicit argument forms for the X86 string instructions. 
For now, only the default segments are supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-18 11:59:40 +00:00
Johnny Chen
5e5a40867a The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset. 
Remove the offending logic and update the test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-18 00:38:03 +00:00
Johnny Chen
e68d8ec252 It used to be that t_addrmode_s4 was used for both: 
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1

It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos).  Modify the
disassembler to reflect the change, and add relevant tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-17 22:04:05 +00:00
Daniel Dunbar
8d06ffca9b MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't have 
been removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127812 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-17 16:25:24 +00:00
Joerg Sonnenberger
d02c8b6cc1 Fix handling of @IDNTPOFF relocations, they need to get STT_TLS. 
While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-17 00:35:10 +00:00
Johnny Chen
276f6f9cf9 There were two issues fixed: 
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
   Modify the ARMDisassemblerCore.cpp file to accomodate the change.

2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:

   imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
                                       // Encoding A1

   It has no business doing such.  Removed the offending logic.

Add test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-15 22:27:33 +00:00
Sean Callanan
9a9d8b9732 Basic sanity checks to ensure that 2- and 3-byte 
VEX prefixes are working for triadic AVX
instructions.  This concludes the patch set to
enable AVX support for the X86 disassebler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-15 01:32:46 +00:00
Johnny Chen
085ea1b633 Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra 
register operand was erroneously added.  Remove an incorrect assert which triggers the bug.

rdar://problem/9131529


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-15 01:13:17 +00:00
Cameron Zwarich
899eaa3569 Roll r127459 back in: 
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 21:52:04 +00:00
Daniel Dunbar
950d3db5f4 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get 
created from the", it broke some GCC test suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 19:30:30 +00:00
Cameron Zwarich
592ca3fda9 Optimize trivial branches in CodeGenPrepare, which often get created from the 
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 04:54:27 +00:00
Johnny Chen
18b475f954 LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. 
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16.  Add extra logic to recover from that.

Fixed an assert reported by Sean Callanan


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 20:01:14 +00:00
Bill Wendling
620d0cc7ac * Correct encoding for VSRI. 
* Add tests for VSRI and VSLI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 00:33:17 +00:00
Bill Wendling
c04a9dea78 Correct the encoding for VRSRA and VSRA instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 00:00:35 +00:00
Bill Wendling
7c6b608a7c * Fix VRSHR and VSHR to have the correct encoding for the immediate. 
* Update the NEON shift instruction test to expect what 'as' produces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 23:48:09 +00:00
Bill Wendling
591432136c A few more tests for instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127209 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 02:51:48 +00:00
Bill Wendling
3116dce338 Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 
expand the testing of the narrowing shift right instructions.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-07 23:38:41 +00:00
Joerg Sonnenberger
89e0f386f3 Be nice to Xcore and the XMOS assembler and avoid quoting section names 
that contain only letters, digits and the characters "_" and ".".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:03:14 +00:00
Eli Friedman
86d822df6d Followup to r126970: add 64-bit encoding tests for str with reg operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126987 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 04:06:47 +00:00
Eli Friedman
ac39bd534b PR9377: Handle x86 str with register operand in a way consistent with gas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 00:10:17 +00:00
Joerg Sonnenberger
ea83b13350 Bug#9033: For the ELF assembler output, always quote the section name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 22:31:08 +00:00
Eli Friedman
78c1e1781c PR9352: Always emit a relocation for weak symbols. Not emitting relocations 
for calls to weak symbols with a definition has the appearance of working
with LLVM-generated code because weak symbol definitions are put in their
own sections.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126933 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 07:24:36 +00:00
Bob Wilson
1473f35c47 TableGen should not ignore BX instructions for the ARM disassembler. pr9368. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126931 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 07:19:52 +00:00
Bob Wilson
181d3fe727 pr9367: Add missing predicated BLX instructions. 
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 01:41:01 +00:00
Kevin Enderby
d39647d913 Fixes an assertion failure while disassembling ARM rsbs reg/reg form. 
Patch by Ted Kremenek!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 23:08:33 +00:00
Bill Wendling
a656b63ee4 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 01:00:59 +00:00
Kevin Enderby
d436d5b1c9 Fix the arm's disassembler for blx that was building an MCInst without the 
needed two predicate operands before the imm operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 18:46:31 +00:00
Chris Lattner
98ea4ce516 split this test into arch specific pieces, so the ARM 
test isn't run when the arm backend isn't built.  This
fixes PR9327


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-25 19:06:35 +00:00
Joerg Sonnenberger
93c65e6e66 Restore r125595 (reverted in r126336) with modifications: 
Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 21:59:22 +00:00
Devang Patel
3fe3424a21 Move arch specific tests in arch specific directories. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126401 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 19:06:27 +00:00
Jim Grosbach
f956183643 Remove file. Previous commit deleted content, but left the file around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 21:43:31 +00:00
Jim Grosbach
33b7bebca4 Revert r125595, which is an X86-only undocumented assembly syntax extension 
enabled for all targets. Non-X86 targets should not have this behavior
enabled by default.

Joerg, if you would like to resubmit with the behavior conditionalized to be
X86-ELF only, that's fine.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 21:26:51 +00:00
Rafael Espindola
21451e533f Put in the symbol table symbols only used in a .globl statement. 
Fixes PR9292.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 20:22:07 +00:00
Sean Callanan
8fbc00b5ba Fixed a bug in the enhanced disassembler that caused 
it to ignore valid uses of FS and GS as additional
base registers in address computations.  Added a test
case for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126302 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 03:31:28 +00:00
Joerg Sonnenberger
00743c2218 Use the same (%dx) hack for in[bwl] as for out[bwl]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 20:40:09 +00:00
Sean Callanan
ec243ae2b8 Added a testcase for the enhanced disassembly bug 
fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 02:19:18 +00:00
Joerg Sonnenberger
d86f482e4a Recognize loopz and loopnz as aliases for loope and loopne. 
From Dimitry Andric.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 00:43:07 +00:00
Rafael Espindola
87ca0e077d Implement xgetbv and xsetbv. 
Patch by Jai Menon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 00:35:18 +00:00
Joerg Sonnenberger
d45e8bf93b Handle FK_PCRel_1 and add a test case for this and FK_PCRel_4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126157 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-21 23:25:41 +00:00
Rafael Espindola
f7ad048f1e Add some limited support for labels in org directives. Hopefully enough to fix 
PR9245.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-20 20:20:07 +00:00
Chris Lattner
824a9076ea implement PR9264: disambiguating 'bt mem, imm' as a btl. 
This is reasonable to do since all bt-mem forms do the
same thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-19 21:06:36 +00:00
Bruno Cardoso Lopes
584bf7bb03 Add assembly parsing support for "msr" and also fix its encoding. Also add 
testcases for the disassembler to make sure it still works for "msr".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-18 19:45:59 +00:00
Joerg Sonnenberger
5ad596f9d2 Recognize monitor/mwait with explicit register arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125805 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-18 00:48:11 +00:00
Joerg Sonnenberger
97755a063e Recognize leavel and leaveq aliases for leave. 
Validate encoding of leave in 64bit mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125795 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-17 23:36:39 +00:00
Rafael Espindola
908159b46a Gas is very inconsistent about when a relaxation/relocation is needed. Do 
the right thing and stop trying to copy it. Fixes PR8944.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125648 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-16 03:25:55 +00:00
Rafael Espindola
7768a9dce1 Add support for pushsection and popsection. Patch by Joerg Sonnenberger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125629 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-16 01:08:29 +00:00
Roman Divacky
738a00eb86 Add support for parsing [expr]. 
This is submitted by Joerg Sonnenberger and fixes his PR8685.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125595 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-15 20:43:39 +00:00
Bruno Cardoso Lopes
a2b6e4151b Fix encoding and add parsing support for the arm/thumb CPS instruction: 
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-14 13:09:44 +00:00
Reid Kleckner
26f23100ac Add encodings and mnemonics for FXSAVE64 and FXRSTOR64. 
These are just FXSAVE and FXRSTOR with REX.W prefixes.  These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125446 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-12 23:24:13 +00:00
Jim Grosbach
b9db0c50d8 Do AsmMatcher operand classification per-opcode. 
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-10 00:08:28 +00:00
Owen Anderson
971b83b67a Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-08 22:39:40 +00:00
Benjamin Kramer
0fd90bc12f Support for .ifdef / .ifndef in the assembler parser. Patch by Joerg Sonnenberger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125120 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-08 22:29:56 +00:00
Bruno Cardoso Lopes
706d946cfe Add support for parsing dmb/dsb instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125055 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-07 22:09:15 +00:00
Jason W Kim
953a2a3dee Teach ARM/MC/ELF about gcc compatible reloc output to get past odd linkage 
failures with relocations.

The code committed is a first cut at compatibility for emitted relocations in
ELF .o.

Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.

Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass

Added reminder fixme to tests for future conversion to .s form.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124996 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-07 01:11:15 +00:00
Jason W Kim
2d7a53aec2 Teach ARM/MC/ELF about EF_ARM_EABI_VERSION. The magic number is set to 
5 to match the current doc.
Added FIXME reminder Make it really configurable later.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124899 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-04 21:41:11 +00:00
Jason W Kim
685c350ae7 Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps. 
(yes, this is different from R_ARM_CALL)

- Adds a new method getARMBranchTargetOpValue() which handles the
  necessary distinction between the conditional and unconditional br/bl
  needed for ARM/ELF

At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...

Added a few FIXME's for future naming fixups in ARMInstrInfo.td




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-04 19:47:15 +00:00
Evan Cheng
4d98ee5234 Fix test for non-darwin targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-01 01:16:18 +00:00
Bob Wilson
d11c57a937 PR9030: Fix disassembly of ARM "mov pc, lr" instruction. 
Patch by Jyun-Yan You.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-28 17:50:30 +00:00
Roman Divacky
14e66553d5 Add support for parsing .float 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-28 14:20:32 +00:00
Nico Weber
4c4c732960 PR8951: Support for .equiv in integrated assembler, patch by Jörg Sonnenberger! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124467 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-28 03:04:41 +00:00
Evan Cheng
c3a20bab75 Fix PLD encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 23:48:34 +00:00
Roman Divacky
54b0f4f2a4 Add support for specifying register name in cfi-register/offset/def 
as well as register number.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124379 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 17:16:37 +00:00
Bruno Cardoso Lopes
106df6da36 Add encoding testcases for ARM vcvtr variations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124289 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 13:53:38 +00:00
Bruno Cardoso Lopes
1b10d5be40 fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 13:28:14 +00:00
Rafael Espindola
59b8cf4512 Jörg Sonnenberger noticed that we were missing this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124139 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 19:40:38 +00:00
Rafael Espindola
184640e96e Handle strings in section names the same way as gas: 
* If the name is a single string, we remove the quotes
* If the name starts without a quote, we include any quotes in the name

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124127 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 18:02:54 +00:00
Rafael Espindola
96aa78c8c5 Add support for the --noexecstack option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 17:55:27 +00:00
Rafael Espindola
54104db434 Add support for lowercase variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 16:11:25 +00:00
Rafael Espindola
0cf5e3d51d Delay the creation of eh_frame so that the user can change the defaults. 
Add support for SHT_X86_64_UNWIND.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 05:43:40 +00:00
Bruno Cardoso Lopes
030160073d Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", 
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 14:07:40 +00:00
Bruno Cardoso Lopes
1115c47203 Add testcases for clz encoding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 19:27:16 +00:00
Bruno Cardoso Lopes
e47f3751d7 Fix the encoding and parsing of clrex instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes
8dd37f7b7d Add cdp/cdp2 instructions for thumb/thumb2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
b32f7a5f4b - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes
6b3a999f22 Add mcr*2 and mr*c2 support to thumb2 targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes
fa5bd27fbe Add mcr* and mr*c support to thumb targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 16:35:57 +00:00
Bruno Cardoso Lopes
3abd75bf1d Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 16:56:52 +00:00
Owen Anderson
6cd0b17ba7 When matching asm operands, always try to match the most restricted type first. 
Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous.  This
is tricky to resolve since neither is a subset of the other.

XFAIL the test for now.  The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 23:01:21 +00:00
Bruno Cardoso Lopes
61505907f5 Create two new generic classes to represent the following VMRS/VMSR variations: 
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123783 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes
e7255a80e3 Fix MRS encoding for arm and thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123778 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes
892fc6d7b6 Fix the encoding of t2ISB by using the right class and also parse it correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes
fdcee77887 Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes
a461d42228 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 20:45:56 +00:00
Daniel Dunbar
2e3cea3153 McARM: Start marking T2 address operands as such, for the benefit of the parser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 03:06:03 +00:00
Rafael Espindola
1c10db3da9 Update tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 18:02:57 +00:00
Evan Cheng
f3eb3bba16 Completed :lower16: / :upper16: support for movw / movt pairs on Darwin. 
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 02:38:49 +00:00
Owen Anderson
0fba714359 As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 22:38:16 +00:00
Evan Cheng
7597212abc Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step 
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 07:58:56 +00:00
Bill Wendling
7caebff83d Sort the register list based on the *actual* register numbers rather than the 
enum values we give to them. <rdar://problem/8823730>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 21:20:59 +00:00
Jason W Kim
86a97f2e4d 1. Support ELF pcrel relocations for movw/movt: 
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 00:19:25 +00:00
Jason W Kim
9081b4b4cf Workaround for bug 8721. 
.s Test added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 23:53:41 +00:00
Chris Lattner
3a5004dc3e Fix PR8946, a missing reg/reg form of movdqu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 17:04:55 +00:00
Daniel Dunbar
352e148cbe McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the 
carry setting flag from the mnemonic.

Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 15:59:50 +00:00
Daniel Dunbar
8ab1112bdc McARM: Flush out hard coded known non-predicated mnemonic list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 21:01:03 +00:00
Rafael Espindola
2f867a63da Correctly disassemble truncated asm. 
Patch by Richard Simth.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122962 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 16:48:42 +00:00
Evan Cheng
bbdcd44361 Convert MC tests to .s so codegen changes won't break them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-03 23:47:14 +00:00
Rafael Espindola
7a54997d67 Fix PR8878. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122658 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-01 19:05:35 +00:00
Nick Lewycky
c00210cef2 Add another non-commutable instruction that gas accepts commuted forms for. 
Fixes PR8861.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122641 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-30 22:10:49 +00:00
Daniel Dunbar
b2624eda5a MC/Mach-O/Thumb: Set the thumb bit in the symbol table. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-29 14:14:06 +00:00
Rafael Espindola
caf1158b0f Correctly encode pcrel|indirect. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122624 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-29 04:31:26 +00:00
Rafael Espindola
a7e450574c Fix bug when trying to output uint16_t or uint32_t. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122615 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-29 02:30:49 +00:00
Rafael Espindola
b40a71fda1 Implement cfi_def_cfa. Also don't convert to dwarf reg numbers twice. Looks 
like 6 is a fixed point of that and so the previous tests were OK :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122614 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-29 01:42:56 +00:00