Jim Grosbach
32ab4aff69
Fix improperly formed assert() call.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142239 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 20:22:59 +00:00
Akira Hatanaka
8ae330ac90
Add definitions of conditional moves with 64-bit operands. Comment out code for
...
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:53:29 +00:00
Hal Finkel
c61291609d
Revert change to function alignment b/c existing logic was fine
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142224 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:53:03 +00:00
Chad Rosier
c378015d1c
Removed set, but unused variables.
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Patch by Joe Abbey <jabbey@arxan.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:48:30 +00:00
Akira Hatanaka
8f3af87e99
Move class and instruction definitions for conditional moves to a seperate file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:43:19 +00:00
Akira Hatanaka
eea367ec97
Revert change made in r142205.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:33:24 +00:00
Akira Hatanaka
bdfd98a080
Redefine count-leading 0s and 1s instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142216 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:26:37 +00:00
Akira Hatanaka
89d306669e
Redefine mfhi/lo and mthi/lo instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142214 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:24:15 +00:00
Akira Hatanaka
f1fddcd9e0
Redefine multiply and divide instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:21:24 +00:00
Akira Hatanaka
2d0a61da62
Add definition of a base class for logical shift/rotate instructions with two
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source registers and redefine 32-bit and 64-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142210 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:17:58 +00:00
Hal Finkel
e9e5791556
Remove >80-col line and unicode
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142209 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:10:08 +00:00
Akira Hatanaka
363934665d
Add definition of a base class for logical shift/rotate immediate instructions
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and have 32-bit and 64-bit instructions derive from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142207 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:06:56 +00:00
Akira Hatanaka
a01820a508
Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142205 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:01:00 +00:00
Michael J. Spencer
9904056a70
Fix CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 17:50:39 +00:00
Devang Patel
827454e6e2
svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp
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There is no reason to have simple IR level pass in lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 17:17:43 +00:00
Hal Finkel
98daa9dcc8
Instructions for Book E PPC should be word aligned, set function alignment to reflect this
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 17:01:41 +00:00
Craig Topper
4b2dc74d3f
Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 05:33:10 +00:00
Bill Wendling
24bb925566
Add comment explaining that the order of processing doesn't matter here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 05:25:09 +00:00
Hal Finkel
b31d3d271f
Add PPC 440 scheduler and some associated tests (new files)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 04:03:55 +00:00
Hal Finkel
c6d08f10bf
Add PPC 440 scheduler and some associated tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 04:03:49 +00:00
Craig Topper
ee62e4f6d1
Add X86 PEXTR and PDEP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
Benjamin Kramer
5efabcf01d
Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing.
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<stdin>:1:12: error: register %rax is only available in 64-bit mode
incl %rax
^~~~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 12:10:27 +00:00
Benjamin Kramer
f82edaffb1
X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands.
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<stdin>:1:4: error: invalid instruction mnemonic 'abc'
abc incl %edi
^~~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 11:28:29 +00:00
Nadav Rotem
c32a8c9073
Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
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no pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 10:02:06 +00:00
Craig Topper
b53fa8bf19
Add X86 BZHI instruction as well as BMI2 feature detection.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:55:05 +00:00
Craig Topper
dc479c4a89
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:05:40 +00:00
Cameron Zwarich
daada347b5
Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.
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These missing flags show up as errors when running -verify-coalescing on
test-suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 06:38:10 +00:00
Cameron Zwarich
d575137634
Fix an obvious typo found when looking at nearby code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 06:38:06 +00:00
Chris Lattner
d8b7aa2613
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
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the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 04:47:35 +00:00
Craig Topper
17730847d5
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 03:51:13 +00:00
Craig Topper
4145c49aa0
Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142089 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 00:21:51 +00:00
Craig Topper
566f233ba6
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 20:46:47 +00:00
Nadav Rotem
4d83b79c76
The CELL backend cannot select patterns for vector trunc-store and shl on v2i64; CellSPU/shift_ops.ll fails when promoting elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 20:05:17 +00:00
Nadav Rotem
004a24b44c
ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when promoting elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 20:03:12 +00:00
Benjamin Kramer
003fad98cc
SmallVector -> array
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 13:28:31 +00:00
Jakob Stoklund Olesen
534849687c
Mark tADDrSPi as having side effects again.
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It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations. I am guessing that it got
moved across a stack pointer update.
Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 00:57:13 +00:00
Chad Rosier
d73462a1c9
Thumb1 does not support dynamic stack realignment.
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rdar://10288916 is tracking this fix.
In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment. Lang's work now
prevents this from happening (LLVM commit r141599). Now that this really
shouldn't happen report a fatal error rather than silently generate bad code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 00:28:24 +00:00
Bill Wendling
918f2155e9
Mark registers as DEAD because they're really just clobbers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 00:27:44 +00:00
Eli Friedman
46995fa7e2
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 23:58:49 +00:00
Bill Wendling
5d79859f66
Make sure that the register is in the register class before adding it as a machine op.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 23:55:44 +00:00
Bill Wendling
969c9ef0dd
Mark the invoke call instruction as implicitly defining the callee-saved registers.
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The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 23:34:37 +00:00
Richard Trieu
8223e45dff
Fix a non-firing assert. Change:
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assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 20:50:26 +00:00
Evan Cheng
b10946a5a9
A few 80-col violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141988 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 20:36:23 +00:00
Hal Finkel
d712f935f7
Add an implementation of the CanLowerReturn function to the PPC backend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 19:51:36 +00:00
Akira Hatanaka
1ce2668c84
Add f128 to datalayout string.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 19:14:50 +00:00
Hal Finkel
8ee53e2eb6
initial test commit (remove whitespace)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141972 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 18:54:13 +00:00
Akira Hatanaka
008b58c4ae
Revert r141932, r141936 and r141937.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 17:16:39 +00:00
Craig Topper
54a11176f6
Add X86 ANDN instruction. Including instruction selection.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 07:06:56 +00:00
Craig Topper
909652f687
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 03:21:46 +00:00
Akira Hatanaka
91d2cc9cdd
Definition of function getMipsRegisterNumbering.
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Patch by Jack Carter and Reed Kotler at Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 03:04:24 +00:00
Akira Hatanaka
2891662cc2
Add definition of class MipsELFWriterInfo.
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Patch by Jack Carter and Reed Kotler at Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 02:55:47 +00:00
Akira Hatanaka
51f72c5a3f
Add missing relocation types.
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Patch by Jack Carter and Reed Kotler at Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 02:47:50 +00:00
Akira Hatanaka
36004b93ef
Fixup enumerations.
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Patch by Jack Carter at Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141934 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 02:38:56 +00:00
Akira Hatanaka
93d2a0a1fa
Add more Mips relocation types.
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Patch by Jack Carter at Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141932 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 02:17:30 +00:00
Jakob Stoklund Olesen
ccbe603869
Ban rematerializable instructions with side effects.
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TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 01:00:49 +00:00
Jakob Stoklund Olesen
0a951fba75
V_SET0 has no side effects.
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TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.
This was part of the cause for PR11125, but the real bug was fixed
in r141923.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141924 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 00:39:50 +00:00
Eli Friedman
ecb830e45c
Fix undefined shift. Patch by Ahmed Charles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 23:36:06 +00:00
Eli Friedman
d83a54fd35
Simplify assertion, and avoid undefined shift. Based on patch by Ahmed Charles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141912 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 23:27:48 +00:00
Eli Friedman
5bd7ff2128
Fix undefined shifts and abs in Alpha backend. Based on patch by Ahmed Charles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 23:13:35 +00:00
Eli Friedman
8e4d0429de
Simplify and avoid undefined shift. Based on patch by Ahmed Charles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 22:40:23 +00:00
Owen Anderson
c18e940c5a
SETEND is not allowed in an IT block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 17:58:39 +00:00
Kalle Raiskila
898f336c51
Mark 'branch indirect' instruction as an indirect branch.
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Not having it confused assembly printing of jumptables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 11:40:03 +00:00
Bill Wendling
4e68054b20
More closely follow libgcc, which has code after the `ret' instruction to
...
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 08:24:19 +00:00
Bill Wendling
1203fe7fc8
Revert r141854 because it was causing failures:
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http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:48:07 +00:00
Bill Wendling
82222c20be
Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:42:32 +00:00
Craig Topper
8ab1d1e900
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:09:14 +00:00
Craig Topper
d501c714cd
Add 'implicit EFLAGS' to patterns for popcnt and lzcnt
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 06:18:52 +00:00
Jim Grosbach
81b2928d80
ARM addrmode5 represents the 'U' bit of the encoding backwards.
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The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 21:59:02 +00:00
Jim Grosbach
c66e7afcf2
Thumb2 assembly parsing and encoding for LDC/STC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 20:54:17 +00:00
Jim Grosbach
b0786b33fa
addrmode2 is gone from these, so no need for the reg0 operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 18:11:24 +00:00
Jim Grosbach
9b8f2a0b36
ARM parsing and encoding for the <option> form of LDC/STC instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 17:34:41 +00:00
Jim Grosbach
01208d56e8
80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 16:36:01 +00:00
Jim Grosbach
bc9c80240b
Tidy up. Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141780 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 16:34:37 +00:00
Akira Hatanaka
41f9a430cb
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141761 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 01:05:13 +00:00
Akira Hatanaka
6baabc1dd0
Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
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Remove unused classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141757 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 00:56:06 +00:00
Nick Lewycky
1f9c6860bf
Fix indent in comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141749 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 00:14:12 +00:00
Jakob Stoklund Olesen
1c062c24ab
Fix -widen-vmovs liveness issues.
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When widening a copy, we are reading a larger register that may not be
live. Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.
We now widen:
%S6<def> = COPY %S4<kill>, %D3<imp-def>
into:
%D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>
This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.
Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 00:06:23 +00:00
Akira Hatanaka
80eb994929
Change name of class to ArithOverflowR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 23:43:48 +00:00
Akira Hatanaka
2dfd3a9789
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
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instructions with two register operands derive from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 23:38:52 +00:00
Akira Hatanaka
76d9f1c022
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141737 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 23:12:12 +00:00
Akira Hatanaka
c2f3ac9de2
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
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arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 23:05:46 +00:00
Akira Hatanaka
68ad5673e8
Fix function isUnalignedLoadStore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 22:04:01 +00:00
Jim Grosbach
2bd0118472
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
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Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:55:36 +00:00
Akira Hatanaka
d8212b2916
Remove unused PatLeaf.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141720 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:53:08 +00:00
Akira Hatanaka
7cc037a137
Change the names of 64-bit logical instructions so that they match the names of
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the real instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:48:01 +00:00
Bill Wendling
e575499d83
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:40:47 +00:00
Akira Hatanaka
395d76c5a3
Remove redundancy in setcc patterns using multiclass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141715 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:40:01 +00:00
Akira Hatanaka
b07a3d6897
Use sltiu instead of sltu when a register operand and immediate are compared.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 20:44:43 +00:00
Jim Grosbach
2cf8dd384e
ARM addressing mode cleanup for LDC/STC.
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We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 20:17:35 +00:00
Akira Hatanaka
06f8231bfb
Add patterns for conditional branches with 64-bit register operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 19:09:09 +00:00
Akira Hatanaka
8191f34797
Add support for 64-bit set-on-less-than instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141695 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 18:53:46 +00:00
Akira Hatanaka
3e3427a5c3
Add support for conditional branch instructions with 64-bit register operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141694 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 18:49:17 +00:00
Jim Grosbach
57dcb85a30
ARM parse alignment specifier for NEON load/store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 17:29:55 +00:00
Jim Grosbach
e53c87b302
ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141671 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 15:59:20 +00:00
Richard Osborne
6c6f28ffe4
Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks.
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This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 12:55:35 +00:00
Kalle Raiskila
56354d48bb
Fix a iterator out of bounds error, that triggers rarely.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 12:55:18 +00:00
Craig Topper
c48b301fb0
Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141656 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 07:13:09 +00:00
Craig Topper
227358e93c
Make Ivy Bridge 16-bit floating point conversion instructions require AVX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 07:01:37 +00:00
Craig Topper
37f2167f15
Add X86 LZCNT instruction. Including instruction selection support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 06:44:02 +00:00
Craig Topper
29480fd798
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 04:34:23 +00:00
Akira Hatanaka
1acb7df498
Make changes necessary for supporting floating point load and store instructions
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that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 01:12:52 +00:00
Jakob Stoklund Olesen
142bd1a54e
Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().
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The VMOVS widening needs to look at the implicit COPY operands. Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.
The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:59:06 +00:00
Akira Hatanaka
a5903acd6b
Modify lowering of GlobalAddress so that correct code is emitted when target is
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Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141618 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:55:05 +00:00
Lang Hames
4ad06e61c0
Fixed natural stack alignment for Linux x86-32. Thanks Eli.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141616 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:51:36 +00:00
Akira Hatanaka
381e97dcf6
Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141615 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:44:20 +00:00
Akira Hatanaka
43aed32e20
Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141613 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:37:28 +00:00
Akira Hatanaka
7bd19bd519
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
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zextloadi32 for which there is no corresponding pseudo or real instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:27:28 +00:00
Akira Hatanaka
d55bb38ddc
Change definitions of classes LoadM and StoreM in preparation for adding support
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for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141603 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:11:12 +00:00
Bill Wendling
3f56d4b957
Simplify check that optional def is there and is CPSR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141602 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:10:41 +00:00
Lang Hames
bb5b3f3359
Add a natural stack alignment field to TargetData, and prevent InstCombine from
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promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.
The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 23:42:08 +00:00
Jim Grosbach
f6c35c59f5
Simplify operand Kind checks a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 23:06:42 +00:00
Bill Wendling
ef2c86f876
Reapply r141365 now that PR11107 is fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:59:55 +00:00
Jim Grosbach
38fbe32315
Add a name to sub-operand for clarity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:55:05 +00:00
Bill Wendling
721e1d2669
If the CPSR is defined by a copy, then we don't want to merge it into an IT
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block. E.g., if we have:
movs r1, r1
rsb r1, 0
movs r2, r2
rsb r2, 0
we don't want this to be converted to:
movs r1, r1
movs r2, r2
itt mi
rsb r1, 0
rsb r2, 0
PR11107 & <rdar://problem/10259534>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:52:53 +00:00
Eli Friedman
dca62d53b7
Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:28:47 +00:00
Benjamin Kramer
717073c237
X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141571 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 19:35:07 +00:00
Nadav Rotem
a7934dd8e4
Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
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instruction set has no 64-bit SRA support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 19:31:45 +00:00
Benjamin Kramer
a86a58695d
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:34:56 +00:00
Bill Wendling
eba564ceac
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
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hang, and possibly SPEC/CINT2006/464_h264ref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:27:30 +00:00
Bill Wendling
8129d21396
When getting the number of bits necessary for addressing mode
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ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
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2011-10-10 07:24:23 +00:00
Craig Topper
1f104804bf
Put a bunch of calls to ToggleFeature behind proper if statements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 05:34:02 +00:00
Chad Rosier
29b9d7e4ea
Fix a regression from r138445. If we're loading from the frame/base pointer
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the tADDrSPi instruction can't be used. Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707
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2011-10-10 01:03:35 +00:00
Justin Holewinski
68226a4d46
PTX: Print .ptr kernel attributes if PTX version >= 2.2
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 15:42:02 +00:00
Craig Topper
da394041c4
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen
b7994fedcb
Prevent potential NOREX bug.
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A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:
%vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2
If such a live range is ever split, its register class must not be
inflated to GR8. The sub-register copy can only target GR8_NOREX.
I dont have a test case for this theoretical bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 20:20:03 +00:00
Jakob Stoklund Olesen
ed74482704
Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
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In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.
TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.
This fixes PR11088.
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2011-10-08 18:28:28 +00:00
Nicolas Geoffray
f8557957fb
Always check if a method or a type exist before trying to create it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141490 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 11:56:36 +00:00
Anton Korobeynikov
2d4b60f3a4
Disable ABS optimization for Thumb1 target, we don't have necessary instructions there.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141481 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 08:38:45 +00:00
Akira Hatanaka
4391bb75ec
Simplify definition of FP move instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 03:50:18 +00:00
Akira Hatanaka
c9289f6a71
Define classes and multiclasses for FP binary instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141475 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 03:38:41 +00:00
Akira Hatanaka
bfca0798cf
Define multiclasses for FP-to-FP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141474 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 03:29:22 +00:00
Akira Hatanaka
a8de1c1be0
Define classes for FP unary instructions and multiclasses for FP-to-fixed point
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conversion instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141473 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 03:19:38 +00:00
Akira Hatanaka
cb518ee5dd
Add patterns for unaligned load and store instructions and enable the
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instruction selector to generate them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 02:24:10 +00:00
Jim Grosbach
460a90540b
ARM NEON assembly parsing and encoding for VDUP(scalar).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:56:00 +00:00
Jim Grosbach
21ff17ce1b
ARM prefix asmparser operand kind enums for readability.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:24:09 +00:00
Bill Wendling
2acf638216
Take all of the invoke basic blocks and make the dispatch basic block their new
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successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.
This more closely resembles what the CFG is actually doing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141436 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:18:02 +00:00
Bill Wendling
f1083d4139
Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit
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it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 22:08:37 +00:00
Bill Wendling
ce370cfd89
Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
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do. This will be useful later on with the new SJLJ stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 21:25:38 +00:00
Jakob Stoklund Olesen
b66f18486a
Constrain both operands on MOVZX32_NOREXrr8.
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This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.
Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.
This fixes a miscompilation in 20040709-2 in the gcc test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141410 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 20:15:54 +00:00
Jim Grosbach
186ffac4d3
Improve ARM assembly parser diagnostic for unexpected tokens.
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Consider:
mov r8, r11 fred
Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list
^
Now we generate:
x.s:5:14: error: unexpected token in argument list
mov r8, r11 fred
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 18:27:04 +00:00
Evan Cheng
7c1780c5fe
High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 17:21:44 +00:00
Bob Wilson
6d2f9cec71
Reenable tail calls for iOS 5.0 and later.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 17:17:49 +00:00
Bob Wilson
2fef4573df
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 16:59:21 +00:00
Anton Korobeynikov
244455e6d6
Peephole optimization for ABS on ARM.
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Patch by Ana Pazos!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 16:15:08 +00:00
Craig Topper
75fe5f3bab
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
Craig Topper
1b526a98e3
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:53:50 +00:00
Craig Topper
25f6dfd108
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:35:38 +00:00
Bill Wendling
217f0e9ca4
Use the correct vreg here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:41:14 +00:00
Bill Wendling
083a8eb063
Generate the dispatch code for a 'thumb' function. This is very similar to the
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others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:37:36 +00:00
Owen Anderson
7011eee9b5
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:33:11 +00:00