Chris Lattner
133ce871df
Teach codegen to handle:
...
(X != null) | (Y != null) --> (X|Y) != 0
(X == null) & (Y == null) --> (X|Y) == 0
so that instcombine can stop doing this for pointers. This is part of PR3351,
which is a case where instcombine doing this for pointers (inserting ptrtoint)
is pessimizing code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92406 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-02 00:00:03 +00:00
Chris Lattner
aac00392c3
rename file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-01 23:55:04 +00:00
Chris Lattner
f031e8ad01
Teach codegen to lower llvm.powi to an efficient (but not optimal)
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multiply sequence when the power is a constant integer. Before, our
codegen for std::pow(.., int) always turned into a libcall, which was
really inefficient.
This should also make many gfortran programs happier I'd imagine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92388 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-01 03:32:16 +00:00
Chris Lattner
0fba8cf9ff
Make this more likely to generate a libcall.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-01 03:26:51 +00:00
Sanjiv Gupta
223497e1ef
Extern declaration for unordered.f32 libcall was not being emitted. Fixed that.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92242 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-29 03:24:34 +00:00
Sanjiv Gupta
917283a418
Fixed llc crash for zext (i1 -> i8) loads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92201 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-28 04:53:24 +00:00
Chris Lattner
04b091a782
handle equality memcmp of 8 bytes on x86-64 with two unaligned loads and a
...
compare. On other targets we end up with a call to memcmp because we don't
want 16 individual byte loads. We should be able to use movups as well, but
we're failing to select the generated icmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92107 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-24 01:07:17 +00:00
Chris Lattner
8047d9a6be
move an optimization for memcmp out of simplifylibcalls and into
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SDISel. This optimization was causing simplifylibcalls to
introduce type-unsafe nastiness. This is the first step, I'll be
expanding the memcmp optimizations shortly, covering things that
we really really wouldn't want simplifylibcalls to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92098 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-24 00:37:38 +00:00
Sanjiv Gupta
76d2f9a4db
Reapply 91904.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91996 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23 11:19:09 +00:00
Sanjiv Gupta
e433d5e1f4
deleting empty file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91994 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23 10:35:24 +00:00
Sanjiv Gupta
6d48855a56
Reverting back 91904.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91993 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23 09:46:01 +00:00
Dale Johannesen
9949933d6e
Use more sensible type for flags in asms. PR 5570.
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Patch by Sylve`re Teissier (sorry, ASCII only).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23 07:32:51 +00:00
Eric Christopher
d060b2576a
Update objectsize intrinsic and associated dependencies. Fix
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lowering code and update testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91979 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23 02:51:48 +00:00
Anton Korobeynikov
a1508f9514
Add testcase for PR5703
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91931 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 22:37:23 +00:00
Evan Cheng
b1f4981333
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 17:47:23 +00:00
Sanjiv Gupta
66500208a5
While converting one of the operands to a memory operand, we need to check if it is Legal and does not result into a cyclic dep.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91904 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 14:25:37 +00:00
Sanjiv Gupta
bcfd12a234
Emit direction operand in binary insns that stores in memory.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91777 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-19 13:52:01 +00:00
Sanjiv Gupta
3f5d7642ce
Test cases for changes done in 91768.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91773 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-19 11:38:14 +00:00
Evan Cheng
9ab2b98ba5
Increase opportunities to optimize (brcond (srl (and c1), c2)).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91717 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 21:31:31 +00:00
Evan Cheng
400073d546
On recent Intel u-arch's, folding loads into some unary SSE instructions can
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be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 07:40:29 +00:00
Dan Gohman
f838e2366a
Tidy up this testcase and add test for tailcall optimization
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with unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91650 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 01:05:06 +00:00
Bob Wilson
5afffaed5c
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
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The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 01:03:29 +00:00
Dan Gohman
f042396b0f
Remove "tail" keywords. These calls are not intended to be tail calls.
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This protects this test from depending on codegen not performing the
tail call optimization by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91648 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 01:02:18 +00:00
Jakob Stoklund Olesen
f8ad5bcdb5
Add test case for the phi reuse patch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91642 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:11:44 +00:00
Sean Callanan
108934c65d
Instruction fixes, added instructions, and AsmString changes in the
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X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
Evan Cheng
4c2b001f13
Revert this dag combine change:
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Fold (zext (and x, cst)) -> (and (zext x), cst)
DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91574 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-17 00:40:05 +00:00
Nick Lewycky
0588bcef8d
Make this test pass on Linux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 07:35:25 +00:00
Evan Cheng
2e489c4f9d
Re-enable 91381 with fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 00:53:11 +00:00
Dale Johannesen
fc49bd2447
Do better with physical reg operands (typically, from inline asm)
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in local register allocator. If a reg-reg copy has a phys reg
input and a virt reg output, and this is the last use of the phys
reg, assign the phys reg to the virt reg. If a reg-reg copy has
a phys reg output and we need to reload its spilled input, reload
it directly into the phys reg than passing it through another reg.
Following 76208, there is sometimes no dependency between the def of
a phys reg and its use; this creates a window where that phys reg
can be used for spilling (this is true in linear scan also). This
is bad and needs to be fixed a better way, although 76208 works too
well in practice to be reverted. However, there should normally be
no spilling within inline asm blocks. The patch here goes a long way
towards making this actually be true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91485 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 00:29:41 +00:00
Kenneth Uildriks
76df3f398c
For fastcc on x86, let ECX be used as a return register after EAX and EDX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91410 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 03:27:52 +00:00
Evan Cheng
d7760a4905
Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91405 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 03:07:11 +00:00
Evan Cheng
9818c043d2
Make 91378 more conservative.
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1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91399 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 03:00:32 +00:00
Evan Cheng
ad9c0a3d8b
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 00:53:42 +00:00
Evan Cheng
8acb3100de
Fold (zext (and x, cst)) -> (and (zext x), cst).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 00:52:11 +00:00
Evan Cheng
99b653c36f
Propagate zest through logical shift.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91378 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 00:41:36 +00:00
Dan Gohman
2e141d744e
Fix integer cast code to handle vector types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91362 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14 23:40:38 +00:00
Evan Cheng
dd99f3a7dc
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91223 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-12 20:03:14 +00:00
Anton Korobeynikov
8d1ffbd1ad
Lower setcc branchless, if this is profitable.
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Based on the patch by Brian Lucas!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91175 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11 23:01:29 +00:00
Dan Gohman
87862e77bb
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91158 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11 21:31:27 +00:00
Dan Gohman
192db0027c
Change this to the correct PR number.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91148 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11 20:09:21 +00:00
Dan Gohman
a4f9cc4e55
Fix the result type of SELECT nodes lowered from Select instructions with
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aggregate return values. This fixes PR5754.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91145 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11 19:50:50 +00:00
Anton Korobeynikov
817a46454a
Honour setHasCalls() set from isel.
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This is used in some weird cases like general dynamic TLS model.
This fixes PR5723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91144 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11 19:39:55 +00:00
Evan Cheng
50d070561e
Tests for 91103 and 91104.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91105 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11 06:02:21 +00:00
Evan Cheng
6fd78ec8a2
It's not safe to coalesce a move where src and dst registers have different subregister indices. e.g.:
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%reg16404:1<def> = MOV8rr %reg16412:2<kill>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91061 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-10 20:59:45 +00:00
Evan Cheng
ce72f3fbdf
Fix test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09 22:24:42 +00:00
Evan Cheng
c363094e04
Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g.
...
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>
iff ptr is 16-byte aligned (or can be made into 16-byte aligned).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90984 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09 21:00:30 +00:00
Evan Cheng
7bd6478cd6
Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90925 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09 01:53:58 +00:00
Evan Cheng
d831cda3e7
- Support inline asm 'w' constraint for 128-bit vector types.
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- Also support the 'q' NEON registers asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-08 23:06:22 +00:00
Anton Korobeynikov
9aa1ec87b0
Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90819 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-08 01:03:04 +00:00
David Greene
e1a2fd5ad4
Use FileCheck and set nounwind on calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90790 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-07 19:40:26 +00:00
Dan Gohman
d84ea47b89
Don't enable the post-RA scheduler on x86 except at -O3. In its
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current form, it is too expensive in compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90781 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-07 19:04:31 +00:00
Anton Korobeynikov
7cca606aaa
Dynamic stack realignment use of sp register as source/dest register
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in "bic sp, sp, #15 " leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90724 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-06 22:39:50 +00:00
Bill Wendling
dc492e0370
Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90653 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05 07:30:23 +00:00
Jakob Stoklund Olesen
6b74e505be
Also attempt trivial coalescing for live intervals that end in a copy.
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The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.
The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.
This patch takes care of a few more cases that r90163 missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90502 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-04 00:16:04 +00:00
Nate Begeman
93e0ed31c5
Don't pull vector sext through both hands of a logical operation, since doing so prevents the fusion of vector sext and setcc into vsetcc.
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Add a testcase for the above transformation.
Fix a bogus use of APInt noticed while tracking this down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03 07:11:29 +00:00
Bob Wilson
324f4f1633
Recognize canonical forms of vector shuffles where the same vector is used for
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both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90417 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03 06:40:55 +00:00
Bill Wendling
3627b48110
Remove unnecessary check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90352 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-02 22:02:20 +00:00
Evan Cheng
9836a26da3
Fix PR5391: support early clobber physical register def tied with a use (ewwww)
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- A valno should be set HasRedefByEC if there is an early clobber def in the middle of its live ranges. It should not be set if the def of the valno is defined by an early clobber.
- If a physical register def is tied to an use and it's an early clobber, it just means the HasRedefByEC is set since it's still one continuous live range.
- Add a couple of missing checks for HasRedefByEC in the coalescer. In general, it should not coalesce a vr with a physical register if the physical register has a early clobber def somewhere. This is overly conservative but that's the price for using such a nasty inline asm "feature".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90269 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01 22:25:00 +00:00
Jim Grosbach
2a37b9c750
test case for IV-Users simplification loop improvement
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90260 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01 21:53:51 +00:00
Jakob Stoklund Olesen
579d6d9fe3
Use CFG connectedness as a secondary sort key when deciding the order of copy coalescing.
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This means that well connected blocks are copy coalesced before the less connected blocks. Connected blocks are more difficult to
coalesce because intervals are more complicated, so handling them first gives a greater chance of success.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90194 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01 03:03:00 +00:00
Evan Cheng
a4025df42d
Fix PR5614: parts of a physical register def may be killed the rest.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90180 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-01 00:44:45 +00:00
Jakob Stoklund Olesen
ce7a663140
New virtual registers created for spill intervals should inherit allocation hints from the original register.
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This helps us avoid silly copies when rematting values that are copied to a physical register:
leaq _.str44(%rip), %rcx
movq %rcx, %rsi
call _strcmp
becomes:
leaq _.str44(%rip), %rsi
call _strcmp
The coalescer will not touch the movq because that would tie down the physical register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90163 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-30 22:55:54 +00:00
Mon P Wang
8b6a20accd
Add test case for r90108
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90109 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-30 02:42:27 +00:00
Duncan Sands
fb245e2d46
While this test is testing a problem in the generic part of codegen,
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the problem only shows for msp430 and pic16 which is why it specifies
them using -march. But it is wrong to put such tests in CodeGen/Generic,
since not everyone builds these targets. Put a copy of the test in each
of the target test directories.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90005 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-27 16:04:14 +00:00
Evan Cheng
695b9f3d5e
Test for 89905.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89906 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-26 00:35:01 +00:00
Evan Cheng
e7c9195706
ProcessImplicitDefs should watch out for invalidated iterator and extra implicit operands on copies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89880 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-25 21:13:39 +00:00
Bruno Cardoso Lopes
d71cebf575
Support PIC loading of constant pool entries
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89863 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-25 12:17:58 +00:00
Dale Johannesen
f7801b493e
Do not store R31 into the caller's link area on PPC.
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This violates the ABI (that area is "reserved"), and
while it is safe if all code is generated with current
compilers, there is some very old code around that uses
that slot for something else, and breaks if it is stored
into. Adjust testcases looking for current behavior.
I've verified that the stack frame size is right in all
testcases, whether it changed or not. 7311323.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89811 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-24 22:59:02 +00:00
Evan Cheng
d7f0810c93
Enable predication of NEON instructions in Thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89748 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-24 08:06:15 +00:00
Anton Korobeynikov
5cdc3a949a
Materialize global addresses via movt/movw pair, this is always better
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than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-24 00:44:37 +00:00
Jim Grosbach
77b02beb1f
move fconst[sd] to UAL. <rdar://7414913>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89700 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23 21:08:25 +00:00
Jim Grosbach
bbf56bb37b
update test for 89694
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89695 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23 20:39:53 +00:00
Edward O'Callaghan
18d18b71d5
Miss two, PR5307.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89596 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 15:35:28 +00:00
Edward O'Callaghan
f4a93dd70e
Convert Thumb2 tests to FileCheck for PR5307.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89595 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 15:18:27 +00:00
Benjamin Kramer
bfd987ba57
Turns out stuff gets allocated to different registers depending on the subtarget.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89594 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 15:15:52 +00:00
Edward O'Callaghan
11cc4fab52
Convert ARM tests to FileCheck for PR5307.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89593 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 14:23:33 +00:00
Benjamin Kramer
3ebd44d20f
Convert test to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89589 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 13:16:36 +00:00
Edward O'Callaghan
de9b6b1cd5
Forgot to alter RUN line when converting to FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89588 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 13:09:48 +00:00
Edward O'Callaghan
85d1aab444
Fix for bad FileCheck converts in revision 89584.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89586 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 12:50:05 +00:00
Edward O'Callaghan
81fff07daf
Convert a few tests to FileCheck for PR5307.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89584 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 11:45:44 +00:00
Jim Grosbach
21ce2e3c74
Revert 89562. We're being sneakier than I was giving us credit for, and this
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isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89568 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21 23:34:09 +00:00
Jim Grosbach
f3b33d0b2a
Darwin requires a frame pointer for all non-leaf functions to support correct
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backtraces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89562 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21 21:40:08 +00:00
Jakob Stoklund Olesen
b99b63c2e5
Don't leave temporary files in the test directory.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89531 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21 02:05:31 +00:00
Dale Johannesen
5b8bce11d6
When generating a vector the really slow way, via loads
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and stores, handle the case where the element size is not
a valid target type correctly (PPC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21 00:53:23 +00:00
Evan Cheng
c26abd9487
Enable hoisting load from constant memories.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89510 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 23:31:34 +00:00
Sean Callanan
b9e6b34e1e
Recommitting PALIGNR shift width fixes.
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Thanks to Daniel Dunbar for fixing clang intrinsics:
http://llvm.org/viewvc/llvm-project?view=rev&revision=89499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89500 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 22:28:42 +00:00
Dale Johannesen
5ca124691b
Remove an incorrect overaggressive optimization
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(PPC specific).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89496 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 22:16:40 +00:00
Sean Callanan
1bbf6d1a6f
Reverting PALIGNR fix until I figure out how this
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broke the Clang testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89495 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 22:09:28 +00:00
Sean Callanan
201dfa7432
Fixed PALIGNR to take 8-bit rotations in all cases.
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Also fixed the corresponding testcase, and the PALIGNR
intrinsic (tested for correctness with llvm-gcc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89491 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 21:40:28 +00:00
Evan Cheng
4aedb61d03
Remat VLDRD from constpool. Clean up some instruction property specifications.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 19:57:15 +00:00
Duncan Sands
c088ae8b84
Fix PR5558, which was caused by a wrong fix for PR3393 (see commit 63048),
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which was an expensive checks failure due to a bug in the checking. This
patch in essence reverts the original fix for PR3393, and refixes it by a
tweak to the way expensive checking is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89454 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 10:45:10 +00:00
Dan Gohman
b4afb137ef
Fix fast-isel to avoid selecting the return instruction if a
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tail call has been encountered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89444 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 02:51:26 +00:00
Evan Cheng
9b82425cb0
Also CSE non-pic load from constant pools.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89440 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 02:10:27 +00:00
Evan Cheng
9ef4835bd8
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 00:54:03 +00:00
Daniel Dunbar
2b86caf05b
Unbreak test, Bruno please check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89329 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-19 07:18:49 +00:00
Evan Cheng
2ef9c8a43d
More consistent thumb1 asm printing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-19 06:57:41 +00:00
Evan Cheng
5b397c93a5
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89326 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-19 06:32:27 +00:00
Bruno Cardoso Lopes
2045c47aff
- Add sugregister logic to handle f64=(f32,f32).
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- Support mips1 like load/store of doubles:
Instead of:
sdc $f0, X($3)
Generate:
swc $f0, X($3)
swc $f1, X+4($3)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89322 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-19 06:06:13 +00:00
Bill Wendling
77bd09b650
Test from Dhrystone to make sure that we're not emitting an aligned load for a
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string that's aligned at 8-bytes instead of 16-bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89295 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-19 01:33:57 +00:00
Bob Wilson
41a0456a3c
Fix buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89274 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-18 23:30:38 +00:00
Richard Osborne
bea7df56ce
Add XCore support for indirectbr / blockaddress.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-18 23:20:42 +00:00
Bob Wilson
60f34b9fb0
Tail duplication still needs to iterate. Duplicating new instructions onto
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the tail of a block may make that block a new candidate for duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89264 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-18 22:52:37 +00:00
Jakob Stoklund Olesen
0b25ae1afb
Fix PR5300.
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When TwoAddressInstructionPass deletes a dead instruction, make sure that all
register kills are accounted for. The 2-addr register does not get special
treatment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89246 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-18 21:33:35 +00:00
Jakob Stoklund Olesen
5052c1547e
Fix inverted test and add testcase from failing self-host.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89167 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-18 00:02:18 +00:00
Jakob Stoklund Olesen
6c8a0715c4
Remove fragile test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89150 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 21:52:40 +00:00
Jim Grosbach
f04777b945
Enable arm jumpt table adjustment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89143 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 21:24:11 +00:00
Anton Korobeynikov
d2aad77261
Forgot to commit test fixes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89138 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 20:38:36 +00:00
Jakob Stoklund Olesen
95a2c8f1d0
Enable -split-phi-edges by default, except when -regalloc=local.
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The local register allocator doesn't like it when LiveVariables is run.
We should also disable edge splitting under -O0, but that has to wait a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89125 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 19:15:50 +00:00
Evan Cheng
9e97f3c2e2
Revert 89021. It's miscompiling llvm-gcc driver driver at -O0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89082 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 09:55:52 +00:00
Jakob Stoklund Olesen
2cbe71cdf0
Enable -split-phi-edges by default
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89021 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 01:07:22 +00:00
Evan Cheng
6cccc30679
MOV64rm should be marked isReMaterializable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89019 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 00:55:55 +00:00
Jim Grosbach
1187285e90
Convert to FileCheck
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89007 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 00:20:26 +00:00
Jim Grosbach
727f0c37fb
Convert to FileCheck
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89002 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 00:03:38 +00:00
Jim Grosbach
2c0fb63738
Cleanup. Missed removing these when converting. Oops.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89001 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-17 00:00:33 +00:00
Dan Gohman
1d8c9e721e
Fix this test - there don't appear to be any actual Reload Reuses
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in this testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88998 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 23:49:55 +00:00
Dan Gohman
10190cceec
Revert r87049, which was the workaround for the regression triggered
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by the recent FixedStackPseudoSourceValue-related changes, now that
the specific bug that affected it is fixed, in r88954.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88997 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 23:43:42 +00:00
Jim Grosbach
9f07f3b009
Convert to FileCheck
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88991 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 23:19:29 +00:00
Evan Cheng
600c043697
- Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots.
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- Mark MOVUPSrm re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88974 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 21:56:03 +00:00
Jim Grosbach
2f74603460
Convert to FileCheck
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88947 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 20:04:15 +00:00
Lang Hames
0d6dd493f4
Added a testcase for PR5495.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88946 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 20:03:13 +00:00
Jim Grosbach
4adcade9b7
Convert to FileCheck
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88942 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 19:46:46 +00:00
Jim Grosbach
c0517504e5
tbb opt off by default
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88921 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 17:24:45 +00:00
David Greene
ddff941357
Support spill comments.
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Have the asm printer emit a comment if an instruction is a spill or
reload and have the spiller mark copies it introdues so the asm printer
can also annotate those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 15:12:23 +00:00
Evan Cheng
39aa7251a2
Check if subreg index is zero.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88899 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 06:31:49 +00:00
Evan Cheng
285a7d57dc
For some targets, a copy can use a register multiple times, e.g. ppc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88895 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 05:52:06 +00:00
Evan Cheng
2d947263d5
xfail for now. It has been failing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88892 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 05:44:04 +00:00
Bruno Cardoso Lopes
6e0b658dad
- Fix a small bug while handling target constant pools (one param was missing).
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- Add a smarter constant pool loading, instead of:
lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)
Generate:
lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88886 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-16 04:33:42 +00:00
Jim Grosbach
a44321776e
Detect need for autoalignment of the stack earlier to catch spills more
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conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-15 21:45:34 +00:00
Jim Grosbach
e11d26b3d8
remove xfail
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88817 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 21:57:35 +00:00
Richard Osborne
13c4fabf99
Add XCore support for arbitrary-sized aggregate returns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88802 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 19:33:35 +00:00
Evan Cheng
fae3e92345
Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88753 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 03:42:17 +00:00
Evan Cheng
d57cdd5683
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
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- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 02:55:43 +00:00
Evan Cheng
e17ae4f82e
Add radar number.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88739 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 02:11:32 +00:00
Evan Cheng
8fdd84cfa7
Fix PR5412: Fix an inverted check and another missing sub-register check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88738 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 02:09:09 +00:00
Dan Gohman
ed9bab3b4d
Enable the tail call optimization when the caller returns undef.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88737 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 02:06:30 +00:00
Evan Cheng
0cd22dd738
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14 01:50:00 +00:00
Evan Cheng
1f6a3c820a
Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88719 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 23:16:41 +00:00
Dan Gohman
c4c550c758
When optimizing for size, don't tail-merge unless it's likely to be a
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code-size win, and not when it's only likely to be code-size neutral,
such as when only a single instruction would be eliminated and a new
branch would be required.
This fixes rdar://7392894.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88692 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 21:02:15 +00:00
Evan Cheng
236490d870
Fix PR5410: LiveVariables lost subreg def:
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D0<def,dead> = ...
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= S0<use, kill>
S0<def> = ...
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D0<def> =
The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88690 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 20:36:40 +00:00
Dan Gohman
01205a80f5
Don't let a noalias difference disrupt the tailcall optimization.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88672 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 18:49:38 +00:00
Dale Johannesen
1e608819aa
Adjust isConstantSplat to allow for big-endian targets.
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PPC is such a target; make it work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87060 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 01:45:18 +00:00
Daniel Dunbar
6242495be2
Update test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87049 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 01:01:58 +00:00
Jim Grosbach
cb2c2b738a
Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86997 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 17:19:09 +00:00
Benjamin Kramer
9e3728be62
Fix typo in run line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86984 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 12:35:27 +00:00
Evan Cheng
60f9061820
RegScavenger::enterBasicBlock should always reset register state.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86972 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 07:49:10 +00:00
Evan Cheng
586f69a118
- Teach LSR to avoid changing cmp iv stride if it will create an immediate that
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cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86969 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 07:35:05 +00:00
Dan Gohman
ad6af45dc1
Tail merge at any size when there are two potentials blocks and one
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can be made to fall through into the other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86909 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12 00:39:10 +00:00
Kenneth Uildriks
c158dde219
x86 users can now return arbitrary sized structs. Structs too large to fit in return registers will be returned through a hidden sret parameter introduced during SelectionDAG construction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86876 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 19:59:24 +00:00
Dan Gohman
2210c0bea8
Add support for tail duplication to BranchFolding, and extend
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tail merging support to handle more cases.
- Recognize several cases where tail merging is beneficial even when
the tail size is smaller than the generic threshold.
- Make use of MachineInstrDesc::isBarrier to help detect
non-fallthrough blocks.
- Check for and avoid disrupting fall-through edges in more cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86871 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 19:48:59 +00:00
Evan Cheng
012397489b
Add nounwind.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86814 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11 07:11:02 +00:00