Dan Gohman
89b20c07e9
Make the comment for ScalarizeVectorOp mention that it is only for use
...
with single-element vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37752 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-27 14:06:22 +00:00
Dan Gohman
7f32156bb9
Generalize MVT::ValueType and associated functions to be able to represent
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extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37719 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-25 16:23:39 +00:00
Dan Gohman
ea859be53c
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 14:59:07 +00:00
Evan Cheng
0b2ce1fc19
std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37701 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 01:35:51 +00:00
Dan Gohman
2d74a318de
Tidy up ValueType names in comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37688 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-21 14:48:26 +00:00
Dan Gohman
b9f1019696
Rename TargetLowering::getNumElements and friends to
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TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37687 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-21 14:42:22 +00:00
Evan Cheng
b13cdbd865
Xforms:
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(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37685 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-21 07:39:16 +00:00
Dan Gohman
b5bec2b6f6
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
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for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37656 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 14:13:56 +00:00
Chris Lattner
aeeccfc5b2
add isVarArg to CCState
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37640 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 00:11:09 +00:00
Chris Lattner
e10e6f7a36
make ComputeTopDownOrdering significantly faster and use less stack space
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by making it non-recursive
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37629 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-18 21:28:10 +00:00
Dan Gohman
7a0a4fc912
Make chain dependencies blue, in addition to being dashed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37626 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-18 15:30:16 +00:00
Tanya Lattner
24e5aada7d
Codegen support (stripped out) for the annotate attribute.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37608 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-15 22:26:58 +00:00
Chris Lattner
c2c28fc24c
Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info
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for tied register constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37601 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-15 19:11:01 +00:00
Duncan Sands
f40708223e
Workaround for PR1508.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37597 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-15 19:04:19 +00:00
Dan Gohman
51eaa86758
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37579 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-14 22:58:02 +00:00
Duncan Sands
ea632439d4
Only correctly lower exception handing intrinsics if exception handling is
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turned on. Likewise for scanning of invokes to mark landing pads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37570 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-13 16:53:21 +00:00
Dan Gohman
6595635175
Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and
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VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.
This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37569 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-13 15:12:02 +00:00
Dan Gohman
2046e12f02
When creating CopyFromReg nodes, always use legal types. And use the
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correct types for the result vector, even though it is currently bitcasted
to a different type immediately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37568 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-13 14:55:16 +00:00
Duncan Sands
f19f6bb31e
The fix that was applied for PR1224 stops the compiler
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crashing but breaks exception handling. The problem
described in PR1224 is that invoke is a terminator that
can produce a value. The value may be needed in other
blocks. The code that writes to registers values needed
in other blocks runs before terminators are lowered (in
this case invoke) so asserted because the value was not
yet available. The fix that was applied was to do invoke
lowering earlier, before writing values to registers.
The problem this causes is that the code to copy values
to registers can be output after the invoke call. If
an exception is raised and control is passed to the
landing pad then this copy-code will never execute. If
the value is needed in some code path reached via the
landing pad then that code will get something bogus.
So revert the original fix and simply skip invoke values
in the general copying to registers code. Instead copy
the invoke value to a register in the invoke lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37567 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-13 05:51:31 +00:00
Dale Johannesen
62000eee7d
Do not change the size of function arguments. PR 1489.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37496 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-07 21:07:15 +00:00
Duncan Sands
9fac0b5ff2
Additional fix for PR1422: make sure the landing pad label is placed in the
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correct machine basic block - do not rely on the eh.exception intrinsic
being in the landing pad: the loop optimizers can move it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37463 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-06 10:05:18 +00:00
Dan Gohman
3983358555
Pass the DAG to SDNode::dump to let it do more detailed dumps in some cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37413 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-04 16:17:33 +00:00
Dan Gohman
575e2f4ea8
Resolve implicit alignment before computing the FoldingSet information so
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that the CSE map always contains explicit alignment information. This allows
more loads to be CSE'd when there is a mix of explicit-alignment loads and
implicit-alignment loads.
Also, in SelectionDAG::FindModifiedNodeSlot, add the operands to the
FoldingSetNodeID before the load/store information instead of after, so
that it matches what is done elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-04 15:49:41 +00:00
Duncan Sands
73ef58ab92
Integrate exception filter support and exception catch support. This
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simplifies the code in DwarfWriter, allows for multiple filters and
makes it trivial to specify filters accompanied by cleanups or catch-all
specifications (see next patch). What a deal! Patch blessed by Anton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37398 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-02 16:53:42 +00:00
Duncan Sands
398898cc6a
Since TypeInfos are passed as i8 pointers, a NULL TypeInfo should be passed
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as a null i8 pointer not as a 0 i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37383 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-01 08:18:30 +00:00
Chris Lattner
4e7e6cd13a
Fix CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll, and PR1473.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37362 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-30 16:30:06 +00:00
Chris Lattner
3adf951364
tighten up recursion depth again
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37330 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-25 02:19:06 +00:00
Dan Gohman
fa73ea2d9f
Minor comment cleanups.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37321 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-24 14:36:04 +00:00
Dan Gohman
237898ac1f
Add explicit qualification for namespace MVT members.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37320 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-24 14:33:05 +00:00
Evan Cheng
c843abe868
Fix a typo that caused combiner to create mal-formed pre-indexed store where value store is the same as the base pointer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37318 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-24 02:35:39 +00:00
Anton Korobeynikov
070280e97f
Mark all calls as "could throw", when exceptions are enabled. Emit necessary LP info too. This fixes PR1439
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37311 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-23 11:08:31 +00:00
Chris Lattner
501fee71e0
prevent exponential recursion in isNegatibleForFree
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37310 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-23 07:35:22 +00:00
Chris Lattner
7667c0bac3
same patch as the previous one, but the symmetric case
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37249 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-19 00:46:51 +00:00
Chris Lattner
2ad913b342
Disable the (A == (B-A)) -> 2*A == B xform when the sub has multiple uses (in
...
this case, the xform introduces an extra operation). This compiles
PowerPC/compare-duplicate.ll into:
_test:
subf r2, r3, r4
cmplw cr0, r2, r3
bne cr0, LBB1_2 ;F
instead of:
_test:
slwi r2, r3, 1
subf r3, r3, r4
cmplw cr0, r4, r2
bne cr0, LBB1_2 ;F
This is target independent of course.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37246 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-19 00:43:44 +00:00
Dan Gohman
fcc4dd91e5
Qualify calls to getTypeForValueType with MVT:: too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37233 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 18:41:29 +00:00
Dan Gohman
b55757ec5f
Qualify several calls to functions in the MVT namespace, for consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37230 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 17:52:13 +00:00
Chris Lattner
3fc5b01d38
disable MaskedValueIsZero, ComputeMaskedBits, and SimplifyDemandedBits for
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i128 integers. The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37169 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-17 18:19:23 +00:00
Chris Lattner
b429f7303e
add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37168 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-17 18:15:41 +00:00
Evan Cheng
d60483ef99
Add target hook to specify block size limit for if-conversion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37134 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 23:45:53 +00:00
Dale Johannesen
98a6c62aff
Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37130 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 22:45:30 +00:00
Chris Lattner
c76d4410ab
Use a ptr set instead of a linear search to unique TokenFactor operands.
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This fixes PR1423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37102 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 06:37:59 +00:00
Evan Cheng
93003b8cf2
Bug fix: should check ABI alignment, not pref. alignment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37094 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 02:04:50 +00:00
Lauro Ramos Venancio
b5bb7ffa9c
Fix an infinite recursion in GetNegatedExpression.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37086 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-15 17:05:43 +00:00
Chris Lattner
c90233b836
Fix some subtle issues handling immediate values. This fixes
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test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37069 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-15 01:33:58 +00:00
Chris Lattner
2944652569
implement a simple fneg optimization/propagation thing. This compiles:
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CodeGen/PowerPC/fneg.ll into:
_t4:
fmul f0, f3, f4
fmadd f1, f1, f2, f0
blr
instead of:
_t4:
fneg f0, f3
fmul f0, f0, f4
fmsub f1, f1, f2, f0
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37054 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-14 22:04:50 +00:00
Evan Cheng
2c4f94363a
Can't fold the bit_convert is the store is a truncating store.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36962 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-09 21:49:47 +00:00
Anton Korobeynikov
7294b58ecd
Do not assert, when case range split metric is zero and JTs are not allowed: just emit binary tree in this case. This
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fixes PR1403.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36959 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-09 20:07:08 +00:00
Evan Cheng
c2cd2b29f5
Forgot a check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36910 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-07 21:36:06 +00:00
Evan Cheng
59d5b68dff
Enable a couple of xforms:
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- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36908 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-07 21:27:48 +00:00
Duncan Sands
4fee7034d5
Parameter attributes on invoke calls were being lost due to the wrong
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attribute index being used. Fix proposed by Anton Korobeynikov, who
asked me to implement and commit it for him. This is PR1398.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36906 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-07 20:49:28 +00:00
Anton Korobeynikov
b682448ebd
Detabify
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36891 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-06 20:14:21 +00:00
Chris Lattner
b464c44679
Propagate alignment/volatility in two places.
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Implement support for expanding a bitcast from an illegal vector type to
a legal one (e.g. 4xi32 -> 4xf32 in SSE1). This fixes PR1371 and
CodeGen/X86/2007-05-05-VecCastExpand.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36787 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-05 19:39:05 +00:00
Duncan Sands
3b346368de
A bitcast of a global variable may have been constant folded to a GEP -
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handle this case too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36745 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-04 17:12:26 +00:00
Evan Cheng
a7d4a04d24
Don't create indexed load / store with zero offset!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36716 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 23:52:19 +00:00
Chris Lattner
75c7d2bd55
Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
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and PR1382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36672 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 16:54:34 +00:00
Devang Patel
1997473cf7
Drop 'const'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 01:11:54 +00:00
Anton Korobeynikov
6ad8256d76
Properly set arguments bitwidth of EHSELECT node
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36654 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-02 22:15:48 +00:00
Devang Patel
3e15bf33e0
Use 'static const char' instead of 'static const int'.
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Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-02 21:39:20 +00:00
Devang Patel
794fd75c67
Do not use typeinfo to identify pass in pass manager.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 21:15:47 +00:00
Evan Cheng
498f55989a
Forgot about chain result; also UNDEF cannot have multiple values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36622 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 08:53:39 +00:00
Evan Cheng
45a7ca9b23
* Only turn a load to UNDEF if all of its outputs have no uses (indexed loads
...
produce two results.)
* Do not touch volatile loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36604 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 00:38:21 +00:00
Chris Lattner
e7cf56aeee
Continue refactoring inline asm code. If there is an earlyclobber output
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register, preallocate all input registers and the early clobbered output.
This fixes PR1357 and CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36599 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-30 21:11:17 +00:00
Chris Lattner
bf996f1d5e
refactor GetRegistersForValue to take OpInfo as an argument instead of various
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pieces of it. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36592 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-30 17:29:31 +00:00
Chris Lattner
3ff90dc1c8
refactor some code, no functionality change
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36590 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-30 17:16:27 +00:00
Chris Lattner
6995cf6015
generalize aggregate handling
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36568 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-29 18:58:03 +00:00
Chris Lattner
09e4b7e1b7
memory operands that have a direct operand should have their stores created
...
before the copies into physregs are done. This avoids having flag operands
skip the store, causing cycles in the dag at sched time. This fixes infinite
loops on these tests:
test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308
test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36547 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28 21:12:06 +00:00
Chris Lattner
c83994e5d4
eliminate more redundant constraint type analysis
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36546 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28 21:03:16 +00:00
Chris Lattner
2a600be226
merge constraint type analysis stuff together.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36545 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28 21:01:43 +00:00
Chris Lattner
0c58340aea
Significant refactoring of the inline asm stuff, to support future changes.
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36544 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28 20:49:53 +00:00
Chris Lattner
44b2c5098f
memory inputs to an inline asm are required to have an address available.
...
If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.
This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36536 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28 06:42:38 +00:00
Chris Lattner
f2f3cd5129
Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll and
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CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36534 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28 06:08:13 +00:00
Chris Lattner
b017318122
Fix this to match change to InlineAsm class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36524 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28 04:05:59 +00:00
Chris Lattner
eb7f34f2cb
Fix incorrect legalization of EHSELECTOR. This fixes
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CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36510 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27 17:12:52 +00:00
Evan Cheng
4c6cfad85e
Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36501 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27 07:33:31 +00:00
Chris Lattner
99f9a77c49
improve EH global handling, patch by Duncan Sands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36499 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27 01:20:11 +00:00
Chris Lattner
64c0f84c72
enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrap
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successfully! woohoo...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36496 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-26 21:09:43 +00:00
Anton Korobeynikov
ab8fd40403
Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36490 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-26 20:44:04 +00:00
Dan Gohman
edc1d15984
Fix a typo in a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36485 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-26 19:40:56 +00:00
Evan Cheng
c1a3520580
This was lefted out. Fixed sumarray-dbl.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36445 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25 18:33:21 +00:00
Chris Lattner
6266c18ea1
allow support for 64-bit stack objects
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36420 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25 04:08:28 +00:00
Chris Lattner
964dd86054
Be more careful about folding op(x, undef) when we have vector operands.
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This fixes CodeGen/X86/2007-04-24-VectorCrash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36413 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25 00:00:45 +00:00
Bill Wendling
95b3955034
Assertion when using a 1-element vector for an add operation. Get the
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real vector type in this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36402 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-24 21:13:23 +00:00
Scott Michel
f147a8d56e
Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about
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tests always being true in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36387 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-24 01:24:20 +00:00
Christopher Lamb
95c218a83e
PR400 phase 2. Propagate attributed load/store information through DAGs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36356 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-22 23:15:30 +00:00
Lauro Ramos Venancio
2c5c111b6c
X86 TLS: Implement review feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36318 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-21 20:56:26 +00:00
Reid Spencer
c67bdc288a
Revert Christopher Lamb's load/store alignment changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36309 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-21 18:36:27 +00:00
Christopher Lamb
2330e4d4c4
add support for alignment attributes on load/store instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36301 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-21 08:16:25 +00:00
Lauro Ramos Venancio
0d3b67809c
Allow the lowering of ISD::GLOBAL_OFFSET_TABLE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36290 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-20 23:02:39 +00:00
Lauro Ramos Venancio
b3a0417cad
Implement "general dynamic", "initial exec" and "local exec" TLS models for
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X86 32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-20 21:38:10 +00:00
Chris Lattner
61a4c072b9
allow SRL to simplify its operands, as it doesn't demand all bits as input.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36245 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18 03:06:49 +00:00
Chris Lattner
ec06e9a670
When replacing a node in SimplifyDemandedBits, if the old node used any
...
single-use nodes, they will be dead soon. Make sure to remove them before
processing other nodes. This implements CodeGen/X86/shl_elim.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36244 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18 03:05:22 +00:00
Chris Lattner
0a16a1f738
fix a pasto
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36242 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18 03:01:40 +00:00
Chris Lattner
8c7d2d56bf
Fix a bug in my previous patch, grabbing the shift amount width from the
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wrong operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36223 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17 22:53:02 +00:00
Chris Lattner
895c4ab564
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
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This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36221 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17 21:14:16 +00:00
Chris Lattner
95a5e0507e
SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits
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a chance to hack on it. This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
instead of:
_baz:
srwi r2, r4, 24
rlwimi r2, r3, 8, 0, 23
srwi r2, r2, 9
extsh r3, r2
blr
This implements CodeGen/PowerPC/sign_ext_inreg1.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36212 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17 19:03:21 +00:00
Anton Korobeynikov
bed2946a96
Removed tabs everywhere except autogenerated & external files. Add make
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target for tabs checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-16 18:10:23 +00:00
Chris Lattner
1c35968d4d
disable switch lowering using shift/and. It still breaks ppc bootstrap for
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some reason. :( Will investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36011 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-14 19:39:41 +00:00
Anton Korobeynikov
e01017bba4
Fix PR1325: Case range optimization was performed in the case it
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shouldn't. Also fix some "latent" bug on 64-bit platforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35990 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-14 13:25:55 +00:00
Chris Lattner
3ff981749b
disable shift/and lowering to work around PR1325 for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35985 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-14 02:26:56 +00:00
Anton Korobeynikov
8085bcfdca
Fix PR1323 : we haven't updated phi nodes in good manner :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35963 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-13 06:53:51 +00:00
Chris Lattner
3a508c94a6
the result of an inline asm copy can be an arbitrary VT that the register
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class supports. In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector
result to the right type. This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35944 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12 06:00:20 +00:00
Chris Lattner
4829b1c6ab
fold noop vbitconvert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35943 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12 05:58:43 +00:00
Chris Lattner
c2941779c3
Fix weirdness handling single element vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35941 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12 04:44:28 +00:00
Reid Spencer
f75b874957
For PR1284:
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Implement the "part_set" intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35938 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12 02:48:46 +00:00
Chris Lattner
c24bbaddf8
fix an infinite loop compiling ldecod, notice by JeffC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35910 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 16:51:53 +00:00
Chris Lattner
1eba01e9a0
Fix this harder.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35888 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 06:50:51 +00:00
Chris Lattner
c56a81dff1
don't create shifts by zero, fix some problems with my previous patch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35887 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 06:43:25 +00:00
Chris Lattner
20a35c3fa5
Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often
...
allows other simplifications. For example, this compiles:
int isnegative(unsigned int X) {
return !(X < 2147483648U);
}
Into this code:
x86:
movl 4(%esp), %eax
shrl $31, %eax
ret
arm:
mov r0, r0, lsr #31
bx lr
thumb:
lsr r0, r0, #31
bx lr
instead of:
x86:
cmpl $0, 4(%esp)
sets %al
movzbl %al, %eax
ret
arm:
mov r3, #0
cmp r0, #0
movlt r3, #1
mov r0, r3
bx lr
thumb:
mov r2, #1
mov r1, #0
cmp r0, #0
blt LBB1_2 @entry
LBB1_1: @entry
cpy r2, r1
LBB1_2: @entry
cpy r0, r2
bx lr
Testcase here: test/CodeGen/Generic/ispositive.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35883 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 05:32:27 +00:00
Chris Lattner
1982ef20c4
Codegen integer abs more efficiently using the trick from the PPC CWG. This
...
improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll
X86 Old: X86 New:
_test: _test:
movl 4(%esp), %ecx movl 4(%esp), %eax
movl %ecx, %eax movl %eax, %ecx
negl %eax sarl $31, %ecx
testl %ecx, %ecx addl %ecx, %eax
cmovns %ecx, %eax xorl %ecx, %eax
ret ret
PPC Old: PPC New:
_test: _test:
cmpwi cr0, r3, -1 srawi r2, r3, 31
neg r2, r3 add r3, r3, r2
bgt cr0, LBB1_2 ; xor r3, r3, r2
LBB1_1: ; blr
mr r3, r2
LBB1_2: ;
blr
ARM Old: ARM New:
_test: _test:
rsb r3, r0, #0 add r3, r0, r0, asr #31
cmp r0, #0 eor r0, r3, r0, asr #31
movge r3, r0 bx lr
mov r0, r3
bx lr
Thumb Old: Thumb New:
_test: _test:
neg r2, r0 asr r2, r0, #31
cmp r0, #0 add r0, r0, r2
bge LBB1_2 eor r0, r2
LBB1_1: @ bx lr
cpy r0, r2
LBB1_2: @
bx lr
Sparc Old: Sparc New:
test: test:
save -96, %o6, %o6 save -96, %o6, %o6
sethi 0, %l0 sra %i0, 31, %l0
sub %l0, %i0, %l0 add %i0, %l0, %l1
subcc %i0, -1, %l1 xor %l1, %l0, %i0
bg .BB1_2 restore %g0, %g0, %g0
nop retl
.BB1_1: nop
or %g0, %l0, %i0
.BB1_2:
restore %g0, %g0, %g0
retl
nop
It also helps alpha/ia64 :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35881 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 05:11:38 +00:00
Reid Spencer
18da072088
For PR1146:
...
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35877 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 02:44:20 +00:00
Chris Lattner
c6eb6d7255
apparently some people commit without building the tree, or they forget to
...
commit a LOT of files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35858 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-10 03:20:39 +00:00
Jeff Cohen
2da8da46ba
No longer needed.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35850 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 23:42:32 +00:00
Chris Lattner
2b95fd67da
remove dead target hooks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35847 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 23:34:08 +00:00
Chris Lattner
b445d0cbb9
remove some dead target hooks, subsumed by isLegalAddressingMode
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 22:27:04 +00:00
Anton Korobeynikov
54e2b142be
Use integer log for metric calculation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35834 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 21:57:03 +00:00
Jeff Cohen
efc3662636
Unbreak VC++ build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35817 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 14:32:59 +00:00
Anton Korobeynikov
4198c58c71
Next stage into switch lowering refactoring
...
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35816 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 12:31:58 +00:00
Reid Spencer
5694b6e90e
For PR1146:
...
Adapt handling of parameter attributes to use the new ParamAttrsList class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35814 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 06:17:21 +00:00
Chris Lattner
1a6acc214d
implement CodeGen/X86/inline-asm-x-scalar.ll:test3
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35802 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 05:31:20 +00:00
Chris Lattner
ff33cc4d08
add some assertions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35800 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 05:23:13 +00:00
Chris Lattner
4b993b19f9
Fix PR1316
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35783 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 00:33:58 +00:00
Chris Lattner
921169b103
Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35779 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-08 22:23:26 +00:00
Chris Lattner
e303ac9052
minor comment fix
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35696 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-06 17:47:14 +00:00
Reid Spencer
3f108cb555
Change the bit_part_select (non)implementation from "return 0" to abort.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35679 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-05 01:20:18 +00:00
Reid Spencer
addd11d98e
Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35678 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-04 23:48:25 +00:00
Anton Korobeynikov
5502bf67cd
Properly emit range comparisons for switch cases, where neighbour cases
...
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35672 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-04 21:14:49 +00:00
Scott Michel
c9dc114578
1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
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2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35605 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-02 21:36:32 +00:00
Reid Spencer
a4f9c4d29a
For PR1297:
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Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35546 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-01 07:34:11 +00:00
Reid Spencer
577cc32d9a
For PR1297:
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Change getOperationName to return std::string instead of const char*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35545 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-01 07:32:19 +00:00
Chris Lattner
c8d288f8fa
move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35529 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-31 04:18:03 +00:00
Chris Lattner
d2f340b746
switch TL::getValueType to use MVT::getValueType.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35527 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-31 04:05:24 +00:00
Chris Lattner
1436bb657d
add one addressing mode description hook to rule them all.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35520 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30 23:14:50 +00:00
Dale Johannesen
2041a0ef75
Fix incorrect combination of different loads. Reenable zext-over-truncate
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combination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30 21:38:07 +00:00
Evan Cheng
b0b6c76ffe
Disable load width reduction xform of variant (zext (truncate load x)) for
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big endian targets until llvm-gcc build issue has been resolved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35449 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-29 07:56:46 +00:00
Evan Cheng
7aff11a1ed
Scale 1 is always ok.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35407 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28 01:55:52 +00:00
Evan Cheng
caaf69107e
Remove isLegalAddressImmediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35406 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28 01:53:55 +00:00
Evan Cheng
baeccc8741
GEP index sinking fixes:
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1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35403 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28 01:49:39 +00:00
Anton Korobeynikov
dd43321079
Remove dead code
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35380 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 12:05:48 +00:00
Anton Korobeynikov
b17b08d1f2
Split big monster into small helpers. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35379 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 11:29:11 +00:00
Evan Cheng
d0083bc5ec
SDISel does not preserve all, it changes CFG and other info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35376 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 00:53:36 +00:00
Evan Cheng
15213b77cf
SIGN_EXTEND_INREG requires one extra operand, a ValueType node.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35350 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-26 07:12:51 +00:00
Anton Korobeynikov
3a84b9baf6
First step of switch lowering refactoring: perform worklist-driven
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strategy, emit JT's where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35338 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-25 15:07:15 +00:00
Chris Lattner
5df99b376f
Implement support for vector operands to inline asm, implementing
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CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35332 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-25 05:00:54 +00:00
Chris Lattner
c13dd1cf4c
implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35327 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-25 04:35:41 +00:00
Chris Lattner
065421f99f
Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35324 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-25 02:18:14 +00:00
Chris Lattner
4234f57fa0
switch TargetLowering::getConstraintType to take the entire constraint,
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not just the first letter. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-25 02:14:49 +00:00
Chris Lattner
82dcb4fe23
don't rely on ADL
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35299 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-24 17:37:03 +00:00
Evan Cheng
dae54ce7fc
Adjust offset to compensate for big endian machines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35293 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-24 00:02:43 +00:00
Evan Cheng
e177e307fc
Make sure SEXTLOAD of the specific type is supported on the target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35289 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23 22:13:36 +00:00
Evan Cheng
b37b80ce46
Also replace uses of SRL if that's also folded during ReduceLoadWidth().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35286 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23 20:55:21 +00:00