MO_VirtualRegister but if the register number is one of a physical
register is it considered as a physical register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11315 91177308-0d34-0410-b5e6-96231b3b80d8
I will observe that the concept of using WriteAsOperand is completely broken,
but then we all knew that, didn't we?
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instead of randomly groping about inside its outEdges array.
Make SchedGraph::addDummyEdges() use getNumOutEdges() instead of
outEdges.size().
Get rid of ifdefed-out code in SchedGraph::buildGraph().
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It's not clear why the code was looking for signed chars < 0, but it can't
matter to the assembler anyway, so the check goes away. This also fixes
compatibility with arrays of [us]byte that have constantexprs in them.
Also slightly restructure some code to be cleaner.
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Using the SlotCalculator is total overkill for this file, a simple map
will suffice. Why doesn't this use the NameMangler interface?
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implementation of a Target{RegInfo, InstrInfo, Machine, etc} now has a separate
header and a separate implementation file.
This means that instead of a massive SparcInternals.h that forces a
recompilation of the whole target whenever a minor detail is changed, you should
only recompile a few files.
Note that SparcInternals.h is still around; its contents should be minimized.
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a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
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* Restore registers *after* everything else to avoid any possible side effects
This fixes McCat-imp.
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* There is now only one pass to print out assembly instead of two
* It is a FunctionPass
* The Module-level printing of globals is now in doFinalization() method of the
FunctionPass
* The code has been reformatted to follow LLVM coding standards
* Some comments, not all, were doxygenified
* Last but not least, the function to create an instance of this pass is also no
longer a method in the UltraSparc class.
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externally-visible linkage, and SaveStateToModule must default to true for llc.
I don't remember why I made it const; perhaps it should be deconstified.
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each instruction produces as "operand" -1, and the other operands as 0
.. n, as before. PhyRegAlloc::saveState() is refactored into
PhyRegAlloc::saveStateForValue().
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for the Sparc backend: breaking up constant expressions. Thus, we cannot have it
guarded by a conditional, it should never be disabled.
Also, it's now available for the JIT since it is a FunctionPass.
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MachineConstantPool. This involved refactoring the two classes involved in
printing out Sparc assembly. In fact, they should share all this code anyway.
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it will be converted to a MachineConstantPool index during instruction
selection
* This is now eligible to become a FunctionPass since it does not have any side
effects outside of the function it is processing.
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implementing verifySavedState().
In saveState(), use the new AllocInfo::AllocStateTy enum, and increment
Insn each time through the loop.
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Prototype option to save state in a global instead of as a Constant in
the Module. (Turned off, for now, with the on/off switch welded in the off
position. You get the idea.)
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Make FnAllocState contain vectors of AllocInfo, instead of LLVM Constants.
Give doFinalization a method comment, and let it do the work of converting
AllocInfos to LLVM Constants.
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* Fix order of #includes
* Make code layout more consistent
* Eliminate extraneous whitespace and comment-lines
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* Make file description more readable
* Make code layout more consistent, include comment in assert so it's visible
during execution if it hits
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Try to improve method comments a little.
Get rid of some excess whitespace; put braces on previous line when possible.
Add stub for method to verify the work of saveState().
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* It's no longer a BasicBlock pass: update comment on run() method
* Fix placement of braces to be consistent
* Delete extraneous whitespace
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the module. This change converts it from being a basic block pass to being
a simple pass. This allows elimination of the annotation and simplification
of the logic for moving constants into global variables.
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Make insertFarJumpAtAddr() return void, because nothing uses its return value.
Remove some commented-out code.
Implement replaceMachineCodeForFunction() for SPARC.
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Rename SlotCalculator::getValSlot() to SlotCalculator::getSlot(),
SlotCalculator::insertValue() to SlotCalculator::getOrCreateSlot(),
SlotCalculator::insertVal() to SlotCalculator::insertValue(), and
SlotCalculator::doInsertVal() to SlotCalculator::doInsertValue().
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jello statistic for this (just divide #-bytes-of-code-emitted by 4).
Rewrite head-of-file comment.
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Shorten the markSuggestedColorUsable method.
Add a switch for saving reg. alloc. state (coming soon).
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(I also zapped printMachineCode() and printLabel() at the previous checkin,
but forgot to mention it.)
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PhyRegAlloc.cpp:
Don't include TargetMachine.h or TargetRegInfo.h, because these are provided
by PhyRegAlloc.h.
Merge class RegisterAllocator into class PhyRegAlloc.
Simplify & move ctor, dtor to PhyRegAlloc.h.
Make some of PhyRegAlloc's reference members into pointer members,
so they can be more easily messed with.
MarkAllocatedRegs() becomes a member method, with fewer args.
PhyRegAlloc.h:
Include Pass.h, TargetMachine.h and TargetRegInfo.h. Don't declare
TargetRegInfo forward.
Give AddedInstrns the obvious clear() method.
Make some of PhyRegAlloc's reference members into pointer members,
so they can be more easily messed with.
Add prototype for markAllocatedRegs().
Remove unused inline void constructLiveRanges().
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functionality of FunctionInfo pass as doFinalization method.
Rename pass to match names of other passes like it.
Rename the pass creator fn to mimic the other creator fn names.
Include StringExtras for utostr().
Make symbol prologue/epilogue stuff redundant with
EmitBytecodeToAssembly, in preparation for refactoring.
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some confusion when trying to generate files (it probably couldn't tell that
./file and $(SourceDir)/file may be the same file).
Now, just let VPATH find everything, and list the primary tblgen file first in
the list of dependencies so that we can just use $< to reference it in the make
rule.
This should hopefully fix the nightly tester.
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much cleaner and easier.
Labeled .td as a suffix for tblgen files in Makefile.rules.
Modified build rules so that source files generated during the build are placed
in the build directory and not the source directory (and not in a Debug
directory). This makes the system cleaner and allows us to have a read-only
source tree.
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Adjusted Makefile to work with new autoconf-style object root.
Specifically, use the new -I option of tblgen to find include files.
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* Generate a single BA instead of 6-instruction JUMP if possible
(this occurs both in the creation and overwriting of the stub code)
* If possible, rewrite the ORIGINAL call to call the generated function
directly, thus bypassing the stub entirely
Also added some statistics on how often calls are overwritten and how often the
CompilationCallback is invoked.
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* Break apart saving and restoring registers into separate functions
* Instead of saving single and double FP registers, just save the double
registers -- aliasing helps preserve the single FP registers as well.
* Request just as much memory for a stub as we actually use
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rounding up to a page, we need to request (num instrs * 4) bytes. However, I
think that 64 bytes is overkill for the stub function.
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registers are global, are NOT windowed, and hence can be clobbered!
* Removed unused register shorthand notations
* Fixed and cleaned up comments in inline assembly
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another delayed instr. would cause the later sanity-check (assertion)
in PhyRegAlloc.cpp to fail, even though there is really no error.
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addPassesToEmitMachineCode now both take a FunctionPassManager.
Factory methods for function passes now return type FunctionPass *.
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we no longer need to find the live-before set of the delayed
branch since that set is now included the live-before/after
set of the instructions in each delay slot. Just assert that instead.
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just PreSelection
* Wrapped code at 80 columns
* Added the DecomposeMultiDimRefs Pass to the JIT compilation path
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because saving i1 and i2 to their ``designated'' stack slots corrupts unknown
memory in other functions, standard libraries, and worse.
In addition, this has the benefit of improving JIT performance because we
eliminate writing out 4 instructions in CompilationCallback() and 2 loads and 2
stores.
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2. Handle fp-to-uint conversions directly here instead of relying on
a pre-transformation to replace them with the 2-step conversion.
3. Use size rather than explicitly checking types when deciding what
opcodes to use, wherever possible. This is less error prone (the
bug fix above was not the first time!).
4. Float-to-pointer casts shd now work though this hasn't been tested.
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this is not an optional transformation on SPARC and is now handled
directly by instruction selection.
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* Doxygen-ified comments
* Added capability to make far calls (i.e., beyond 30 bits in CALL instr)
which implies that we need to delete function references that were added by
the call to addFunctionReference() because the actual call instruction is 10
instructions away (thanks to 64-bit address construction)
* Cleaned up code that generates far jumps by using an array+loop
SparcV9CodeEmitter.h:
* Explained more of the side-effects of emitFarCall()
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Note that some generated operators (like &, | or ^) may
not be supported by the assembler -- but if they've got
this far, it's better to generate them and let the assembler decide.
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since it is *necessary* for correct code generation. Only optional
transformations belong in the PreOpts pass (which needs to be renamed
from PreSelection to PreOpts).
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that depends on machine register size.
Moved insertCallerSavingCode() to PhyRegAlloc and
moved isRegVolatile and modifiedByCall to TargetRegInfo: they are all
machine independent. Remove several dead functions.
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immed. field. Moved insertCallerSavingCode() to PhyRegAlloc: it is
now machine independent. Remove all uses of PhyRegAlloc.
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spilling values used by an instruction in the delay slot of the branch
(which will eventually be moved before the branch).
2. Bug fix: Delete the delay slot instr, not the branch instr, when
moving delay slot instr. out!!!!
3. Move code to insert caller-saves moved here from SparcRegInfo:
it is now machine-independent.
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machine-independent.
Fix problem with using branch operand reg. as temp. reg. when
spilling values used by an instruction in the delay slot of the branch
(which will eventually be moved before the branch).
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Single and FP double reg types (which share the same reg class).
Now all methods marking/finding unused regs consider the regType
within the reg class, and SparcFloatRegClass specializes this code.
(2) Remove machine-specific regalloc. methods that are no longer needed.
In particular, arguments and return value from a call do not need
machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
overloading when an include file is omitted.
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causing a nasty array bound error later.
2. Fix silly typo causing logical shift of unsigned long to use
SRL instead of SRLX.
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info (since multiple reg types may share the same reg class).
(2) Remove machine-specific regalloc. methods that are no longer needed.
In particular, arguments and return value from a call do not need
machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
overloading when an include file is omitted.
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found to consider regType info (since multiple reg types may share
the same reg class, e.g., single and double on Sparc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7327 91177308-0d34-0410-b5e6-96231b3b80d8
now works in instructions which require a 2-bit or 3-bit INTcc code.
Incidentally, that means that the representation of INTcc registers is now the
same in both integer and FP instructions. Thus, code became much simpler and
cleaner.
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allow, i.e. make a sequence of instructions to enable an indirect call using
jump-and-link and 2 temporary registers (which we save and ultimately restore).
Warning: if the delay slot of a function call is used to do meaningful work and
not just a NOP, this behavior is incorrect. However, the Sparc backend does not
yet utilize the delay slots effectively, so it is not necessary to make an
overly complicated algorithm for something that's not used.
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* FP double registers are now coded correctly
* Removed function which converted registers based on register types, it was
broken (because regTypes are broken)
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(1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops.
(2) Conditional move instructions must distinguish signed and unsigned
condition codes, e.g., MOVLE vs. MOVLEU.
(3) Conditional-move-on-register was using the cond-move-on-cc opcodes,
which produces a valid-looking instruction with bogus registers!
(4) Here's a really cute one: dividing-by-2^k for negative numbers needs to
add 2^k-1 before shifting, not add 1 after shifting. Sadly, these
are the same when k=0 so our poor test case worked fine.
(5) Casting between signed and unsigned values was not correct:
completely reimplemented.
(6) Zero-extension on unsigned values was bogus: I was only doing the
SRL and not the SLLX before it. Don't know WHAT I was thinking!
(7) And the most important class of changes: Sign-extensions on signed values.
Signed values are not sign-extended after ordinary operations,
so they must be sign-extended before the following cases:
-- passing to an external or unknown function
-- returning from a function
-- using as operand 2 of DIV or REM
-- using as either operand of condition-code setting operation
(currently only SUBCC), with smaller than 32-bit operands
Also, a couple of improvements:
(1) Fold cast-to-bool into Not(bool). Need to do this for And, Or, XOR also.
(2) Convert SetCC-Const into a conditional-move-on-register (case 41)
if the constant is 0. This was only being done for branch-on-SetCC-Const
when the branch is folded with the SetCC-Const.
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(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same
register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
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(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
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integer overflow):
We need to use %icc and not %xcc for comparisons on 32-bit or smaller
integer values.
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correct: empirically, "regType" is wrong for a number of registers. Thus, one
can only rely on the "regClass" to figure out what kind of register one is
dealing with.
This change switches to using only "regClass" and adds a few extra DEBUG() print
statements and a few clean-ups in comments and code, mostly minor.
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the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
actually assigned into the right portion of the instruction.
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area to avoid using up precious stack space within the 4095 offset limit
from %fp. Such objects that would themselves live at a large offset
were being put there already so this is a simple change.
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deletes it, but we were merrily trying to fix the operands of that
instruction anyway! Instead, fix the replacement instruction.
(2) An Improvement: Check for and extract global values in all operands,
not just in known pointer operands. For example, they can occur in
call arguments, and probably other unforeseeable places as well.
This also eliminates the special-case handling of Load and Store.
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not just an Instruction*, at least in one unfortunate case:
the first operand to the va_arg instruction.
Modify ValueToDefVecMap to map from Value*, not Instruction*.
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(1) select: Ok to convert a pointer to a float or double.
(2) regalloc: Some MachineInstr* for caller-saving code before a call
were being inserted before and after the call!
(3) Don't insert the caller-saving instructions in the
MachineCodeForInstruction for the Call instruction.
*All* instructions generated by register allocation need to be
recorded in those maps, but it needs to be done uniformly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7051 91177308-0d34-0410-b5e6-96231b3b80d8
Move LowerAllocations, PrintFunction, and SymbolStripping passes, and
the corresponding -disable-strip and -d options, over here to the SPARC
target-specific bits of llc. Rename -d to -dump-asm.
tools/llc/Makefile:
Reindent. Add x86 library so that llc compiles again.
tools/llc/llc.cpp:
Remove support for running arbitrary optimization passes. Use opt instead.
Remove LowerAllocations, PrintFunction, and SymbolStripping passes, as noted
above.
Allow user to select a backend (x86 or SPARC); default to guessing from
the endianness/pointer size of the input bytecode file.
Fix typos.
Delete empty .s file and exit with error status if target does not support
static compilation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6776 91177308-0d34-0410-b5e6-96231b3b80d8
SETTING the operand to be an immediate or have verified that one of the operands
is really a SignExtended or Unextended immediate value already, which warrants
an 'i' opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6662 91177308-0d34-0410-b5e6-96231b3b80d8
* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6655 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed instruction scheduling as it is too slow to run in a JIT environment
* Removed other passes because they aren't necessary and can slow JIT down
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6652 91177308-0d34-0410-b5e6-96231b3b80d8
Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and
expect %fsr as the parameter in assembly. They are disabled (since not used)
until an encoding, both for code generation and output, is chosen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6619 91177308-0d34-0410-b5e6-96231b3b80d8
Update file comment to contain a bunch of the overview mapping-info
documentation previously buried within the file.
Remove some unnecessary include/using stmts.
Rename pass to MappingInfoCollector.
Rewrite a lot of it so it doesn't use global instance variables and so
it outputs into MappingInfo objects and then dumps those out, instead of going
straight to an assembly file.
Change name of factory to getMappingInfoCollector.
Fold prologue & epilogue writers into MappingInfo methods.
lib/Target/Sparc/FInfo.cpp:
Correct file comment to reflect above change
lib/Target/Sparc/Sparc.cpp:
Change name of factory to getMappingInfoCollector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6617 91177308-0d34-0410-b5e6-96231b3b80d8
in Emitter.cpp, just convert the Sparc version of the constant pool into
what's already supported and inter-operate.
* Implemented a first pass at lazy function resolution in the JITResolver. That
required adding a SparcV9CodeEmitter pointer to simplify generating
bit-patterns of the instructions.
* SparcV9CodeEmitter now creates and destroys static TheJITResolver, which makes
sense because the SparcV9CodeEmitter is the only user of TheJITResolver, and
lives for the entire duration of the JIT (via PassManager which lives in VM).
* Changed all return values in the JITResolver to uint64_t because of the 64-bit
Sparc architecture.
* Added a new version of getting the value of a GlobalValue in the
SparcV9CodeEmitter, which now works for already-generated functions (JITted or
library functions).
* Removed little-used and unused functions, cleaning up the internal view of the
SparcV9CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6612 91177308-0d34-0410-b5e6-96231b3b80d8
the loop, and in both cases. In the first case, it is a VReg that is a constant
so it may be actually converted to a constant. In the second case, it is already
a constant, but then if it doesn't change its type (e.g. to become a register
and have the value loaded from memory if it is too large to live in its
instruction field), we must change the opcode BEFORE the 'continue', otherwise
we miss the opportunity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6602 91177308-0d34-0410-b5e6-96231b3b80d8
rewriting it. I also vacuumed out all the commented-out code and
inaccurate comments, etc.
(We need to put the mapping information in a data structure so that we can
pass it out to the JIT, instead of automagically converting it to .byte
directives.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6574 91177308-0d34-0410-b5e6-96231b3b80d8