Eric Christopher
3c14f24c9d
Implement the 'M' output modifier for arm inline asm. This is fairly
...
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.
rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 01:40:44 +00:00
Akira Hatanaka
342837d0dc
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
...
Need this to prevent emitting illegal conditional move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 01:07:07 +00:00
Rafael Espindola
36ea4f0206
Add 132187 back now that the real problem is fixed.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 00:24:37 +00:00
Cameron Zwarich
de64aaf6c8
Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
...
and add some basic tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:54:00 +00:00
Bruno Cardoso Lopes
be64b39431
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
...
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:46:09 +00:00
Rafael Espindola
157371f376
It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while I check.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132230 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:36:02 +00:00
Cameron Zwarich
f5e771db37
Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass()
...
was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 22:26:04 +00:00
Rafael Espindola
5b23b7fe31
Make size computation less brittle.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 22:05:41 +00:00
Evan Cheng
4abce0c90b
Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 20:11:27 +00:00
Jakob Stoklund Olesen
11f6cc96bf
Delete MethodBodies that only filtered reserved registers.
...
The register allocators know to filter reserved registers from the allocation
orders, so we don't need all of this boilerplate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132199 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 18:27:13 +00:00
Eli Friedman
a4d487fc1e
Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 18:02:04 +00:00
Rafael Espindola
25b15d8502
Remove DwarfRegNum from the individual bits of the condition register.
...
These should be DW_OP_bit_piece of CR (64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 16:15:27 +00:00
Rafael Espindola
81a2745830
Remove DwarfRegNum from CARRY. I should be encoded with DW_OP_bit_piece.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 16:01:08 +00:00
Rafael Espindola
81e193cc1f
Remove dwarf numbers from subregs. We should use DW_OP_bit_piece to
...
refer to them.
I tested this with both check-all and the gdb testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132187 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 15:08:24 +00:00
Eric Christopher
33281b2361
Make the branch encoding for tBcc more obvious that it's a 4-byte opcode
...
followed by a conditional and imm8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 03:50:53 +00:00
Eric Christopher
86bbcbf4b0
Fix comment.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132178 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 03:46:51 +00:00
Chad Rosier
62660310d9
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist.
...
crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 23:13:19 +00:00
Akira Hatanaka
33458fedb6
Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if
...
a function has any function calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 20:30:31 +00:00
Rafael Espindola
a5e62019d7
Fix some dwarf register numbers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132136 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 19:25:47 +00:00
Akira Hatanaka
cf0cd8005c
Add support for C++ exception handling.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 18:59:03 +00:00
Eric Christopher
32bfb2c513
Reorganize these slightly according to operand type.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132128 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 18:22:26 +00:00
Akira Hatanaka
78e72d60ec
Set HasSetDirective to true.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 18:16:18 +00:00
Stuart Hastings
2aa0f23e1c
Reverting 132105: it broke some LLVM-GCC DejaGNU tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 04:09:49 +00:00
Cameron Zwarich
421b106872
Mark tBX as an indirect branch rather than a return.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 03:41:12 +00:00
Stuart Hastings
aa4e6afc9b
Correctly handle a one-word struct passed byval on x86_64.
...
rdar://problem/6920088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 02:44:56 +00:00
Eli Friedman
76927d7303
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
...
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 23:49:02 +00:00
Akira Hatanaka
37d22d92df
Define WeakRefDirective.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 23:30:30 +00:00
Cameron Zwarich
ad70f6d2b1
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 21:53:50 +00:00
Eric Christopher
7bb1c40549
Clean up comment a bit.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132083 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 21:19:19 +00:00
Eric Christopher
8f89463894
Implement the 'm' modifier. Note that it only works for memory operands.
...
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 20:51:58 +00:00
Akira Hatanaka
d85b3ecbb3
Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already
...
been defined in MipsInstrFPU.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132076 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 20:08:05 +00:00
Akira Hatanaka
9c3d57c45e
Custom-lower FCOPYSIGN nodes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 19:32:07 +00:00
Eli Friedman
783c66414a
Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 19:09:45 +00:00
Akira Hatanaka
4c62f765a3
Update MaxCallFrameSize regardless of the relocation model selected.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 18:08:32 +00:00
Akira Hatanaka
f15f498507
Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() should
...
return 0 if there are no function calls made.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 17:52:48 +00:00
Akira Hatanaka
edacba83dc
Coding style fixes. Added comments.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 17:32:06 +00:00
Francois Pichet
1b47720391
Remove unused OpcodeMask enumerator.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 17:02:53 +00:00
Francois Pichet
d9e57c146d
Fix MSVC warning: "is out of range for enum constant"
...
MSVC doesn't support 64 bit enum.
OpcodeMask is not used anywhere in the code base.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 15:58:10 +00:00
Cameron Zwarich
da86a08284
Restore an accidentally removed comment.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:48:17 +00:00
Cameron Zwarich
8e9bace414
Move some code to a more logical place.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132043 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:45:29 +00:00
Cameron Zwarich
106acd4158
Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This
...
fixes <rdar://problem/9495913>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:45:27 +00:00
Cameron Zwarich
328634598f
Change the order of tBX's operands so that the predicate operands come after the
...
target register, matching BX. I filed this bug because I was confused at first:
PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007 >
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132041 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:45:23 +00:00
Cameron Zwarich
8f161c3a95
Rename tBX_Rm to tBX.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:45:20 +00:00
Cameron Zwarich
b36c1ae6d5
Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better
...
reflect their actual meaning and match the ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:45:14 +00:00
Rafael Espindola
fc2bb8c444
Replace the -unwind-tables option with a per function flag. This is more
...
LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132033 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 03:44:17 +00:00
Akira Hatanaka
053546c31e
Fix lowering of DYNAMIC_STACKALLOC nodes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 02:20:00 +00:00
Bruno Cardoso Lopes
56926a3961
Fix PR9762
...
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 00:35:03 +00:00
Eric Christopher
4db7dec70b
Implement the arm 'L' asm modifier.
...
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 23:27:13 +00:00
Eric Christopher
e1739d598d
Implement the immediate part of the 'B' modifier.
...
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 23:15:43 +00:00
Eric Christopher
fef50062ea
Add more unimplemented asm modifiers and some documentation of what they
...
do.
Part of rdar://9119939.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 22:27:43 +00:00
Eric Christopher
0628d38085
Add support for the arm 'y' asm modifier.
...
Fixes part of rdar://9444657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132011 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 22:10:34 +00:00
Akira Hatanaka
ce98deb9f5
Enable printing of immediates that do not fit in 16-bit. .cprestore can have
...
offsets that are larger than 0x10000.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 21:22:21 +00:00
Akira Hatanaka
4231c7ea6d
Implement byval structure argument passing. The following limitations or
...
deficiencies exist:
- Works only if ABI is o32.
- Zero-sized structures cannot be passed.
- There is a lot of redundancy in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 19:18:33 +00:00
Devang Patel
8ec0c1c07b
Remove dead code.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 18:27:52 +00:00
Charles Davis
6b918b8466
Add a method to TargetRegisterInfo to get the register number that the Win64 EH
...
scheme uses internally. Implement it for x86 (the only architecture that LLVM
supports for which this matters right now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 16:57:53 +00:00
Evan Cheng
b5a55d979c
- Teach SelectionDAG::isKnownNeverZero to return true (op x, c) when c is
...
non-zero.
- Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension
when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero.
rdar://9490949
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131948 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 01:48:22 +00:00
Akira Hatanaka
b4d8d31e59
Simplify offset calculation of stack frame objects for $gp restore location and
...
variable arguments in LowerCall and LowerFormalArguments. This should also fix
the bug in which handling of variable arguments is incorrect when the front-end
optimizes away unused fixed arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131942 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 00:23:52 +00:00
Akira Hatanaka
46da136ec7
Expand f64 FPOW.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131928 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 22:23:58 +00:00
Akira Hatanaka
f89532f8f6
Add pattern for double-to-integer conversion. Patch by Sasa Stankovic.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 22:16:43 +00:00
Akira Hatanaka
bdd2ce9741
Fixes related to coding style.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 21:13:59 +00:00
Akira Hatanaka
f8928c07e7
Fix MipsAsmPrinter::printSavedRegsBitmaskChange. Remove functions and variables
...
in MipsFunctionInfo that are no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 20:34:30 +00:00
Chris Lattner
32232fc2b5
clarify this, apparently it is confusing :)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 20:17:44 +00:00
Akira Hatanaka
69c19f7316
Change StackDirection from StackGrowsUp to StackGrowsDown.
...
The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
the stack pointer) are set before instruction selection is completed. There is
no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
no longer necessary to assign negative offsets to fixed objects for incoming
arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in
MipsFrameLowering::adjustMipsStackFrame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 20:16:59 +00:00
Cameron Zwarich
d34d429401
Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches
...
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131894 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 01:57:17 +00:00
Chris Lattner
92f920c109
add a missing alias to make us more bug compatible with gcc, PR9378
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 22:31:57 +00:00
Renato Golin
1ec11fb8b5
RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 21:41:23 +00:00
Chris Lattner
87943e3698
add a note.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 18:28:46 +00:00
Johnny Chen
75f4296c7c
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
...
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 17:51:04 +00:00
Chris Lattner
b6fcf4cfbc
move PR9408 here.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 05:45:06 +00:00
Chris Lattner
40f5fbcc5c
add a copy ctor to TargetLibraryInfo.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131806 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-21 20:09:13 +00:00
Benjamin Kramer
b22da2a72c
X86: smulo -> add is now done target-independently in DAGCombiner, remove the patterns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-21 18:32:01 +00:00
Cameron Zwarich
37fed38ec1
Fix PR9978 by adding RIP to GR64_TC so it can be used as an address in PIC code. It
...
is already in GR64 for the same reasons. Since it isn't allocatable it can't cause
any problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-21 04:13:49 +00:00
Akira Hatanaka
52106e1e25
Use the correct register to access stack frame objects.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131785 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-21 03:01:03 +00:00
Akira Hatanaka
f346c69530
Insert instructions that copy $sp to or from $fp at the right locations.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131784 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-21 02:29:26 +00:00
Akira Hatanaka
43299776d7
Change the order fixed objects are created in MipsTargetLowering::LowerCall in
...
preparation for reversing StackDirection.
Fixed objects are created in the following order:
1. Incoming arguments passed on stack.
2. va_arg objects (include both arguments that are passed in registers and
pointer to the location of the first va_arg argument).
3. $gp restore slot.
4. Outgoing arguments passed on stack.
5. Pointer to alloca'd space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 23:22:14 +00:00
Eli Friedman
c088345f13
Add fast-isel support for byval calls on x86.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131764 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 22:21:04 +00:00
Akira Hatanaka
d37776d1c1
In CC_MipsO32, allocate a stack space regardless of whether the argument is
...
passed in register or on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131758 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 21:39:54 +00:00
Akira Hatanaka
6ffbf82e22
Define functions that get/set maximum call frame size.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131752 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 20:11:17 +00:00
Rafael Espindola
b8adb8af0f
adds some attributes to attribute section when cpu is "xscale"
...
(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 20:10:34 +00:00
Rafael Espindola
298c8e12ea
fixes target address tBL and tBLX and sets relocation type
...
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 20:01:01 +00:00
Stuart Hastings
0e29ed081b
Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.
...
rdar://problem/8614450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 19:04:40 +00:00
Akira Hatanaka
17a1e87751
Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle
...
saving and restoring them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131745 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 18:39:33 +00:00
Evan Cheng
0b65599015
Revert accidental commit.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 17:38:48 +00:00
Benjamin Kramer
eb274e6bdd
Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131730 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 15:11:26 +00:00
Benjamin Kramer
6e35e4c8c1
Remove noisy semicolons.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 09:20:25 +00:00
Akira Hatanaka
cd0f90f831
Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 02:30:51 +00:00
Akira Hatanaka
d992f6c666
Remove code that creates unnecessary frame objects.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131711 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 01:45:06 +00:00
Akira Hatanaka
da0a3571d6
Define variables and functions in MipsFunctionInfo.
...
This is the first of a series of patches that attempt to simplify handling of
stack frame objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131710 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 01:17:58 +00:00
Chad Rosier
a166089f36
Don't attempt to tail call optimize for Win64.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 00:59:28 +00:00
Evan Cheng
2e6496026f
Revert r131664 and fix it in instcombine instead. rdar://9467055
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 00:54:37 +00:00
Eli Friedman
dc51575a5f
Add fast-isel support for zeroext and signext ret instructions on x86.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 22:16:13 +00:00
Eric Christopher
2bbecd8f6d
Oddly people want to use the 'r' constraint for fp constants on x86.
...
Fixes rdar://9218925
Fixes PR9601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 21:33:47 +00:00
Jason W Kim
861b9c6a39
This fixes one divergence between LLVM and binutils for ARM in the
...
text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:55:25 +00:00
Rafael Espindola
a3bff99f0a
ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
...
Fixes PR9934.
We really need to start tblgening the relocation info :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:32:34 +00:00
Akira Hatanaka
a1a7ba8382
Align i64 arguments to 64 bit boundaries.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:29:48 +00:00
Evan Cheng
0efaa5e6a1
crc32 with 64-bit output zeros upper 32-bits. rdar://9467055
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 18:57:12 +00:00
Akira Hatanaka
59d266029c
Increase number of available registers when target is MIPS32.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131660 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 18:25:03 +00:00
Akira Hatanaka
95b8ae190e
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 18:06:05 +00:00
Stuart Hastings
d22f036c2a
Reverting 131641 to investigate 'bot complaint.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 17:54:42 +00:00
Jim Grosbach
6635b04a43
80 columns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 17:34:53 +00:00
Akira Hatanaka
d48cfaec35
Fix data layout string. i64 is aligned to 64 bit boundaries.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 17:21:09 +00:00
Stuart Hastings
b6dcf3c514
Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be
...
pseudos. rdar://problem/8614450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 16:59:50 +00:00
Cameron Zwarich
055cdfc541
Use the correct register class for Cell varargs spilling. This fixes all of the
...
verifier failures in the CodeGen/CellSPU tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 04:44:19 +00:00
Mon P Wang
28e2b1d29a
Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 04:15:07 +00:00
Cameron Zwarich
d76773a221
Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 03:11:06 +00:00
Cameron Zwarich
0113e4e3f2
Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless
...
piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 02:56:28 +00:00
Cameron Zwarich
462b6dc6bf
Reuse the TargetInstrDesc.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 02:56:23 +00:00
Cameron Zwarich
21803721d5
Correctly constrain a register class when computing frame offsets, as the Thumb2
...
add instruction takes an rGPR. This fixes the last of PR8825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 02:18:27 +00:00
Eli Friedman
22486c9aba
Revert unintentional commit.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131597 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 23:13:10 +00:00
Eli Friedman
107ffd58f7
More instcombine simplifications towards better debug locations.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131596 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 23:11:30 +00:00
Cameron Zwarich
631fcbf810
Add missing mayLoad / mayStore flags to instruction definitions without patterns,
...
which fixes all of the CodeGen/MBlaze verifier failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131595 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 23:03:10 +00:00
Cameron Zwarich
e4c6445405
Reserve the segment registers on x86 to fix verifier failures in any code that
...
uses them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 22:24:48 +00:00
Cameron Zwarich
20a41cb2b2
Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 21:54:32 +00:00
Tanya Lattner
db28247522
Handle perfect shuffle case that generates a vrev for vectors of floats.
...
Add test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 21:44:54 +00:00
Cameron Zwarich
955db42568
Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 21:25:14 +00:00
Johnny Chen
a96581f4f7
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 20:32:41 +00:00
Chad Rosier
871f664093
Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 19:59:50 +00:00
Evan Cheng
b936e3006f
Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131555 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 18:59:17 +00:00
Evan Cheng
d48fda46f5
Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 18:47:27 +00:00
Justin Holewinski
657d1bed23
PTX: add flag to disable mad/fma selection
...
Patch by Dan Bailey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 15:42:23 +00:00
Tanya Lattner
2a8eb722c7
In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
...
Updated test case and reverted change to the PerfectShuffle Table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 06:42:21 +00:00
Cameron Zwarich
141ec63962
Fix typo.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 02:29:50 +00:00
Cameron Zwarich
7d336c0c68
Fix more of PR8825 by correctly using rGPR registers when lowering atomic
...
compare-and-swap intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 02:20:07 +00:00
Cameron Zwarich
d6ffcd88ba
Actually, the address operand of the Thumb2 LDREX / STREX instructions *can*
...
take r13, so we can just make it a GPR. This fixes PR8825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 23:26:20 +00:00
Cameron Zwarich
3c60ff4f3d
Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They
...
were marked as taking a tGPR when in reality they take an rGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 23:11:12 +00:00
Tanya Lattner
c81c9709ef
vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 20:48:40 +00:00
Mon P Wang
fee22869ca
Enable autodetect of popcnt
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 18:33:37 +00:00
Eli Friedman
19515b4e52
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
...
This is r131438 with a couple small fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131474 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 18:29:03 +00:00
Eli Friedman
b8e0d3412c
Clean up the mess created by r131467+r131469.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 18:02:22 +00:00
Stuart Hastings
6db2c2fe21
Revert 131467 due to buildbot complaint.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131469 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 16:59:46 +00:00
Stuart Hastings
504421e327
Fix an obscure issue in X86_64 parameter passing: if a tiny byval is
...
passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131467 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 16:45:55 +00:00
Nadav Rotem
86694297ff
Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode
...
with two different types, in cases where the index and the ptr had different
types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131461 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 08:31:57 +00:00
Eric Christopher
6abb7bae10
Update comment.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 08:16:14 +00:00
Eric Christopher
c324f72ab7
Support XOR and AND optimization with no return value.
...
Finishes off rdar://8470697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 08:10:18 +00:00
Eric Christopher
811c2b7110
Couple less magic numbers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 07:50:41 +00:00
Eric Christopher
8102bf003e
Make this code a little less magic number laden.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 07:47:55 +00:00
Chris Lattner
5d4718b1c7
add a note
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 07:22:33 +00:00
Eli Friedman
c93943b6fe
Back out r131444 and r131438; they're breaking nightly tests. I'll look into
...
it more tomorrow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 02:36:59 +00:00
Eli Friedman
cdc9a20561
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 00:13:47 +00:00
Jim Grosbach
0c72076190
Kill some dead code.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 22:24:07 +00:00
Eli Friedman
57f4b03621
Remove dead code. Fix associated test to use FileCheck.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 21:28:22 +00:00
Eli Friedman
482feb33b2
Make fast-isel work correctly s/uadd.with.overflow intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 21:06:17 +00:00
Rafael Espindola
6469540adf
sets bit 0 of the function address of thumb function in .symtab
...
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 16:17:21 +00:00
Eli Friedman
d0118a2371
Fix a FIXME by moving the fast-isel implementation of the objectsize intrinsic from the x86 code to the generic code.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-14 00:47:51 +00:00
Rafael Espindola
a3f88148e6
Don't produce a vmovntdq if we don't have AVX support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-14 00:30:01 +00:00
Eli Friedman
d25d16c901
Zap useless code; this hasn't done anything useful since fast-isel switched to being bottom-up (a very long time ago).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131329 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-14 00:19:32 +00:00
Julien Lerouge
eea6c95d5d
Fix a source of non determinism in FindUsedTypes, use a SetVector instead of a
...
set.
rdar://9423996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-13 05:20:42 +00:00
Akira Hatanaka
01765eb0a1
Fix setting of isCommutable flag.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-12 17:42:08 +00:00
Eric Christopher
c493a1f317
Turn this into a table, this will make more sense shortly.
...
Part of rdar://8470697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 21:44:58 +00:00
Owen Anderson
18901d63bf
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 17:00:48 +00:00
Nadav Rotem
4301222525
Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 08:12:09 +00:00
Bill Wendling
61512ba251
Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp
...
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 01:11:55 +00:00
Eric Christopher
b38fe4b52d
Optimize atomic lock or that doesn't use the result value.
...
Next up: xor and and.
Part of rdar://8470697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 23:57:45 +00:00
Eric Christopher
988397dcbc
Refactor lock versions of binary operators to be a little less
...
cut and paste.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131139 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 18:36:16 +00:00
Jason W Kim
f4351ceb93
First cut at getting debugging support for ARM/MC/ELF/.o
...
DWARF stuff also gets fixed up by ELFARMAsmBackend::ApplyFixup(),
but the offset is not guaranteed to be mod 4 == 0 as in text/data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 18:07:25 +00:00
Justin Holewinski
0d10970789
PTX: add PTX 2.3 setting in PTX sub-target.
...
Patch by Wei-Ren Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 12:32:11 +00:00
Eric Christopher
49ac3d7da9
Fix td file comments for Mips.
...
Patch by Liu <proljc@gmail.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09 18:16:46 +00:00
Mon P Wang
183c627d89
Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09 17:47:27 +00:00
Benjamin Kramer
f51190b697
X86: Add a bunch of peeps for add and sub of SETB.
...
"b + ((a < b) ? 1 : 0)" compiles into
cmpl %esi, %edi
adcl $0, %esi
instead of
cmpl %esi, %edi
sbbl %eax, %eax
andl $1, %eax
addl %esi, %eax
This saves a register, a false dependency on %eax
(Intel's CPUs still don't ignore it) and it's shorter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-08 18:36:07 +00:00
Jakob Stoklund Olesen
ca66226e7e
Eliminate the ARM sub-register indexes that are not needed by the sources.
...
Tablegen will invent its own names for these indexes, and the register file is a
bit simpler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07 21:22:42 +00:00
Eric Christopher
33c110e602
Fix the non-MC encoding of pkhbt and pkhtb.
...
Patch by Stephen Hines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07 04:37:27 +00:00
Akira Hatanaka
325e66d81a
1. Keep lines in 80 columns.
...
2. Remove unused function.
3. Correct indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 22:11:29 +00:00
Eli Friedman
fc5d305597
Make the logic for determining function alignment more explicit. No functionality change.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 20:34:06 +00:00
Rafael Espindola
f2b0423200
Dead code elimination.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130984 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 14:56:22 +00:00
Justin Holewinski
ab0145d2a9
PTX: add PTX 2.3 language target
...
Patch by Wei-Ren Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 11:40:36 +00:00
Rafael Espindola
108709d4d1
Move PPC Linux to CFI.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05 21:34:33 +00:00
Eli Friedman
297015913a
PR9848: pandn is not commutative.
...
No test because I can't think of any way to write one that won't break quickly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130932 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05 17:45:31 +00:00
Bill Wendling
087aad44cb
Remove a flag that would set the ".eh" symbol as .globl. MachO was the only one
...
who used this flag, and it now emits CFI and doesn't emit this anymore. All
other targets left this flag "false".
<rdar://problem/8486371>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130918 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05 06:49:15 +00:00
Jakob Stoklund Olesen
4f5de9bb40
Fix X86RegisterInfo::getMatchingSuperRegClass for sub_8bit_hi.
...
It is OK for B to be any GR8_ABCD_H superclass, the returned register class
doesn't have to map surjectively onto B.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 23:54:54 +00:00
Jakob Stoklund Olesen
21f7902a89
Implement SystemZRegisterInfo::getMatchingSuperRegClass to enable cross-class joins.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130857 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 19:02:04 +00:00
Devang Patel
64915dec28
Do not emit location expression size twice.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 19:00:57 +00:00
Rafael Espindola
6af0b762db
Fix cmake build.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 18:46:56 +00:00
Akira Hatanaka
6b7588e6c4
Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 17:54:27 +00:00
Jakob Stoklund Olesen
b89383aeff
Implement MSP430RegisterInfo::getMatchingSuperRegClass to enable cross-class
...
coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 01:01:36 +00:00
Jakob Stoklund Olesen
2944b4fe05
Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers.
...
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.
LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 22:31:24 +00:00
Bill Wendling
9493a285d1
Replace the "movnt" intrinsics with a native store + nontemporal metadata bit.
...
<rdar://problem/8460511>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 21:11:17 +00:00
Akira Hatanaka
9ff1b9b259
Fix function MipsRegisterInfo::getRegisterNumbering.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130774 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 18:41:54 +00:00
Bob Wilson
e1a56ae747
Temporarily disable use of divmod compiler-rt functions for iOS.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 17:33:22 +00:00
Bruno Cardoso Lopes
0a69ba309f
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever
...
it's possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130764 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 17:29:29 +00:00
Bruno Cardoso Lopes
54ad87ab78
Add a few ARM coprocessor intrinsics. Testcases included
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 17:29:22 +00:00
Benjamin Kramer
d2189bf12a
Remove unused variables caught by GCC's -Wunused-but-set-variable.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130755 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 16:00:27 +00:00
Michael J. Spencer
34868ee4de
Add pentium{3,4}m cpus. Patch by Alexander Best!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130749 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 03:42:50 +00:00
Eric Christopher
2fc496fcf5
xmm0 is an implicit parameter in this and so shouldn't be in the
...
string template.
Fixes rdar://8493866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 01:28:32 +00:00
Dan Gohman
cca82149ad
Add an unfolded offset field to LSR's Formula record. This is used to
...
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 00:46:49 +00:00
Eric Christopher
52f6c03a45
Apparently the check for direct calls is unnecessary.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-02 20:16:33 +00:00
Rafael Espindola
2866edf120
Add 130690 back.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-02 15:58:16 +00:00
Rafael Espindola
b2d7336fde
Revert while I debug the tests that use march but not mtriple.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-02 15:42:31 +00:00
Rafael Espindola
433771c514
Move ppc OS X to cfi too. I am building it on an old ppc mini, but it will take some time.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130690 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-02 15:00:52 +00:00
Rafael Espindola
450a5a1207
Add r130623 back now that ELF has been fixed to work with -fno-dwarf2-cfi-asm.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130658 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-01 15:44:13 +00:00
Chandler Carruth
9bc1537488
Remove an unused variable from this function introduced in r130637,
...
likely a result of copy/paste.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130640 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-01 06:14:10 +00:00
Rafael Espindola
5426a9ee37
GCC uses a different encoding of pointers in the FDE when using
...
-fno-dwarf2-cfi-asm. Implement the same behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130637 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-01 04:49:54 +00:00
Rafael Espindola
c35280647b
I forgot these files in the previous commit.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-01 04:19:24 +00:00
Rafael Espindola
debd7e4e8b
Simplify the handling of pcrel relocations on ELF. Now we do the right thing
...
for all symbol differences and can drop the old EmitPCRelSymbolValue
method.
This also make getExprForFDESymbol on ELF equal to the one on MachO, and it
can be made non-virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-01 03:50:49 +00:00
Rafael Espindola
2b3e12d0cb
Revert the previous patch while I figure out how to make llvm-gcc
...
less agressive about disabling cfi on linux :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-30 23:03:44 +00:00
Jakob Stoklund Olesen
60045c233a
X86AsmPrinter doesn't know how to handle the X86II::MO_GOT_ABSOLUTE_ADDRESS flag
...
after folding ADD32ri to ADD32mi, so don't do that.
This only happens when the greedy register allocator gets itself in trouble and
spills %vreg9 here:
16L %vreg9<def> = MOVPC32r 0, %ESP<imp-use>; GR32:%vreg9
48L %vreg9<def> = ADD32ri %vreg9, <es:_GLOBAL_OFFSET_TABLE_>[TF=1], %EFLAGS<imp-def,dead>; GR32:%vreg9
That should never happen, the live range should be split instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-30 23:00:05 +00:00
Rafael Espindola
89fc9e8f5e
Enable CFI on OS X.
...
Currently the output should be almost identical to the one produced by CodeGen
to make the transition easier.
The only two differences I know of are:
* Some files get an extra advance loc of size 0. This will be fixed when
relaxations are enabled.
* The optimization of declaring an EH symbol as an external variable is not
implemented. This is a subset of adding the nounwind attribute, so we if really
this at -O0 we should probably do it at the IL level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-30 22:29:54 +00:00
Rafael Espindola
f1a5c7ec04
Add all the plumbing needed for MC to expand cfi to the old tables in
...
the final assembly. It is the same technique used when targeting
assemblers that don't support .loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-30 03:44:37 +00:00
Eric Christopher
5ac179ccd2
80-col.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 23:12:01 +00:00
Eli Friedman
b451770b26
Zap a couple now-unused functions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 22:56:48 +00:00
Eli Friedman
c573e2c7ea
Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 22:48:03 +00:00