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13051 Commits

Author SHA1 Message Date
David Goodwin
c2e8a7e8d2 Fixed to address code review. No functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-10 00:48:55 +00:00
David Goodwin
0855dee564 Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-10 00:15:47 +00:00
Jim Grosbach
803b48a155 Now that the default is 'enabled,' a separate command line option for ARM is 
not necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86621 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 23:11:45 +00:00
Jim Grosbach
92eb919e80 Enable dynamic stack realignment by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86604 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 22:32:40 +00:00
Jim Grosbach
ad353c74ad Set dynamic stack realignment to real values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86602 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 22:32:03 +00:00
Bill Wendling
2718e43d6a Similar to r86588, but for Darwin this time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86592 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 21:45:26 +00:00
Bill Wendling
b1ec31d711 The jump table was being generated before the end label for exception handling 
was generated. This caused code like this:

## The asm code for the function
        .section        __TEXT,__const
        .align  2
lJTI11_0:
LJTI11_0:
        .long    LBB11_16
        .long    LBB11_4
        .long    LBB11_5
        .long    LBB11_6
        .long    LBB11_7
        .long    LBB11_8
        .long    LBB11_9
        .long    LBB11_10
        .long    LBB11_11
        .long    LBB11_12
        .long    LBB11_13
        .long    LBB11_14
Leh_func_end11:   ## <---now in the wrong section!

The `Leh_func_end11' would then end up in the wrong section, causing the
resulting EH frame information to be wrong:

__ZL11CheckRightsjPKcbRbRP6NSData.eh:
    .set    Lset500eh,Leh_frame_end11-Leh_frame_begin11
    .long   Lset500eh  ; Length of Frame Information Entry                                                                                                                   
Leh_frame_begin11:
    .long   Leh_frame_begin11-Leh_frame_common
    .long   Leh_func_begin11-.
    .set    Lset501eh,Leh_func_end11-Leh_func_begin11
    .long   Lset501eh                                   ; FDE address range                                                                                                                                   
`Lset501eh' is now something huge instead of the real value.

The X86 back-end generates the jump table after the EH information is
emitted. Do the same here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86588 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 21:20:14 +00:00
Jim Grosbach
43cca695a8 Work around assembler not recognizing #0.0 form immediate for vmcp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86548 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 15:27:51 +00:00
Bruno Cardoso Lopes
b8e0ebf034 Fix PR5149. 
http://llvm.org/bugs/show_bug.cgi?id=5149



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86543 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 14:27:49 +00:00
Jim Grosbach
e5165490b7 Use Unified Assembly Syntax for the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 00:11:35 +00:00
Anton Korobeynikov
f0b47b7f6d Add and-not (bic) patterns. Based heavily on patch by Brian Lucas! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86471 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-08 15:33:12 +00:00
Anton Korobeynikov
830fe7bc2d Move OR patterns upper to all logical stuff. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86470 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-08 15:32:44 +00:00
Anton Korobeynikov
ff2c186d59 Some nice peephole patterns. Based on patch by Brian Lucas! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86469 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-08 15:32:28 +00:00
Anton Korobeynikov
764cfaabd2 Print tab before operand of jcc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-08 15:32:11 +00:00
Anton Korobeynikov
52f28e9b63 Fix invalid operand updates & implement post-inc memory operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86466 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-08 14:27:38 +00:00
Anton Korobeynikov
773943ac5c Throw an error when stack realignment stuff fails instead of silent 
code miscompilation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86463 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-08 12:58:40 +00:00
Chris Lattner
7e89738f98 Make TargetData::getStringRepresentation spit out native integer types, 
this gives llvm-gcc generated modules the right data.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86435 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-08 02:32:01 +00:00
Jim Grosbach
31bc849123 Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86425 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-08 00:27:19 +00:00
Evan Cheng
fdc834046e Refactor code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86423 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-08 00:15:23 +00:00
Nate Begeman
0b10b91465 x86 vector shuffle cleanup/fixes: 
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect.  The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86415 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 23:17:15 +00:00
Jim Grosbach
31c24bf5b3 80-column cleanup of file header comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86408 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 22:00:39 +00:00
Jim Grosbach
8a5ec86a3d Support alignment specifier for NEON vld/vst instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86404 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 21:25:39 +00:00
Nick Lewycky
f80fcd00b3 Improve tail call elimination to handle the switch statement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86403 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 21:10:15 +00:00
Evan Cheng
bf992817f2 t2ldrpci_pic can be used for blockaddress as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86400 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 19:40:04 +00:00
Chris Lattner
59a9178fbe indicate what the native integer types for the target are. 
Please verify.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 19:07:32 +00:00
Anton Korobeynikov
06ac0820a6 First try of the post-inc operands handling... Not fully worked, though :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86386 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:15:25 +00:00
Anton Korobeynikov
6534f83ae8 Add some dummy support for post-incremented loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86385 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:15:06 +00:00
Anton Korobeynikov
8983da729a Add 8 bit libcalls and make use of them for msp430 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86384 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:14:39 +00:00
Anton Korobeynikov
8046ef4379 Add few pseudo-source-values 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86383 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:13:57 +00:00
Anton Korobeynikov
123ed8f099 Initial support for addrmode handling. Tests by Brian Lucas! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86382 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:13:35 +00:00
Anton Korobeynikov
603fce9ebb Some preliminary variable asmprinting 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:12:58 +00:00
Anton Korobeynikov
5c192fbe45 Use '.L' for global private prefix (as mspgcc) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86380 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:12:38 +00:00
Anton Korobeynikov
b7790e11c4 Drop old asmprinter stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86379 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 17:12:21 +00:00
Anton Korobeynikov
e8ea011cc7 It turns out that the testcase in question uncovered subreg-handling bug. 
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86375 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 15:20:32 +00:00
Chris Lattner
e82bdc4809 add the ability for TargetData to return information about legal integer 
datatypes on a given CPU.  This is intended to allow instcombine and other
transformations to avoid converting big sequences of operations to an
inconvenient width, and will help clean up after SRoA.  See also "Adding 
legal integer sizes to TargetData" on Feb 1, 2009 on llvmdev, and PR3451.

Comments welcome.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86370 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 09:35:34 +00:00
Chris Lattner
2e07494170 more cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86369 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 09:23:04 +00:00
Chris Lattner
8f9b0f6e88 add some missing #includes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86367 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 09:20:54 +00:00
Chris Lattner
b7aadfac5e rewrite TargetData to use StringRef/raw_ostream instead of thrashing std::strings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86366 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 09:13:23 +00:00
Jeffrey Yasskin
2d274412ed Make the need-stub variables accurate and consistent. In the case of 
MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 08:51:52 +00:00
Eric Christopher
761411c21b Fix a couple of shuffle patterns to use movhlps instead 
of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86360 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 08:45:53 +00:00
Mon P Wang
0ace1a9f30 Fixed Overload table bug noticed by Jakob 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86332 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 04:07:33 +00:00
Evan Cheng
d457e6e9a5 Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 04:04:34 +00:00
Evan Cheng
78e5c1140a - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical 
except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 03:52:02 +00:00
Ted Kremenek
b6aae88ac0 Update CMake file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86325 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 03:26:59 +00:00
Kenneth Uildriks
b4997aeab7 Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86324 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 02:11:54 +00:00
Johnny Chen
0430152a11 My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm 
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0).  The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86319 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 00:54:36 +00:00
Jim Grosbach
bd79fc8ef2 80-columns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86310 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 00:13:30 +00:00
Evan Cheng
b9803a8fa6 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:52:48 +00:00
Anton Korobeynikov
fc2cba8362 Honour subreg machine operands during asmprinting 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86303 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:45:15 +00:00
Bob Wilson
54c78ef2fe Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86301 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:33:28 +00:00
Evan Cheng
e7e0d62efd Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86294 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 22:24:13 +00:00
Daniel Dunbar
2928c83b01 Pass StringRef by value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86251 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 10:58:06 +00:00
Dan Gohman
40c57860da Factor out the printing of the leading tab into printInlineAsm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86199 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 00:04:54 +00:00
Dan Gohman
7289ed2ee7 Use SUBREG_TO_REG instead of INSERT_SUBREG to model x86-64's 
implicit zero-extend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86196 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 23:53:08 +00:00
Dan Gohman
73bb251cd7 Remove uninteresting and confusing debug output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 18:47:09 +00:00
Chris Lattner
6c9fab7404 add a note from PR5313 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86146 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 18:19:19 +00:00
Mon P Wang
82c443655d Reintroduce support for overloading target intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86114 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-05 03:19:08 +00:00
Jim Grosbach
4371cda7f8 Grammar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86068 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 23:20:40 +00:00
Jim Grosbach
db1751a922 Now that the memory leak from McCat/08-main has been fixed (86056), re-enable 
aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86064 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 23:11:07 +00:00
Jim Grosbach
6db06a0866 If a function has no stack frame at all, dynamic realignment isn't necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86057 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 22:41:51 +00:00
Jim Grosbach
c5848f4ced dynamic stack realignment necessitates scanning the floating point callee- 
saved instructions even if no stack adjustment for those saves is needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86056 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 22:41:00 +00:00
Bob Wilson
3d90dbee69 Add PowerPC codegen for indirect branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86050 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 21:31:18 +00:00
Jakob Stoklund Olesen
ad68264f59 Print out an informative comment for KILL instructions. 
The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.

With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86041 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 19:24:37 +00:00
Evan Cheng
b9f51cbe98 The .n suffix must go after the predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86019 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 07:38:48 +00:00
Evan Cheng
7883fa942f Use ldr.n to workaround a darwin assembler bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 00:00:39 +00:00
Evan Cheng
5a1cd36019 Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85965 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 23:13:34 +00:00
Evan Cheng
b23b2015eb fconsts / fconstd immediate should be proceeded with #. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85952 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 21:59:33 +00:00
Anton Korobeynikov
747409a290 Move subtarget check upper for NEON reg-reg fixup pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85914 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 18:46:11 +00:00
Evan Cheng
f6c0bffa8d Trim unnecessary include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85878 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 07:08:08 +00:00
Bob Wilson
af14e663ac For Thumb indirect branches, use "mov pc, reg" which does not switch 
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85874 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 06:29:56 +00:00
Evan Cheng
ba908640b3 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:52:54 +00:00
Evan Cheng
b4db6a46e0 Clean up copyRegToReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85870 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:51:39 +00:00
Evan Cheng
3f4e47be0a Add QPR_8 as a superreg class of SPR_8 and DPR_8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85869 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:50:57 +00:00
Ted Kremenek
92dbd0b320 Update CMake file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85861 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 04:14:12 +00:00
Anton Korobeynikov
7aaf94bb0d Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 01:04:26 +00:00
Anton Korobeynikov
ab453e0641 Revert r85049, it is causing PR5367 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85847 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 00:24:48 +00:00
Bob Wilson
b62d257cf5 Revert previous change to a comment. The BlockAddresses go in the 
constant pool so they don't get wrapped separately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85844 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 00:02:05 +00:00
Bob Wilson
907eebd5a6 Put BlockAddresses into ARM constant pools. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 20:59:23 +00:00
Kevin Enderby
60131c0d0b Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should 
have been passed as a reference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85823 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 20:14:39 +00:00
David Goodwin
2f54a2fd85 Fix schedule model for BFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85809 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 17:28:36 +00:00
Bob Wilson
31ba10b743 Hyphenate some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85808 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 17:10:37 +00:00
Bob Wilson
28989a8ddc Add support for BlockAddress values in ARM constant pools. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85806 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 16:59:06 +00:00
Bob Wilson
69e8445ced Prune unnecessary include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85805 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 16:58:31 +00:00
Evan Cheng
d3e18fad7e These are done / no longer care. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85798 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 07:58:25 +00:00
Evan Cheng
e3b88fc01e Add an entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85797 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 07:51:19 +00:00
Evan Cheng
7baae87d8f Unbreak ARMBaseRegisterInfo::copyRegToReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85787 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 04:44:55 +00:00
Anton Korobeynikov
2ae0eec1c0 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
3a639a07ea Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:39 +00:00
Anton Korobeynikov
2e1da9fea4 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85765 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:06 +00:00
Anton Korobeynikov
f95215f551 Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:10:38 +00:00
Evan Cheng
e3ce8aab0a Fix a couple more places where we are creating ld / st instructions without memoperands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85746 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-01 22:04:35 +00:00
Evan Cheng
48d8afab73 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85743 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-01 21:12:51 +00:00
Chris Lattner
43f44aa160 improve x86 codegen support for blockaddress. We now compile 
the testcase into:

_test1:                                                     ## @test1
## BB#0:                                                    ## %entry
	leaq	L_test1_bb6(%rip), %rax
	jmpq	*%rax
L_test1_bb:                                                 ## Address Taken
LBB1_1:                                                     ## %bb
	movb	$1, %al
	ret
L_test1_bb6:                                                ## Address Taken
LBB1_2:                                                     ## %bb6
	movb	$2, %al
	ret

Note, it is very very strange that BlockAddressSDNode doesn't carry 
around TargetFlags.  Dan, please fix this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85703 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-01 03:25:03 +00:00
Evan Cheng
de17fb6e4d Use cbz and cbnz instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85698 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 23:46:45 +00:00
Jim Grosbach
8cd0a8cb82 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 22:57:36 +00:00
Jim Grosbach
bcf2f2c159 Expand 64-bit logical shift right inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:42:19 +00:00
Jim Grosbach
b4a976c304 Expand 64-bit arithmetic shift right inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:00:56 +00:00
Jim Grosbach
c2b879fcfe Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 19:38:01 +00:00
Evan Cheng
9eda68988e It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 03:39:36 +00:00
Kevin Enderby
9c41fa87ea Updates to the ARM target assembler for llvm-mc per review comments from 
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand.  And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 22:55:57 +00:00
Bob Wilson
57f224a5a4 Add a note about Robert Muth's alternate jump table implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85624 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 22:22:46 +00:00
Dan Gohman
0115e164ba Fix MachineLICM to use the correct virtual register class when 
unfolding loads for hoisting.  getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 22:18:41 +00:00
Bob Wilson
929ffa2414 Fix a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 20:13:25 +00:00
Rafael Espindola
c1382b745f This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 14:33:14 +00:00
Bob Wilson
ddb16df912 Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 05:45:42 +00:00
Dan Gohman
f705adbe5e Initial x86 support for BlockAddresses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 01:28:02 +00:00
Jim Grosbach
95d9504d46 Dial back the realignment a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85546 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 00:08:40 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Jim Grosbach
84e58d03c9 To get more thorough testing from llc-beta nightly runs, do dynamic stack 
realignment regardless of whether it's strictly necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85476 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 02:41:21 +00:00
Bob Wilson
a597103c32 Revert r85346 change to control tail merging by CodeGenOpt::Level. 
I'm going to redo this using the OptimizeForSize function attribute.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85426 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 20:46:46 +00:00
Bob Wilson
8d4de5abfa Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 18:26:41 +00:00
Evan Cheng
30c80211b6 fconsts and fconstd are obviously re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85410 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 18:19:56 +00:00
Jim Grosbach
ca5dfb71ba Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85406 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 17:33:28 +00:00
Evan Cheng
c59420867e Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 06:55:03 +00:00
Evan Cheng
89321166da X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85379 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 06:30:34 +00:00
Chris Lattner
0eeb913aa1 Previously, all operands to Constant were themselves constant. 
In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85375 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 05:14:34 +00:00
Evan Cheng
39382427f1 Use fconsts and fconstd to materialize small fp constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 01:44:26 +00:00
Evan Cheng
a1eaa3c52b Add a second ValueType argument to isFPImmLegal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85361 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 01:43:28 +00:00
Dan Gohman
aa123224c4 Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides 
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.

This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85357 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 00:55:57 +00:00
Bob Wilson
04ea6e5150 Add an indirect branch pattern for ARM. Testcase will be coming soon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85355 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 00:37:03 +00:00
Chris Lattner
ab21db79ef rename indbr -> indirectbr to appease the residents of #llvm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85351 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 00:19:10 +00:00
Bob Wilson
cd4f04d6bc Record CodeGen optimization level in the BranchFolding pass so that we can 
use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85346 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 23:49:38 +00:00
Bill Wendling
c872e9c07d Add new note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85341 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 23:30:07 +00:00
Jim Grosbach
a6a99b4e16 Enable virtual register based frame index scavenging by default for ARM & T2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85335 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:52:29 +00:00
Bill Wendling
5a56927345 Move and clarify note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85334 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:48:31 +00:00
Jim Grosbach
3dab277857 Infrastructure for dynamic stack realignment on ARM. For now, this is off by 
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85333 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:45:39 +00:00
Bill Wendling
de020736c0 Note corrected. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85332 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:43:24 +00:00
Bill Wendling
d8499c9b7f Modify note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85331 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:40:45 +00:00
Bill Wendling
1ff2c485e2 Add a note. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85329 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:34:43 +00:00
Chris Lattner
627b470981 cppbackend support for indbr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85312 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 21:24:48 +00:00
Chris Lattner
f0dca28da7 CBE support for indbr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85311 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 21:21:06 +00:00
Johnny Chen
90d7dcfdd9 Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85299 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 20:51:49 +00:00
Johnny Chen
eadeffb306 Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between 
BL_pred and BLr9_pred.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85297 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 20:45:15 +00:00
Evan Cheng
eb2f969a4d Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85281 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 19:56:55 +00:00
Bob Wilson
f3b0d1a555 Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" 
instruction format that already takes care of setting this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85280 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 19:52:03 +00:00
Johnny Chen
76b39e88e4 Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85271 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 18:44:24 +00:00
Sanjiv Gupta
e70b897126 Remove unnecessary gotos to fall-thru successors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85257 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 17:40:24 +00:00
Johnny Chen
6a3b5eec89 Test commit. Added '.' to the comment line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85255 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 17:25:15 +00:00
Chris Lattner
1995051395 apparently the X86 JIT isn't fully contextized, it is still using getGlobalContext() :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85252 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 17:01:03 +00:00
Rafael Espindola
f87611272b Correctly align double arguments in the stack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85235 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 14:09:44 +00:00
Evan Cheng
dd22a45acc Now VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85186 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 00:20:49 +00:00
Evan Cheng
699bebac4f Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 00:08:59 +00:00
Evan Cheng
162e30921d Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85178 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 23:45:59 +00:00
Victor Hernandez
046e78ce55 Remove FreeInst. 
Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85176 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 23:43:48 +00:00
Bob Wilson
dda9583e51 Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85173 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:59:12 +00:00
Bob Wilson
d9ecd3108f Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85169 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:42:13 +00:00
Bob Wilson
7e053bb33c Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85167 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:34:44 +00:00
Ted Kremenek
7c44beaf93 Update CMake files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85161 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:06:01 +00:00
Anton Korobeynikov
8b5af25a14 Revert r85134, it breaks mingw build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85138 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 18:40:24 +00:00
Sanjiv Gupta
be9e763697 Make PIC16 overlay a loadable pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85134 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 18:22:59 +00:00
David Goodwin
2e7be612d5 Break anti-dependence breaking out into its own class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 16:59:04 +00:00
Chandler Carruth
8b67f774e9 Move DataTypes.h to include/llvm/System, update all users. This breaks the last 
direct inclusion edge from System to Support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85086 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 01:35:46 +00:00
Jim Grosbach
dd5694203b of -> or 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85065 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 19:14:48 +00:00
Jim Grosbach
f639e9f9e6 80-column cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85064 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 18:55:46 +00:00
Sanjiv Gupta
e1ef91d275 Reapply 85006 with a minor fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85052 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 08:14:11 +00:00
Evan Cheng
4f54c1293a Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85049 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 07:53:28 +00:00
Evan Cheng
ed3ad212ec Don't forget subreg indices when folding load / store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 07:52:27 +00:00
Nick Lewycky
f5a86f45e7 Remove includes of Support/Compiler.h that are no longer needed after the 
VISIBILITY_HIDDEN removal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:57:41 +00:00
Nick Lewycky
6726b6d75a Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:33:48 +00:00
Chris Lattner
a1e1446056 this is done. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85041 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:17:51 +00:00
Nick Lewycky
4a134afaef Remove ICmpInst::isSignedPredicate which was a reimplementation 
CmpInst::isSigned.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85037 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 05:20:17 +00:00
Sanjiv Gupta
ecb28f2b49 Revert back 85006 for now as it breaks PIC16 tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85008 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 18:19:41 +00:00
Sanjiv Gupta
209e6c69d9 Adding support for placing global objects in shared data memory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 18:02:44 +00:00
Evan Cheng
5a850beb2e 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 02:07:42 +00:00
Jim Grosbach
2f1abe2dae Restrict Thumb1 register allocation to low registers, even for instructions that 
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84982 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 00:19:24 +00:00
Jim Grosbach
7388037dd1 FIXME no longer applies. R12 and R3 are available for allocation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84977 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-23 23:07:42 +00:00
Chris Lattner
9ff9b34dd1 some stuff is done, we still have constantexpr simplification to do. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84943 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-23 07:00:55 +00:00
Evan Cheng
c869d063d4 X86 needs critical path anti-dependency breaking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84931 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-23 05:57:35 +00:00
David Goodwin
4c3715c2e5 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 23:19:17 +00:00
Bob Wilson
bac6ed4ba4 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 16:52:21 +00:00
Benjamin Kramer
1395d1df09 Shift art to the right to keep GCC from complaining about multi-line comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84849 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 09:28:49 +00:00
Evan Cheng
87689d3b70 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 06:48:32 +00:00
Evan Cheng
faf93aa233 Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84842 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 06:47:35 +00:00
Evan Cheng
62d1723a9c Trim more includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84832 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 05:11:00 +00:00
Evan Cheng
268c79350e Trim include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84831 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 05:08:49 +00:00
Chris Lattner
c5e5498058 fix warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84826 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 03:42:27 +00:00
Evan Cheng
8000c6c535 Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 00:40:00 +00:00
Anton Korobeynikov
f32df4ce3e Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected. 
Yay for ASCII graphics!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84808 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 00:16:00 +00:00
Jim Grosbach
41fff8c19a Missing piece of the ARM frame index post-scavenging conditionalization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 23:40:56 +00:00
Jim Grosbach
1d6827bbe9 Conditionalize ARM/T2 frame index post-scavenging while working out fixes 
for a few bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84791 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 22:59:24 +00:00
Bob Wilson
20d108140e Most of the NEON shuffle instructions do not support 64-bit element types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84785 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 21:36:27 +00:00
Anton Korobeynikov
a55d33d96e Revert r84764, it breaks mingw build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84783 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 21:15:18 +00:00
Jim Grosbach
65b7f3af76 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 20:44:34 +00:00
Anton Korobeynikov
a91f4c561e Add DAG printing for RMW stuff debugging 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84776 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 19:18:28 +00:00
Anton Korobeynikov
83fceb9481 RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84775 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 19:17:55 +00:00
Anton Korobeynikov
90593d2e1f Implement branch folding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84774 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 19:17:18 +00:00
Anton Korobeynikov
3926fb63c2 Cosmetic changes, no functionality changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84773 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 19:16:49 +00:00
Bob Wilson
b27b51aaa6 Fix NEON VST2LN instruction encoding. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 17:54:01 +00:00
Bob Wilson
407d57489f Revert 84732. It was the wrong fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 17:52:34 +00:00
Sanjiv Gupta
36a9c8f0b3 Build shared lib instead of an archive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 17:27:23 +00:00
Sanjiv Gupta
4e4bba5c80 Add a pass to overlay pic16 data sections for function frame and automatic 
variables. This pass can be invoked by llvm-ld or opt to traverse over the call graph 
to detect what function frames and their automatic variables can be overlaid.
Currently this builds an archive , but needs to be changed to a loadable module.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84753 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 10:42:44 +00:00
Evan Cheng
2095659a85 Match more patterns to movt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 08:15:52 +00:00
Chris Lattner
1ce75ef5ef tidy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84738 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 04:10:24 +00:00
Bob Wilson
b3c8359360 Fix some more NEON instruction encoding problems. 
Thanks to Johnny Chen for discovering the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84732 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 02:27:20 +00:00
Bob Wilson
507df402b0 Leave some NEON instruction encoding bits unspecified instead of setting 
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84730 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 02:15:46 +00:00
Chris Lattner
7d26443bb7 IPSCCP is missing stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84725 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 01:10:37 +00:00
Anton Korobeynikov
12ddf139ce Add note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84713 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:14:15 +00:00
Anton Korobeynikov
514200d5ef Be crazy and assert in case of unsupported modifier passed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84712 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:13:58 +00:00
Anton Korobeynikov
0a2e206b40 Handle external symbols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84711 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:13:42 +00:00
Anton Korobeynikov
8ecaf237e0 Distinguish between pcrel imm operands and 'normal' ones. Fix fixes gross weirdness of asmprinting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84710 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 00:13:25 +00:00