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5558 Commits

Author SHA1 Message Date
Richard Trieu
8223e45dff Fix a non-firing assert. Change: 
assert("bad SymbolicOp.VariantKind");
To:
    assert(0 && "bad SymbolicOp.VariantKind");


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 20:50:26 +00:00
Jakob Stoklund Olesen
ccbe603869 Ban rematerializable instructions with side effects. 
TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 01:00:49 +00:00
Eli Friedman
ecb830e45c Fix undefined shift. Patch by Ahmed Charles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141914 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 23:36:06 +00:00
Eli Friedman
8e4d0429de Simplify and avoid undefined shift. Based on patch by Ahmed Charles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 22:40:23 +00:00
Owen Anderson
c18e940c5a SETEND is not allowed in an IT block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141874 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 17:58:39 +00:00
Jim Grosbach
81b2928d80 ARM addrmode5 represents the 'U' bit of the encoding backwards. 
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141819 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 21:59:02 +00:00
Jim Grosbach
c66e7afcf2 Thumb2 assembly parsing and encoding for LDC/STC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 20:54:17 +00:00
Jim Grosbach
b0786b33fa addrmode2 is gone from these, so no need for the reg0 operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 18:11:24 +00:00
Jim Grosbach
9b8f2a0b36 ARM parsing and encoding for the <option> form of LDC/STC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 17:34:41 +00:00
Jim Grosbach
01208d56e8 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 16:36:01 +00:00
Jim Grosbach
bc9c80240b Tidy up. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 16:34:37 +00:00
Jakob Stoklund Olesen
1c062c24ab Fix -widen-vmovs liveness issues. 
When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 00:06:23 +00:00
Jim Grosbach
2bd0118472 ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. 
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:55:36 +00:00
Bill Wendling
e575499d83 Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:40:47 +00:00
Jim Grosbach
2cf8dd384e ARM addressing mode cleanup for LDC/STC. 
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 20:17:35 +00:00
Jim Grosbach
57dcb85a30 ARM parse alignment specifier for NEON load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 17:29:55 +00:00
Jim Grosbach
e53c87b302 ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141671 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 15:59:20 +00:00
Jakob Stoklund Olesen
142bd1a54e Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo(). 
The VMOVS widening needs to look at the implicit COPY operands.  Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.

The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:59:06 +00:00
Bill Wendling
3f56d4b957 Simplify check that optional def is there and is CPSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:10:41 +00:00
Lang Hames
bb5b3f3359 Add a natural stack alignment field to TargetData, and prevent InstCombine from 
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.

The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 23:42:08 +00:00
Jim Grosbach
f6c35c59f5 Simplify operand Kind checks a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 23:06:42 +00:00
Bill Wendling
ef2c86f876 Reapply r141365 now that PR11107 is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:59:55 +00:00
Jim Grosbach
38fbe32315 Add a name to sub-operand for clarity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141590 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:55:05 +00:00
Bill Wendling
721e1d2669 If the CPSR is defined by a copy, then we don't want to merge it into an IT 
block. E.g., if we have:

  movs  r1, r1
  rsb   r1, 0
  movs  r2, r2
  rsb   r2, 0

we don't want this to be converted to:

  movs  r1, r1
  movs  r2, r2
  itt   mi
  rsb   r1, 0
  rsb   r2, 0

PR11107 & <rdar://problem/10259534>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141589 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:52:53 +00:00
Bill Wendling
eba564ceac Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:27:30 +00:00
Bill Wendling
8129d21396 When getting the number of bits necessary for addressing mode 
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 07:24:23 +00:00
Chad Rosier
29b9d7e4ea Fix a regression from r138445. If we're loading from the frame/base pointer 
the tADDrSPi instruction can't be used.  Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141523 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 01:03:35 +00:00
Anton Korobeynikov
2d4b60f3a4 Disable ABS optimization for Thumb1 target, we don't have necessary instructions there. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141481 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 08:38:45 +00:00
Jim Grosbach
460a90540b ARM NEON assembly parsing and encoding for VDUP(scalar). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:56:00 +00:00
Jim Grosbach
21ff17ce1b ARM prefix asmparser operand kind enums for readability. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:24:09 +00:00
Bill Wendling
2acf638216 Take all of the invoke basic blocks and make the dispatch basic block their new 
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.

This more closely resembles what the CFG is actually doing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141436 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:18:02 +00:00
Bill Wendling
f1083d4139 Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit 
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141419 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 22:08:37 +00:00
Bill Wendling
ce370cfd89 Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to 
do. This will be useful later on with the new SJLJ stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 21:25:38 +00:00
Jim Grosbach
186ffac4d3 Improve ARM assembly parser diagnostic for unexpected tokens. 
Consider:
  mov r8, r11 fred

Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list

^

Now we generate:
x.s:5:14: error: unexpected token in argument list
  mov r8, r11 fred
              ^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141380 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 18:27:04 +00:00
Bob Wilson
6d2f9cec71 Reenable tail calls for iOS 5.0 and later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 17:17:49 +00:00
Bob Wilson
2fef4573df Reenable use of divmod compiler_rt functions for iOS 5.0 and later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 16:59:21 +00:00
Anton Korobeynikov
244455e6d6 Peephole optimization for ABS on ARM. 
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 16:15:08 +00:00
Bill Wendling
217f0e9ca4 Use the correct vreg here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141342 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 23:41:14 +00:00
Bill Wendling
083a8eb063 Generate the dispatch code for a 'thumb' function. This is very similar to the 
others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 23:37:36 +00:00
Owen Anderson
7011eee9b5 Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 23:33:11 +00:00
Bill Wendling
95ce2e9c52 Generate the dispatch table for ARM mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141327 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 22:53:00 +00:00
Bill Wendling
e29fa1df55 Refactor some of the code that sets up the entry block for SjLj EH. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 22:18:16 +00:00
Bill Wendling
5e2cbc1133 Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!) 
Place the immediate to OR into a register so that it works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 21:51:21 +00:00
Bill Wendling
04f15b4f2f * Set the low bit of the return address when we are in thumb mode. 
* Some code cleanup.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 21:29:56 +00:00
Peter Collingbourne
de8f33c199 Build system infrastructure for multiple tblgens. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 01:51:51 +00:00
Bill Wendling
930193cb55 Add the MBBs before inserting the instructions. Doing it afterwards could lead 
to an infinite loop because of the def-use chains.

Also use a frame load instead of store for the LD instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141263 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 00:53:33 +00:00
Cameron Zwarich
8f8aa815b4 Always merge profitable shifts on A9, not just when they have a single use. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141248 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 23:39:02 +00:00
Cameron Zwarich
d78ebe1e12 Remove a check from ARM shifted operand isel helper methods, which were blocking 
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 23:38:50 +00:00
Bill Wendling
5cbef19a1d Get the proper call site numbers for the landing pads. Also remove a magic 
number (18) for the proper addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 23:28:57 +00:00
Owen Anderson
2dbb46a0a0 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 17:16:40 +00:00
Cameron Zwarich
fb77752253 Add braces around something that throws me for a loop. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141173 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 08:59:10 +00:00
Cameron Zwarich
5ee0262014 There is no point in setting out-parameters for a ComplexPattern function when 
it returns false, at least as far as I could tell by reading the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 08:59:05 +00:00
Bill Wendling
bb73468e2b Look at the number of entries in the jump table and jump to a 'trap' block if 
the value exceeds that number.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141143 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 00:39:32 +00:00
Bill Wendling
2a85015313 Checkpoint for SJLJ EH code. 
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141140 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 00:02:33 +00:00
Owen Anderson
2fec6c5ff1 Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 23:26:17 +00:00
Kevin Enderby
9e5887b17e Adding back support for printing operands symbolically to ARM's new disassembler 
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 22:44:48 +00:00
Jim Grosbach
9d39036f62 ARM assembly parsing and encoding for VMOV immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:38:36 +00:00
Jim Grosbach
2a3f19d7e3 Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141043 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:03:26 +00:00
Bill Wendling
ff4216a68a Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 22:44:15 +00:00
Jim Grosbach
68259145d9 ARM parsing/encoding for VCMP/VCMPE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 22:30:24 +00:00
Bill Wendling
f7e4aefd0f Check-pointing the new SjLj EH lowering. 
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:25:38 +00:00
Jim Grosbach
5cd5ac6ad4 ARM assembly parsing and encoding for VMRS/FMSTAT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:12:43 +00:00
Jim Grosbach
b95ed6ec46 Thumb2 ADD/SUB can take SP as a destination register. 
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:51:59 +00:00
Chad Rosier
2bfaf521ae Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions." 
to appease nightly testers.  Not quite there yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 19:30:36 +00:00
Bill Wendling
2e6b97bbf8 No one should be using the method directly. Assert if they do. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 12:47:34 +00:00
Bill Wendling
405ca137a1 Add a convenience method to tell if two things are equal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 12:44:28 +00:00
Bill Wendling
3320f2a3bf Use the ARMConstantPoolMBB class to handle the MBB values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 09:30:42 +00:00
Bill Wendling
9c18f51daa Add ARMConstantPoolMBB to hold an MBB value in the constant pool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140942 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 09:19:10 +00:00
Bill Wendling
14a1a6b018 Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140941 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 09:05:12 +00:00
Bill Wendling
9aca75c4f8 Remove now dead methods and ivar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140940 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 09:04:18 +00:00
Bill Wendling
fe31e67350 Use the new ARMConstantPoolSymbol class to handle external symbols. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140939 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 08:58:29 +00:00
Bill Wendling
ff4a8023ec Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140938 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 08:36:59 +00:00
Bill Wendling
3f4e4592c3 Remove now dead methods and ivar from ARMConstantPoolValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 08:02:05 +00:00
Bill Wendling
5bb779976a Switch over to using ARMConstantPoolConstant for global variables, functions, 
and block addresses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 08:00:54 +00:00
Bill Wendling
3e944e38ea Some more refactoring. 
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140935 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 07:52:37 +00:00
Bill Wendling
029e93888d Add a Create method that accepts 'kind' and 'pcadj' arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140934 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 06:44:24 +00:00
Bill Wendling
f2b76aae2b Refactoring: Separate out the ARM constant pool Constant from the ARM constant 
pool value.

It's not used right now, but will be soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140933 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 06:40:33 +00:00
Chad Rosier
5249041125 Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact 
useful if an optimization assumes the stack has been realigned.  Credit to
Eli for his assistance.
rdar://10043857

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140924 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 02:03:18 +00:00
Jakob Stoklund Olesen
c8e2bb68bb Store sub-class lists as a bit vector. 
This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 22:19:07 +00:00
Jim Grosbach
f391e9f696 Correct for my over-eager delete finger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140892 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 22:02:45 +00:00
Bill Wendling
d98f838284 Constify 'isLSDA' and move a method out-of-line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140868 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 18:42:06 +00:00
Jim Grosbach
6f09fcf5da ARM Darwin default relocation model is PIC. 
This matches clang, so default options in llc and friends are now closer to
clang's defaults.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 17:41:35 +00:00
Jim Grosbach
98602ac9a9 ARM Fixup valus for movt/movw are for the whole value. 
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.

rdar://9653509


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 17:23:05 +00:00
Jim Grosbach
4ebbf7b8a8 ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428



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 2011-09-30 00:50:06 +00:00
Bill Wendling
e00897c5a9 Create a machine basic block in the constant pool and retrieve the symbol for an MBB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140824 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 23:50:42 +00:00
Bill Wendling
4dd9b091cc Support creating a constant pool value for a machine basic block. 
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140823 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 23:48:44 +00:00
NAKAMURA Takumi
13f4a6c940 Target/ARM: Unbreak! CMake! Build! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140774 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 03:32:49 +00:00
Jakob Stoklund Olesen
adcb634d85 Delete NEONMoveFix, now unused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140773 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 02:56:45 +00:00
Jakob Stoklund Olesen
8bb3d3cb30 Use ExecutionDepsFix instead of NEONMoveFix. 
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 02:48:41 +00:00
Bill Wendling
3511cedf36 Move to ISelLowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 01:13:55 +00:00
Evan Cheng
9b88d2d782 Tighten a ARM dag combine condition to avoid an identity transformation, which 
ends up introducing a cycle in the DAG.

rdar://10196296


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 23:16:31 +00:00
Bill Wendling
b18abd077e Perform the lowering only if there are invokes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140719 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 20:29:45 +00:00
Bill Wendling
39689c8154 Ahem...actually *add* the ARMSjLjLowering pass to the pass manager. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 20:29:28 +00:00
James Molloy
acad68da50 Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 14:21:38 +00:00
Ted Kremenek
833217bfb9 Unbreak CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140655 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 23:29:59 +00:00
Jakob Stoklund Olesen
13fd601e0f Implement TII::get/setExecutionDomain() for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 22:57:21 +00:00
Jim Grosbach
25ddc2bf7e ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. 
Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 22:18:54 +00:00
Bill Wendling
0481d29d49 This is the start of the new SjLj EH preparation pass, which will replace the 
current IR-level pass.

The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).

Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140646 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 22:14:12 +00:00
Jim Grosbach
5405d58e21 Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId(). 
Naming conventions consistency. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 20:59:33 +00:00
Jakob Stoklund Olesen
8e695eb5fa Use existing function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140615 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 17:55:08 +00:00
Owen Anderson
2dafe200ca Remove extraneous commit garbage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140581 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 23:14:02 +00:00
Owen Anderson
0afa0094af ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:06:22 +00:00
David Meyer
8f418b11d2 PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 06:13:20 +00:00
Owen Anderson
4d2a00147d Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:25:02 +00:00
Jakob Stoklund Olesen
11ebe3d7c1 Also match negative offsets for addrmode3 and addrmode5. 
Math is hard, and isScaledConstantInRange() always returned false for
negative constants.  It was doing unsigned division of negative numbers
before casting back to signed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140425 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 22:10:33 +00:00
Owen Anderson
4a713570b6 Add more fixed bits to USAT16 encoding to filter out incorrect decodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:57:50 +00:00
Owen Anderson
0781c1f700 Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:26:40 +00:00
Owen Anderson
31d485ec9a Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:07:25 +00:00
Owen Anderson
df0caeb6ec Revert r140412. This affects more instructions than intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:02:01 +00:00
Owen Anderson
d256056581 Thumb2 register-shifted-register loads cannot target the PC or the SP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:00:32 +00:00
Owen Anderson
6126870193 Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:53:44 +00:00
Owen Anderson
e136872970 Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:44:46 +00:00
Owen Anderson
519020adf1 These do not need to be conditional on the presence of CommentStream, as they have a fallback path now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 17:58:45 +00:00
Andrew Trick
3be654f808 Lower ARM adds/subs to add/sub after adding optional CPSR operand. 
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:20:46 +00:00
Andrew Trick
e23dc9c0ef whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140227 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:17:37 +00:00
Owen Anderson
317eaf1993 In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 00:25:23 +00:00
Evan Cheng
0d18174f0f Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 21:38:18 +00:00
Andrew Trick
83a8031336 Restore hasPostISelHook tblgen flag. 
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 18:22:31 +00:00
Andrew Trick
4815d56bb2 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 03:17:40 +00:00
Andrew Trick
3af7a67629 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 03:06:13 +00:00
Jim Grosbach
50f1c37123 Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:46:54 +00:00
Jim Grosbach
6053cd956f Thumb2 assembly parsing and encoding for USAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:30:45 +00:00
Jim Grosbach
8c9898454c Remove incorrect comments. These are not disassmebly only patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:26:34 +00:00
Jim Grosbach
ab3bf97fe0 Thumb2 assembly parsing and encoding for UQASX/UQSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:18:52 +00:00
Jim Grosbach
abb8aacef2 Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:10:37 +00:00
Jim Grosbach
26215425da Thumb CPS definition is not disassembler only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:00:06 +00:00
Jim Grosbach
0efe213ed5 Thumb2 range check on CPS mode immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:58:31 +00:00
Owen Anderson
d9346fbb06 tMOVSr is not allowed in an IT block either. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:57:20 +00:00
Owen Anderson
9f666b5f2e CPS instructions are UNPREDICTABLE inside IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:47:10 +00:00
Jim Grosbach
32f36899e9 Tidy up comments. 
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 2011-09-19 23:38:34 +00:00
Jim Grosbach
d5d0e81a4b Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:31:02 +00:00
Jim Grosbach
6729c48b94 Thumb2 assembly parsing and encoding for UHASX/UHSAX. 
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 2011-09-19 23:13:25 +00:00
Jim Grosbach
4032eaf98c Thumb2 assembly parsing and encoding for UASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140085 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:05:22 +00:00
Owen Anderson
04c7877894 Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:34:23 +00:00
Jim Grosbach
7f739bee26 Thumb2 assembly parsing and encoding for TBB/TBH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:21:13 +00:00
Jim Grosbach
bc80e94865 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 20:31:59 +00:00
Jim Grosbach
326efe5891 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 20:29:33 +00:00
Owen Anderson
061c3c4506 Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140041 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 20:00:02 +00:00
Jim Grosbach
fb12f35545 ARM asm parsing should handle pre-indexed writeback w/o immediate. 
For example, 'ldrb r9, [sp]!' is odd, but valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140035 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 18:42:21 +00:00
Owen Anderson
ecd1c55790 Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 18:07:10 +00:00
Jim Grosbach
8a8d28b039 Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 17:56:37 +00:00
Owen Anderson
cb77551927 Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 23:30:01 +00:00
Owen Anderson
8b22778431 Fix bitfield decoding based on Eli's feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 23:04:48 +00:00
Jim Grosbach
f67e8554bf Thumb2 assembly parsing and encoding for SUB(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:58:42 +00:00
Owen Anderson
e4f2df945a Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:42:36 +00:00
Owen Anderson
89db0f690c Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:29:48 +00:00
Owen Anderson
8a28bdcbcc Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:17:02 +00:00
Jim Grosbach
ee2c2a4f98 Thumb2 assembly parsing and encoding for STR. 
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:55:56 +00:00
Jim Grosbach
947a24cd64 Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139944 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:09:00 +00:00
Owen Anderson
705b48ff86 Fix disassembly of Thumb2 LDRSH with a #-0 offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:08:33 +00:00
Jim Grosbach
642caea2c6 Thumb2 assembly parsing and encoding for STR(immediate). 
Add aliases for STRB/STRH while there. Tests forthcoming for those.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139942 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:06:12 +00:00
Jim Grosbach
8213c96655 Thumb2 assembly parsing and encoding for STMIA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 20:50:13 +00:00
Jim Grosbach
50bd470d85 Thumb2 assembly parsing and encoding for SSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:37:10 +00:00
Jim Grosbach
b105b997a4 Thumb2 assembly parsing and encoding for SSAT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139926 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:32:30 +00:00
Jim Grosbach
05ec8f7ac9 Thumb2 assembly parsing and encoding for SRS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:25:22 +00:00
Jim Grosbach
3443ed525a Thumb2 assembly parsing and encoding for SMMULL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:05:48 +00:00
Jim Grosbach
7ff2472b82 Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139909 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 17:10:44 +00:00
Jim Grosbach
231948f860 Thumb2 assembly parsing and encoding for SMLALD/SMLALDX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139906 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 16:58:03 +00:00
Jim Grosbach
db7e2e59dd Kill some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139904 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 16:45:40 +00:00
Jim Grosbach
fb9cffea4a Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 16:39:25 +00:00
Jim Grosbach
837fc5e9d5 Thumb2 assembly parsing and encoding for SMLAL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 16:38:00 +00:00
Jim Grosbach
eeca7582fa Remove incorrect comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139877 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 23:45:50 +00:00
Owen Anderson
98c5ddabca Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 23:38:46 +00:00
Jim Grosbach
c075d45364 Thumb2 assembly parsing and encoding for SHASX/SHSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139870 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 22:34:29 +00:00
Eli Friedman
74bf18ccea Minor cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139869 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 22:26:18 +00:00
Eli Friedman
7cc156647f Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139865 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 22:18:49 +00:00
Jim Grosbach
e4e4a93e9e Thumb2 assembly parsing and encoding for SASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 21:01:23 +00:00
Jim Grosbach
191d33fd6d Thumb2 assembly parsing and encoding for RSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139839 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 20:54:14 +00:00
Jim Grosbach
689b86ed2e Thumb2 assembly parsing and encoding for REV16/REVSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139828 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 19:46:13 +00:00
Owen Anderson
ede042dc8d Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139820 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 18:36:29 +00:00
Jim Grosbach
1b69a128d6 Thumb2 assembly parsing and encoding for REV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139813 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 18:13:30 +00:00
Jim Grosbach
b6e9a83349 ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139796 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 16:16:50 +00:00
Jim Grosbach
57b21e437a Thumb2 push/pop mnemonic recognition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 15:55:04 +00:00
Jim Grosbach
0b69247b10 Thumb2 assembly parsing and encoding for PKH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 23:16:41 +00:00
Jim Grosbach
21a05e7017 ARMv7a has the PKH instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139753 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 23:16:34 +00:00
Jim Grosbach
e1d58a6556 ARM tighten up the register classes for the PKH instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139748 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 22:52:14 +00:00
Owen Anderson
8adf62034a Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 22:46:14 +00:00
Jim Grosbach
d32872f9ca Thumb2 assembly parsing and encoding for MVN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:24:41 +00:00
Owen Anderson
34626acf7f Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:06:21 +00:00
Jim Grosbach
64944f48a1 Thumb2 assembly parsing and encoding for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139735 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:00:40 +00:00
Jim Grosbach
bf841cf336 Thumb2 assembly parsing and encoding for MSR/MRS. 
Fix a bug in handling default flags for both ARM and Thumb encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 20:03:46 +00:00
Jim Grosbach
c2d3164ab4 Thumb2 assembly parsing for MOV in IT block. 
Select the right 16 vs. 32 bit encoding in an IT block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 19:12:11 +00:00
Jim Grosbach
d0588e2a2e ARM fix assembly parser handling of ranges in register lists. 
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.

rdar://8883573


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 18:08:35 +00:00
Jim Grosbach
d300b94e51 Remove unnecessary scope resolution operator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 22:56:44 +00:00
Owen Anderson
7782a58b87 Correct disassembly printing of Thumb2 post-incremented LDRD and STRD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139639 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:46:26 +00:00
Jim Grosbach
d7a2b3bea8 There's only 16 regs legal in a register list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139637 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:35:57 +00:00
Jim Grosbach
b04546ff5b Tidy up a few 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:30:37 +00:00
Jim Grosbach
8f310d9786 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:27:44 +00:00
Owen Anderson
b6b7f515e2 Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139610 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 17:59:19 +00:00
Owen Anderson
12c7e90d36 Fix encoding of Thumb2 shifted register operands with RRX shifts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 17:34:32 +00:00
Eli Friedman
885f1a0c04 Zap some junk from the ARM instruction descriptions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 02:29:58 +00:00
Jim Grosbach
2d539691a1 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 23:36:42 +00:00
Owen Anderson
cd00dc6852 Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 21:28:46 +00:00
Owen Anderson
fd92d2e106 Fix encoding of PC-relative LDRSHW with an immediate offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 20:36:51 +00:00
Owen Anderson
a073795023 There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139531 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 20:07:22 +00:00
Owen Anderson
a3157b4026 Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 18:56:30 +00:00
Jim Grosbach
1ad60c2adc Thumb2 parsing and encoding for MOV(immediate). 
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 00:15:36 +00:00
Owen Anderson
921d01ae1f LDM writeback is not allowed if Rn is in the target register list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:13:33 +00:00
Owen Anderson
112fb73502 Fix an ambiguously nested if. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:13:02 +00:00
Owen Anderson
cd4338fff5 Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139429 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:05:14 +00:00
Owen Anderson
08fef885eb Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:24:36 +00:00
Owen Anderson
51f6a7abf2 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:48:23 +00:00
Jim Grosbach
468709e43d Thumb2 assembly parsing and encoding for MLA and MLS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:24:45 +00:00
Jim Grosbach
0811fe13d6 Thumb2 assembly parsing and encoding for LDRSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:42:40 +00:00
Jim Grosbach
b6aed508e3 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 18:37:27 +00:00
Owen Anderson
441462f932 All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:48:37 +00:00
Owen Anderson
d2fc31b3f7 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:42:49 +00:00
Jim Grosbach
a77295db19 Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:07:06 +00:00
Jim Grosbach
e64fb28da1 Thumb2 assembly parsing and encoding for LDR post-indexed. 
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 01:01:32 +00:00
Jim Grosbach
eeec025cf5 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 00:39:19 +00:00
Owen Anderson
170580e8f4 Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 00:11:18 +00:00
Jim Grosbach
f0eee6eca8 Thumb2 assembly parsing and encoding for LDRBT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:39:14 +00:00
Jim Grosbach
ab899c1bcc Thumb2 assembly parsing and encoding for LDR(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:10:15 +00:00
Jim Grosbach
8bb5a861a0 Thumb2 assembly parsing and encoding for LDRB(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:41:25 +00:00
Owen Anderson
8a83f71301 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:10:42 +00:00
Jim Grosbach
a8307dd1c9 Thumb2 parsing and encoding for LDR(immediate). 
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 20:58:57 +00:00
Jim Grosbach
94f914e3fd Thumb2 parsing and encoding for LDMDB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 19:57:53 +00:00
James Molloy
a5d5856854 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 19:42:28 +00:00
Jim Grosbach
cfbb3a78db Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix. 
There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139243 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 18:39:47 +00:00
Jim Grosbach
76ecc3d35b Thumb2 parsing and encoding for LDMIA. 
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 18:05:34 +00:00
Owen Anderson
6de3c6f1a9 Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 17:55:19 +00:00
James Molloy
b950585cc5 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 17:24:38 +00:00
Jim Grosbach
ffa5a76344 Thumb2 use 'ldm' as default mnemonic. 
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 16:22:42 +00:00
Jim Grosbach
81d2e3901e Better diagnostic location information for mnemonic suffices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139232 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 16:06:04 +00:00
Jim Grosbach
218affc710 ISB is HasDB, not just HasV7. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139202 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 23:09:19 +00:00
Jim Grosbach
aa833e53dc Thumb2 parsing and encoding for ISB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 22:53:27 +00:00
Jim Grosbach
06c1a51241 Thumb2 parsing and encoding for DMB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 22:14:58 +00:00
Jim Grosbach
77951908b7 Thumb2 parsing and encoding for DBG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 22:06:40 +00:00
Jim Grosbach
ef88a92677 Thumb2 parsing and encoding for CMN and CMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139188 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 21:44:58 +00:00
Eli Friedman
34c4485b74 Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 20:53:37 +00:00
Jim Grosbach
ad2dad930d Thumb2 parsing and encoding for CLREX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 20:27:04 +00:00
Duncan Sands
28b77e968d Add codegen support for vector select (in the IR this means a select 
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 19:07:46 +00:00
Evan Cheng
4a51708448 Fix fall outs from my recent change on how carry bit is modeled during isel. 
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 18:52:20 +00:00
Jim Grosbach
98447daa95 ARM .code directive should always go to the streamer. 
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139155 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 18:46:23 +00:00
Jakob Stoklund Olesen
9b0e1e7a5b Atomic pseudos don't use (as in read) CPSR. They clobber it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 17:40:35 +00:00
Nick Lewycky
1fac6b50ea Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain 
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-05 21:51:43 +00:00
Nick Lewycky
7442a03dcc Fix typo in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139122 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-05 18:35:03 +00:00
Jim Grosbach
6c3e11ea55 Thumb2 parsing and encoding for BXJ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 23:43:09 +00:00
Jim Grosbach
a110988b39 Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139049 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 23:22:08 +00:00
Eli Friedman
4136d23c48 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 22:33:24 +00:00
Jim Grosbach
5f25fb01b4 Thumb2 parsing and encoding for ASR. 
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139040 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 21:28:54 +00:00
Jim Grosbach
8e0c7697fd Tidy up. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 18:46:15 +00:00
Jim Grosbach
d2990107a9 Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 18:43:25 +00:00
Jim Grosbach
5c1ac55542 Thumb2 parsing and encoding for AND (register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 18:41:35 +00:00
Jim Grosbach
f0851e5d95 Thumb2 parsing and encoding for ADD (register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 18:14:46 +00:00
Owen Anderson
a1c110045a Merge the ARM disassembler header into the implementation file, since it is not externally exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138982 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 23:35:51 +00:00
Owen Anderson
a6804444e8 Fix 80 columns violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 23:23:50 +00:00
Benjamin Kramer
36a16015ac Don't drop alignment info on local common symbols. 
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 23:04:27 +00:00
Eli Friedman
7df496d2ad Null-initialize to shut up -Wuninitialized warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 22:27:41 +00:00
Jim Grosbach
2f25d9b933 ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138952 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 18:22:13 +00:00