marqs
df643ec742
improve TVP7002 frontend sync detection
...
Store csync leading edge position so that field change timing can be calculated accurately upon VSYNC detection
2023-03-11 12:32:26 +02:00
marqs
804642bd98
integrate RTL from ossc_pro project
2023-02-28 19:39:59 +02:00
marqs
94c0526265
update project configuration and IP files
2023-02-13 18:55:14 +02:00
marqs
a8a3142071
add sync activity detection on tvp7002 frontend
2023-02-13 18:53:20 +02:00
marqs
76da437125
integrate new tvp7002 frontend
2023-01-31 20:51:06 +02:00
marqs
db1cf5922f
tvp7002 related robustness improvements
...
* bypass VSYNC processing
* enable raw SOG/HSYNC output
* add frontend RTL to read status from unprocessed signals
2023-01-31 20:49:08 +02:00
marqs
fd37e4275b
update to Quartus 21.1
2022-12-27 14:59:47 +02:00
marqs
73dd1963b9
update to Quartus 20.1.1
2021-07-31 18:06:21 +03:00
marqs
9c5e7b5b83
advanced OSD implementation
2020-10-05 23:05:43 +03:00
marqs
daf9ec1611
optimize line3x timing
2020-06-14 20:07:24 +03:00
marqs
2319a6f8bd
misc tool updates
2020-04-28 18:48:35 +03:00
Russell Harmon
bab85e713b
Increase max V. Backporch value from 63 to 236
...
This change allows highly letterboxed content (e.g. the PSP's 480x272
picture in a 720x480 frame) to be "zoomed" to a full screen picture by
treating the letterbox as horizontal and vertical backporch.
Co-authored-by: Chris Lockfort <clockfort@gmail.com>
2020-04-07 12:51:36 -07:00
marqs
0c55cc03bb
use LEDs for debug in latency tester mode
2020-02-09 21:35:50 +02:00
marqs
a076c6d2db
update quartus to 19.1
2020-02-09 21:28:24 +02:00
marqs
85c295c5e2
make pll_reconfig more robust
2019-10-12 22:56:10 +03:00
marqs
9feb96888b
fix PLL reference clock switchover logic
2019-10-09 23:58:55 +03:00
marqs
ba4614a4f8
correct even/odd field naming
2019-10-08 01:07:25 +03:00
marqs
b22365af20
add timeout to pll_reconfig and update postprocess pipeline diagram
2019-10-07 23:20:44 +03:00
marqs
3a12592c53
fix linebuf read address timing bottleneck
2019-10-07 01:25:33 +03:00
marqs
9d496383c3
optimize clock network
...
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-06 23:54:32 +03:00
marqs
d1fd30019f
osd_generator: add M9K support to allow larger character array
2019-10-05 11:33:59 +03:00
marqs
6266976114
first OSD implementation
2019-10-03 02:03:43 +03:00
marqs
aa43991534
add mask color option
2019-09-30 19:31:05 +03:00
marqs
5e0277fb48
add Panasonic hack for improving line count tolerance with line2x
2019-07-01 19:15:57 +03:00
marqs
9e81fb5922
Scanline updates and fixes
...
* Enable overlay pattern customization
* Fix non-alternating mode with line4x interlace sources
* Add alternate interval option for pre-linedoubled sources
2019-03-23 00:09:46 +02:00
paulb-nl
f276cda190
Add support for GBI 360p
2018-10-13 17:33:10 +02:00
marqs
7914a2ee83
clean up and update README
2018-10-08 00:37:42 +03:00
marqs
4676cbd2f0
integrate zero-riscy
2018-10-06 13:19:12 +03:00
marqs
22e49300df
fix line2x reverse LPF trigger
2018-04-18 23:14:24 +03:00
marqs
70ab55c1fa
fix optimized mode mask & position offsets
2018-04-15 23:41:26 +03:00
marqs
37650ca22b
misc improvements
...
* add character LCD backlight timeout option
* increase h.mask range
* show accurate (fpga-calculated) timings on infoscreen
2018-03-28 20:09:40 +03:00
marqs
9ad696dbc3
optimize away one pp stage and unify code formatting
2018-03-12 01:25:23 +02:00
borti4938
6877faa0b6
remove _bb.v files
2018-03-10 19:26:40 +01:00
borti4938
852054cdd0
finer granulated steps for hybrid sl settings
2018-03-07 10:21:18 +01:00
borti4938
985aeb1a93
use explicite ramstyle for post-processing pipeline to keep registers in logic (as suggested in pull-request #21 comments)
2018-03-07 09:45:27 +01:00
borti4938
45ca4e9268
undo changes as suggested in pull-request #21 comments
2018-03-07 09:43:37 +01:00
borti4938
0828addc83
Merge branch 'release' of https://github.com/marqs85/ossc into upstream
2018-03-07 08:29:49 +01:00
marqs
0ab31b30b4
simplify timing constraints
2018-03-07 09:21:19 +02:00
borti4938
5922e64f55
registered outputs to HDMI-TX after final mux
2018-03-06 13:08:47 +01:00
borti4938
209130b167
misc updates:
...
- integrate mask and border generation more deeply into the post processing chain
- delay RLPF by one PP stage (reduce logic length after large mux)
- synthesise a registers after several adder logics
2018-03-06 13:08:20 +01:00
borti4938
d7ee965d89
add missing IP files
2018-03-06 09:36:38 +01:00
borti4938
670f515141
various post processing pipeline updates:
...
- increase number of pipeline stages for scanline generation
- alternative hybrid strength implementation
- add missing file declaration in qsf
2018-03-06 09:36:21 +01:00
borti4938
b10d7f3762
SL Multiplication:
...
- Hybrid value based on Y (Y calculated according to YCoCg appr.)
- Use 8bit input as p-factor
2018-03-06 09:34:12 +01:00
borti4938
ba8ad6ce4c
add missing IP files
2018-03-06 09:33:28 +01:00
borti4938
0b51fd7758
- resolve conflicts from merge
...
- use hybrid contrast for both sl generation methods: multiplication and linear
2018-03-06 09:32:02 +01:00
borti4938
1a405c1e2e
Merge branch 'scanline_contrast' of https://github.com/paulb-nl/ossc into upstream
...
# Conflicts:
# rtl/scanconverter.v
# software/sys_controller/ossc/av_controller.c
2018-03-06 09:30:22 +01:00
paulb-nl
990bc1563e
Add Scanline contrast
...
Reduce scanline strength for bright pixels
2018-02-24 21:56:18 +01:00
borti4938
500a22f316
small simplification on reverse lpf implementation
2018-02-22 13:45:19 +01:00
borti4938
5249d313d8
scanlines generation via multiplication
2018-02-22 08:11:26 +01:00
paulb-nl
a39888845a
Add 32 step grayramp to test pattern
2018-01-20 22:08:10 +01:00
