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68030tk
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42 Commits

Author SHA1 Message Date
MHeinrichs a85ced47d0 dma improved 2017-12-30 01:39:22 +01:00
MHeinrichs 1152df45a6 Better timing & Resetfix 2016-11-30 23:10:23 +01:00
MHeinrichs ba4bc7b8fc timing timing timnig ... when will it end? 2016-10-16 19:58:33 +02:00
MHeinrichs 6665071ebe Improved speed on amiga cycles 2016-10-06 21:37:29 +02:00
MHeinrichs cb8dfae058 Cleaned up and the preempting DSACK is unneccessary?!? 2016-08-25 22:30:49 +02:00
MHeinrichs 00726c0582 Working at 254Mhz in CDTV! 2016-08-24 23:34:13 +02:00
MHeinrichs 23323633f9 Clarified some thing Timing can be adjusted with constants 2016-08-19 00:22:24 +02:00
MHeinrichs 0c2122cd7f Clean up 2016-08-18 07:48:07 +02:00
MHeinrichs 5eee23fe31 Cleaned up a bit 2016-01-24 20:26:06 +01:00
MHeinrichs 7c8801d6ee Reset-Circuit has less delay 2015-10-10 22:11:10 +02:00
MHeinrichs c39e83d66d some erratic tries 2015-07-18 14:06:08 +02:00
MHeinrichs c808e2f06a MIsc. Update 2015-06-26 18:32:40 +02:00
MHeinrichs fa0999c496 Sources for GBA-TK060 2015-03-28 22:03:17 +01:00
MHeinrichs e60f9456e7 DMA Back to A500: Working 2015-02-13 14:50:57 +01:00
MHeinrichs 2286431c0a DMA working for GVP 2015-02-03 21:34:33 +01:00
MHeinrichs 57c9d31821 DMA Improved and Reset pulled up 2015-02-03 10:22:30 +01:00
MHeinrichs f63fd90f80 DMA Improved for A2000 2015-02-01 21:42:02 +01:00
MHeinrichs a8cfe5adb5 Cleaned up 2014-10-16 22:05:48 +02:00
MHeinrichs 419cf9809f Tristating Data was a bad idea 2014-10-07 19:58:39 +02:00
MHeinrichs fb249c6203 Tristating bus drivers 2014-10-05 00:48:20 +02:00
MHeinrichs a42d9d702b More stability in constraints 2014-10-03 07:18:29 +02:00
MHeinrichs 02e2b00074 DMA-Started 2014-09-16 14:51:31 +02:00
MHeinrichs 1f269e383c Stuck at 25MHz 2014-08-12 21:24:42 +02:00
MHeinrichs 1a7a72f376 Update - minor changes 2014-08-12 20:28:14 +02:00
MHeinrichs e7bad9763e Chasing the instability 2014-08-09 23:02:53 +02:00
MHeinrichs c402614193 Wing Commander works but generally instable?! 2014-08-09 14:43:03 +02:00
MHeinrichs f3a861ba82 New file for PCB Rev 0.9d 2014-07-18 14:08:15 +02:00
MHeinrichs 2587047f0d Some Changes regarding CIIN and Timing 2014-06-15 16:53:31 +02:00
MHeinrichs fecb45b004 Caching for mem enabled 2014-06-09 20:27:37 +02:00
MHeinrichs 8adc589599 PE/NE-Sync started 2014-06-09 10:29:32 +02:00
MHeinrichs 8a57db1209 New PCB and start for RW-Signal-Optimization 2014-06-01 22:50:01 +02:00
MHeinrichs 3060b6be03 minor clean up 2014-05-29 22:06:01 +02:00
MHeinrichs 99277e926b dma-working and prework for turbo side 2014-05-28 21:34:35 +02:00
MHeinrichs 2bc1b94e91 DMA-TK-Side first non working version 2014-05-24 21:59:56 +02:00
MHeinrichs d187b3fa35 33MHz @100MHz basis working 2014-05-24 16:03:26 +02:00
MHeinrichs dd9d5e8c4e better amiga timing 2014-05-24 15:17:08 +02:00
MHeinrichs 228e58b64e sync 2014-05-22 15:00:48 +02:00
MHeinrichs 9643ce8642 50Mhz Clock working 2014-05-19 07:35:45 +02:00
MHeinrichs 3f0e99e010 Fixed external interface flaws 2014-05-16 20:18:55 +02:00
MHeinrichs be14e6527f Cleaned up version 
This version is the base for all future experiments.
 2014-05-15 23:05:08 +02:00
MHeinrichs dd8e1d7bac Working! 2014-05-15 22:19:03 +02:00
MHeinrichs 473a4a745b Initial push 
First VErsion after I decided to use version controll ;)
 2014-05-15 21:16:29 +02:00