Thomas Harte
e6ae35638b
Add HDV to Info.plist.
2022-11-15 15:20:12 -05:00
Thomas Harte
9b235a8f64
Create a specific container for HDV files.
2022-11-15 13:18:54 -05:00
Thomas Harte
005f38dbff
Merge branch 'master' into 68020
2022-11-11 20:35:35 -05:00
Thomas Harte
ae8f0d339e
Remove usage of sprintf
.
2022-11-11 20:29:59 -05:00
Thomas Harte
ccadf69630
Add test of operand_flags
and operand_size
; add entries for missing 68000 and 68010 instructions.
2022-10-31 15:15:05 -04:00
Thomas Harte
bbd2cd47ea
Decode [MUL/DIV][U/S].l.
2022-10-30 11:32:36 -04:00
Thomas Harte
63ad2e8263
Decode EXTB.l.
2022-10-30 11:20:43 -04:00
Thomas Harte
23e4a47f8b
Accept CHK.l and LINK.l decodings.
2022-10-30 11:16:32 -04:00
Thomas Harte
6ad1d74ddd
Parse and record duality of CHK2/CMP2.
2022-10-29 21:32:48 -04:00
Thomas Harte
12ca79e645
Decode CAS2.
2022-10-28 14:02:49 -04:00
Thomas Harte
85df54ee7d
Decode CAS.
2022-10-28 13:57:00 -04:00
Thomas Harte
2b220659dd
Incorporate PACK and UNPK.
2022-10-28 13:37:30 -04:00
Thomas Harte
e79388fc02
Codify RTM, TST, TRAPcc, Bcc, BF*.
2022-10-28 13:17:35 -04:00
Thomas Harte
041eb79bf8
Move 68010 up into the verified area.
2022-10-27 10:52:26 -04:00
Thomas Harte
adbd23eaea
Having verified manually, lock in 68010 instruction set.
2022-10-27 09:55:02 -04:00
Thomas Harte
8ddf20b36a
Provide cleaner output.
2022-10-25 22:33:25 -04:00
Thomas Harte
fd20323c25
Refactor to permit newer-chip testing.
2022-10-25 21:27:01 -04:00
Thomas Harte
9a56d053f8
Introduce/extend 68k enums to cover 68020 instruction set.
2022-10-22 15:20:30 -04:00
Thomas Harte
7c328edd4a
Use built-in install build trigger.
2022-10-21 15:28:50 -04:00
Thomas Harte
9be9e1ab0c
Use built-in install build trigger.
2022-10-21 15:28:11 -04:00
Thomas Harte
ad5047dbd5
Show failing operations as strings.
2022-10-19 22:25:09 -04:00
Thomas Harte
df7f94f362
Include MacintoshVolume in test build.
2022-10-19 14:41:08 -04:00
Thomas Harte
a364499d17
Revert inadvertent commits.
2022-10-17 23:15:45 -04:00
Thomas Harte
1f19141746
Eliminate BiggerInt
.
2022-10-11 16:19:47 -04:00
Thomas Harte
4d3221fc55
Enable dead code stripping; allow Xcode 14 to tag.
2022-09-16 19:53:36 -04:00
Thomas Harte
59388230a6
Record new macOS version number.
2022-09-16 16:14:59 -04:00
Thomas Harte
dc35ec8fa0
Merge branch 'master' into AppleIISCSI
2022-09-15 12:05:58 -04:00
Thomas Harte
0f017302ce
Fix tests.
2022-09-13 16:33:44 -04:00
Thomas Harte
dad1d7744e
Disable test generation.
2022-09-08 16:41:10 -04:00
Thomas Harte
de8ce3380c
Record only 8 bits for byte accesses.
2022-09-06 20:49:45 -04:00
Thomas Harte
b848b1389a
Include gaps in captured transactions, better collect final RAM state.
2022-09-06 15:08:35 -04:00
Thomas Harte
2c44ddfa95
Better bucket, and attempt to cover exceptions.
2022-09-06 11:26:38 -04:00
Thomas Harte
0fe94b2e6d
Capture ::SameAddress versus ::NewAddress, for TAS recognition.
2022-09-05 22:26:30 -04:00
Thomas Harte
93c1f7fc90
Include prefetch in 68000 state.
2022-09-05 22:00:04 -04:00
Thomas Harte
b6da1019bd
Bucket tests by operation, aim for ~1,000,000 total.
2022-09-05 21:52:48 -04:00
Thomas Harte
cee3f78059
Attempt to output only relevant RAM.
2022-09-03 15:45:06 -04:00
Thomas Harte
68f810883d
Begin process of creating on-disk tests.
2022-09-02 16:52:27 -04:00
Thomas Harte
cd7671e8fa
Merge branch 'master' into AppleIISCSI
2022-08-29 11:47:48 -04:00
Thomas Harte
330d852686
Adopt same format as the master.
2022-08-29 11:46:53 -04:00
Thomas Harte
303ea496f1
Incorporate new additional padding.
2022-08-29 11:45:11 -04:00
Thomas Harte
722e3a141d
Fix types, introduce Apple II mapper.
2022-08-24 12:00:03 -04:00
Thomas Harte
22a3f4de2c
Merge branch 'master' into AppleIISCSI
2022-08-23 20:00:02 -04:00
Thomas Harte
4ff2e7f546
Tweak info box copyright text: include symbol and newline.
2022-08-23 19:45:03 -04:00
Thomas Harte
cf356c59aa
Switch the Macintosh mapper to use Apple::PartitionMap.
2022-08-23 19:39:47 -04:00
Thomas Harte
1555b51d99
Begin a stumbling effort to generalise my implementation of the Apple Partition Map.
2022-08-23 16:46:47 -04:00
Thomas Harte
017f55390a
Better represent on-disk structure.
2022-08-23 16:19:04 -04:00
Thomas Harte
e9771ce540
Merge branch 'master' into AppleIISCSI
2022-08-22 21:43:39 -04:00
Thomas Harte
02f65cb7db
Commit new macOS version number.
2022-08-22 21:39:45 -04:00
Thomas Harte
246bd5a6ac
Merge branch 'master' into AppleIISCSI
2022-08-22 17:09:57 -04:00
Thomas Harte
1b197d0bb2
Resolve crash of machines that require the ROM requester.
2022-08-22 17:02:09 -04:00
Thomas Harte
4c38fa8ad3
Resolve crash of machines that require the ROM requester.
2022-08-22 17:01:41 -04:00
Thomas Harte
3d234147a6
Add in collected specs.
2022-08-22 10:22:19 -04:00
Thomas Harte
f30f13f0bc
Add overt include.
2022-08-22 10:03:24 -04:00
Thomas Harte
a6b8285d9c
Factor out the blitter sequencer.
2022-08-19 16:38:15 -04:00
Thomas Harte
ce46ec4d3e
Clean up, marginally.
2022-08-19 16:12:39 -04:00
Thomas Harte
43c6db3610
Remove various other redundancies.
2022-08-19 16:12:05 -04:00
Thomas Harte
175314cd16
Accept whatever Apple thinks is an appropriate optimisation level.
2022-08-19 15:58:14 -04:00
Thomas Harte
bb54ac14b8
Prove that new output errors are [probably] external to the Blitter.
2022-08-15 11:10:17 -04:00
Thomas Harte
856e3d97bf
Merge branch 'master' into SerialisedBlitter
2022-08-15 10:54:36 -04:00
Thomas Harte
c7373a5d3e
Overtly treat .ST images as FAT12.
2022-08-13 10:09:34 -04:00
Thomas Harte
6b001e3106
Add ST RAM size selection to the macOS UI.
2022-08-10 14:58:19 -04:00
Thomas Harte
4c90a4ec93
Remove 'Faulty peek' JSON breakages.
2022-08-08 15:22:18 -04:00
Thomas Harte
f58f7102f7
Provide more context when JSON decoding fails.
2022-08-08 15:18:03 -04:00
Thomas Harte
adf3405e6b
Be overt about performance side effect.
2022-08-08 15:17:04 -04:00
Thomas Harte
8d34d9a06a
Add missing paramter.
2022-08-08 11:01:07 -04:00
Thomas Harte
0d540fd211
Merge branch 'SerialisedBlitter' of github.com:TomHarte/CLK into SerialisedBlitter
2022-08-08 10:59:50 -04:00
Thomas Harte
025c79ca65
Factor out GZip shenanigans.
2022-08-08 10:52:55 -04:00
Thomas Harte
868d179132
Compress all Blitter logs.
2022-08-07 21:55:33 -04:00
Thomas Harte
cfccfd48e5
Allow for GZipped tests.
2022-08-07 21:53:19 -04:00
Thomas Harte
2f3dfdcc67
Add Spindizzy test.
2022-08-07 21:27:11 -04:00
Thomas Harte
7f423e39ed
Resolve type warning.
2022-08-07 19:03:56 -04:00
Thomas Harte
e6505dc985
Recognise that some of these traces don't capture all bus transactions.
2022-08-07 19:03:14 -04:00
Thomas Harte
bcdb2d135d
Remove partially-captured head.
2022-08-06 22:35:18 -04:00
Thomas Harte
c5d1cffad2
Include bus activity.
2022-08-06 22:21:02 -04:00
Thomas Harte
54b4a0771d
Provide better exposition.
2022-08-06 21:52:26 -04:00
Thomas Harte
85f75ab1f3
Introduce Addams Family test case.
2022-08-06 21:47:36 -04:00
Thomas Harte
668332f6c7
Any one failure will do.
2022-08-06 14:59:13 -04:00
Thomas Harte
021ddb3565
Ensure pipeline is fully flushed before registers are accessed.
2022-08-06 14:55:31 -04:00
Thomas Harte
6981bc8a82
Add yet more context.
2022-08-06 14:47:24 -04:00
Thomas Harte
7030646671
Avoid infinite loop.
2022-08-06 14:42:09 -04:00
Thomas Harte
3781b5eb0e
Provide further context.
2022-08-06 14:40:12 -04:00
Thomas Harte
e897cd99f9
Fix transcription of write.
2022-08-06 10:11:26 -04:00
Thomas Harte
cc9b6bbc61
Stop after a first mismatch.
2022-08-06 10:10:19 -04:00
Thomas Harte
318cea4ccd
Attempt a full bus-transaction comparison.
2022-08-06 10:06:49 -04:00
Thomas Harte
93d2a612ee
Add an explicit flush-pipeline step; some tests now pass.
2022-07-29 16:33:46 -04:00
Thomas Harte
1ac0a4e924
Provide a loop count directly from the sequencer.
...
This avoids the caller having to take a guess at iterations.
2022-07-29 12:14:59 -04:00
Thomas Harte
d85d70a133
Add documentation, formal begin function.
2022-07-26 22:01:43 -04:00
Thomas Harte
76979c8059
Add missing tests.
2022-07-26 21:47:02 -04:00
Thomas Harte
86246e4f45
Introduce partial Blitter sequencer test.
2022-07-26 21:28:12 -04:00
Thomas Harte
3e4044c7a0
Use softer-edged luminance.
2022-07-25 13:24:08 -04:00
Thomas Harte
146e739390
$ACTION seems to be the thing outside of Xcode Cloud.
2022-07-25 13:16:28 -04:00
Thomas Harte
f204162986
Use valid version numbers, only for archive builds.
2022-07-25 10:33:15 -04:00
Thomas Harte
8679854c91
Update copyright year, use valid version numbers.
2022-07-25 10:21:25 -04:00
Thomas Harte
0383d0333e
Add build date (i.e. version) into Info.plist.
2022-07-25 10:15:48 -04:00
Thomas Harte
0c6d7e07ee
Merge pull request #1072 from TomHarte/BetterAppDelegate
...
Eliminate purposeless AppDelegate instance storage.
2022-07-18 10:15:25 -04:00
Thomas Harte
b28a3ebb4d
Eliminate purposeless instance storage.
2022-07-18 09:35:38 -04:00
Thomas Harte
28a7dc194c
Increase saturation.
2022-07-17 22:01:30 -04:00
Thomas Harte
a943a0b59a
Make sharpening slightly more aggressive.
2022-07-17 19:22:09 -04:00
Thomas Harte
8f2e94a1d8
Switch name back to emphasise _async_.
2022-07-16 14:41:04 -04:00
Thomas Harte
3de1e762b7
Avoid retain cycles.
2022-07-15 15:22:12 -04:00
Thomas Harte
ee7ef81054
Avoid potential attempt to free enqueued buffers at dealloc.
2022-07-15 15:21:58 -04:00
Thomas Harte
bae47fca20
Free buffers before disposing of queue.
2022-07-15 15:13:21 -04:00
Thomas Harte
60f997a52c
Fix stereo buffering, various audio asserts.
2022-07-14 21:59:40 -04:00
Thomas Harte
bf03bda314
Generalise AsyncTaskQueue, DeferringAsyncTaskQueue and AsyncUpdater into a single template.
2022-07-14 16:39:26 -04:00
Thomas Harte
9133e25a7b
Allocate buffers once, ahead of time, and reuse.
2022-07-14 14:44:10 -04:00
Thomas Harte
ddfc2e4ca4
Provide sample length ahead of time.
2022-07-14 14:34:11 -04:00
Thomas Harte
4c031bd335
Don't use kAudioQueueProperty_IsRunning
as it seems not to be trustworthy.
2022-07-13 22:22:19 -04:00
Thomas Harte
6a509c1280
Improve comments, marginally reduce dynamic_cast
ing.
2022-07-13 18:36:40 -04:00
Thomas Harte
dcb68c16fe
Eliminate AudioQueueBufferMaxLength
.
2022-07-13 15:24:43 -04:00
Thomas Harte
10108303e7
Eliminate AudioQueueStop
, which is very slow, use AudioQueueStart
only as required.
2022-07-13 15:04:58 -04:00
Thomas Harte
b7ad94c676
Attempt to get a bit more rigorous in diagnosing queue stoppages.
2022-07-12 21:43:33 -04:00
Thomas Harte
1c537a877e
Remove unnecessary lock.
2022-07-12 16:22:19 -04:00
Thomas Harte
4b9d92929a
Tweak logic.
2022-07-12 16:02:30 -04:00
Thomas Harte
5b69324ee9
Tidy up comments.
2022-07-12 15:58:16 -04:00
Thomas Harte
df15d60b9e
Switch to AudioQueueNewOutputWithDispatchQueue
, reducing runloop contention.
2022-07-12 15:03:35 -04:00
Thomas Harte
59da143e6a
Add overt flushes to the SDL target.
2022-07-12 10:57:22 -04:00
Thomas Harte
4ddbf095f3
Fully banish flush
from the processors.
2022-07-12 10:49:53 -04:00
Thomas Harte
4e9ae65459
Reintroduce sync matching.
2022-07-12 09:56:13 -04:00
Thomas Harte
d16dc3a5d7
Move limit up to 20fps.
2022-07-12 07:45:07 -04:00
Thomas Harte
a1544f3033
Do a better job of keeping the queue populated.
2022-07-11 20:50:02 -04:00
Thomas Harte
f2fb9cf596
Avoid unnecessary queue jump.
2022-07-10 21:35:05 -04:00
Thomas Harte
6dabdaca45
Switch to int
; attempt to do a better job of initial audio filling.
2022-07-09 13:33:46 -04:00
Thomas Harte
51ed3f2ed0
Reduce modal-related thread hopping.
2022-07-09 13:03:45 -04:00
Thomas Harte
b03d91d5dd
Permit granular specification of what to flush.
2022-07-08 15:38:29 -04:00
Thomas Harte
07ce0f0133
Attempt safe shutdown.
2022-07-07 16:56:10 -04:00
Thomas Harte
96189bde4b
Loop the Master System into the experiment.
2022-07-07 16:46:08 -04:00
Thomas Harte
3e2a6ef3f4
Hacks up an [unsafe] return to something best-effort-updater-esque.
...
For profiling, mainly.
2022-07-07 16:35:45 -04:00
Thomas Harte
7886c2df7a
Start experimenting with a more event-based approach to timing.
2022-07-07 10:48:42 -04:00
Thomas Harte
f7e75da4bd
Disable [temporarily?] outdated shadowing tests.
2022-06-29 15:14:51 -04:00
Thomas Harte
825136b168
Fix installation of LCW test value; thereby permit all tests.
2022-06-29 15:04:21 -04:00
Thomas Harte
5a9eb58d33
Fix test generator: IO state can be cleared.
2022-06-29 14:57:14 -04:00
Thomas Harte
beb4993548
Remove card pages from the equation.
2022-06-29 14:51:50 -04:00
Thomas Harte
48e8bfbb0e
Introduce failing is-IO test.
2022-06-29 14:44:17 -04:00
Thomas Harte
5dfbc58959
Fix test generator's concept of hires2 shadowing.
2022-06-29 14:41:56 -04:00
Thomas Harte
924de35cf3
Go all in on support for physical shadowing.
2022-06-29 14:39:56 -04:00
Thomas Harte
60d3519993
Clarify, attempt to implement as internally documented.
2022-06-28 22:32:31 -04:00
Thomas Harte
c6b4570424
Fix Markdown code marking.
2022-06-28 17:12:38 -04:00
Thomas Harte
f5d56cc473
Add first pass at testing shadowing.
2022-06-28 17:12:25 -04:00
Thomas Harte
4e52572b03
Omit language card write tests.
2022-06-28 16:57:09 -04:00
Thomas Harte
6abc317986
Avoid permitting writes in the Cx00 region after uninhibiting the language card.
2022-06-28 16:35:47 -04:00
Thomas Harte
22c0b588c4
Tidy up slightly, without fixing failure.
2022-06-28 16:32:35 -04:00
Thomas Harte
6c9fc0ac75
Introduce [failing] write area tests.
2022-06-28 16:28:00 -04:00
Thomas Harte
ef322dc705
Reformulate to allow addition of write tests, momentarily.
2022-06-28 16:22:41 -04:00
Thomas Harte
d0df156b05
Merge branch 'IIgsMemoryMap' of github.com:TomHarte/CLK into IIgsMemoryMap
2022-06-28 11:26:13 -04:00
Thomas Harte
7aeaa4a485
Tweak paging semantics, to allow simple multiple dependencies.
2022-06-27 21:38:45 -04:00
Thomas Harte
823c7765f8
Avoid manual index counting.
2022-06-27 11:16:05 -04:00
Thomas Harte
5cb0aebdf4
For the sake of poor Xcode, stop after a single failure.
2022-06-27 11:10:51 -04:00
Thomas Harte
686dccb48d
Correct comparison.
2022-06-26 21:49:58 -04:00
Thomas Harte
1f7700edac
Ensure proper register hits.
2022-06-26 21:20:57 -04:00
Thomas Harte
5adc656066
Make some attempt to use the JSON tests.
2022-06-25 21:41:37 -04:00
Thomas Harte
9cf64ea643
Import generated tests.
2022-06-25 16:46:57 -04:00
Thomas Harte
f2c2027a8c
Disable test generation for commit.
2022-06-24 16:50:23 -04:00
Thomas Harte
ef5ac1442f
Don't invent an address for STP and WAI.
2022-06-24 13:05:32 -04:00
Thomas Harte
1c1ce625a7
Vector reads signal VDA.
2022-06-24 10:37:39 -04:00
Thomas Harte
a442077eac
Allow repetition for MVN and MVP only.
2022-06-24 10:34:43 -04:00
Thomas Harte
6c638712f3
Attempt to capture MVP and MVN in their entirety.
2022-06-24 07:39:58 -04:00
Thomas Harte
2e7afb13c7
Exit gracefully upon a STP or WAI.
2022-06-23 21:03:40 -04:00
Thomas Harte
65140b341d
Simplify slightly, per new S reporting rule.
2022-06-22 16:43:00 -04:00
Thomas Harte
2f684ee66d
Use null for values that were never loaded.
2022-06-21 21:47:18 -04:00
Thomas Harte
ab0c290489
Use 'x' instead of 'i'.
2022-06-19 06:58:23 -04:00
Thomas Harte
15ac2c3e5a
Output to files, at volume, with extended bus flags.
2022-06-18 22:00:50 -04:00
Thomas Harte
0c24a27ba6
Completely prints tests.
2022-06-18 21:32:50 -04:00
Thomas Harte
eb82e06fab
Add randomised initial state, fix PC.
2022-06-18 19:21:56 -04:00
Thomas Harte
f8e6954739
Ensure complete runs of each tested opcode.
2022-06-18 16:26:40 -04:00
Thomas Harte
b62f484d93
Start scaffolding a 65816 test generator.
2022-06-18 13:28:15 -04:00
Thomas Harte
6cc41d6dda
Restore 1000 test count.
2022-06-14 22:02:53 -04:00
Thomas Harte
d91f8a264e
Flip presumption, reenabling most tests.
2022-06-14 21:57:14 -04:00
Thomas Harte
e066546c13
Resolve PEA timing errors.
2022-06-13 14:08:42 -04:00
Thomas Harte
7dc66128c2
Fix strobe output.
2022-06-13 10:49:47 -04:00
Thomas Harte
e484e4c9d7
Expand test to make sure that correct data strobes are active.
2022-06-13 10:39:06 -04:00
Thomas Harte
f316cbcf94
The old implementation was correct.
2022-06-11 21:15:08 -04:00
Thomas Harte
0a6b2b7d32
Verify newer CMPA.l, RTE, TRAP[V] and CHK.
2022-06-11 11:17:18 -04:00
Thomas Harte
c3345dd839
Fix MOVEM timing.
2022-06-10 21:52:07 -04:00
Thomas Harte
917b7fbf80
Notarise won't fix status of CLR, NEGX, NEG, NOT.
2022-06-10 16:50:38 -04:00
Thomas Harte
97715e7ccc
Expand test set to include those with timing discrepancies.
2022-06-10 16:34:05 -04:00
Thomas Harte
43c0dea1bd
With the difference in RESET times now factored out, test timing too.
2022-06-10 16:12:54 -04:00
Thomas Harte
2e4652209b
Remove entire RESET sequence, move to testing PEA.
2022-06-10 15:57:54 -04:00
Thomas Harte
e2d811a7a0
Notarise digressions that appear to be correct, remove now-working RTE/RTR.
2022-06-09 21:48:15 -04:00
Thomas Harte
dd5c903fd6
DIVS also appears sometimes to differ.
2022-06-09 20:19:39 -04:00
Thomas Harte
2e1675066d
Reinstate address error non-testing.
2022-06-09 16:59:06 -04:00
Thomas Harte
be84ce657b
Add an optional testing whitelist.
2022-06-09 16:18:04 -04:00
Thomas Harte
64053d697f
Take improved guess at address error stacking order.
2022-06-09 16:17:09 -04:00
Thomas Harte
a59ad06438
Print out summary of failure.
2022-06-09 13:13:33 -04:00
Thomas Harte
5af03d74ec
Add note to self about first diagnosis.
2022-06-09 12:21:39 -04:00
Thomas Harte
ba2803c807
Include all bus activity after the split.
2022-06-09 11:30:22 -04:00
Thomas Harte
fdcbf617d8
Avoid STOP.
2022-06-09 08:42:31 -04:00
Thomas Harte
cc7a4f7f91
Fix test build.
2022-06-08 21:15:11 -04:00
Thomas Harte
2e42bda0a3
Permit instructions that end in an address error to differ in transactions.
2022-06-08 16:15:33 -04:00
Thomas Harte
168dc12e27
Avoid spurious mismatches.
2022-06-08 16:03:02 -04:00
Thomas Harte
fd1955e15b
Attempt to randomise and test register contents.
2022-06-08 15:12:47 -04:00
Thomas Harte
f4f93f4836
Test a single, whole instruction; record read/write.
2022-06-08 14:53:04 -04:00
Thomas Harte
dd0a7533ab
Randomise all parts of memory other than the opcode.
2022-06-08 14:43:51 -04:00
Thomas Harte
50130b7004
Minor layout tweak.
2022-06-08 11:42:42 -04:00
Thomas Harte
ab52c5cef2
Pass first all-zeroes test, establishing that processors aren't being fully reset.
2022-06-08 10:56:54 -04:00
Thomas Harte
c7fa93a5bc
Attempt human-legible explanation of differences encountered.
2022-06-08 10:51:05 -04:00
Thomas Harte
400b73b5a2
Allow capture to be limited; retain timestamps.
2022-06-08 09:49:27 -04:00
Thomas Harte
788b026cf5
Log and attempt to compare some activity. Sort of.
2022-06-07 16:56:05 -04:00
Thomas Harte
c4ae5d4c8d
Establishes at least that both 68000s can run.
2022-06-06 21:47:10 -04:00
Thomas Harte
ca8dd61045
Start sketching out an old vs new 68000 test.
2022-06-06 21:19:57 -04:00
Thomas Harte
7b3cf6e747
Add missing instruction: RESET.
2022-06-03 11:15:39 -04:00
Thomas Harte
640b04e59e
Test only well-defined flags.
...
Albeit that timing is still off.
2022-06-03 10:18:46 -04:00
Thomas Harte
10b9b13673
Disable divide-by-zero PC test in lieu of better documentation.
2022-06-03 08:27:20 -04:00
Thomas Harte
aaac777651
Merge branch 'master' into 68000Mk2
2022-06-02 17:08:41 -04:00
Thomas Harte
e7b3705060
Merge pull request #1007 from TomHarte/IPFFileFormat
...
Adds partial support for the IPF file format.
2022-06-02 12:58:47 -04:00
Thomas Harte
90d720ca28
Don't test undocumented flags.
2022-06-02 12:30:39 -04:00
Thomas Harte
6dd89eb0d7
Adjust my expectation as to length.
2022-06-02 12:11:54 -04:00
Thomas Harte
e1abf431cb
Don't test undefined flags.
2022-05-30 16:23:51 -04:00
Thomas Harte
8e0fa3bb5f
DIV # with a divide by zero should be 44 cycles.
2022-05-29 21:22:45 -04:00
Thomas Harte
9eea471e72
Resolve infinite recursion.
2022-05-29 20:39:22 -04:00
Thomas Harte
2a40e419fc
Fix CHK tests: timing and expected flags.
2022-05-29 15:26:56 -04:00
Thomas Harte
5f030edea4
Simplify transaction.
2022-05-26 19:37:30 -04:00
Thomas Harte
88e33353a1
Fix instruction and time counting, and initial state.
2022-05-26 09:17:37 -04:00
Thomas Harte
f3c0c62c79
Switch register-setting interface.
2022-05-26 07:52:14 -04:00
Thomas Harte
866787c5d3
Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence.
2022-05-25 20:22:38 -04:00
Thomas Harte
64491525b4
Work further to guess at caller's intention for set_state.
...
Probably I should just eliminate the initial reset, somehow.
2022-05-25 17:01:18 -04:00
Thomas Harte
68b184885f
Reapply only the status.
2022-05-25 16:54:25 -04:00
Thomas Harte
06f3c716f5
Make better effort to establish initial state.
2022-05-25 16:47:41 -04:00
Thomas Harte
22714b8c7f
Capture state at instruction end, for potential inspection.
2022-05-25 16:32:26 -04:00
Thomas Harte
f9d1c554b7
Fix for the actual number of cycles in a standard reset.
2022-05-25 16:05:28 -04:00
Thomas Harte
f2a7660390
Merge branch 'master' into 68000Mk2
2022-05-25 15:40:10 -04:00
Thomas Harte
4961e39fb6
Mention DIVU/DIVS flags.
2022-05-25 15:39:00 -04:00
Thomas Harte
0bedf608c0
Add details on gaps in coverage.
2022-05-25 15:36:27 -04:00
Thomas Harte
1ab831f571
Add the option to log a list of all untested instructions.
2022-05-25 13:17:01 -04:00
Thomas Harte
2c6b9b4c9d
Switch comparative trace tests to 68000 Mk2.
2022-05-25 11:32:00 -04:00
Thomas Harte
463fbb07f9
Adapt remaining 68000 tests to use Mk2.
2022-05-25 10:55:17 -04:00
Thomas Harte
4b07c41df9
Ensure alignment of storage.
2022-05-24 11:29:28 -04:00
Thomas Harte
a87f6a28c9
Fix LINK A7.
2022-05-23 10:43:17 -04:00
Thomas Harte
98325325b1
Fix UNLINK A7.
2022-05-23 10:27:44 -04:00
Thomas Harte
26bf66e3f8
Fix shifts and rolls.
2022-05-23 10:09:46 -04:00
Thomas Harte
c6b3281274
Attempt the shifts and rolls.
2022-05-23 09:29:19 -04:00
Thomas Harte
1e8adc2bd9
Fix MOVEP to R.
2022-05-23 09:00:37 -04:00
Thomas Harte
c73021cf3c
Implement MOVE.
2022-05-23 08:46:06 -04:00
Federico Berti
1a26d4e409
Update nbcd_pea.json
...
Add missing bracket
2022-05-23 12:14:00 +01:00
Thomas Harte
269263eecf
Implement RTE, RTS, RTR.
2022-05-22 21:16:38 -04:00
Thomas Harte
4e21cdfc63
Enable NEGX/CLR tests.
2022-05-22 20:55:21 -04:00
Thomas Harte
faef5633f8
Ensure MOVE from SR has an effective address to write to.
2022-05-22 20:52:00 -04:00
Thomas Harte
7d1f1a3175
Implement MOVE [to/from] [CCR/SR].
2022-05-22 19:45:22 -04:00
Thomas Harte
4e34727195
Fully implement TAS.
2022-05-22 16:14:03 -04:00
Thomas Harte
1dd6ed6ae3
Implement TAS Dn, with detour for other TASes.
2022-05-22 16:08:30 -04:00
Thomas Harte
cb4d6710df
Switch to a more direct indication of progress.
2022-05-22 11:27:58 -04:00
Thomas Harte
284f23c6ea
Implement JMP.
2022-05-22 07:16:38 -04:00
Thomas Harte
4b35899a12
Bcc: properly establish offset.
2022-05-21 20:59:34 -04:00
Thomas Harte
94288d5a94
Excludes DBcc from standard operand fetch.
2022-05-21 19:53:28 -04:00
Thomas Harte
c869eb1eec
Correct omission: wasn't testing the final PC.
...
Plenty of new errors incoming.
2022-05-21 15:56:27 -04:00
Thomas Harte
176c8355cb
The tests in chk.json now pass.
2022-05-21 14:32:58 -04:00
Thomas Harte
e46a3c4046
Implement JSR.
2022-05-21 10:29:36 -04:00
Thomas Harte
256da43fe5
Fix MOVEM other than postinc and predec.
2022-05-20 20:47:54 -04:00
Thomas Harte
a818650027
Add a faulty attempt at MOVEM.
2022-05-20 18:48:19 -04:00
Thomas Harte
c7c12f9638
After a quick check, eori_andi_ori also now passes.
2022-05-20 14:47:11 -04:00
Thomas Harte
ee942c5c17
Fix PC-relative fetches.
2022-05-20 14:42:51 -04:00
Thomas Harte
d157819c49
Implement the various to-[SR/CCR] actions, which do a 'repeat' prefetch.
...
(which isn't exactly a repeat, at least in the SR cases, because the function code might have changed)
2022-05-20 14:29:14 -04:00
Thomas Harte
2d91fb5441
Implement MOVEP.
2022-05-20 14:22:32 -04:00
Thomas Harte
81431a5453
Attempt BTST, BCHG, BCLR and BSET.
2022-05-20 12:58:45 -04:00
Thomas Harte
6d7ec07216
Uncover another three already-working test files.
2022-05-20 12:44:57 -04:00
Thomas Harte
b4978d1452
Implement BSR, adding one more test file to the working set.
2022-05-20 12:40:35 -04:00
Thomas Harte
45e9648b8c
Implement Bcc.
2022-05-20 12:04:43 -04:00
Thomas Harte
ce32957d9d
Shuffle two more into the working column.
2022-05-20 11:53:12 -04:00
Thomas Harte
452dd3ccfd
Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.
2022-05-20 11:20:23 -04:00
Thomas Harte
e5c1621382
Add missing fallthrough
, patterns for all ADDs and SUBs.
2022-05-20 07:02:02 -04:00
Thomas Harte
af3518dc1f
Implement various ADD, SUB patterns.
2022-05-19 20:50:37 -04:00
Thomas Harte
6cfc0e80d9
Don't test the unrecognised instruction exception.
2022-05-19 19:45:38 -04:00
Thomas Harte
334e3ec529
Add privilege and instruction error exceptions; permit two operands to be stored.
2022-05-19 16:55:16 -04:00
Thomas Harte
84c165459f
ext.json now passes.
2022-05-19 16:32:40 -04:00
Thomas Harte
22b63fe1f8
Add EXT, and notes to self.
2022-05-19 15:41:02 -04:00
Thomas Harte
c6c6213460
Bifurcate the fetch-operand flow.
...
Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.
2022-05-19 10:27:51 -04:00
Thomas Harte
29f6b02c04
Factor out register setup/testing, generalising the DIVU/DIVS flag check.
2022-05-18 21:13:34 -04:00
Thomas Harte
1bf7c0ae5f
Attempt better to avoid entering a second instruction.
2022-05-18 21:00:34 -04:00
Thomas Harte
44ae084794
Avoid the repeated .fill; reduces debug-build executor test time to 1.5s.
...
i.e. eliminates about 95% of costs.
2022-05-18 17:10:23 -04:00
Thomas Harte
13a1809101
Avoid memset.
2022-05-18 17:00:35 -04:00
Thomas Harte
c35200fbd0
Shuffle mildly, primarily to avoid repeated 16mb allocations.
2022-05-18 16:59:37 -04:00
Thomas Harte
4a40581deb
Completes performance of NBCD D0.
2022-05-17 16:10:20 -04:00
Thomas Harte
3db2de7478
Works 68000 mk2 into the comparative tests.
...
... revealing that I've leant a little too hard on __LINE__.
2022-05-16 20:04:13 -04:00
Thomas Harte
b0518040b5
Plants the seek of a 68000 mark 2.
2022-05-16 11:44:16 -04:00
Thomas Harte
20a191f144
Switch to same tests, run through a more modern emulator.
2022-05-15 16:33:08 -04:00
Thomas Harte
f60f1932f2
Restrict DIVU and DIVS tests to those which are well-defined.
2022-05-14 20:28:54 -04:00
Thomas Harte
7f704fdae1
Improve README.
2022-05-13 16:28:56 -04:00
Thomas Harte
dd63a6b61e
Correct all [A/S/N]BCD tests.
2022-05-13 16:18:58 -04:00
Thomas Harte
1935d968c5
Add ability to suggest solutions.
2022-05-13 15:27:11 -04:00
Thomas Harte
84cfbaa0a4
Remove manual test count, now that all are being performed.
2022-05-13 11:00:26 -04:00
Thomas Harte
0d81992f6a
Move object creation.
2022-05-13 10:50:16 -04:00
Thomas Harte
6594b38567
Tidy up, and reduce for now to a summary report.
2022-05-13 08:02:20 -04:00
Thomas Harte
2e796f31d4
Support interrupts; documentation to come.
2022-05-12 20:52:24 -04:00
Thomas Harte
3d8f5d4302
Improve failure logging.
...
This confirms that it's only the *BCDs and DIVU/DIVS in which I do not match the tests.
2022-05-12 20:23:32 -04:00
Thomas Harte
2fa6b2301b
Move string logic into Preinstruction
.
2022-05-12 19:46:08 -04:00
Thomas Harte
4ba20132b9
Avoid repeated allocations on the new path, reducing total runtime by almost two thirds.
2022-05-12 16:35:41 -04:00
Thomas Harte
192513656a
After much guesswork, fix SBCD and thereby pass flamewing tests.
2022-05-12 11:39:01 -04:00
Thomas Harte
f3c1b1f052
Name flags, remove closing underscores on exposed data fields.
2022-05-12 08:19:41 -04:00
Thomas Harte
56ce1ec6e8
No need to subclass.
2022-05-11 21:25:38 -04:00
Thomas Harte
de168956e4
Fix tested operand order.
2022-05-11 16:44:39 -04:00
Thomas Harte
5b80844d81
Add a sanity test count, temporarily.
2022-05-11 16:34:28 -04:00
Thomas Harte
17add4b585
Introduce and overwhelmingly fail the flamewing BCD tests.
2022-05-11 15:19:39 -04:00
Thomas Harte
943c924382
Add missing: MOVE to/from USP, RESET.
2022-05-11 07:52:23 -04:00
Thomas Harte
ab8e1fdcbf
Take a swing at access faults and address errors.
2022-05-10 16:20:30 -04:00
Thomas Harte
f2a6a12f79
Remove further vestiges of timing.
2022-05-09 20:58:51 -04:00
Thomas Harte
0af8660181
Remove add_pc
and decline_branch
in favour of operation-specific signals.
2022-05-09 16:19:25 -04:00
Thomas Harte
330ec1b848
TODO is done.
2022-05-09 11:52:33 -04:00
Thomas Harte
8e5650fde9
Clean up Instruction.hpp.
2022-05-09 10:13:42 -04:00
Thomas Harte
539932dc56
Provide function codes. TODO: optionally.
2022-05-09 09:18:02 -04:00
Thomas Harte
5ab5e1270e
Fix test for new MOVEM semantics.
2022-05-09 09:17:48 -04:00
Thomas Harte
98cb9cc1eb
Fix CHK operand size.
2022-05-07 21:16:44 -04:00
Thomas Harte
bf8c97abbb
Permit TRAP, TRAPV and CHK to push the next PC rather than the current.
2022-05-07 20:32:39 -04:00
Thomas Harte
2b3900fd14
Fix LINK A7.
2022-05-07 08:15:26 -04:00
Thomas Harte
1defeca1ad
Implement RTS, RTR, RTE.
2022-05-06 12:30:49 -04:00
Thomas Harte
ac6a9ab631
Fix TAS Dn.
2022-05-06 12:23:04 -04:00
Thomas Harte
8176bb6f79
Expose issues with TST and TAS.
2022-05-06 12:18:56 -04:00
Thomas Harte
9c266d4316
Proceed to unimplemented TST.
2022-05-06 11:33:57 -04:00
Thomas Harte
d478a1b448
Proceed to next failure: PEA.
2022-05-06 10:04:20 -04:00
Thomas Harte
607ddd2f78
Preserve MOVEM order in Operation
.
2022-05-06 09:45:06 -04:00
Thomas Harte
06fe320cc0
Correct source counting, but this leaves the operands still being the wrong way around.
2022-05-05 21:06:53 -04:00
Thomas Harte
d7d0a5c15e
Implement MOVEM to memory.
2022-05-05 18:51:29 -04:00
Thomas Harte
47f4bbeec6
Switch to a contiguous block of 16 registers.
2022-05-05 15:31:59 -04:00
Thomas Harte
70cdc2ca9f
Fix MOVEP to register.
...
Advance to lack of MOVEM.
2022-05-05 12:37:47 -04:00
Thomas Harte
f63a872387
BTST does not write back.
2022-05-05 12:32:15 -04:00
Thomas Harte
46686b4b9c
Start testing move.
2022-05-04 20:38:56 -04:00
Thomas Harte
15c90e546f
Fix rotates and shifts to memory.
2022-05-04 19:44:59 -04:00
Thomas Harte
5aabe01b6d
Mostly fix LINK and UNLK.
2022-05-04 08:41:55 -04:00
Thomas Harte
d3b55a74a5
Fix LEA, proceed to non-functional LINK and UNLK.
2022-05-03 20:45:36 -04:00
Thomas Harte
de58ec71fd
Fix EXT, SWAP.
2022-05-03 20:17:36 -04:00
Thomas Harte
052ba80fd7
Add enough wiring to complete but fail EXT and JMP/JSR.
2022-05-03 15:49:55 -04:00
Thomas Harte
39f0ec7536
Get far enough through CHK to realise that MOVEM probably needs to be divided by direction.
2022-05-03 15:40:04 -04:00
Thomas Harte
af973138df
Correct decoding of Bcc.b, satisfying Bcc and BSR tests.
2022-05-03 15:32:54 -04:00
Thomas Harte
5a87506f3d
Fix Bcc, making decision that add_pc
is relative to start of instruction.
2022-05-03 15:21:42 -04:00
Thomas Harte
90f0005cf2
Proceed to failing Bcc and flagging up my lack of an implementation for BSR.
2022-05-03 14:45:49 -04:00
Thomas Harte
d8b3748d24
Fix Scc size, DBcc behaviour.
2022-05-03 14:40:51 -04:00
Thomas Harte
b6ffff5bbd
Distinguish [ADD/SUB]QA from [ADD/SUB]Q.
2022-05-03 14:17:26 -04:00
Thomas Harte
5ebae85a16
Start recording successes.
2022-05-03 11:28:50 -04:00
Thomas Harte
b3cf13775b
Consume operand_flags into Instruction.hpp.
2022-05-03 11:09:57 -04:00
Thomas Harte
2f2d6bc08b
Correct CMPw.
2022-05-03 09:05:34 -04:00
Thomas Harte
fc9a35dd04
Test add/sub, add an exception for invalid Sequence
s.
2022-05-02 20:09:38 -04:00
Thomas Harte
3827ecd6d3
Proceed to complete test running.
2022-05-02 12:57:45 -04:00
Thomas Harte
14532867a4
Sneaks towards testing EXT.
2022-05-02 08:00:56 -04:00
Thomas Harte
56fe00c5fb
Correct errors preparatory to Executor's lack of flow controller actions.
2022-05-01 20:40:57 -04:00
Thomas Harte
6b073c6067
Attempt to round out addressing modes, shift to a header, as per templating on BusHandler.
2022-05-01 15:10:54 -04:00
Thomas Harte
9359f6477b
Start drafting an Executor.
2022-04-29 17:12:06 -04:00
Thomas Harte
85242ba896
Add to Xcode project, template on Model as per CLR being odd. Fill in some obvious answers.
2022-04-29 11:10:14 -04:00
Thomas Harte
d16dab6f62
Starts introducing a sequencer, to resolve responsibility of perform
.
2022-04-29 10:40:19 -04:00
Thomas Harte
1d8d2b373b
Port all simple instruction bodies.
2022-04-28 16:55:47 -04:00
Thomas Harte
bb73eb0db3
Start working on an isolation of 68000 instruction execution.
2022-04-28 15:35:40 -04:00
Thomas Harte
8a18685902
Relocated RegisterSizes to Numeric.
2022-04-28 15:10:08 -04:00
Thomas Harte
9cbbb6e508
Adjust path to match namespace; add to Qt project.
2022-04-27 08:05:36 -04:00
Thomas Harte
9908769bb3
Normalise test name.
2022-04-26 20:32:39 -04:00
Thomas Harte
8ff0b71b29
Subsume MOVEQ into MOVE.l; add missing invalid_operands.
2022-04-25 19:58:19 -04:00
Thomas Harte
959db77b88
Eliminate concept of skips.
2022-04-22 20:59:25 -04:00
Thomas Harte
d4b766bf3f
Introduce directional ADD/SUB/AND/OR.
...
Just 512 failures to go.
2022-04-22 20:37:09 -04:00
Thomas Harte
4c806d7c51
Tidy up slightly, ahead of a final push to getting complete test success.
...
After which I can start undoing style errors.
2022-04-22 14:51:25 -04:00
Thomas Harte
c16a60c5ea
Import correct STOP, LINK, EXT.
2022-04-22 14:36:29 -04:00
Thomas Harte
96afcb7a43
Introduce remainder of tests.
2022-04-22 14:33:43 -04:00
Thomas Harte
e5a8d8b9ad
Import corrected TRAPs and RTE/RTR.
2022-04-22 14:26:44 -04:00
Thomas Harte
efeee5160e
Add tests for RTE, RTR, TRAP, TRAPV, CHK.
2022-04-22 10:06:39 -04:00
Thomas Harte
06fb502047
Add MUL/DIV tests and exclusions.
2022-04-22 09:47:16 -04:00