Jim Grosbach
b657a90929
ARM assembly parsing for 'msr' plain 'cpsr' operand.
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Plain 'cpsr' is an alias for 'cpsr_fc'.
rdar://11153753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 03:17:53 +00:00
Craig Topper
769bbfd951
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 05:20:24 +00:00
Akira Hatanaka
9dd16d41a2
Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 03:01:13 +00:00
Akira Hatanaka
02365945a6
Revert r153924. There were buildbot failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 02:51:09 +00:00
Akira Hatanaka
885020a7a7
MIPS disassembler support.
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Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 02:20:58 +00:00
Akira Hatanaka
a551a48402
Initial 64 bit direct object support.
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This patch allows llvm to recognize that a 64 bit object file is being produced
and that the subsequently generated ELF header has the correct information.
The test case checks for both big and little endian flavors.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153889 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 19:25:22 +00:00
Silviu Baranga
50ac2e9229
Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153874 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 15:20:39 +00:00
Jim Grosbach
ad353c6303
ARM assembler should prefer non-aliases encoding of cmp.
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When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 19:59:02 +00:00
Jim Grosbach
a45e3747e6
ARM encoding for VSWP got the second operand incorrect.
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Make the non-tied register operand names line up with what the base
class encoding handler expects.
rdar://11157236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 18:53:01 +00:00
Jim Grosbach
2d30d947ec
ARM integrated assembler should encoding choice for add/sub imm.
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For 'adds r2, r2, #56 ' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.
rdar://11156277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 17:20:40 +00:00
Jim Grosbach
c0164f8608
ARM assembly parsing needs to be paranoid about negative immediates.
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Make sure to treat immediates as unsigned when doing relative comparisons.
rdar://11153621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 16:31:31 +00:00
James Molloy
cb0809b82b
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
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Patch by Tim Northover!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 09:15:32 +00:00
Jim Grosbach
b22e70d835
ARM assembly 'cmp lr, #0 ' should not encode using 'cmn'.
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The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.
rdar://11129224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 21:19:52 +00:00
Richard Barton
6e9d66c756
Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28 10:18:11 +00:00
Eli Bendersky
cc85160672
Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
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* Removed test/lib/llvm.exp - it is no longer needed
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
left in the test suite so this code is no longer required. test/lit.cfg is
now much shorter and clearer
* Removed a lot of duplicate code in lit.local.cfg files that need access to
the root configuration, by adding a "root" attribute to the TestingConfig
object. This attribute is dynamically computed to provide the same
information as was previously provided by the custom getRoot functions.
* Documented the config.root attribute in docs/CommandGuide/lit.pod
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-25 09:02:19 +00:00
Silviu Baranga
6fe310e155
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 14:14:49 +00:00
Silviu Baranga
b7c2ed6664
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 13:24:43 +00:00
Silviu Baranga
a0c48eb8f6
Added soft fail cases for the disassembler when decoding MUL instructions on ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 13:14:39 +00:00
Kevin Enderby
f0586f08df
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
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case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 20:54:32 +00:00
Joerg Sonnenberger
4fd3d29275
Fix generation of the address size override prefix. Add assertions for
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the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 05:48:07 +00:00
Akira Hatanaka
fb54afbcb8
Incremental big endian patch by Jack Carter.
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These changes allow us to compile big endian from the command line for 32 bit
Mips targets. This patch will result in code and data actually being produced
in the correct endianess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 00:52:01 +00:00
Jim Grosbach
48c9533181
Assembler should accept redefinitions of unused variable symbols.
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rdar://11027851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 21:33:21 +00:00
Kevin Enderby
9f2e160f7a
Fix assembling ARM vst2 instructions with double-spaced registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 17:41:51 +00:00
Jim Grosbach
07cdd80ccc
ARM non-scattered MachO relocations for movw/movt.
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Needed when building -mdynamic-no-pic code.
rdar://10459256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 17:25:45 +00:00
Silviu Baranga
5c062ad926
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 15:54:56 +00:00
Jim Grosbach
ae151ed87d
MC asm parser macro argument count was wrong when empty.
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evaluated to '1' when the argument list was empty (should be '0').
rdar://11057257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152967 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 00:11:42 +00:00
Jim Grosbach
be7cf2b377
ARM ldm/stm register lists can be out of order.
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It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.
rdar://11064740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 20:48:38 +00:00
Jim Grosbach
213d2e7dc3
ARM optional operand on MRC/MCR assembly instructions.
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rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 00:45:58 +00:00
Jim Grosbach
9426ac7b57
ARM vmrs system registers mvfr0 and mvfr1 handling.
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rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 00:27:18 +00:00
Jim Grosbach
b84ad4aa7d
ARM case-insensitive checking for APSR_nzcv.
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rdar://11056591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 21:34:14 +00:00
Kristof Beyls
8a6bcc3722
Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 17:50:29 +00:00
Kevin Enderby
0f5ab7c5f3
Change the X86 assembler to not require a segment register on string
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instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13 19:47:55 +00:00
Kevin Enderby
8b15278964
Change the second line of the test added for r152414 to use CHECK-NEXT.
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Suggestion by Bill Wendling!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152582 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-12 21:38:09 +00:00
Kevin Enderby
84faf65912
Added a missing error check for X86 assembly with mismatched base and index
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registers not both being 64-bit or both being 32-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-12 21:32:09 +00:00
Bill Wendling
e060eb8916
Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.
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Patch by Kay Tiong Khoo!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 07:37:27 +00:00
Kevin Enderby
58dfaa1465
Add the missing call to Error when a bad X86 scale expression is parsed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152443 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 22:24:10 +00:00
Kevin Enderby
faf72ffda3
Fix the x86 disassembler to at least print the lock prefix if it is the first
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prefix. Added a FIXME to remind us this still does not work when it is not the
first prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 17:52:49 +00:00
NAKAMURA Takumi
63054f99af
test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152406 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 14:52:38 +00:00
Rafael Espindola
6507d84d6c
Use llvm-mc instead of llc. Patch by Jack Carter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152242 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 20:58:59 +00:00
Eli Friedman
54427e5219
Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 19:58:46 +00:00
Kevin Enderby
158c8a49c2
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 18:33:12 +00:00
Jim Grosbach
bc978a60d9
ARM vpush/vpop assembler mnemonics accept an optional size suffix.
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rdar://10988114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 23:16:31 +00:00
Eli Friedman
ec93b6deca
Make aliases for shld and shrd match gas. PR12173.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 04:31:54 +00:00
Kevin Enderby
b0578512c7
Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
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runs into the undefined 15 condition code value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 22:13:02 +00:00
Richard Trieu
562a67db32
Fix flags for test in MC/MachO/ARM/empty-function-nop.ll
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 00:29:09 +00:00
Jim Grosbach
c01810eeb7
ARM implement TargetInstrInfo::getNoopForMachoTarget()
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Without this hook, functions w/ a completely empty body (including no
epilogue) will cause an MCEmitter assertion failure.
For example,
define internal fastcc void @empty_function() {
unreachable
}
rdar://10947471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 23:53:30 +00:00
David Meyer
c46255a32e
In the ObjectFile interface, replace isInternal(), isAbsolute(), isGlobal(), and isWeak(), with a bitset of flags.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 23:47:53 +00:00
Rafael Espindola
489d679271
On ELF, create relocations to the abbreviation and line sections when producing
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debug info for assembly files. We were already doing the right thing when
producing debug info for C/C++.
ELF linkers don't know dwarf, so they depend on these relocations to produce
valid dwarf output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 21:13:05 +00:00
Jim Grosbach
7b25ecf6ad
ARM BL/BLX instruction fixups should use relocations.
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We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.
To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.
rdar://10927209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 21:36:23 +00:00
Craig Topper
930a1ebd92
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 01:54:29 +00:00
Michael J. Spencer
32d22ee11d
Emit global ctors into .CRT$XCU instead of .ctors on Win32. Patch by Joe Groff!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151289 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 21:56:08 +00:00
Kevin Enderby
b80d571ea8
Updated the llvm-mc disassembler C API to support for the X86 target.
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rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 18:18:17 +00:00
Craig Topper
28a713b20a
Add vmfunc instruction to X86 assembler and disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 01:39:49 +00:00
Craig Topper
9e3d0b3351
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 08:19:49 +00:00
Eli Bendersky
0f0c411079
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
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Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 06:28:33 +00:00
David Meyer
5f7692604d
For ELF, also call fixSymbolsInTLSFixups() on expressions passed to EmitValue (literal values). Previously only called on expressions in instructions. New test cases added to tls.s, tls-i386.s. Resolves PR11981.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150582 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 15:09:06 +00:00
James Molloy
3015dfb7d7
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 10:56:31 +00:00
Kevin Enderby
d49b2a7a9d
Fixed a crash in llvm-mc for Mach-O when a symbol difference expression uses a
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symbol from an assignment. In this case the symbol did not have a fragment so
MCObjectWriter::IsSymbolRefDifferenceFullyResolved() should not have been
calling IsSymbolRefDifferenceFullyResolvedImpl() with a NULL fragment and should
just have returned false in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149442 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 23:02:57 +00:00
Devang Patel
885f65b4a1
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 22:47:12 +00:00
Devang Patel
be3e310d5e
Intel syntax. Support .intel_syntax directive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 20:02:42 +00:00
James Molloy
2d8955a77c
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
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Fixes PR11877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28 15:58:32 +00:00
Rafael Espindola
8b01c82f25
Small improvement to the recursion detection logic from the previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28 06:22:14 +00:00
Rafael Espindola
e71cc86ad1
Handle recursive variable definitions directly. This gives us better error
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messages and allows us to fix PR11865.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28 05:57:00 +00:00
Devang Patel
a28101e61a
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27 19:48:28 +00:00
James Molloy
34982576a4
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
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This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 09:25:43 +00:00
Jim Grosbach
74423e32ce
ARM assemly parsing and validation of IT instruction.
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"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 19:52:01 +00:00
Jim Grosbach
a57a36abe7
NEON VLD4(all lanes) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 00:01:08 +00:00
Jim Grosbach
5e59f7e15e
NEON VLD3(all lanes) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 23:47:04 +00:00
Jim Grosbach
c389af94b6
ARM Darwin symbol ref differences w/o subsection-via-symbols.
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When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148865 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 21:45:25 +00:00
Devang Patel
3b96e1fe3b
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 21:43:36 +00:00
Jim Grosbach
88a54de799
NEON VST4(one lane) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:53:13 +00:00
Jim Grosbach
e983a134e7
NEON VLD4(one lane) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:37:25 +00:00
Jim Grosbach
1ac2060678
NEON Two-operand assembly aliases for VSRA.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:55:36 +00:00
Jim Grosbach
5d9bad4098
Remove redundant test file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148820 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:55:32 +00:00
Jim Grosbach
5e497d3992
NEON Two-operand assembly aliases for VSLI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:49:15 +00:00
Jim Grosbach
d8ee0cc4e8
NEON Two-operand assembly aliases for VSRI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:46:58 +00:00
Jim Grosbach
28f1f9100f
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:46:54 +00:00
Jim Grosbach
539aab771f
NEON VST4(multiple 4 element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:58:13 +00:00
Jim Grosbach
8abe7e3364
NEON VLD4(multiple 4 element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:43:17 +00:00
Jim Grosbach
4adb182342
NEON VST3(single element from one lane) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:07:41 +00:00
Jim Grosbach
d7433e2873
NEON VST3(multiple 3-element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 23:45:44 +00:00
Jim Grosbach
c387fc66bd
NEON VLD3(multiple 3-element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 23:20:46 +00:00
Devang Patel
f2d213745e
Intel syntax: Robustify parsing of memory operand's displacement experssion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 22:35:25 +00:00
Jim Grosbach
3a678af71d
NEON VLD3 lane-indexed assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 21:53:26 +00:00
Rafael Espindola
16d7d437e0
Add support for .cfi_signal_frame. Fixes pr11762.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 21:51:52 +00:00
Devang Patel
3e08131185
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 20:20:06 +00:00
Jim Grosbach
8b31f95bdd
Simplify some NEON assembly pseudo definitions.
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Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 19:39:08 +00:00
Devang Patel
7c64fe651a
Intel syntax: Parse segment registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 18:31:58 +00:00
Devang Patel
1aea430b88
Intel syntax: Robustify register parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:32:05 +00:00
Devang Patel
fdd3b30151
Intel syntax: Parse ... PTR [-8]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:21:01 +00:00
Devang Patel
cf0e269d16
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:14:06 +00:00
Jim Grosbach
51222d1551
NEON use vmov.i32 to splat some f32 values into vectors.
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For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 18:09:51 +00:00
Devang Patel
a951f77ca3
Post process 'and', 'sub' instructions and select better encoding, if available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:40:55 +00:00
Devang Patel
e60540f380
Intel syntax: There is no need to create unary expr for simple negative displacement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:15:51 +00:00
Devang Patel
ac0f048602
Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 17:53:25 +00:00
Jim Grosbach
904b7be27e
Add testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 01:36:59 +00:00
Jim Grosbach
0b4c673886
Thumb2 alternate syntax for LDR(literal) and friends.
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Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 22:46:46 +00:00
Devang Patel
b8ba13f009
Process instructions after match to select alternative encoding which may be more desirable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 22:42:29 +00:00
Jim Grosbach
256ba4f42a
Thumb2 relaxation for LDR(literal).
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If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.
rdar://10711829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148424 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 21:54:16 +00:00
Jim Grosbach
8b9300b972
MC tweak symbol difference resolution for non-local symbols.
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When the non-local symbol in the expression is in the same fragment
as the second symbol, the assembler can still evaluate the expression
without needing a relocation.
For example, on ARM:
_foo:
ldr lr, (_foo - 4)
rdar://10348687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148341 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 22:14:39 +00:00
Jim Grosbach
283f1fff47
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148339 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 22:03:42 +00:00
Devang Patel
2f8af1d643
Intel syntax: Fix parser match class to check memory operand size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 21:48:03 +00:00
Devang Patel
6220fea2a8
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 21:25:10 +00:00
Devang Patel
9a3d293cf3
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 19:08:07 +00:00
Devang Patel
40bced0306
Intel syntax: Ignore mnemonic aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 18:30:45 +00:00
Devang Patel
d37ad247cc
Intel syntax: Robustify memory operand parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 18:00:18 +00:00
Devang Patel
4a5c0fd70e
Add new test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 18:45:31 +00:00
Devang Patel
989a681464
Remove test case, as Chris suggested.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 19:54:02 +00:00
Devang Patel
21d3c40fb0
Add test case to check intel syntax parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148034 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 18:40:46 +00:00
Kevin Enderby
8704b7897d
The error check for using -g with a .s file already containing dwarf .file
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directives was in the wrong place and getting triggered incorectly with a
cpp .file directive. This change fixes that and adds a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 18:04:47 +00:00
Rafael Espindola
29a17145ad
Add big endian mips support. Based on a patch by Jack Carter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147924 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 04:04:14 +00:00
Rafael Espindola
fddf804597
Add the skeleton of an asm parser for mips.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147923 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 03:56:41 +00:00
Kevin Enderby
38fdb7d9fc
Various crash reporting tools have a problem with the dwarf generated for
...
assembly source when it generates the TAG_subprogram dwarf debug info for
the labels that have nothing between them as in this bit of assembly source:
% cat ZeroLength.s
_func1:
_func2:
nop
One solution would be to not emit the subsequent labels with the same address
and use the next label with a different address or the end of the section for
the AT_high_pc value of the TAG_subprogram.
Turns out in llvm-mc it is not possible in all cases to determine of two
symbols have the same value at the point we put out the TAG_subprogram dwarf
debug info.
So we will have llvm-mc instead of putting out TAG_subprogram's put out
DW_TAG_label's. And the DW_TAG_label does not have a AT_high_pc value which
avoids the problem.
This commit is only the functional change to make the diffs clear as to what is
really being changed. The next commit will be to clean up the names of such
things like MCGenDwarfSubprogramEntry to something like MCGenDwarfLabelEntry.
rdar://10666925
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147860 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10 17:52:29 +00:00
Rafael Espindola
99b4237c16
Split Finish into Finish and FinishImpl to have a common place to do end of
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file error checking. Use that to error on an unfinished cfi_startproc.
The error is not nice, but is already better than a segmentation fault.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147717 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 03:13:18 +00:00
Craig Topper
06f554d06a
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 06:23:39 +00:00
Craig Topper
e6a3a2990e
Add FMA4 instructions to disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 05:20:36 +00:00
Rafael Espindola
ed23bdb65f
Implement cfi_restore. Patch by Brian Anderson!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 21:43:03 +00:00
Craig Topper
1604ccfc01
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 20:43:40 +00:00
Rafael Espindola
6f0b181bc7
Implement .cfi_escape. Patch by Brian Anderson!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147352 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 20:24:47 +00:00
Craig Topper
19f18be449
Expose FMA3 instructions to the disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-29 20:03:14 +00:00
Jim Grosbach
4050bc4cab
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:19:05 +00:00
Rafael Espindola
b975c27adc
Fix incorrect relocation generation. Patch by Kristof Beyls.
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Fixes PR11214.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 21:36:43 +00:00
Jim Grosbach
8d9550bde9
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
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Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 18:04:04 +00:00
Akira Hatanaka
bc24985c5f
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
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ELF relocations.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147118 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 01:05:17 +00:00
Jim Grosbach
af33a0cfe0
ARM VFP optional data type on VMOV GPR<-->SPR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:24:15 +00:00
Jim Grosbach
520dc78d92
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
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Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 21:04:19 +00:00
Jim Grosbach
2cc5cda464
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
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These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:54:00 +00:00
Jim Grosbach
e6949b1399
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 19:40:55 +00:00
Jim Grosbach
3471d4fbbd
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:38:54 +00:00
Jim Grosbach
06d738c76a
Enable and fix a test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147011 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:20:00 +00:00
Jim Grosbach
5b484312c6
ARM assembly parsing and encoding for VST2 single-element, double spaced.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:46:29 +00:00
Jim Grosbach
514806b52e
ARM enable a few more tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:03:00 +00:00
Jim Grosbach
95fad1c603
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 19:21:26 +00:00
Jim Grosbach
04b5d93250
ARM assembly shifts by zero should be plain 'mov' instructions.
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"mov r1, r2, lsl #0 " should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:59:38 +00:00
Jim Grosbach
2f196747f1
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 23:06:24 +00:00
Jim Grosbach
d22170e16a
ARM NEON two-operand aliases for VPADD.
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rdar://10602276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:51:03 +00:00
Jim Grosbach
61b74b4247
ARM NEON implied destination aliases for VMAX/VMIN.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:57:38 +00:00
Jim Grosbach
eeaf1c1636
ARM NEON relax parse time diagnostics for alignment specifiers.
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There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:31:43 +00:00
Rafael Espindola
8f7d12ccfd
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
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asm parsing and testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 01:14:52 +00:00
Eli Friedman
7e840efc23
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 23:46:18 +00:00
Jim Grosbach
a738da7bd3
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:56:33 +00:00
Jim Grosbach
60d99a5278
ARM NEON VTBL/VTBX assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:27:11 +00:00
Jim Grosbach
9b1b390288
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:25:46 +00:00
Kevin Enderby
c3fc3136a1
Improve the implementation of .incbin directive by replacing a loop by using
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getStreamer().EmitBytes. Suggestion by Benjamin Kramer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 22:34:45 +00:00
Jim Grosbach
ec04a3f8db
ARM NEON fix alignment encoding for VST2 w/ writeback.
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Add tests for w/ writeback instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:49:24 +00:00
Kevin Enderby
c55accaddb
Add the .incbin directive which takes the binary data from a file and emits
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it to the streamer. rdar://10383898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:47:48 +00:00
Jim Grosbach
e90ac9bce9
ARM NEON VST2 assembly parsing and encoding.
...
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:35:22 +00:00
Jim Grosbach
8d11c6349f
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
...
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:30:24 +00:00
Jim Grosbach
a39cda7aff
ARM assembler support for the target-specific .req directive.
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rdar://10549683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 02:16:11 +00:00
Jim Grosbach
863d2af947
Thumb2 assembler aliases for "mov(shifted register)"
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rdar://10549767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 22:45:11 +00:00
Jim Grosbach
27debd60a1
ARM LDM/STM system instruction variants.
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rdar://10550269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 21:48:29 +00:00
Jim Grosbach
0da6e867cf
Test for 146516
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 21:06:59 +00:00
Jim Grosbach
55b02f28c1
ARM thumb2 parsing of "rsb rd, rn, #0 ".
...
rdar://10549741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:50:38 +00:00
Jim Grosbach
0f293de207
ARM NEON two-operand aliases for VQDMULH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:40:37 +00:00
Jim Grosbach
e91e7bcadc
ARM pre-UAL NEG mnemonic for convenience when porting old code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:23:22 +00:00
Akira Hatanaka
d1472e8657
Add test/MC/Mips/dg.exp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146472 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 04:12:49 +00:00
Akira Hatanaka
692be5491a
Move direct object emitter test to directory test/MC/Mips. Rename it to
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elf-relsym.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 03:50:34 +00:00
Nick Lewycky
5a3d4c9830
Don't rely on a particular version string for llvm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 00:34:14 +00:00
Jan Sjödin
37e7ecf52b
XOP instructions and encoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 19:37:49 +00:00
Roman Divacky
a0c17a495b
Add support for gnu_indirect_function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 17:34:04 +00:00
Chandler Carruth
59164b731b
Don't assume things about the exact details of the LLVM version number,
...
such as what VCS information is attached.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 21:40:31 +00:00
Rafael Espindola
f3aefb56de
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
...
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 02:28:43 +00:00
Jim Grosbach
840bf7eda7
ARM assembly aliases for BIC<-->AND (immediate).
...
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:02:17 +00:00
Jim Grosbach
a4e3c7fc4b
ARM assembly parsing and encoding for VLD2 with writeback.
...
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:28:25 +00:00
Rafael Espindola
3c68acd202
Handle reloc_signed_4byte in here. Not doing so was a regression from my
...
previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146273 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 19:57:29 +00:00
Kevin Enderby
94c2e85bea
The second part of support for generating dwarf for assembly source files. This
...
generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.
The next part will be to get the clang driver to enable this when assembling
a .s file. rdar://9275556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146262 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 18:09:40 +00:00
Rafael Espindola
1d5969d839
Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
...
symbol difference. This matches gas behavior and fixes PR11513.
We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 03:03:58 +00:00
Jim Grosbach
8759c3f548
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:19:04 +00:00
Jim Grosbach
6b044c2609
ARM VSHR implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:06:06 +00:00
Jim Grosbach
318df74104
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:04:40 +00:00
Jim Grosbach
120313435d
ARM VSUB implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:56:26 +00:00
Jim Grosbach
beef39ab63
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146181 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:53:19 +00:00
Jim Grosbach
9e7b42a40e
ARM VQADD implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389
ARM a few more VMUL implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:42:35 +00:00
Jim Grosbach
730fe6c1b6
ARM NEON two-operand aliases for VSHL(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:30:04 +00:00
Jim Grosbach
ff4cbb4c9a
ARM NEON two-operand aliases for VSHL(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:12:35 +00:00
Jim Grosbach
a44f2c4a28
ARM optional destination operand variants for VEXT instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:43:47 +00:00
Jim Grosbach
71a0a2ec0b
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:41:54 +00:00
Jim Grosbach
3bc8a3d3af
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:31:07 +00:00
Jim Grosbach
af4edea67b
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:40:58 +00:00
Jim Grosbach
9fa0a743e6
ARM two-operand aliases for VAND/VEOR/VORR instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f
ARM two-operand aliases for VADDW instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13
ARM two-operand aliases for VADD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:52:54 +00:00
Jim Grosbach
577b09155f
Darwin assembler improved relocs when w/o subsections_via_symbols.
...
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:46:59 +00:00
Jim Grosbach
8524bca750
Thumb2 alias for long-form pop and friends.
...
rdar://10542474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca
ARM support the .arm and .thumb directives for assembly mode switching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:51:15 +00:00
Jim Grosbach
d552a644be
Tidy up. Move MachO tests to MachO directory.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:50:28 +00:00
NAKAMURA Takumi
18851edbc4
test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
...
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 06:48:26 +00:00
Jim Grosbach
23261af193
ARM mode 'mul' operand ordering tweak.
...
Same as r145922, just for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2
Thumb2: MUL two-operand form encoding operand order fix.
...
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:03:45 +00:00
Jim Grosbach
df33e0d05e
Thumb2 encoding choice correction for PLD.
...
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
286ea03382
test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
...
MC/MachO assumes x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 03:56:05 +00:00
Jim Grosbach
d9a6e8978d
Fix ARM handling of tBcc branch relaxation.
...
rdar://10069056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:08:19 +00:00
Jim Grosbach
713c70238c
Tweak ADDrr fix. Bad check for explicit .w
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 22:27:04 +00:00
Jim Grosbach
6e507c645d
Update tests for r145860. Add a few new ones.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 22:21:28 +00:00
Jim Grosbach
da84786bee
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
...
rdar://10529348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 21:06:26 +00:00
Jim Grosbach
253ef7a779
ARM assembly parsing for the rest of the VMUL data type aliases.
...
Finish up rdar://10522016.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 20:29:59 +00:00
Jim Grosbach
c4f0b309ee
ARM tests for VLD1 single lane w/ writeback.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:03:52 +00:00
Jim Grosbach
dad2f8e7fb
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
...
Add the 16-bit lane variants while I'm at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 18:52:30 +00:00