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6355 Commits

Author SHA1 Message Date
Rafael Espindola
fcbd1a749f Fixes win64. It was broken by a previous patch where I missed the !isWin64 
and then forced every register to be a vr128 on win64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109060 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:19:57 +00:00
Chris Lattner
908bafe6fa add some rough support for making mcinst lowering work without an 
asmprinter or mangler around.  This is option #B for killing off 
X86InstrInfo::GetInstSizeInBytes.  Option #A (killing 
"needsexactsize") was sent for consideration to llvmdev.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109056 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:03:35 +00:00
Bruno Cardoso Lopes
e29f37f6a1 Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 21:37:59 +00:00
Nate Begeman
c8ea673bc0 Fix a couple issues with Win64 ABI 
1) all registers were spilled as xmm, regardless of actual size
2) win64 abi doesn't do the varargs-size-in-%al thing

Still to look into:

xmm6-15 are marked as clobbered by call instructions on win64 even though they aren't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109035 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 20:49:52 +00:00
Bruno Cardoso Lopes
928fc3b4a0 Avoid AVX instructions to be selected instead of its SSE form 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109032 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 20:38:42 +00:00
Eric Christopher
dab4dac2a0 Pulling out previous patch, must've run the tests in 
the wrong directory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109005 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 09:23:56 +00:00
Eric Christopher
87f41370a8 Lower MEMBARRIER on x86 and support processors without SSE2. 
Fixes a pile of libgomp failures in the llvm-gcc testsuite due
to the libcall not existing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109004 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 09:05:23 +00:00
Bruno Cardoso Lopes
cf6ca03128 Add AVX only vzeroall and vzeroupper instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109002 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes
7d7d15a159 Add new AVX vpermilps, vpermilpd and vperm2f128 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes
4b13f3cf3d Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108983 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
1154f426d7 Add new AVX vextractf128 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 23:19:02 +00:00
Chris Lattner
6e8154354f make asmprinter optional, even though passing in null will cause things to explode right now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108955 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:45:33 +00:00
Chris Lattner
cb63ecba31 continue pushing dependencies around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108952 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:35:40 +00:00
Chris Lattner
c0115b5ca1 reduce X86MCInstLower dependencies on asmprinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:30:53 +00:00
Chris Lattner
0c13cf36ad pass around MF, not MMI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108949 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:26:07 +00:00
Chris Lattner
7648bd428b cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:23:57 +00:00
Chris Lattner
1a34c83caf move two asmprinter methods into the asmprinter .cpp file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108945 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 22:18:19 +00:00
Bruno Cardoso Lopes
e1c29be6f0 Add new AVX instruction vinsertf128 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108892 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 19:44:51 +00:00
Eric Christopher
72852a8cfb Constify some arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 06:52:21 +00:00
Bruno Cardoso Lopes
43945d99de Add AVX vbroadcast new instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 00:11:13 +00:00
Daniel Dunbar
7b81a0ef17 Update CMake files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 00:08:13 +00:00
Chris Lattner
aef40351f6 fix a layering problem by moving the x86 implementation 
of AsmPrinter and InstLowering into libx86 and out of the
asmprinter subdirectory.  Now X86/AsmPrinter just depends on
MC stuff, not all of codegen and LLVM IR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 23:41:57 +00:00
Bruno Cardoso Lopes
94143ee625 Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 23:32:44 +00:00
Daniel Dunbar
77e2dd7bb2 X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same 
instruction, we only want to allow the one for the current subtarget.
 - This also fixes suffix matching for jmp instructions, because it eliminates
   the ambiguity between 'jmpl' and 'jmpq'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 20:44:16 +00:00
Daniel Dunbar
926f2bb3d8 X86-64: Mark WINCALL and more tail call instructions as code gen only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108685 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 07:21:07 +00:00
Daniel Dunbar
e4c52a2c41 X86: Mark some tail call pseduo instruction as code gen only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108684 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 07:21:04 +00:00
Daniel Dunbar
df4c47be29 X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 07:21:01 +00:00
Daniel Dunbar
90b374cded MC/X86: We now match instructions like "incl %eax" correctly for the arch we are 
assembling; remove crufty custom cleanup code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108681 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 06:14:54 +00:00
Daniel Dunbar
cf246b7f0b X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108680 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 06:14:49 +00:00
Daniel Dunbar
6c2c9a27c5 X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108679 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 06:14:44 +00:00
Daniel Dunbar
54074b5f04 TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher. 
- Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 05:44:09 +00:00
Daniel Dunbar
d73ada7d24 Target: Give the TargetAsmParser access to the TargetMachine. 
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108664 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 00:33:49 +00:00
Chris Lattner
89a902e1c2 the stackifier is global! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108626 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-17 17:42:04 +00:00
Chris Lattner
a40ce7e394 doxygenify some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108625 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-17 17:40:51 +00:00
Eric Christopher
697cba8ec2 Remove unnecessary check that was subsumed into canRealignStack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-17 00:33:04 +00:00
Eric Christopher
acdb4b9203 Make comment a bit more clear as well as return statement since 
needsStackRealignment is currently checking the can conditions as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108581 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-17 00:25:41 +00:00
Jakob Stoklund Olesen
78e6e00922 Remove the isMoveInstr() hook. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-16 22:35:46 +00:00
Jakob Stoklund Olesen
84d499a698 Use MI.isCopy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108565 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-16 22:35:34 +00:00
Bill Wendling
7431beaba2 Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and 
thus is a much more meaningful name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-16 22:20:36 +00:00
Jakob Stoklund Olesen
b47bb13331 Keep valgrind quiet. 
The isLive() method can read uninitialized memory, but it still gives correct
results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108561 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-16 22:00:33 +00:00
Dale Johannesen
323200d905 Accept registers with P modifier. PR 5314. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108545 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-16 18:35:46 +00:00
Jakob Stoklund Olesen
468a2a44e2 Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill 
pass that inserted it.

It is no longer necessary to limit the live ranges of FP registers to a single
basic block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108536 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-16 17:41:44 +00:00
Jakob Stoklund Olesen
e098e7a96d Search for a free FP register instead of just assuming FP7 is not in use. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108535 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-16 17:41:40 +00:00
Jakob Stoklund Olesen
e928ec9480 Allow x87 FP registers to be alive globally in a function. 
FP_REG_KILL instructions are still inserted, but can be disabled by passing
-live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly.

CFG edges are partioned into bundles where the x87 stack must be allocated
identically. Code is insertad at the end of each basic block that shuffles the
live FP registers to match the outgoing bundles expectations.

This fix is in preparation for some upcoming register allocator improvements
that may extend the live range of registers beyond a basic block, similar to
LICM. It also provides a nice runtime speedup if you are building with
-mfpmath=387.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-16 16:38:12 +00:00
Evan Cheng
60108e96bb Split -enable-finite-only-fp-math to two options: 
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-15 22:07:12 +00:00
Chris Lattner
d1c58cf7bb fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3, 
this fixes rdar://8192860.  Unfortunately it can only be triggered
with llc because llvm-mc matches another (correctly encoded) version
of this, so no testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-15 20:13:34 +00:00
Jakob Stoklund Olesen
6881898eb5 Last COPY conversion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108387 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 23:58:21 +00:00
Jakob Stoklund Olesen
b5378ea12e Use TargetOpcode::COPY instead of X86-native register copy instructions when 
lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108385 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 23:50:27 +00:00
Chris Lattner
41af1cdd1c fix indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108368 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 23:04:59 +00:00
Benjamin Kramer
38e59891ee Don't pass StringRef by reference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 22:38:02 +00:00
Chris Lattner
9fe2c67045 Merge lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h, 
patch by Michael Spencer!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 18:14:33 +00:00
Evan Cheng
dedd974e7e Fix for PR7193 was overly conservative. The only case where sibcall callee 
address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.

This fixes PR7610.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108327 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 06:44:01 +00:00
Dan Gohman
a10b8494a5 Don't propagate debug locations to instructions for materializing 
constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108302 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 01:07:44 +00:00
Bruno Cardoso Lopes
7dbf7d8b1c Add AVX 256-bit compare instructions and a bunch of testcases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108286 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 22:06:38 +00:00
Bruno Cardoso Lopes
87a85c7ef0 AVX 256-bit conversion instructions 
Add the x86 VEX_L form to handle special cases where VEX_L must be set.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 21:07:28 +00:00
Kevin Enderby
52a18aedae Added a check that pusha cannot be encoded in 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108265 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 20:05:41 +00:00
Chris Lattner
37a746bc85 my work on adding segment registers to LEA missed the 
disassembler.  Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 04:23:55 +00:00
Bruno Cardoso Lopes
fd920fa59a Add AVX 256-bit packed logical forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108224 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 02:38:35 +00:00
Bruno Cardoso Lopes
6991623dd7 Add AVX 256-bit unop arithmetic instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108223 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 01:53:31 +00:00
Bruno Cardoso Lopes
4344d85769 Since AVX is a superset of all SSE versions, only use HasAVX for AVX instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108222 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 00:38:47 +00:00
David Greene
8f17bc4fbd Move some SIMD fragment code into X86InstrFragmentsSIMD so that the 
utility classes can be used from multiple files.  This will aid
transitioning to a new refactored x86 SIMD specification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108213 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 23:41:28 +00:00
Bruno Cardoso Lopes
a0d09a85e2 Add AVX 256 binary arithmetic instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108207 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 23:04:15 +00:00
Bruno Cardoso Lopes
f428fee70d More refactoring of basic SSE arith instructions. Open room for 256-bit instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 22:41:32 +00:00
Dan Gohman
cfbf0ed8b0 Apply the SSE dependence idiom for SSE unary operations to 
SD instructions too, in addition to SS instructions. And
add a comment about it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108191 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 20:46:04 +00:00
Bruno Cardoso Lopes
aa099be71f Add AVX 256-bit MOVMSK forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108184 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 20:06:32 +00:00
Dan Gohman
ed42f1e58f Check begin!=end, rather than !begin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 18:12:35 +00:00
Dan Gohman
be4d10d7fa Don't fast-isel an x87 comparison opcode, as fast-isel doesn't 
support branching on x87 comparisons yet. This fixes PR7624.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108149 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 15:46:30 +00:00
Rafael Espindola
5a717a3ae7 Convert getLoadStoreRegOpcode to use a switch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108123 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 03:43:04 +00:00
Jakob Stoklund Olesen
8b78d4b5bb A basic block that only uses RFP registers still needs the FP_REG_KILL marker. 
This fixes PR7375.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108120 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 02:12:47 +00:00
Rafael Espindola
0bfd09201e Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp to 
getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.

Update getLoadStoreRegOpcode to handle GR32_AD.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108115 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 00:52:33 +00:00
Jakob Stoklund Olesen
a66450d227 Use target independent COPY instructions for the fake fextend and fround 
operations in x87 code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108098 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-11 18:19:39 +00:00
Jakob Stoklund Olesen
aef48d7b36 Remove obsolete README_SSE note. 
We are generating movaps for all XMM register copies, including scalar
floating point values. This is known to be at least as good as movss and movsd
for all known architectures up to and including Nehalem because it avoids a
partial register stall.

The SSEDomainFix pass will switch movaps to movdqa when appropriate (i.e., when
operands come from the integer unit). We don't now that switching movaps to
movapd has any benefit.

The same applies to andps -> pand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108096 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-11 17:13:42 +00:00
Jakob Stoklund Olesen
75be45cb2e Avoid SSE instructions in FastIsel when it is not available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108091 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-11 16:22:13 +00:00
Jakob Stoklund Olesen
4ea8771535 X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108076 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-11 05:44:30 +00:00
Jakob Stoklund Olesen
1ba318982e Use COPY in X86FastISel::X86SelectRet. 
Don't try a cross-class copy. That is very unlikely anywy since return value
registers are usually register class friendly. (%EAX, %XMM0, etc).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108074 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-11 05:17:02 +00:00
Jakob Stoklund Olesen
5127f79913 Use COPY in FastISel everywhere it is safe and trivial. 
The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108069 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-11 03:31:00 +00:00
Jakob Stoklund Olesen
2b336bc4fe Don't emit st(0)/st(1) copies as FpMOV instructions. Use FpSET_ST? instead. 
Based on a patch by Rafael Espíndola.

Attempt to make the FpSET_ST1 hack more robust, but we are still relying on
FpSET_ST0 preceeding it. This is only for supporting really weird x87 inline
asm.

We support:

  FpSET_ST0
  INLINEASM

  FpSET_ST0
  FpSET_ST1
  INLINEASM

with and without kills on the arguments. We don't support:

  FpSET_ST1
  FpSET_ST0
  INLINEASM

nor

  FpSET_ST1
  INLINEASM

Just Don't Do It!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-10 17:42:34 +00:00
Dan Gohman
84023e0fbe Reapply bottom-up fast-isel, with several fixes for x86-32: 
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-10 09:00:22 +00:00
Jakob Stoklund Olesen
d737fcafc4 An x86 function returns a floating point value in st(0), and we must make sure 
it is popped, even if it is ununsed. A CopyFromReg node is too weak to represent
the required sideeffect, so insert an FpGET_ST0 instruction directly instead.

This will matter when CopyFromReg gets lowered to a generic COPY instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108037 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-10 04:04:25 +00:00
Bruno Cardoso Lopes
58dbf3784d Declare YMM subregisters in the right way! Thanks Jakob 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108022 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 21:46:19 +00:00
Bruno Cardoso Lopes
d52e78efac Add AVX 256-bit packed MOVNT variants 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 21:42:42 +00:00
Jakob Stoklund Olesen
61905c8ab3 Remember the *_TC opcodes for load/store 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 21:27:55 +00:00
Bruno Cardoso Lopes
2bfb8f6ef8 Add AVX 256-bit unpack and interleave 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108017 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 21:20:35 +00:00
Jakob Stoklund Olesen
1f32340d95 Automatically fold COPY instructions into stack load/store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 20:43:13 +00:00
Jakob Stoklund Olesen
9c50e8b890 Fix a few tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108011 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 20:43:09 +00:00
Bruno Cardoso Lopes
e86b01c153 Start the support for AVX instructions with 256-bit %ymm registers. A couple of 
notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 18:27:43 +00:00
Bob Wilson
02266e29f9 --- Reverse-merging r107947 into '.': 
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 16:37:18 +00:00
Bruno Cardoso Lopes
be95c15903 Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX 
fields to use. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107952 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 01:56:45 +00:00
Dan Gohman
01dcb18cf3 Fix the memoperand offsets in code generated for va_start. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107948 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 01:06:48 +00:00
Chris Lattner
c5f5626a29 have the mc lowering process handle a few tail call forms, lowering them to 
jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.

This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.

However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107946 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 00:49:41 +00:00
Dan Gohman
bf87e24917 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting 
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 00:39:23 +00:00
Bruno Cardoso Lopes
1cd050931f Factor out x86 segment override prefix encoding, and also use it for VEX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 00:38:14 +00:00
Chris Lattner
757e8d6d2e reject pseudo instructions early in the encoder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107939 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 00:17:50 +00:00
Bruno Cardoso Lopes
96716c7b92 Remove trailing whitespaces from file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 00:07:19 +00:00
Chris Lattner
599b531a96 Change LEA to have 5 operands for its memory operand, just 
like all other instructions, even though a segment is not
allowed.  This resolves a bunch of gross hacks in the 
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 23:46:44 +00:00
Chris Lattner
ac0ed5dc08 add some long-overdue enums to refer to the parts of the 5-operand 
X86 memory operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107925 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 22:41:28 +00:00
Jakob Stoklund Olesen
61c8eccf24 Remember the VR64 register class 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107920 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 22:30:35 +00:00
Chris Lattner
834df19452 Rework segment prefix emission code to handle segments 
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 22:28:12 +00:00
Chris Lattner
751e1123ce introduce a new X86II::getMemoryOperandNo method, which 
returns the start of the memory operand for an instruction.

Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107916 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 22:27:06 +00:00
Jakob Stoklund Olesen
7db1e7a527 Teach the x86 floating point stackifier to handle COPY instructions. 
This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.

Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107899 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 19:46:30 +00:00
Jakob Stoklund Olesen
320bdcbfe2 Implement X86InstrInfo::copyPhysReg 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107898 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 19:46:25 +00:00
Jakob Stoklund Olesen
0bc25f4040 Convert EXTRACT_SUBREG to COPY when emitting machine instrs. 
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 16:40:22 +00:00
Jakob Stoklund Olesen
5c00e07795 Remove references to INSERT_SUBREG after de-SSA. 
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 16:40:15 +00:00
Eric Christopher
fb31ccb68c A slight reworking of the custom patterns for x86-64 tpoff codegen and 
correct the testcase for valid assembly.

Needs more tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 07:36:46 +00:00
Dan Gohman
f595141525 Revert 107840 107839 107813 107804 107800 107797 107791. 
Debug info intrinsics win for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 01:00:56 +00:00
Jakob Stoklund Olesen
5febd075df fix copies to/from GR8_ABCD_H even more 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107832 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 23:04:56 +00:00
Chris Lattner
da3051a17f finish up support for callw: PR7195 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107826 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 22:35:13 +00:00
Chris Lattner
9fc05227a2 Implement the major chunk of PR7195: support for 'callw' 
in the integrated assembler.  Still some discussion to be
done.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
cc69e13a36 Add more assembly opcodes for SSE compare instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107823 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 22:24:03 +00:00
Evan Cheng
bcc8017c73 Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 22:15:37 +00:00
Devang Patel
03753fc734 Print undefined/unknown debug value as "undef". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107818 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 21:52:21 +00:00
Jakob Stoklund Olesen
f2e4afd96c Allow copies between GR8_ABCD_L and GR8_ABCD_H. 
This fixes PR7540.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 20:33:27 +00:00
Dan Gohman
4df83ed159 Implement bottom-up fast-isel. This has the advantage of not requiring 
a separate DCE pass over MachineInstrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 19:20:32 +00:00
Dan Gohman
f423a69839 Add X86FastISel support for return statements. This entails refactoring 
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 18:32:53 +00:00
Bruno Cardoso Lopes
ced9ec9bac Add AVX AES instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 18:24:20 +00:00
Dan Gohman
eabaed26c3 Give FunctionLoweringInfo an MBB member, avoiding the need to pass it 
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107791 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 16:47:08 +00:00
Dan Gohman
a4160c3434 Simplify FastISel's constructor by giving it a FunctionLoweringInfo 
instance, rather than pointers to all of FunctionLoweringInfo's
members.

This eliminates an NDEBUG ABI sensitivity.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 16:29:44 +00:00
Dan Gohman
c9403659a9 Split the SDValue out of OutputArg so that SelectionDAG-independent 
code can do calling-convention queries. This obviates OutputArgReg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 15:54:55 +00:00
Bruno Cardoso Lopes
4f6bdf9042 Add AVX SSE4.2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107752 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
332fce49e3 Use only one multiclass to pinsrq instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107750 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes
5e9fa98523 Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107749 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes
09df2ae0d0 Add AVX SSE4.1 insertps, ptest and movntdqa instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
3c14822312 Add AVX SSE4.1 extractps and pinsr instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 01:01:13 +00:00
Bruno Cardoso Lopes
4fd32db6a6 Add AVX SSE4.1 Extract Integer instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 00:07:24 +00:00
Dale Johannesen
e2b448c208 Accept RIP-relative symbols with 'i' constraint, and 
print the (%rip) only if the 'a' modifier is present.
PR 7528.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107727 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:27:00 +00:00
Bruno Cardoso Lopes
ee94e8297e Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107723 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
36869b69b0 Add part of AVX SSE4.1 packed move with sign/zero extend instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107720 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
0106680a2c Fix comment from previous patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107717 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes
07de40629f Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 22:36:24 +00:00
Dan Gohman
c9af33c685 CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext. 
SelectBasicBlock doesn't needs its BasicBlock argument.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 22:19:37 +00:00
Devang Patel
0d881dabc1 Propagate debug loc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 22:08:15 +00:00
Dan Gohman
14152b480d Reapply r107655 with fixes; insert the pseudo instruction into 
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 20:24:04 +00:00
Devang Patel
be35be614c Fix PR7545 crash. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107678 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 18:18:32 +00:00
Dan Gohman
258c58cc62 Revert r107655. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 15:49:48 +00:00
Dan Gohman
b81c771c0d Fix a bunch of custom-inserter functions to handle the case where 
the pseudo instruction is not at the end of the block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 15:18:19 +00:00
Eric Christopher
f7a0c7bf8b Fix up -fstack-protector on linux to use the segment 
registers.  Split out testcases per architecture and os
now.

Patch from Nelson Elhage.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107640 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 05:18:56 +00:00
Eric Christopher
62f35a2c13 Have the X86 backend use Triple instead of a string and some enums. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107625 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-05 19:26:33 +00:00
Chris Lattner
32b4b5aea6 more tidying. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107615 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-05 05:53:14 +00:00
Chris Lattner
c06cbad141 some notes about suboptimal insertps's 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107613 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-05 05:48:41 +00:00
Chris Lattner
a5b412581c rip out even more sporadic v2f32 support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107610 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-05 04:38:33 +00:00
Chris Lattner
39aa20a981 rip out the various v2f32 "mmx" handling logic, now that 
v2f32 is illegal on x86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107609 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-05 04:36:27 +00:00
Chris Lattner
f172ecd964 Just rip v2f32 support completely out of the X86 backend. In 
the example in the testcase, we now generate:

_test1:                                 ## @test1
	movss	4(%esp), %xmm0
	addss	8(%esp), %xmm0
	movl	12(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

_test1:                                                     ## @test1
	subl	$20, %esp
	movl	24(%esp), %eax
	movq	%mm0, (%esp)
	movq	%mm0, 8(%esp)
	movss	(%esp), %xmm0
	addss	12(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$20, %esp
	ret

v2f32 support did not work reliably because most of the X86
backend didn't know it was legal.  It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode.  If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32.  However,
we generally don't try very hard to be abi compatible on gcc
extended vectors. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 23:07:25 +00:00
Chris Lattner
e35d9842f7 fix PR7518 - terrible codegen of <2 x float>, by only marking 
v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 22:57:10 +00:00
Chris Lattner
9d19989fe3 indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107599 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 22:56:10 +00:00
Bill Wendling
f43f6bc3ec Revert r107583. I no longer think that this is the way to solve the problem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107585 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 09:16:57 +00:00
Bill Wendling
4a991a6fa6 Mark sse_load_f32 and sse_load_f64 as having memory operands 
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107583 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-04 08:59:55 +00:00
Bruno Cardoso Lopes
68b559e5f3 Add AVX SSE4.1 blend, mpsadbw and vdp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
4a544be3a8 Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107558 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
c607570563 Add AVX SSE4.1 Horizontal Minimum and Position instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107552 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 00:49:21 +00:00
Evan Cheng
ed2ae136d2 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 00:40:23 +00:00
Bruno Cardoso Lopes
2c70d4ad35 Add AVX SSE4.1 round instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
03560600b4 Simple refactoring of SSE4.1 instructions, making room for the AVX forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107540 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 23:27:59 +00:00
Bruno Cardoso Lopes
f5cd8c51e3 - Add support for the rest of AVX SSE3 instructions 
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 22:06:54 +00:00
Evan Cheng
98ec91ea80 - Two-address pass should not assume unfolding is always successful. 
- X86 unfolding should check if the instructions being unfolded has memoperands.
  If there is no memoperands, then it must assume conservative alignment. If this
  would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
  etc. should not unfold the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 20:36:18 +00:00
Bruno Cardoso Lopes
f12ad66741 Shrink down SSE3 code by more multiclass refactoring 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107448 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 23:10:49 +00:00
Bruno Cardoso Lopes
944facac2e Shrink down SSE3 code by some multiclass refactoring - 1st part 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107438 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 22:33:18 +00:00
Bruno Cardoso Lopes
c6fcdeb8f9 Move SSE3 Move patterns to a more appropriate section 
Add AVX SSE3 packed horizontal and & sub instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107405 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
7144821c61 Add AVX SSE3 packed addsub instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 17:08:18 +00:00
Dan Gohman
20d4be151b Enable on-demand fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:58:57 +00:00
Dan Gohman
abd1d859b3 Fix X86FastISel's add folding to actually work, and not fall back 
to SelectionDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:58:21 +00:00
Bruno Cardoso Lopes
79b634c244 Add AVX SSE3 replicate and convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:33:39 +00:00
Dan Gohman
5c87bf64d6 Teach X86FastISel to fold constant offsets and scaled indices in 
the same address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:27:15 +00:00
Bruno Cardoso Lopes
6596a62076 - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
7ac7ed868a Move MOVD/MODQ code around, creating sections for each of them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107308 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes
e26f14d150 Add AVX SSE2 mask creation and conditional store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
130acd15fc Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes
1e4b723b20 Add AVX SSE2 packed integer extract/insert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 17:03:03 +00:00
Gabor Greif
e1c2b9cc3d use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 13:03:37 +00:00
Bruno Cardoso Lopes
876085dcfa Add AVX SSE2 integer unpack instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
d252fec7ae Add AVX SSE2 packed integer shuffle instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
555bea62dd Small refactoring of SSE2 packed integer shuffle instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes
6d5d2b5de2 Add AVX SSE2 pack with saturation integer instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c0ea94a37c Add AVX SSE2 integer packed compare instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
5a3a476750 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
6c9fa43716 Add *several* AVX integer packed binop instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes
2c818072cc Move SSE2 Packed Integer instructions around, and create specific sections for each of them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107211 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes
8d3cebca8e Add AVX Move Aligned/Unaligned packed integers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 21:25:12 +00:00
Bruno Cardoso Lopes
147b7cad2f Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
721ef73d88 Add AVX non-temporal stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107178 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
de173ca1fb Move non-temporal movs to their own section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:42:37 +00:00
Bruno Cardoso Lopes
ea86423cbd Add sqrt, rsqrt and rcp AVX instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107166 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:26:30 +00:00
Duncan Sands
78337b4d4d Remove pointless and unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107130 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 12:48:49 +00:00
Bruno Cardoso Lopes
b22dc70a5c Refactoring of arithmetic instruction classes with unary operator 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107116 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 01:33:09 +00:00
Bruno Cardoso Lopes
4548260ab5 Described the missing AVX forms of SSE2 convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 00:36:02 +00:00
Bill Wendling
c25ccf85e5 Reduce indentation via early exit. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:08:32 +00:00
Gabor Greif
1cfe44a460 use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106944 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 11:51:52 +00:00
Jakob Stoklund Olesen
4f5d84e4ad When creating X86 MUL8 and DIV8 instructions, make sure we don't produce 
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.

Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).

This fixes PR7312.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 00:39:23 +00:00
Bruno Cardoso Lopes
bdffc16d65 Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes
161476ec34 Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
95325b08a3 revert this now, it's using avx instead of sse :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes
544a95d716 Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:27:51 +00:00
Dale Johannesen
1784d160e4 The hasMemory argument is irrelevant to how the argument 
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:55:36 +00:00
Dan Gohman
ca5b8553ea pcmpeqd and friends are Commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106886 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:05:35 +00:00
Bill Wendling
730c07e50d - Reapply r106066 now that the bzip2 build regression has been fixed. 
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:48:10 +00:00
Bruno Cardoso Lopes
39afa908de Move the last piece of SSE2 convert instructions to the Convert Instructions section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106877 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:29:27 +00:00
Bruno Cardoso Lopes
6560ed35b4 More SSE refactoring, this time with different types of MOVs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:22:12 +00:00
Bruno Cardoso Lopes
0491e132fc Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106867 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 18:06:22 +00:00
Bruno Cardoso Lopes
a0ae87fd5d Add some AVX convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
8b94297727 Refactoring of SSE convert intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 23:37:07 +00:00
Bruno Cardoso Lopes
f241b26792 Refactoring of SSE conversion instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 22:22:21 +00:00