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5790 Commits

Author SHA1 Message Date
Chris Lattner
eaa7c06d86 ADd a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27324 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-01 04:08:29 +00:00
Chris Lattner
348ba3f9bf Shrinkify some more intrinsic definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27322 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 22:41:56 +00:00
Evan Cheng
67d3d4c085 An entry about packed type alignments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27321 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 22:35:14 +00:00
Chris Lattner
6cea814f2c Pull operand asm string into base class, shrinkifying intrinsic definitions. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27320 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 22:34:05 +00:00
Evan Cheng
e668bdaa52 TargetData.cpp::getTypeInfo() was returning alignment of element type as the 
alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignment. The correct fix would
be to return a target dependent alignment value provided via TargetLowering
(or some other interface).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27319 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 22:33:42 +00:00
Chris Lattner
b5c4d17a6c Fix 80 column violations :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27315 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 21:57:36 +00:00
Evan Cheng
653159f4aa Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed 
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27314 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 21:55:24 +00:00
Evan Cheng
4b1734f70b Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27310 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 21:29:33 +00:00
Chris Lattner
7376a5e129 fix a pasto 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27308 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 21:19:06 +00:00
Chris Lattner
a9cb441642 Add vperm support for all datatypes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27307 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 20:00:35 +00:00
Chris Lattner
e3fea5a1c1 Rearrange code a bit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27306 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 19:52:36 +00:00
Chris Lattner
32a988a095 Add, sub and shuffle are legal for all vector types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27305 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 19:48:58 +00:00
Evan Cheng
b067a1e7e6 Add support to use pextrw and pinsrw to extract and insert a word element 
from a 128-bit vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27304 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 19:22:53 +00:00
Evan Cheng
1eda6e7924 Add vector_extract and vector_insert nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27303 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 19:21:16 +00:00
Chris Lattner
9f7e127133 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27302 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 19:00:22 +00:00
Chris Lattner
33497cc992 note to self: *save* file, then check it in 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27291 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 06:04:53 +00:00
Chris Lattner
4468c22458 Implement an item from the readme, folding vcmp/vcmp. instructions with 
identical instructions into a single instruction.  For example, for:

void test(vector float *x, vector float *y, int *P) {
  int v = vec_any_out(*x, *y);
  *x = (vector float)vec_cmpb(*x, *y);
  *P = v;
}

we now generate:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v0, v1, v0
        mfcr r4, 2
        stvx v0, 0, r3
        rlwinm r3, r4, 27, 31, 31
        xori r3, r3, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

instead of:

_test:
        mfspr r2, 256
        oris r6, r2, 57344
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v2, v1, v0
        mfcr r4, 2
***     vcmpbfp v0, v1, v0
        rlwinm r4, r4, 27, 31, 31
        stvx v0, 0, r3
        xori r3, r4, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

Testcase here: CodeGen/PowerPC/vcmp-fold.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27290 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 06:02:07 +00:00
Chris Lattner
9492151e32 compactify some more instruction definitions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27288 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 05:38:32 +00:00
Chris Lattner
5f7b01963f Compactify comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27287 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 05:32:57 +00:00
Chris Lattner
a17b1557ad Lower vector compares to VCMP nodes, just like we lower vector comparison 
predicates to VCMPo nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27285 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 05:13:27 +00:00
Chris Lattner
8f5d316ff2 These are done 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27284 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 04:53:21 +00:00
Chris Lattner
36f4b0da9d Mark INSERT_VECTOR_ELT as expand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27276 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 01:48:55 +00:00
Evan Cheng
33e85ca7b6 Expand all INSERT_VECTOR_ELT (obviously bad) for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27275 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 01:30:39 +00:00
Evan Cheng
fb47a9b1c8 Typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27272 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 00:33:57 +00:00
Evan Cheng
ef698ca30d Ok for vector_shuffle mask to contain undef elements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27271 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-31 00:30:29 +00:00
Chris Lattner
8768bf6ee3 Add the rest of the vmul instructions and the vmulsum* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27268 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 23:39:06 +00:00
Chris Lattner
3c4f4e9f1b Use a new tblgen feature to significantly shrinkify instruction definitions that 
directly correspond to intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27266 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 23:21:27 +00:00
Chris Lattner
30a6abaef0 Add a bunch of new instructions for intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27265 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 23:07:36 +00:00
Evan Cheng
7d9061e300 Make sure all possible shuffles are matched. 
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27259 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 19:54:57 +00:00
Evan Cheng
1b32f22b0f More logical ops patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27257 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 07:33:32 +00:00
Evan Cheng
0876aa5178 Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27256 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 06:21:22 +00:00
Evan Cheng
c5fb2b14ca Add 128-bit pmovmskb intrinsic support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27255 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-30 00:33:26 +00:00
Evan Cheng
591f740a40 Change SSE pack operation definitions to fit what the intrinsics expected. 
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27254 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 23:53:14 +00:00
Evan Cheng
506d3dfa90 - Added some SSE2 128-bit packed integer ops. 
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27252 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 23:07:14 +00:00
Evan Cheng
691c923e47 Need to special case splat after all. Make the second operand of splat 
vector_shuffle undef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27250 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 19:02:40 +00:00
Evan Cheng
5aa97b200b Floating point logical operation patterns should match bit_convert. Or else 
integer vector logical operations would match andp{s|d} instead of pand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27248 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 18:47:40 +00:00
Evan Cheng
475aecf467 - More shuffle related bug fixes. 
- Whenever possible use ops of the right packed types for vector shuffles /
  splats.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27246 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 03:04:49 +00:00
Evan Cheng
c999c745c0 Another entry about shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27245 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 03:03:46 +00:00
Evan Cheng
4f5633883b - Only use pshufd for v4i32 vector shuffles. 
- Other shuffle related fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27244 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 01:30:51 +00:00
Chris Lattner
f3a627262c add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27243 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-29 00:24:13 +00:00
Evan Cheng
c46349de29 Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics. 
The source operands type are v4sf with upper bits passes through.
Added matching code for these.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27240 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 23:51:43 +00:00
Evan Cheng
36b27f3cde Fixing buggy code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27239 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 23:41:33 +00:00
Chris Lattner
d732a2915b add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27227 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 18:56:23 +00:00
Jim Laskey
a99791886d Expose base register for DwarfWriter. Refactor code accordingly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 13:48:33 +00:00
Jim Laskey
2d2a6131da Added missing paren on behalf of Ramana Radhakrishnan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27223 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 10:17:11 +00:00
Evan Cheng
ed4ca7f6c3 Missed X86::isUNPCKHMask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27222 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 08:27:15 +00:00
Evan Cheng
9bbfd4f68c movlps and movlpd should be modeled as two address code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27221 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 07:01:28 +00:00
Evan Cheng
6a6d354d4c Update 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27220 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 06:55:45 +00:00
Evan Cheng
be296ac5ca Typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27219 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 06:53:49 +00:00
Evan Cheng
2064a2b47e * Prefer using operation of matching types. e.g unpcklpd rather than movlhps. 
* Bug fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27218 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 06:50:32 +00:00
Nate Begeman
816cee2216 Fix a couple typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27216 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 04:18:18 +00:00
Nate Begeman
98e70cc124 Add a few more altivec intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27215 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 04:15:58 +00:00
Evan Cheng
4c4a2e2a0d Added a couple of entries about movhps and movlhps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27212 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:49:12 +00:00
Evan Cheng
000e4dd54b All unpack cases are now being handled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27211 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:44:05 +00:00
Evan Cheng
4fcb922c70 - Clean up / consoladate various shuffle masks. 
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27210 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:43:26 +00:00
Chris Lattner
ecc219b8d4 implement a bunch more intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27209 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 02:29:37 +00:00
Chris Lattner
7f20b13518 Use normal lvx for scalar_to_vector instead of lve*x. They do the exact 
same thing and we have a dag node for the former.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27205 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 01:43:22 +00:00
Chris Lattner
48b61a729d Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27201 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 00:40:33 +00:00
Evan Cheng
0038e59803 Model unpack lower and interleave as vector_shuffle so we can lower the 
intrinsics as such.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27200 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 00:39:58 +00:00
Jim Laskey
414e682bac Translate llvm target registers to dwarf register numbers properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27180 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 20:18:45 +00:00
Chris Lattner
749b758b2e unbreak the build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27174 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 16:52:45 +00:00
Chris Lattner
3ee9ffb0e5 Add a bunch of notes from my journey thus far. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27170 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 07:41:00 +00:00
Chris Lattner
b86bd2cee2 Split out altivec notes into their own README 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27168 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 07:04:16 +00:00
Evan Cheng
a0b3afbe14 Use pcmpeq to generate vector of all ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27167 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 07:00:16 +00:00
Evan Cheng
999f3b538f Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27166 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 06:59:32 +00:00
Chris Lattner
fb143ce459 Fix the JIT encoding of VSEL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27160 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 03:34:17 +00:00
Chris Lattner
eeaf72af39 Fix the JIT encoding of VSPLTI* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27159 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 03:28:57 +00:00
Nate Begeman
f15485a8d0 SelectionDAGISel can now natively handle Switch instructions, in the same 
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 01:32:24 +00:00
Chris Lattner
bd6be6f52d add vsel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27153 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 22:38:43 +00:00
Nate Begeman
c02e5a8668 Readme note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27152 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 19:19:27 +00:00
Chris Lattner
6d92caddc4 Codegen vector predicate compares. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27151 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 10:06:40 +00:00
Evan Cheng
ffea91e522 Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27150 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 09:53:12 +00:00
Evan Cheng
5b6a01b59c Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27149 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 09:52:32 +00:00
Evan Cheng
e506f9ae35 Add immAllZerosV helper 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27148 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 09:51:39 +00:00
Chris Lattner
b8a45c2798 Add all of the altivec comparison instructions. Add patterns for the 
non-predicate altivec compare intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27143 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 04:57:17 +00:00
Chris Lattner
5d72907e00 Add and 8/16-bit adds, add all integer subtracts, add saturating subtract 
intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27142 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 02:39:02 +00:00
Chris Lattner
e7d959c069 implement the vsldoi intrinsic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27139 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-26 00:41:48 +00:00
Chris Lattner
af9136bc0c fix the pattern for vandc, it's NOT vnand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27136 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 23:10:40 +00:00
Chris Lattner
6509ae859a add patterns for VANDC/VNOR, implementing 
CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27135 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 23:05:29 +00:00
Chris Lattner
c985d828bc add a vnot helper node for matching 'not' on vectors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27132 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 23:00:08 +00:00
Chris Lattner
2430a5f0c7 Add some logical operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27127 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 22:16:05 +00:00
Evan Cheng
6e16ee5634 Added missing (any_extend (load ...)) patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27120 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 09:45:48 +00:00
Evan Cheng
c60bd97b94 Build arbitrary vector with more than 2 distinct scalar elements with a 
series of unpack and interleave ops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27119 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 09:37:23 +00:00
Chris Lattner
984f38bf4f implement a bunch of intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27118 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 08:01:02 +00:00
Chris Lattner
b22a04d881 Move all Altivec stuff out into a new PPCInstrAltivec.td file. 
Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27117 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 07:51:43 +00:00
Chris Lattner
8d052bc711 Add some basic patterns for other datatypes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27116 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 07:39:07 +00:00
Chris Lattner
150ffa7842 add all supported formats to the vector register file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27115 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 07:36:56 +00:00
Chris Lattner
5a2025465b Add support for __builtin_altivec_vnmsubfp /vmaddfp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27112 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 07:05:55 +00:00
Chris Lattner
420736dc85 #include Intrinsics.h into all dag isels 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 06:47:10 +00:00
Chris Lattner
9c61dcf1aa Codegen things like: 
<int -1, int -1, int -1, int -1>
and
 <int 65537, int 65537, int 65537, int 65537>

Using things like:
  vspltisb v0, -1
and:
  vspltish v0, 1

instead of using constant pool loads.

This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27106 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 06:12:06 +00:00
Evan Cheng
ecac9cb959 Added SSE cachebility ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27103 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 06:03:26 +00:00
Evan Cheng
cc4f047dca Instruction encoding bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27102 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 06:00:03 +00:00
Chris Lattner
ea93f63964 Add new intrinsic node definitions for tblgen use 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27100 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 02:29:35 +00:00
Evan Cheng
7b1d34bc6c Added 128-bit packed integer subtraction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27096 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 01:33:37 +00:00
Evan Cheng
3246e06f84 Added CVTTPS2PI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27095 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 01:31:59 +00:00
Evan Cheng
7dda4052f5 Added CVTSS2SI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27094 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 01:00:18 +00:00
Evan Cheng
bc4832bc64 Support for scalar to vector with zero extension. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27091 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 23:15:12 +00:00
Jim Laskey
ff70fe61ed D'oh - should be even numbered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27088 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 22:48:02 +00:00
Evan Cheng
c653d48022 Added LDMXCSR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27087 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 22:28:37 +00:00
Chris Lattner
ac53eadc29 plug the intrinsics into the patterns for movmsk* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27083 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 21:49:18 +00:00
Jim Laskey
47622e3721 Add dwarf register numbering to register data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 21:15:58 +00:00
Jim Laskey
8da17b242f Add support for dwarf register numbering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27080 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 21:13:21 +00:00
Chris Lattner
057f09bc0b add another note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27077 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 20:04:27 +00:00
Chris Lattner
e6cd96d467 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27076 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 19:59:17 +00:00
Chris Lattner
da10f19d5c Shuffle some includes around 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27073 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 18:52:35 +00:00
Chris Lattner
da91bdcfb0 expose intrinsic info to the targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27070 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 18:44:11 +00:00
Chris Lattner
8edd11f33d Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ?? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27069 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 18:24:43 +00:00
Chris Lattner
54e869e18c Like the comment says, prefer to use the implicit add done by [r+r] addressing 
modes than emitting an explicit add and using a base of r0.  This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27068 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 17:58:06 +00:00
Jim Laskey
98a6979b25 Clean up some commentary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27064 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 10:00:56 +00:00
Chris Lattner
7fbcef7102 Disable the i32->float G5 optimization. It is unsafe, as documented in the 
comment.

This fixes 177.mesa, and McCat/09-vor with the td scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27060 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 07:53:47 +00:00
Chris Lattner
64b3a08bc6 add support for using vxor to build zero vectors. This implements 
Regression/CodeGen/PowerPC/vec_zero.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27059 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 07:48:08 +00:00
Evan Cheng
386031a06f Handle BUILD_VECTOR with all zero elements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27056 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 07:29:27 +00:00
Chris Lattner
9d5da1d96c Gabor points out that we can't spell. :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 07:12:19 +00:00
Evan Cheng
5217a5b58c All v2f64 shuffle cases can be handled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27044 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 06:40:32 +00:00
Evan Cheng
2c0dbd01d2 More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27040 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 02:58:06 +00:00
Evan Cheng
b20aaceb52 A new entry 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27039 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 02:57:03 +00:00
Reid Spencer
cf22612fad Ignore the burg output files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27033 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 02:21:35 +00:00
Evan Cheng
14aed5e66b Handle more shuffle cases with SHUFP* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27024 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 01:18:28 +00:00
Chris Lattner
716aefcd91 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27000 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 21:28:44 +00:00
Evan Cheng
8fc23cd0e9 Typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26997 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 20:26:04 +00:00
Chris Lattner
dc6af72781 Add PPC vector bit-convert support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26995 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 19:54:27 +00:00
Jim Laskey
f1d78e8335 Add support to locate local variables in frames (early version.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26994 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 18:12:57 +00:00
Jim Laskey
99db0442f0 Change interface to DwarfWriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26991 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 18:09:44 +00:00
Jim Laskey
580418e082 Modify how CBE handles #lines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26990 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 18:08:29 +00:00
Chris Lattner
29b4dd0c9c Fix the encodings of these new instructions, hopefully fixing the JIT 
failures from last night


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26981 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 16:13:50 +00:00
Evan Cheng
24dc1f5975 Following icc's lead: use movdqa to load / store 128-bit integer vectors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26980 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 07:44:07 +00:00
Chris Lattner
bc641b9d8b Eliminate IntrinsicLowering from TargetMachine. 
Make the CBE and V9 backends create their own, since they're the only ones that use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26974 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 05:43:16 +00:00
Chris Lattner
ef98691ca3 remove always-null IntrinsicLowering argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26971 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 05:28:02 +00:00
Evan Cheng
3b047f7bfa Add v4i32 <-> v4f32 bitconvert patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26969 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 02:36:37 +00:00
Evan Cheng
a971f6f967 Add 128-bit integer vector load and add (for testing). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26967 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 01:57:24 +00:00
Nate Begeman
ce9448218a Add support for 8 bit immediates with 16/32 bit cmp instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26966 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 01:29:48 +00:00
Evan Cheng
ca6e8eafd2 Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do 
64-bit vector shuffle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26964 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 22:07:06 +00:00
Evan Cheng
0cea6d2b9c SHUFP* are two address code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26959 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 20:08:18 +00:00
Evan Cheng
a88973f826 Some clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26957 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 19:22:18 +00:00
Evan Cheng
1bffadd7fb - Supposely movlhps is faster / better than unpcklpd. 
- Don't forget pshufd is only available with sse2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26956 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 19:16:21 +00:00
Evan Cheng
0188ecba85 - Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support 
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26954 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 18:59:22 +00:00
Evan Cheng
63d3300da1 - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches 
PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26951 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 08:01:21 +00:00
Chris Lattner
c04b423f14 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26950 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 07:33:46 +00:00
Evan Cheng
2da953f77a Fix PSHUF* and SHUF* jit code emission problems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26949 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 07:10:28 +00:00
Chris Lattner
9d86a9dff2 This has been implemented. Tweak it into another note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26944 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 05:33:23 +00:00
Chris Lattner
ecfe55e65b When possible, custom lower 32-bit SINT_TO_FP to this: 
_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 05:30:33 +00:00
Chris Lattner
e5ba580ab0 Add support for "ri" addressing modes where the immediate is a 14-bit field 
which is shifted left two bits before use.  Instructions like STD use this
addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26942 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 05:26:03 +00:00
Chris Lattner
6df1154644 fix a warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26941 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 04:18:34 +00:00
Evan Cheng
b9df0ca67b Some splat and shuffle support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26940 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 02:53:00 +00:00
Evan Cheng
a9f2a717e9 Add a couple more pseudo instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26939 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 02:52:03 +00:00
Chris Lattner
eb8b09f69f Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-22 01:44:36 +00:00
Evan Cheng
4a7da36546 Didn't mean to check this in. No MMX support yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26933 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 23:04:23 +00:00
Evan Cheng
48090aa814 - Use movaps to store 128-bit vector integers. 
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26932 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 23:01:21 +00:00
Chris Lattner
9b3bd467d0 These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 20:51:05 +00:00
Chris Lattner
f3ce43210a Don't emit pseudo instructions! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26926 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 20:19:37 +00:00
Nate Begeman
c0a8b6df2a Update readme 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26924 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 18:58:20 +00:00
Chris Lattner
13feb58aa1 Print absolute memory references like this: 
lwz r2, 8(0)
instead of this:
       lwz r2, 8(r0)

This fixes the llc/llc-beta failures on PPC last night.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26922 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 17:21:13 +00:00
Evan Cheng
7ab54047e7 Combine 2 entries 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26921 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 07:18:26 +00:00
Evan Cheng
50a6d8c835 Add a note about x86 register coallescing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26920 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 07:12:57 +00:00
Evan Cheng
82521dd838 - Remove scalar to vector pseudo ops. They are just wrong. 
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26919 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 07:09:35 +00:00
Chris Lattner
8151914321 With Evan's latest tblgen patch, this code is obsolete, thanks Evan! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26917 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 06:37:40 +00:00
Chris Lattner
8593f9891d When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26913 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:51:38 +00:00
Chris Lattner
ef040dd4a3 minor note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26912 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:47:09 +00:00
Evan Cheng
811ec1c92a x86 ISD::SCALAR_TO_VECTOR support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26911 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:33:35 +00:00
Evan Cheng
5c791c8ba4 Junk unused vector register classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26910 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 00:30:59 +00:00
Chris Lattner
d97964457e Handle constant addresses more efficiently, folding the low bits into the 
disp field of the load/store if possible.  This compiles
CodeGen/PowerPC/load-constant-addr.ll to:

_test:
        lis r2, 2838
        lfs f1, 26848(r2)
        blr

instead of:

_test:
        lis r2, 2838
        ori r2, r2, 26848
        lfs f1, 0(r2)
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26908 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 22:38:22 +00:00
Chris Lattner
23baa1b310 remove dead variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26907 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 22:37:23 +00:00
Chris Lattner
bd83afd3cd Fix a couple of bugs in permute/splat generate, thanks to Nate for actually 
figuring these out! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26904 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 18:26:51 +00:00
Chris Lattner
e376e00247 reenable this hack, the tblgen version isn't quite ready 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26902 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 17:54:43 +00:00
Chris Lattner
32f57d9e26 Fix the pattern for VADDUWM, add i32 splat 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26901 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 17:51:58 +00:00
Evan Cheng
e63d746ef6 Use tblgen'd VECTOR_SHUFFLE selection code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 08:14:16 +00:00
Chris Lattner
dd4d2d0e40 Add support for generating vspltw, instead of a vperm instruction with a 
constant pool load.  This generates significantly nicer code for splats.

When tblgen gets bugfixed, we can remove the custom selection code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26898 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:51:10 +00:00
Chris Lattner
88a99ef7cc Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26897 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:37:44 +00:00
Chris Lattner
ef819f8fbb fix duplicate definition errors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26896 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:33:01 +00:00
Chris Lattner
39afef3150 Add a build_vector node 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26895 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:18:01 +00:00
Chris Lattner
3c0f9cc90c Check in some intermediate code that adds a skeleton for matching vsplt* 
instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26894 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:15:45 +00:00
Evan Cheng
ba753c61b7 Move a few things around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26893 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:04:52 +00:00
Chris Lattner
fa818d0b8b add vector_shuffle 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26891 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 05:40:45 +00:00
Chris Lattner
08e25de4d3 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26889 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 05:05:55 +00:00
Chris Lattner
556aae0df0 add vsplat instructions, fix sched description for vperm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26888 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 04:47:33 +00:00
Chris Lattner
f1d0b2beda Custom lower arbitrary VECTOR_SHUFFLE's to VPERM. 
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26887 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:53:53 +00:00
Chris Lattner
2bc6dc27e9 Claim to have v16i8 for perm masks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26886 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:53:02 +00:00
Chris Lattner
abdff1ee6d add the vperm instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26883 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:00:56 +00:00
Chris Lattner
8bcf926277 add a note with a testcase 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26877 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 22:27:41 +00:00
Chris Lattner
28097d086f Add a note about the MUL -> FMADD vector bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26874 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 22:08:08 +00:00
Evan Cheng
c12e6c488e Vector undef's 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26870 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 09:38:54 +00:00
Chris Lattner
b2177b9405 Custom lower SCALAR_TO_VECTOR into lve*x. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26868 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:55:52 +00:00
Chris Lattner
ab515b09bf PPC doesn't have SCALAR_TO_VECTOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26865 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:17:19 +00:00
Chris Lattner
528180ed7b add support for vector undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26863 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:10:09 +00:00
Evan Cheng
d3864b5743 Remind us of exit value substitution 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26862 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:09:23 +00:00
Evan Cheng
5fef51e9aa Turning on LSR by default 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26861 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:08:49 +00:00
Evan Cheng
0def9c3d7d Remember which tests are hurt by LSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26860 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 06:08:11 +00:00
Chris Lattner
a17409dfd6 minor fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26857 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 05:43:01 +00:00
Chris Lattner
28b1a0b532 notes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26856 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 05:33:30 +00:00
Chris Lattner
0a7bff01d0 we don't use lmw/stmw. When we want them they are easy enough to add 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26853 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 04:33:37 +00:00
Chris Lattner
a064d28843 rename these nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26848 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 01:13:28 +00:00
Evan Cheng
2246f8449f Use the generic vector register classes VR64 / VR128 rather than V4F32, 
V8I16, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26838 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-18 01:23:20 +00:00
Nate Begeman
79691bc1f3 Fix subfic to match subc by default instead of sub so that it is correctly 
cost-modeled as producing a flag.  This fixes the test I just added for neg


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26835 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 22:41:37 +00:00
Evan Cheng
df57fa0c7d Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26833 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 20:31:41 +00:00
Evan Cheng
06a8aa14b3 Move some pattern fragments to the right files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26831 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 19:55:52 +00:00
Chris Lattner
89fad2c3b2 Disable x86 fastcc from passing args in registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26824 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 17:27:47 +00:00
Chris Lattner
1c636e9d98 Parameterize the number of integer arguments to pass in registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26818 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 05:10:20 +00:00
Evan Cheng
8586b953a0 Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26817 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 02:36:22 +00:00
Evan Cheng
5bd4d48c24 Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g. 
ADD32ri8.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26816 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 02:25:01 +00:00
Evan Cheng
7f31ad39fb - Nuke 16-bit SBB instructions. We'll never use them. 
- Nuke a bogus comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26815 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 02:24:04 +00:00