Jim Grosbach
6b5252db2d
Encode the register list operands for ARM mode LDM/STM instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 00:37:59 +00:00
Bill Wendling
52925b60f1
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
...
conditional. Check for those instructions explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
Jim Grosbach
f38bfd1918
Remove hard tab characters.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:23:15 +00:00
Jim Grosbach
c4bc2111a7
80 column fix.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:21:57 +00:00
Jim Grosbach
d8a11c25fa
trailing whitespace
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:21:03 +00:00
Jim Grosbach
0d2d2e9246
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
...
encoder functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:19:55 +00:00
Evan Cheng
e09206d4d7
Fix fpscr <-> GPR latency info.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117737 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:16:55 +00:00
Jim Grosbach
3df518e67e
add FIXME
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:56:51 +00:00
Jim Grosbach
8e0a3eb957
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
...
the ARMExpandPseudos pass rather than during the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:35:25 +00:00
Eric Christopher
0e6233bfd7
Handle comparison values we already have - this fixes the consumer-typeset
...
failure for llvm-gcc on arm fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 21:08:19 +00:00
Jim Grosbach
a3c1629ff5
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
...
handle it in the asm lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 20:37:06 +00:00
Jim Grosbach
e317b13a2d
Fix typo.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 20:21:49 +00:00
Jim Grosbach
f32ecc69e5
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 20:21:36 +00:00
Jim Grosbach
86875a2463
ARM mode LDREX*/STREX* binary encodings.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117695 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 19:58:57 +00:00
Jim Grosbach
27e900888e
Encoding information for ARM conditional move instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 19:28:17 +00:00
Evan Cheng
089751535d
Avoiding overly aggressive latency scheduling. If the two nodes share an
...
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 18:09:28 +00:00
Evan Cheng
d7e473c629
- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
...
- Compute CopyToReg use operand latency correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117674 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 18:07:31 +00:00
Jim Grosbach
80eb233a3c
Handle ARM addrmode5 instructions with an offset.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117672 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 17:41:25 +00:00
John Thompson
44ab89eb37
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 17:29:13 +00:00
Jim Grosbach
d8d716fad3
Revert 117660. Apparently it's not as trivial as that...
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 16:50:53 +00:00
Jim Grosbach
da54c6dd4f
ARM addrmode5 instructions have neither writeback nor post-indexed modes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 16:38:59 +00:00
Jim Grosbach
16c7425cff
Trailing whitespace.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117651 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 14:46:02 +00:00
Benjamin Kramer
61a4d56a03
ARMAsmParser: Plug a memory leak.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 09:43:39 +00:00
Eric Christopher
c223e2b10b
Add an unreachable to silence warning - the switch is actually
...
fully enumerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117647 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 09:26:59 +00:00
Chris Lattner
14b93851cc
add simple support for addrmode5 operands, allowing
...
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 00:27:31 +00:00
Chris Lattner
e73d4f8ec7
give better error diagnostics, for example:
...
t.s:1:14: error: invalid operand for instruction
vldr.64 d17, [r0]
^
instead of:
t.s:1:1: error: unrecognized instruction
vldr.64 d17, [r0]
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117611 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:41:58 +00:00
Chris Lattner
6274ec48b3
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
...
the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117609 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:37:33 +00:00
Chris Lattner
fa42fad8bf
move a method out of line.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117605 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:28:01 +00:00
Chris Lattner
550276ee5b
remove the rest of hte owningptr's, no functionality change.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117603 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 20:52:15 +00:00
Benjamin Kramer
57ca3ccd45
Reduce malloc thrashing.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117572 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 18:41:23 +00:00
Jim Grosbach
ab682a2090
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 18:34:10 +00:00
Chris Lattner
c0ddfaa134
rearrange ParseRegisterList.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 17:23:41 +00:00
Chris Lattner
3a69756e39
refactor some code to simplify it, eliminating some owningptr's.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117559 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 17:20:03 +00:00
Evan Cheng
7e2fe9150f
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 06:47:08 +00:00
Evan Cheng
9e08ee5d16
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 02:00:25 +00:00
Evan Cheng
0104d9de04
- Assign load / store with shifter op address modes the right itinerary classes.
...
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 01:49:06 +00:00
Dale Johannesen
e49406fd63
Fix pastos in handling of AVX cvttsd2si, PR8491.
...
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 00:35:54 +00:00
Owen Anderson
cfd0e1f3ae
Add correct NEON encodings for vtbl and vtbx.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 00:18:46 +00:00
Owen Anderson
3eff4af42d
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:56:39 +00:00
Bob Wilson
1fa9d301a8
Fix compiler warnings about signed/unsigned comparisons.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:49:00 +00:00
Evan Cheng
f40deed62f
Shifter ops are not always free. Do not fold them (especially to form
...
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:41:30 +00:00
Jim Grosbach
7e3383c007
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 23:12:14 +00:00
Owen Anderson
498ec20703
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
...
for specifying fractional bits for fixed point conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 22:49:00 +00:00
Jim Grosbach
6b15639e26
Trailing whitespace
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 21:39:08 +00:00
Owen Anderson
d2fbdb7f5c
Provide correct encodings for the get_lane and set_lane variants of vmov.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 21:28:09 +00:00
Kevin Enderby
529b1a4398
Added the x86 instruction ud2b (2nd official undefined instruction).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:46:49 +00:00
Jim Grosbach
ccf72caa92
JIT imm12 encoding for constant pool entry references.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:39:40 +00:00
Bob Wilson
f20700ca77
SelectionDAG shuffle nodes do not allow operands with different numbers of
...
elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:38:28 +00:00
Jim Grosbach
f31430f6ec
ARM JIT fix for LDRi12 and company.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 19:55:59 +00:00
Owen Anderson
f587a9352a
Provide correct NEON encodings for vdup.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 19:25:54 +00:00
Michael J. Spencer
6dad10ed66
x86-Win32: Switch ftol2 calling convention from stdcall to C.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 18:52:38 +00:00
Jim Grosbach
093177d5cd
The new LDR* instruction patterns should handle the necessary encoding of
...
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 17:52:51 +00:00
Owen Anderson
0745c389d9
Add correct NEON encodings for vsli and vsri.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 17:40:08 +00:00
Owen Anderson
dd31ed67e6
Add correct NEON encodings for vsra and vrsra.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 17:29:29 +00:00
Jim Grosbach
063efbf569
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
...
encoding tricks. Handle the 'imm doesn't fit in the insn' case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 16:50:31 +00:00
Kevin Enderby
e460890351
Yet another tweak to X86 instructions to add ud2a as an alias to ud2
...
(still to add ud2b).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 03:01:02 +00:00
Kevin Enderby
5a378076a4
Another tweak to X86 instructions to add the missing flex instruction (without
...
the wait prefix).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 02:53:04 +00:00
Kevin Enderby
f4630ecc3f
Tweaks to X86 instructions to allow the 'w' suffix in places it makes
...
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler
allows for these instructions. Done differently than in r117031 that
caused a valgrind error which was later reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 02:32:19 +00:00
Jim Grosbach
77aee8e22c
LDRi12 machine instructions handle negative offset operands normally (simple
...
integer values), not with the addrmode2 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 01:19:41 +00:00
Kevin Enderby
41e8cc73cf
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
...
will accept versions that the darwin assembler allows. Forms ending in "pi" and
forms without all the operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:59:28 +00:00
Jim Grosbach
f85dd04bfa
One more spot where the new arm mode LDR instruction representation
...
doesn't need the additional addrmode2 register operand. Missed it the first
time around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:38:16 +00:00
Wesley Peck
a06038369b
Adding disassembler to the MicroBlaze backend.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:23:01 +00:00
Jim Grosbach
c1d30212e9
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
...
rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:19:44 +00:00
Jim Grosbach
28e3fe961f
Since I parameterized this bit, I should probably actually use said parameter.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117418 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 23:58:04 +00:00
Dale Johannesen
1de4aa904e
Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches
...
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet). No functional change except
for dump output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 23:11:10 +00:00
Owen Anderson
86ed2324a6
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 22:50:46 +00:00
Jim Grosbach
3e55612472
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 22:37:02 +00:00
Owen Anderson
632c235a31
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 21:58:41 +00:00
Owen Anderson
ac92262b61
Simplify classes for shift instructions, which are never commutable.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 21:13:59 +00:00
Owen Anderson
3557d00a38
Provide correct NEON encodings for vshl, register and immediate forms.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 20:56:57 +00:00
Jim Grosbach
0eb7d06ab1
Grammar.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117388 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 19:34:41 +00:00
Jim Grosbach
c3baf62800
Nuke extraneous comment. It's applicable elsewhere, but not in this func.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 19:22:23 +00:00
Owen Anderson
bc4118bd36
Add correct NEON encoding for vpadal.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 18:18:03 +00:00
Rafael Espindola
de42e5c09b
handle X86::EH_RETURN64 and X86::EH_RETURN.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 18:09:55 +00:00
Owen Anderson
a88ea03bf2
Add NEON encodings for vmov and vmvn of immediates.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 17:40:54 +00:00
Rafael Espindola
e4f506ff4b
Implement some relaxations for arithmetic instructions. The limitation
...
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 14:09:12 +00:00
Kalle Raiskila
505faa6b12
Change v64 datalayout in SPU.
...
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays,
we use array alignment for v64 too. This makes the
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.
This also makes an "unaligned store" test to be
aligned, with different (but functionally equivalent)
code generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 10:45:47 +00:00
Evan Cheng
c8141dfc7f
Use instruction itinerary to determine what instructions are 'cheap'.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 02:08:50 +00:00
Evan Cheng
0e9996ca94
NEON vmov's are in Neon domain.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 02:03:05 +00:00
Bob Wilson
b3a6817d06
Tidy up redundant check.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 00:02:19 +00:00
Rafael Espindola
3336384239
Produce the headers directly in the Finish method. This allows us to use
...
the existing streamer methods that are endian safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 22:26:55 +00:00
Dale Johannesen
d155d7e428
An stdcall function calling a non-stdcall function
...
cannot use tailcall. PR 8461.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 22:17:05 +00:00
Owen Anderson
5258b61966
Add correct encodings for NEON vabal.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117315 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 21:29:04 +00:00
Owen Anderson
410aebc670
Add correct NEON encodings for vaba.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:52:57 +00:00
Owen Anderson
31e6ed890a
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117294 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:17:22 +00:00
Owen Anderson
4110b4325d
Provide correct NEON encodings for vbsl.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:13:13 +00:00
Jim Grosbach
458f2dc5d1
imm12 operands aren't Thumb2 only, so rename the printer helper function.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 20:00:01 +00:00
Owen Anderson
162875a9f3
Add correct instruction encodings for vbic, vorn, and vmvn.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:43:52 +00:00
Rafael Espindola
4921e2356e
Add a virtual destructor.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:38:32 +00:00
Owen Anderson
8c71eff594
Provide correct NEON encodings for vand, veor, and vorr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:28:30 +00:00
Owen Anderson
d0c5b6170f
Add NEON encoding tests for vcgt and vacgt.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 18:03:59 +00:00
Rafael Espindola
cecbc3d282
Add support for emitting ARM file attributes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:50:35 +00:00
Owen Anderson
10c15e5d58
Add tests for NEON encodings of vcge and vacge.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:49:32 +00:00
Owen Anderson
4fe20bbd66
Add a warning about our inability to test the encoding of vceq with immediate zero.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117273 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 17:33:02 +00:00
Rafael Espindola
24ba4f7f5f
Add X86::reloc_global_offset_table and use it to have a single place where
...
we check for _GLOBAL_OFFSET_TABLE_.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-24 17:35:42 +00:00
Eric Christopher
a4633f5d74
Move rejection of NEON parameters earlier in fast isel call processing,
...
note that we can actually handle some f64 arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 09:37:17 +00:00
Benjamin Kramer
4d1dca92bd
Make the disassembler tables const so they end up in read-only memory.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 09:10:44 +00:00
Michael J. Spencer
c527407010
X86: Emit _fltused instead of __fltused on Windows x64.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 09:06:59 +00:00
Chandler Carruth
19e57025d4
Move the remaining attribute macros to systematic names based on the attribute
...
name and prefixed with 'LLVM_'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 08:40:19 +00:00
Chandler Carruth
5117709a1d
Remove a define which is never referenced.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117202 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 08:25:16 +00:00
Chandler Carruth
100c267249
Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
...
until other LLVM projects using these are cleaned up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 08:10:43 +00:00
Evan Cheng
5c2d428f43
Enable ARM fastcc.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 02:19:37 +00:00
Evan Cheng
dd9dd6f857
Latency between CPSR def and branch is zero.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23 02:04:38 +00:00
Jim Grosbach
a9a968d1ef
Trailing whitespace.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117188 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 23:48:29 +00:00
Gabor Greif
41f31ef28e
fix memory-layout assumption which only holds on little-endian systems
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 23:16:11 +00:00
Jim Grosbach
f8da5f5dfa
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 22:12:16 +00:00
Evan Cheng
b179b46cc5
Transfer implicit ops when forming load multiple and return instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 21:29:58 +00:00
Owen Anderson
9b26497273
Add correct NEON encodings for vqdmlal.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:35:48 +00:00
Jim Grosbach
385e136dce
Add the encoding information for the rest of the ARM mode multiply instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:15:30 +00:00
Owen Anderson
92205842ca
Provide correct encodings for NEON vmlal.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117131 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 19:05:25 +00:00
Evan Cheng
1f8b40d51c
Silence compiler warnings.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:57:05 +00:00
Owen Anderson
18341e9e31
Provide correct NEON encodings for vmla.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:54:37 +00:00
Jim Grosbach
3870b750e6
More ARM multiply instuction binary encodings.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:35:16 +00:00
Evan Cheng
76f920d316
Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 18:23:05 +00:00
Jim Grosbach
929a7056d8
Parameterize a bit of ARM encoding information, simplifying some instruction
...
definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 17:42:06 +00:00
Benjamin Kramer
a3ac427507
Make some symbols static, move classes into anonymous namespaces.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 17:35:07 +00:00
Jim Grosbach
9463d0e400
More ARM multiply instruction encoding information.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 17:16:17 +00:00
Wesley Peck
eecb858ca8
Making the e_machine configurable by the target backend in ELFObjectWriter.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 15:52:49 +00:00
Andrew Trick
0966ec0861
Reverting r117031 to cleanup valgrind errors.
...
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117087 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 03:58:29 +00:00
Eric Christopher
4f512efee9
Add some basic ret instruction support to arm fast-isel.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117085 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 01:28:00 +00:00
Sean Callanan
751752e7ca
Fixed handling of immediate operand sizes, which
...
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix. Also added
a test case for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 01:24:11 +00:00
Jim Grosbach
f50af8b5b8
ARM binary encoding for some of the multiply instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:52:30 +00:00
Jim Grosbach
3686046a2c
ARM binary encodings for MVN variants.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:19:32 +00:00
Jim Grosbach
3fea19105d
ARM Binary encoding information for BFC/BFI instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 22:03:21 +00:00
Eric Christopher
1778772d1b
These don't need to be virtual.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 21:47:51 +00:00
Owen Anderson
90d4cf9314
Move the encoding logic for Q registers into getMachineOpValue().
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:49:13 +00:00
Owen Anderson
d451f888b8
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
...
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:21:49 +00:00
Eric Christopher
5b924809e4
Handle storing args to the stack for calls.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 20:09:54 +00:00
Wesley Peck
4da992aeba
Adding initial AsmParser implementation for the MBlaze backend. It is
...
mostly based on the ARM AsmParser at this time and is not particularly
functional.
Changed the MBlaze data layout from:
"E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
"E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.
Cleaned up the MBlaze source code:
1. The floating point register class has been removed. The
MicroBlaze does not have floating point registers. Floating
point values are simply stored in integer registers.
2. Renaming the CPURegs register class to GPR to reflect the
standard naming.
3. Removing a lot of stale code from AsmPrinter after
the conversion to InstPrinter.
4. Simplified sign extended loads by marking them as
expanded in ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117054 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 19:48:38 +00:00
Eric Christopher
212ae937bb
More load/store refactoring, call reg+offset simplification from within
...
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 19:40:30 +00:00
Jim Grosbach
3ab5658a12
trailing whitespace
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 19:38:40 +00:00
Owen Anderson
1e93466c3a
Add correct NEON encodings for vhadd and vrhadd.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:55:04 +00:00
Owen Anderson
9d50559bae
Add correct encodings for NEON vaddw.s* and vaddw.u*.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:20:25 +00:00
Owen Anderson
e0e6dc3f4e
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 18:09:17 +00:00
Kevin Enderby
0b9325c97d
More tweaks to X86 instructions to allow the 'w' suffix in places it makes
...
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler allows
for these instructions. Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 17:16:46 +00:00
Duncan Sands
dbbd99faf1
The return value of this call is not used, so no point
...
in assigning it to a variable (gcc-4.6 warning).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 16:06:28 +00:00
Duncan Sands
6abfa46987
Remove some variables that are never really used
...
(gcc-4.6 warns about these).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 16:03:28 +00:00
Duncan Sands
1e1ca0b56d
Add parentheses to pacify gcc, which warns otherwise.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117020 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 16:02:12 +00:00
Wesley Peck
42bd9b30d9
Removing stale AsmPrinter directory from MicroBlaze backend.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116998 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 05:05:06 +00:00
Oscar Fuentes
b692360955
Deleted lib/Target/MBlaze/AsmPrinter/CMakeLists.txt. This way the
...
CMake build does not try to build that library, which collides with
MBlaze/InstPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 05:01:26 +00:00
Wesley Peck
4e9141fd4c
Recommit 116986 with capitalization typo fixed.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116993 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:57:26 +00:00
Andrew Trick
5b7a825ec5
putback r116983 and fix simple-fp-encoding.ll tests
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:40:16 +00:00
Wesley Peck
60e7127e86
Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it
...
compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:34:22 +00:00
Owen Anderson
d9707e3d85
Revert r116983, which is breaking all the buildbots.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:11:16 +00:00
Wesley Peck
13a949071c
Major update of the MicroBlaze backend. The new features are:
...
1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116986 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 03:09:55 +00:00
Michael J. Spencer
e9c253e0bc
X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 01:41:01 +00:00
Evan Cheng
d6865de2d2
Add missing scheduling itineraries for transfers between core registers and VFP registers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 01:12:00 +00:00
Owen Anderson
d7795540d0
Implement correct encodings for NEON vadd, both integer and floating point.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 00:48:00 +00:00
Michael J. Spencer
dd0a00a6e3
CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args.
...
This should be the minimum set of functions that could possibly need it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 00:08:21 +00:00
Eric Christopher
2d8f6fe610
Custom lower f64 args passed in integer registers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21 00:01:47 +00:00
Michael J. Spencer
6e56b18e57
Fix Whitespace.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116972 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 23:40:27 +00:00
Bill Wendling
01aabdac44
Add encoding for moving a value between two ARM core registers and a doublework
...
extension register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116970 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 23:37:40 +00:00
Bill Wendling
7d31a169af
Add encodings for movement between ARM core registers and single-precision
...
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 22:44:54 +00:00
Dale Johannesen
e4d31593c5
Fix crash introduced in 116852. 8573915.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 22:03:37 +00:00
Dale Johannesen
e93d99cf07
Remove Synthesizable from the Type system; as MMX vector
...
types are no longer Legal on X86, we don't need it.
No functional change. 8499854.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 21:32:10 +00:00
Rafael Espindola
64e6719ee8
Handle _GLOBAL_OFFSET_TABLE_ correctly.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 16:46:08 +00:00
Chandler Carruth
1cd9708f5c
Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three
...
#includes in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 08:27:02 +00:00
Eric Christopher
3659ac22c0
Fix a TODO by removing some unnecesary copies.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 08:02:24 +00:00
Jim Grosbach
b8e67fc92b
Fix backwards conditional.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 01:10:01 +00:00
Jim Grosbach
8b95c3ebfb
Add dynamic realignment when rematerializing the base register.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 00:02:50 +00:00
Jim Grosbach
f6d7df6f21
Nuke a commented out bit that got missed a while back.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 23:48:47 +00:00
Jim Grosbach
e4ad387a5a
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
...
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 23:27:08 +00:00
Jim Grosbach
8155ea4c3a
Update comments to remove obsolete references.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 21:34:47 +00:00
Dale Johannesen
575cd148ce
Enable using vdup for vector constants which are splat of
...
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 20:00:17 +00:00
Evan Cheng
2312842de0
Re-enable register pressure aware machine licm with fixes. Hoist() may have
...
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 18:58:51 +00:00
Owen Anderson
081c34b725
Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which
...
must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize
the pass's dependencies.
Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.
I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems
with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass
registration/creation, please send the testcase to me directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 17:21:58 +00:00
Daniel Dunbar
9869413802
Revert r116781 "- Add a hook for target to determine whether an instruction def
...
is", which breaks some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 17:14:24 +00:00
Che-Liang Chiou
b48f2c2e1d
Add lower argument and return of device function
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 13:14:40 +00:00
Michael J. Spencer
94f7eeb84d
X86: Add MS-CRT libcalls.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 07:32:52 +00:00
Michael J. Spencer
87b8665878
Fix Whitespace.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 07:32:42 +00:00
Evan Cheng
11e8b74a7a
- Add a hook for target to determine whether an instruction def is
...
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:55:07 +00:00
Bob Wilson
3454ed9545
Support alignment for NEON vld-lane and vst-lane instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:16:32 +00:00
Kevin Enderby
87f4a1a433
Added a few tweaks to the Intel Descriptor-table support instructions to allow
...
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes. This is again for use just with assembly source for llvm-mc .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
Jim Grosbach
70987fbc60
ARM encoding information for [SU]SAT* instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116768 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 23:35:38 +00:00
Eric Christopher
6e5367d6a3
Revert r116220 - thus turning arm fast isel back on by default.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 22:53:53 +00:00
Bill Wendling
b41ee96d76
Don't recompute MachineRegisterInfo in the Optimize* method.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 21:22:31 +00:00
Jim Grosbach
5c57639c28
For Thumb2, try to use frame pointer references for stack slots even when a
...
base register is available. rdar://8525298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116729 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 18:39:46 +00:00
Rafael Espindola
aa85c21633
Produce ELF::R_386_GOTPC relocations.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116728 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 18:36:12 +00:00
Kevin Enderby
7aef62ff8c
Added a handful of x86-32 instructions that were missing so that llvm-mc would
...
be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 17:04:36 +00:00
Jim Grosbach
0f0127f4a6
ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate
...
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 16:48:59 +00:00
Jim Grosbach
e038a206df
Grammar tweak.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 16:38:50 +00:00
Kalle Raiskila
940e7965f1
Improve lowering of sext to i128 on SPU.
...
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 09:34:19 +00:00
Eric Christopher
4cf34c6c04
Remove the check for invalid calling conventions. Testing shows that they're
...
working just fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116698 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 06:49:12 +00:00
Eric Christopher
fa87d66752
Lift arg promotion from the X86 backend. This should be unified at some point.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 02:17:53 +00:00
Eric Christopher
404be0c04f
Now that we handle all allocas via a non-SP reg offset remove all of the
...
special case handling for ARM::SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 11:08:44 +00:00
Eric Christopher
ec8bf972f5
Allow more load types to be materialized through the allocas.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 06:07:26 +00:00
Eric Christopher
d56d61af01
Optimize GEP off of intermediate allocas.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116681 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:51:42 +00:00
Eric Christopher
7208dbf2d5
Fix comment.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116680 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:42:53 +00:00
Eric Christopher
dc0b0ef6cd
Turn on AddOperator folding in GEP.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116679 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:41:46 +00:00
Eric Christopher
45c607134b
Use the i12 immediate versions of the load instructions - they're handled
...
more in the post-passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-17 01:40:27 +00:00
Rafael Espindola
f230df9af4
Add a MCObjectFormat class so that code common to all targets that use a
...
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116675 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-16 18:23:53 +00:00
Michael J. Spencer
84ac4d5a2a
X86-Windows: Emit an undefined global __fltused symbol when targeting Windows
...
if any floating point arguments are passed to an external function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116665 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-16 08:25:41 +00:00
Eric Christopher
47650ece37
Fix some funky formatting that got through.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-16 01:10:35 +00:00
Bill Wendling
07fda9f9b6
ARMCodeEmitter::emitMiscInstruction is dead. Long live
...
ARMCodeEmitter::emitMiscInstruction!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 23:35:12 +00:00
Eric Christopher
c9a91fdaf9
Make sure offset is 0 for load/store register to the stack call.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 23:07:10 +00:00
Eric Christopher
00ed59a968
Formatting.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 22:49:28 +00:00
Eric Christopher
315030ca74
Fix else if -> if in store machinery.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 22:32:37 +00:00
Bill Wendling
2695d8edd1
Reformatting. No functionalogicality changes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116625 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 21:50:45 +00:00
Eric Christopher
a322425642
Refactor ARM fast-isel reg + offset to be a base + offset.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 21:32:12 +00:00
Jim Grosbach
5ad01c7728
Encoding information for the various ARM saturating add/sub instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116612 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 19:49:46 +00:00