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5342 Commits

Author SHA1 Message Date
Jim Grosbach
e4e4a93e9e Thumb2 assembly parsing and encoding for SASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 21:01:23 +00:00
Jim Grosbach
191d33fd6d Thumb2 assembly parsing and encoding for RSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139839 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 20:54:14 +00:00
Jim Grosbach
689b86ed2e Thumb2 assembly parsing and encoding for REV16/REVSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139828 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 19:46:13 +00:00
Owen Anderson
ede042dc8d Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139820 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 18:36:29 +00:00
Jim Grosbach
1b69a128d6 Thumb2 assembly parsing and encoding for REV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139813 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 18:13:30 +00:00
Jim Grosbach
b6e9a83349 ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139796 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 16:16:50 +00:00
Jim Grosbach
57b21e437a Thumb2 push/pop mnemonic recognition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 15:55:04 +00:00
Jim Grosbach
0b69247b10 Thumb2 assembly parsing and encoding for PKH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 23:16:41 +00:00
Jim Grosbach
21a05e7017 ARMv7a has the PKH instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139753 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 23:16:34 +00:00
Jim Grosbach
e1d58a6556 ARM tighten up the register classes for the PKH instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139748 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 22:52:14 +00:00
Owen Anderson
8adf62034a Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 22:46:14 +00:00
Jim Grosbach
d32872f9ca Thumb2 assembly parsing and encoding for MVN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:24:41 +00:00
Owen Anderson
34626acf7f Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:06:21 +00:00
Jim Grosbach
64944f48a1 Thumb2 assembly parsing and encoding for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139735 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:00:40 +00:00
Jim Grosbach
bf841cf336 Thumb2 assembly parsing and encoding for MSR/MRS. 
Fix a bug in handling default flags for both ARM and Thumb encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 20:03:46 +00:00
Jim Grosbach
c2d3164ab4 Thumb2 assembly parsing for MOV in IT block. 
Select the right 16 vs. 32 bit encoding in an IT block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 19:12:11 +00:00
Jim Grosbach
d0588e2a2e ARM fix assembly parser handling of ranges in register lists. 
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.

rdar://8883573


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 18:08:35 +00:00
Jim Grosbach
d300b94e51 Remove unnecessary scope resolution operator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 22:56:44 +00:00
Owen Anderson
7782a58b87 Correct disassembly printing of Thumb2 post-incremented LDRD and STRD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139639 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:46:26 +00:00
Jim Grosbach
d7a2b3bea8 There's only 16 regs legal in a register list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139637 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:35:57 +00:00
Jim Grosbach
b04546ff5b Tidy up a few 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:30:37 +00:00
Jim Grosbach
8f310d9786 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:27:44 +00:00
Owen Anderson
b6b7f515e2 Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139610 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 17:59:19 +00:00
Owen Anderson
12c7e90d36 Fix encoding of Thumb2 shifted register operands with RRX shifts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 17:34:32 +00:00
Eli Friedman
885f1a0c04 Zap some junk from the ARM instruction descriptions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 02:29:58 +00:00
Jim Grosbach
2d539691a1 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 23:36:42 +00:00
Owen Anderson
cd00dc6852 Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 21:28:46 +00:00
Owen Anderson
fd92d2e106 Fix encoding of PC-relative LDRSHW with an immediate offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 20:36:51 +00:00
Owen Anderson
a073795023 There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139531 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 20:07:22 +00:00
Owen Anderson
a3157b4026 Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 18:56:30 +00:00
Jim Grosbach
1ad60c2adc Thumb2 parsing and encoding for MOV(immediate). 
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 00:15:36 +00:00
Owen Anderson
921d01ae1f LDM writeback is not allowed if Rn is in the target register list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:13:33 +00:00
Owen Anderson
112fb73502 Fix an ambiguously nested if. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:13:02 +00:00
Owen Anderson
cd4338fff5 Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139429 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:05:14 +00:00
Owen Anderson
08fef885eb Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:24:36 +00:00
Owen Anderson
51f6a7abf2 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:48:23 +00:00
Jim Grosbach
468709e43d Thumb2 assembly parsing and encoding for MLA and MLS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:24:45 +00:00
Jim Grosbach
0811fe13d6 Thumb2 assembly parsing and encoding for LDRSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:42:40 +00:00
Jim Grosbach
b6aed508e3 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 18:37:27 +00:00
Owen Anderson
441462f932 All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:48:37 +00:00
Owen Anderson
d2fc31b3f7 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:42:49 +00:00
Jim Grosbach
a77295db19 Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:07:06 +00:00
Jim Grosbach
e64fb28da1 Thumb2 assembly parsing and encoding for LDR post-indexed. 
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 01:01:32 +00:00
Jim Grosbach
eeec025cf5 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 00:39:19 +00:00
Owen Anderson
170580e8f4 Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 00:11:18 +00:00
Jim Grosbach
f0eee6eca8 Thumb2 assembly parsing and encoding for LDRBT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:39:14 +00:00
Jim Grosbach
ab899c1bcc Thumb2 assembly parsing and encoding for LDR(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:10:15 +00:00
Jim Grosbach
8bb5a861a0 Thumb2 assembly parsing and encoding for LDRB(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:41:25 +00:00
Owen Anderson
8a83f71301 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:10:42 +00:00
Jim Grosbach
a8307dd1c9 Thumb2 parsing and encoding for LDR(immediate). 
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 20:58:57 +00:00
Jim Grosbach
94f914e3fd Thumb2 parsing and encoding for LDMDB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 19:57:53 +00:00
James Molloy
a5d5856854 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 19:42:28 +00:00
Jim Grosbach
cfbb3a78db Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix. 
There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139243 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 18:39:47 +00:00
Jim Grosbach
76ecc3d35b Thumb2 parsing and encoding for LDMIA. 
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 18:05:34 +00:00
Owen Anderson
6de3c6f1a9 Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 17:55:19 +00:00
James Molloy
b950585cc5 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 17:24:38 +00:00
Jim Grosbach
ffa5a76344 Thumb2 use 'ldm' as default mnemonic. 
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 16:22:42 +00:00
Jim Grosbach
81d2e3901e Better diagnostic location information for mnemonic suffices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139232 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 16:06:04 +00:00
Jim Grosbach
218affc710 ISB is HasDB, not just HasV7. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139202 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 23:09:19 +00:00
Jim Grosbach
aa833e53dc Thumb2 parsing and encoding for ISB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 22:53:27 +00:00
Jim Grosbach
06c1a51241 Thumb2 parsing and encoding for DMB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 22:14:58 +00:00
Jim Grosbach
77951908b7 Thumb2 parsing and encoding for DBG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 22:06:40 +00:00
Jim Grosbach
ef88a92677 Thumb2 parsing and encoding for CMN and CMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139188 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 21:44:58 +00:00
Eli Friedman
34c4485b74 Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 20:53:37 +00:00
Jim Grosbach
ad2dad930d Thumb2 parsing and encoding for CLREX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 20:27:04 +00:00
Duncan Sands
28b77e968d Add codegen support for vector select (in the IR this means a select 
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 19:07:46 +00:00
Evan Cheng
4a51708448 Fix fall outs from my recent change on how carry bit is modeled during isel. 
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 18:52:20 +00:00
Jim Grosbach
98447daa95 ARM .code directive should always go to the streamer. 
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139155 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 18:46:23 +00:00
Jakob Stoklund Olesen
9b0e1e7a5b Atomic pseudos don't use (as in read) CPSR. They clobber it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 17:40:35 +00:00
Nick Lewycky
1fac6b50ea Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain 
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-05 21:51:43 +00:00
Nick Lewycky
7442a03dcc Fix typo in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139122 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-05 18:35:03 +00:00
Jim Grosbach
6c3e11ea55 Thumb2 parsing and encoding for BXJ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 23:43:09 +00:00
Jim Grosbach
a110988b39 Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139049 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 23:22:08 +00:00
Eli Friedman
4136d23c48 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 22:33:24 +00:00
Jim Grosbach
5f25fb01b4 Thumb2 parsing and encoding for ASR. 
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139040 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 21:28:54 +00:00
Jim Grosbach
8e0c7697fd Tidy up. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 18:46:15 +00:00
Jim Grosbach
d2990107a9 Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 18:43:25 +00:00
Jim Grosbach
5c1ac55542 Thumb2 parsing and encoding for AND (register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 18:41:35 +00:00
Jim Grosbach
f0851e5d95 Thumb2 parsing and encoding for ADD (register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 18:14:46 +00:00
Owen Anderson
a1c110045a Merge the ARM disassembler header into the implementation file, since it is not externally exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138982 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 23:35:51 +00:00
Owen Anderson
a6804444e8 Fix 80 columns violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 23:23:50 +00:00
Benjamin Kramer
36a16015ac Don't drop alignment info on local common symbols. 
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 23:04:27 +00:00
Eli Friedman
7df496d2ad Null-initialize to shut up -Wuninitialized warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 22:27:41 +00:00
Jim Grosbach
2f25d9b933 ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138952 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 18:22:13 +00:00
James Molloy
c047dcade5 Fix up r137380 based on post-commit review by Jim Grosbach. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 18:02:14 +00:00
Owen Anderson
7f17b5a483 t2Bcc is allowed to have a predicate without a preceding IT instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 17:47:45 +00:00
Jim Grosbach
20ed2e7939 Thumb2 assembly parsing and encoding for ADD(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 00:28:52 +00:00
Chad Rosier
dd1e7517b5 Fixup for functions that return a bool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138918 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 23:49:05 +00:00
Jim Grosbach
de98273189 Static relocation model Thumb jump table interworking. 
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138912 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 22:23:09 +00:00
Owen Anderson
b45b11bce1 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 22:00:41 +00:00
Jim Grosbach
c075510e43 Thumb2 t2Bcc should encode as t2B when condition is 'always'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138898 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:17:31 +00:00
Owen Anderson
721cb1fde0 Fix encoding for tBcc with immediate offset operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 20:26:14 +00:00
Owen Anderson
d84192fe4f When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. 
<rdar://problem/10046188>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 20:00:11 +00:00
Jim Grosbach
b80ab8e369 Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. 
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138879 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 18:39:39 +00:00
Owen Anderson
559c277aa9 Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138874 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 18:30:20 +00:00
Jim Grosbach
c9a9b44285 tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 18:29:05 +00:00
Jim Grosbach
72335d55d9 Thumb2 parsing and encoding for ADC(register). 
Also add instruction aliases for non-.w versions of SBC since they're the
same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 18:23:08 +00:00
Eli Friedman
4d3f329453 64-bit atomic cmpxchg for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 17:52:22 +00:00
Jim Grosbach
0f3abd8d68 Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 17:07:33 +00:00
Jakob Stoklund Olesen
6154582983 Put VMOVS widening under a command line option, off by default. 
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.

The failing test case is complicated, I am working on a reduction.

<rdar://problem/10044201>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 17:00:02 +00:00
Eli Friedman
3d93861c23 Some minor cleanups for r138845. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 00:41:05 +00:00
Eli Friedman
2bdffe4882 Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 00:31:29 +00:00
Owen Anderson
eaca928a37 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 22:58:27 +00:00
Owen Anderson
21df36c57a Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 22:15:17 +00:00
Owen Anderson
a7710edd98 Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138835 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 22:10:03 +00:00
Owen Anderson
391ac65377 Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138834 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 22:03:20 +00:00
Owen Anderson
10096dbdef Clean up whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 21:58:18 +00:00
Evan Cheng
37fefc20d3 Follow up to r138791. 
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 19:09:48 +00:00
Evan Cheng
342e3161d9 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 01:34:54 +00:00
Jim Grosbach
d3765189bf Revert 138781. It's not playing nicely with the immediate forms for ADC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138782 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 23:24:15 +00:00
Jim Grosbach
e94a5b1218 Thumb2 assembler aliases for ADC/SBC w/o the .w suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 23:20:54 +00:00
Owen Anderson
694e0ffb8a Add missing encoding information for some of the GPR<->FP register moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 23:15:25 +00:00
Jim Grosbach
f8e1e3e729 Thumb2 parsing and encoding for IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 22:24:09 +00:00
Owen Anderson
acb274baac Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 21:14:19 +00:00
Owen Anderson
1f26758510 Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138760 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 20:42:00 +00:00
Owen Anderson
c4e16de765 addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138758 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 20:16:50 +00:00
Owen Anderson
0da10cf44d Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 19:36:44 +00:00
Eli Friedman
4db5acaf48 Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 18:23:02 +00:00
Owen Anderson
07700d486e Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 17:59:41 +00:00
Owen Anderson
63553c77cd Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 17:17:09 +00:00
Benjamin Kramer
2753ae314f Silence GCC warnings and make an array const. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138706 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-27 17:36:14 +00:00
Owen Anderson
f1eab597b2 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 23:32:08 +00:00
Owen Anderson
d7568e1c35 Correct encoding of BL with immediate offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 22:54:51 +00:00
Jim Grosbach
4af54a461f ARM assembly parsing tweak for pldw. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 22:21:51 +00:00
Owen Anderson
9f7e831994 Spelling fail. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138667 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:47:57 +00:00
Jim Grosbach
89df996ab2 Thumb2 assembler parsing and encoding of IT instruction. 
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138665 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:43:41 +00:00
Owen Anderson
2b568fb3ce Fix ARM codegen breakage caused by r138653. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138657 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:12:37 +00:00
Owen Anderson
9ab0f25fc1 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 20:43:14 +00:00
Owen Anderson
1af7f7291d Update for feedback from Jim. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 19:39:26 +00:00
Benjamin Kramer
86ce852a15 ARMDisassembler: Always return a size, even when disassembling fails. 
This should fix PR10772.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 18:21:36 +00:00
Owen Anderson
96425c8464 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 18:09:22 +00:00
Owen Anderson
9bd655dcde Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. 
This is the last disassembly crash detected by exhaustive Thumb2 instruction space.  Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 06:19:51 +00:00
Eli Friedman
069e2ed794 Atomic load/store on ARM/Thumb. 
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 02:59:24 +00:00
Nick Lewycky
b210cbf692 Remove stray fullstop. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138589 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 21:46:20 +00:00
Owen Anderson
99906830e8 Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 18:30:18 +00:00
Andrew Trick
b9ca5124f8 ARM fix for missing implicit operands on ldmia_ret. 
rdar://10005094: miscompile of 176.gcc


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138568 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 17:50:53 +00:00
Andrew Trick
51972da576 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 17:40:54 +00:00
Jim Grosbach
0c49ac05cd Explicitly disallow predication in Thumb1 assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138562 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 17:23:55 +00:00
Evan Cheng
77eaaf0a0c Hide -global-merge option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138540 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 01:22:49 +00:00
Evan Cheng
b8cfe4ff41 Add a command line option to disable global merge pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138536 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 01:00:36 +00:00
Evan Cheng
0f660260e6 Remove a out-of-place comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138534 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 00:54:42 +00:00
Owen Anderson
f44082091c Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 22:40:22 +00:00
Jim Grosbach
b9d3ff8729 ARM asm backend initialize isThumbMode based on target triple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138501 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 22:27:35 +00:00
Jim Grosbach
4d23e99d2a Thumb .n mnemonic qualifiers can be ignored for now. 
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 22:19:48 +00:00
Jim Grosbach
f69c804036 Thumb parsing and encoding for SUB (SP minu immediate). 
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 21:42:27 +00:00
Owen Anderson
12a1e3bbcb Be careful not to walk off the end of the operand info list while updating VFP predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 21:35:46 +00:00
Jim Grosbach
72f39f8436 Thumb parsing and encoding support for ADD SP instructions. 
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 21:22:15 +00:00
Jim Grosbach
df9ce6bbc5 When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate. 
rdar://10015134

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138467 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 20:06:14 +00:00
Jim Grosbach
f95aaf951b Add missing explicit writeback operand to tSTMIA_UPD. 
rdar://10014745

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138457 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 18:19:42 +00:00
Evan Cheng
3e74d6fdd2 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 18:08:43 +00:00
Jim Grosbach
c7e0bb2325 Thumb add SP assembly syntax fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 18:04:27 +00:00
Jim Grosbach
5b81584f74 Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. 
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 17:46:13 +00:00
Owen Anderson
e234d02204 Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 17:21:43 +00:00
Jim Grosbach
5aa29a0cff Move ARM frame-unwinding EHABI handling a touch earlier. 
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138386 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 21:32:34 +00:00
Jim Grosbach
d04f6a581c [SU]XT[BH] are only available on ARMv6 and up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138373 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 20:53:08 +00:00
Evan Cheng
7801136b95 Some refactoring so TargetRegistry.h no longer has to include any files 
from MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 20:15:21 +00:00
Jim Grosbach
ec8b866434 Thumb parsing and encoding for SVC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138360 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 19:49:10 +00:00
Jim Grosbach
803b1aa8ef Thumb parsing and encoding for tSTRspi. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 18:39:41 +00:00
Jim Grosbach
1e84f19337 Thumb parsing and encoding for STM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 18:15:37 +00:00
Jim Grosbach
aa875f8c6f Factor low reg checking into a helper function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 18:13:04 +00:00
Owen Anderson
82265a2c72 Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 17:51:38 +00:00
Owen Anderson
6153a036f5 Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 17:45:18 +00:00
Jim Grosbach
cefe4c9c48 Clean up Thumb load/store multiple definitions. 
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138338 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 17:41:15 +00:00
Owen Anderson
e732cb0043 Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 17:37:32 +00:00
Jim Grosbach
04d55f1905 Thumb parsing and encoding for SBC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138311 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:55:58 +00:00
Jim Grosbach
934755ac04 Thumb parsing and encoding for RSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:47:13 +00:00
Owen Anderson
8e1e60b5f8 Reject invalid imod values in t2CPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:44:04 +00:00
Owen Anderson
c6788c83b4 t2SMLAD is a four-register instruction, not a three-register one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:31:45 +00:00
Owen Anderson
22d35086fe Correct operand naming of t2USAT16 to allow proper decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138300 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:27:47 +00:00
Jim Grosbach
86b5d2b02d Revert r138278 now that r138289 has fixed the root issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138299 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:25:48 +00:00
Owen Anderson
2379fc235f Match operand naming to allow correct decoding of t2LDRSH_POST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:22:05 +00:00
Jim Grosbach
6dcafc0d0b Improve error checking for tPUSH and tPOP register lists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:17:34 +00:00
Owen Anderson
796c3659c9 Match operand names to provide correct decoding for Thumb2 SMULL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:16:48 +00:00
Owen Anderson
2c9f83533b Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:10:16 +00:00
Jim Grosbach
7260c6a4ea Thumb assemmbly parsing diagnostic improvements for LDM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:01:07 +00:00
Jim Grosbach
5e8701002b Temporarilly mark tMUL as not commutable. 
It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138278 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 22:00:18 +00:00
Owen Anderson
838130e3b9 Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138273 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 21:34:00 +00:00
Owen Anderson
357ec6850b Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 20:27:12 +00:00
Jim Grosbach
11e03e7c2d Tighten up ARM reglist validation a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:50:36 +00:00
Owen Anderson
2cbf210450 Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:42:13 +00:00
Owen Anderson
f1c8e3e70e Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:22:06 +00:00
Jim Grosbach
a33b31be45 Clean up predicates on ARM target instruction aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:04:24 +00:00
Owen Anderson
b113ec55e8 Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 17:56:58 +00:00
Chad Rosier
fea95c6bad Remove the VMOVQQ pseudo instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 00:52:40 +00:00
Chad Rosier
bdc18572be Remove VMOVQQQQ pseudo instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 00:40:14 +00:00
Jakob Stoklund Olesen
ac3656ed7a Add <imp-def> operands to QQ and QQQQ stack loads. 
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138164 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 00:17:45 +00:00
Chad Rosier
e5038e191d VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. 
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 00:17:25 +00:00
Jim Grosbach
0780b6303b Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 23:24:36 +00:00
Jim Grosbach
2c3f70e5d4 Thumb assembly parsing and encoding for NEG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138131 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:51:03 +00:00
Jim Grosbach
3a244bd8b3 Fix NEG alias 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:30:58 +00:00
Jim Grosbach
7a01069420 Be more lenient on tied operand matching for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:30:46 +00:00
Jim Grosbach
7a32fa1c78 Update tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:19:48 +00:00
Jim Grosbach
88ae2bc6d5 Thumb assembly parsing and encoding for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:07:46 +00:00
Jim Grosbach
4ec6e888ec Thumb assembly parsing and encoding for MOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 20:46:54 +00:00
Jim Grosbach
73a1c2cea1 Tidy up. Tab character. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138072 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 20:30:19 +00:00
Jim Grosbach
b86e2dbf61 Tab characters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138066 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:41:46 +00:00
Jim Grosbach
1b7b68f087 Thumb assembly parsing and encoding for LSL(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:29:25 +00:00
Jim Grosbach
05b0156734 Thumb assembly parsing and encoding for LDRSB and LDRSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138061 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:17:58 +00:00
Jim Grosbach
38466309d5 Thumb assembly parsing and encoding for LDRH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:55:51 +00:00
Jim Grosbach
48ff5ffe9e Thumb assembly parsing and encoding for LDRB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:49:59 +00:00